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@@ -0,0 +1,14 @@
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# RT-Thread building script for component
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from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
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CPPPATH = [cwd]
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ASFLAGS = ''
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group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
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Return('group')
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@@ -0,0 +1,188 @@
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/*
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* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020/03/26 Huaqi First Nuclei RISC-V porting implementation
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*/
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#include "riscv_encoding.h"
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#ifndef __riscv_32e
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#define RT_SAVED_REGNUM 30
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#else
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#define RT_SAVED_REGNUM 14
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#endif
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#define RT_CONTEXT_SIZE (RT_SAVED_REGNUM * REGBYTES)
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.extern rt_interrupt_from_thread
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.extern rt_interrupt_to_thread
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.section .text
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/*
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* void rt_hw_context_switch_to(rt_ubase_t to);
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* a0 --> to_thread
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*/
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.globl rt_hw_context_switch_to
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/* Start the first task. This also clears the bit that indicates the FPU is
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in use in case the FPU was used before the scheduler was started - which
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would otherwise result in the unnecessary leaving of space in the stack
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for lazy saving of FPU registers. */
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.align 3
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rt_hw_context_switch_to:
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/* Setup Interrupt Stack using
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The stack that was used by main()
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before the scheduler is started is
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no longer required after the scheduler is started.
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Interrupt stack pointer is stored in CSR_MSCRATCH */
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la t0, _sp
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csrw CSR_MSCRATCH, t0
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LOAD sp, 0x0(a0) /* Read sp from first TCB member(a0) */
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/* Pop PC from stack and set MEPC */
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LOAD t0, 0 * REGBYTES(sp)
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csrw CSR_MEPC, t0
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/* Pop mstatus from stack and set it */
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LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp)
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csrw CSR_MSTATUS, t0
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/* Interrupt still disable here */
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/* Restore Registers from Stack */
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LOAD x1, 1 * REGBYTES(sp) /* RA */
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LOAD x5, 2 * REGBYTES(sp)
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LOAD x6, 3 * REGBYTES(sp)
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LOAD x7, 4 * REGBYTES(sp)
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LOAD x8, 5 * REGBYTES(sp)
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LOAD x9, 6 * REGBYTES(sp)
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LOAD x10, 7 * REGBYTES(sp)
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LOAD x11, 8 * REGBYTES(sp)
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LOAD x12, 9 * REGBYTES(sp)
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LOAD x13, 10 * REGBYTES(sp)
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LOAD x14, 11 * REGBYTES(sp)
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LOAD x15, 12 * REGBYTES(sp)
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#ifndef __riscv_32e
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LOAD x16, 13 * REGBYTES(sp)
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LOAD x17, 14 * REGBYTES(sp)
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LOAD x18, 15 * REGBYTES(sp)
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LOAD x19, 16 * REGBYTES(sp)
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LOAD x20, 17 * REGBYTES(sp)
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LOAD x21, 18 * REGBYTES(sp)
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LOAD x22, 19 * REGBYTES(sp)
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LOAD x23, 20 * REGBYTES(sp)
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LOAD x24, 21 * REGBYTES(sp)
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LOAD x25, 22 * REGBYTES(sp)
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LOAD x26, 23 * REGBYTES(sp)
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LOAD x27, 24 * REGBYTES(sp)
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LOAD x28, 25 * REGBYTES(sp)
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LOAD x29, 26 * REGBYTES(sp)
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LOAD x30, 27 * REGBYTES(sp)
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LOAD x31, 28 * REGBYTES(sp)
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#endif
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addi sp, sp, RT_CONTEXT_SIZE
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mret
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.align 2
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.global eclic_msip_handler
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eclic_msip_handler:
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addi sp, sp, -RT_CONTEXT_SIZE
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STORE x1, 1 * REGBYTES(sp) /* RA */
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STORE x5, 2 * REGBYTES(sp)
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STORE x6, 3 * REGBYTES(sp)
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STORE x7, 4 * REGBYTES(sp)
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STORE x8, 5 * REGBYTES(sp)
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STORE x9, 6 * REGBYTES(sp)
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STORE x10, 7 * REGBYTES(sp)
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STORE x11, 8 * REGBYTES(sp)
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STORE x12, 9 * REGBYTES(sp)
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STORE x13, 10 * REGBYTES(sp)
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STORE x14, 11 * REGBYTES(sp)
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STORE x15, 12 * REGBYTES(sp)
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#ifndef __riscv_32e
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STORE x16, 13 * REGBYTES(sp)
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STORE x17, 14 * REGBYTES(sp)
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STORE x18, 15 * REGBYTES(sp)
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STORE x19, 16 * REGBYTES(sp)
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STORE x20, 17 * REGBYTES(sp)
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STORE x21, 18 * REGBYTES(sp)
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STORE x22, 19 * REGBYTES(sp)
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STORE x23, 20 * REGBYTES(sp)
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STORE x24, 21 * REGBYTES(sp)
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STORE x25, 22 * REGBYTES(sp)
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STORE x26, 23 * REGBYTES(sp)
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STORE x27, 24 * REGBYTES(sp)
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STORE x28, 25 * REGBYTES(sp)
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STORE x29, 26 * REGBYTES(sp)
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STORE x30, 27 * REGBYTES(sp)
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STORE x31, 28 * REGBYTES(sp)
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#endif
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/* Push mstatus to stack */
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csrr t0, CSR_MSTATUS
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STORE t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp)
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/* Push additional registers */
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/* Store sp to task stack */
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LOAD t0, rt_interrupt_from_thread
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STORE sp, 0(t0)
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csrr t0, CSR_MEPC
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STORE t0, 0(sp)
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jal rt_hw_taskswitch
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/* Switch task context */
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LOAD t0, rt_interrupt_to_thread
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LOAD sp, 0x0(t0)
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/* Pop PC from stack and set MEPC */
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LOAD t0, 0 * REGBYTES(sp)
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csrw CSR_MEPC, t0
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/* Pop additional registers */
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/* Pop mstatus from stack and set it */
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LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp)
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csrw CSR_MSTATUS, t0
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/* Interrupt still disable here */
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/* Restore Registers from Stack */
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LOAD x1, 1 * REGBYTES(sp) /* RA */
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LOAD x5, 2 * REGBYTES(sp)
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LOAD x6, 3 * REGBYTES(sp)
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LOAD x7, 4 * REGBYTES(sp)
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LOAD x8, 5 * REGBYTES(sp)
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LOAD x9, 6 * REGBYTES(sp)
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LOAD x10, 7 * REGBYTES(sp)
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LOAD x11, 8 * REGBYTES(sp)
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LOAD x12, 9 * REGBYTES(sp)
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LOAD x13, 10 * REGBYTES(sp)
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LOAD x14, 11 * REGBYTES(sp)
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LOAD x15, 12 * REGBYTES(sp)
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#ifndef __riscv_32e
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LOAD x16, 13 * REGBYTES(sp)
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LOAD x17, 14 * REGBYTES(sp)
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LOAD x18, 15 * REGBYTES(sp)
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LOAD x19, 16 * REGBYTES(sp)
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LOAD x20, 17 * REGBYTES(sp)
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LOAD x21, 18 * REGBYTES(sp)
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LOAD x22, 19 * REGBYTES(sp)
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LOAD x23, 20 * REGBYTES(sp)
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LOAD x24, 21 * REGBYTES(sp)
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LOAD x25, 22 * REGBYTES(sp)
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LOAD x26, 23 * REGBYTES(sp)
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LOAD x27, 24 * REGBYTES(sp)
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LOAD x28, 25 * REGBYTES(sp)
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LOAD x29, 26 * REGBYTES(sp)
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LOAD x30, 27 * REGBYTES(sp)
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LOAD x31, 28 * REGBYTES(sp)
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#endif
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addi sp, sp, RT_CONTEXT_SIZE
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mret
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@@ -0,0 +1,257 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020/03/26 Huaqi Nuclei RISC-V Core porting code.
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include "cpuport.h"
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#define SYSTICK_TICK_CONST (SOC_TIMER_FREQ / RT_TICK_PER_SECOND)
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/* Interrupt level for kernel systimer interrupt and software timer interrupt */
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#define RT_KERNEL_INTERRUPT_LEVEL 0
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/* Initial CSR MSTATUS value when thread created */
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#define RT_INITIAL_MSTATUS (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL)
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/**
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* @brief from thread used interrupt context switch
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*
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*/
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volatile rt_ubase_t rt_interrupt_from_thread = 0;
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/**
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* @brief to thread used interrupt context switch
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*
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*/
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volatile rt_ubase_t rt_interrupt_to_thread = 0;
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/**
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* @brief flag to indicate context switch in interrupt or not
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*
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*/
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volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
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/**
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* @brief thread stack frame of saved context
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*
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*/
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struct rt_hw_stack_frame
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{
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rt_ubase_t epc; /*!< epc - epc - program counter */
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rt_ubase_t ra; /*!< x1 - ra - return address for jumps */
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rt_ubase_t t0; /*!< x5 - t0 - temporary register 0 */
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rt_ubase_t t1; /*!< x6 - t1 - temporary register 1 */
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rt_ubase_t t2; /*!< x7 - t2 - temporary register 2 */
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rt_ubase_t s0_fp; /*!< x8 - s0/fp - saved register 0 or frame pointer */
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rt_ubase_t s1; /*!< x9 - s1 - saved register 1 */
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rt_ubase_t a0; /*!< x10 - a0 - return value or function argument 0 */
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rt_ubase_t a1; /*!< x11 - a1 - return value or function argument 1 */
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rt_ubase_t a2; /*!< x12 - a2 - function argument 2 */
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rt_ubase_t a3; /*!< x13 - a3 - function argument 3 */
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rt_ubase_t a4; /*!< x14 - a4 - function argument 4 */
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rt_ubase_t a5; /*!< x15 - a5 - function argument 5 */
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#ifndef __riscv_32e
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rt_ubase_t a6; /*!< x16 - a6 - function argument 6 */
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rt_ubase_t a7; /*!< x17 - s7 - function argument 7 */
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rt_ubase_t s2; /*!< x18 - s2 - saved register 2 */
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rt_ubase_t s3; /*!< x19 - s3 - saved register 3 */
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rt_ubase_t s4; /*!< x20 - s4 - saved register 4 */
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rt_ubase_t s5; /*!< x21 - s5 - saved register 5 */
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rt_ubase_t s6; /*!< x22 - s6 - saved register 6 */
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rt_ubase_t s7; /*!< x23 - s7 - saved register 7 */
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rt_ubase_t s8; /*!< x24 - s8 - saved register 8 */
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rt_ubase_t s9; /*!< x25 - s9 - saved register 9 */
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rt_ubase_t s10; /*!< x26 - s10 - saved register 10 */
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rt_ubase_t s11; /*!< x27 - s11 - saved register 11 */
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rt_ubase_t t3; /*!< x28 - t3 - temporary register 3 */
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rt_ubase_t t4; /*!< x29 - t4 - temporary register 4 */
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rt_ubase_t t5; /*!< x30 - t5 - temporary register 5 */
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rt_ubase_t t6; /*!< x31 - t6 - temporary register 6 */
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#endif
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rt_ubase_t mstatus; /*!< - machine status register */
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};
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/**
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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rt_uint8_t *rt_hw_stack_init(void *tentry,
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void *parameter,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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struct rt_hw_stack_frame *frame;
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rt_uint8_t *stk;
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int i;
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stk = stack_addr + sizeof(rt_ubase_t);
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stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
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stk -= sizeof(struct rt_hw_stack_frame);
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frame = (struct rt_hw_stack_frame *)stk;
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for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
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{
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((rt_ubase_t *)frame)[i] = 0xdeadbeef;
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}
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frame->ra = (rt_ubase_t)texit;
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frame->a0 = (rt_ubase_t)parameter;
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frame->epc = (rt_ubase_t)tentry;
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frame->mstatus = RT_INITIAL_MSTATUS;
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return stk;
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}
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/**
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* @brief Do rt-thread context switch in interrupt context
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*
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* @param from thread sp of from thread
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* @param to thread sp of to thread
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*/
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void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
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{
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if (rt_thread_switch_interrupt_flag == 0)
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rt_interrupt_from_thread = from;
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rt_interrupt_to_thread = to;
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rt_thread_switch_interrupt_flag = 1;
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RT_YIELD();
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}
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/**
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* @brief Do rt-thread context switch in task context
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*
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* @param from thread sp of from thread
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* @param to thread sp of to thread
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*/
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void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to)
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{
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rt_hw_context_switch_interrupt(from, to);
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}
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/**
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* @brief shutdown CPU
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*
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*/
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RT_WEAK void rt_hw_cpu_shutdown()
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{
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rt_uint32_t level;
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rt_kprintf("shutdown...\n");
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level = rt_hw_interrupt_disable();
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while (level)
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{
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RT_ASSERT(0);
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}
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}
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/**
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* @brief Do extra task switch code
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*
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* @details
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*
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* - Clear software timer interrupt request flag
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* - clear rt_thread_switch_interrupt_flag to 0
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*/
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void rt_hw_taskswitch(void)
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{
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/* Clear Software IRQ, A MUST */
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SysTimer_ClearSWIRQ();
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rt_thread_switch_interrupt_flag = 0;
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}
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/**
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* @brief Setup systimer and software timer interrupt
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*
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* @details
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||||
*
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* - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level
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||||
* - Set software timer interrupt as VECTOR interrupt with lowest interrupt level
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||||
* - Enable these two interrupts
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*/
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void rt_hw_ticksetup(void)
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||||
{
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||||
uint64_t ticks = SYSTICK_TICK_CONST;
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/* Make SWI and SysTick the lowest priority interrupts. */
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/* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */
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SysTick_Config(ticks);
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ECLIC_DisableIRQ(SysTimer_IRQn);
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ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
|
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ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
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ECLIC_EnableIRQ(SysTimer_IRQn);
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/* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */
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ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT);
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ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
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ECLIC_EnableIRQ(SysTimerSW_IRQn);
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}
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||||
|
||||
/**
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||||
* systimer interrupt handler eclic_mtip_handler
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||||
* is hard coded in startup_<Device>.S
|
||||
* We define SysTick_Handler as eclic_mtip_handler
|
||||
* for easy understanding
|
||||
*/
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||||
#define SysTick_Handler eclic_mtip_handler
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||||
|
||||
/**
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||||
* @brief This is the timer interrupt service routine.
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||||
*
|
||||
*/
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||||
void SysTick_Handler(void)
|
||||
{
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||||
/* Reload systimer */
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||||
SysTick_Reload(SYSTICK_TICK_CONST);
|
||||
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||||
/* enter interrupt */
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||||
rt_interrupt_enter();
|
||||
|
||||
/* tick increase */
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable cpu interrupt
|
||||
*
|
||||
* @details
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||||
*
|
||||
* - Disable cpu interrupt by clear MIE bit in MSTATUS
|
||||
* - Return the previous value in MSTATUS before clear MIE bit
|
||||
*
|
||||
* @return the previous value in MSTATUS before clear MIE bit
|
||||
*/
|
||||
rt_base_t rt_hw_interrupt_disable(void)
|
||||
{
|
||||
return __RV_CSR_READ_CLEAR(CSR_MSTATUS, MSTATUS_MIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Restore previous saved interrupt status
|
||||
*
|
||||
* @param level previous saved MSTATUS value
|
||||
*/
|
||||
void rt_hw_interrupt_enable(rt_base_t level)
|
||||
{
|
||||
__RV_CSR_WRITE(CSR_MSTATUS, level);
|
||||
}
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020/03/26 hqfang Nuclei RISC-V Core porting code.
|
||||
*/
|
||||
|
||||
#ifndef __CPUPORT_H__
|
||||
#define __CPUPORT_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
#include <nuclei_sdk_soc.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Scheduler utilities. */
|
||||
#define RT_YIELD() \
|
||||
{ \
|
||||
/* Set a software interrupt(SWI) request to request a context switch. */ \
|
||||
SysTimer_SetSWIRQ(); \
|
||||
/* Barriers are normally not required but do ensure the code is completely \
|
||||
within the specified behaviour for the architecture. */ \
|
||||
__RWMB(); \
|
||||
__FENCE_I(); \
|
||||
}
|
||||
|
||||
extern void rt_hw_ticksetup(void);
|
||||
extern void rt_hw_taskswitch(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,218 @@
|
||||
/*
|
||||
* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020/03/26 hqfang First Nuclei RISC-V porting implementation
|
||||
*/
|
||||
|
||||
#include "riscv_encoding.h"
|
||||
|
||||
.section .text.entry
|
||||
.align 8
|
||||
|
||||
/**
|
||||
* \brief Global interrupt disabled
|
||||
* \details
|
||||
* This function disable global interrupt.
|
||||
* \remarks
|
||||
* - All the interrupt requests will be ignored by CPU.
|
||||
*/
|
||||
.macro DISABLE_MIE
|
||||
csrc CSR_MSTATUS, MSTATUS_MIE
|
||||
.endm
|
||||
|
||||
/**
|
||||
* \brief Macro for context save
|
||||
* \details
|
||||
* This macro save ABI defined caller saved registers in the stack.
|
||||
* \remarks
|
||||
* - This Macro could use to save context when you enter to interrupt
|
||||
* or exception
|
||||
*/
|
||||
/* Save caller registers */
|
||||
.macro SAVE_CONTEXT
|
||||
csrrw sp, CSR_MSCRATCHCSWL, sp
|
||||
/* Allocate stack space for context saving */
|
||||
#ifndef __riscv_32e
|
||||
addi sp, sp, -20*REGBYTES
|
||||
#else
|
||||
addi sp, sp, -14*REGBYTES
|
||||
#endif /* __riscv_32e */
|
||||
|
||||
STORE x1, 0*REGBYTES(sp)
|
||||
STORE x4, 1*REGBYTES(sp)
|
||||
STORE x5, 2*REGBYTES(sp)
|
||||
STORE x6, 3*REGBYTES(sp)
|
||||
STORE x7, 4*REGBYTES(sp)
|
||||
STORE x10, 5*REGBYTES(sp)
|
||||
STORE x11, 6*REGBYTES(sp)
|
||||
STORE x12, 7*REGBYTES(sp)
|
||||
STORE x13, 8*REGBYTES(sp)
|
||||
STORE x14, 9*REGBYTES(sp)
|
||||
STORE x15, 10*REGBYTES(sp)
|
||||
#ifndef __riscv_32e
|
||||
STORE x16, 14*REGBYTES(sp)
|
||||
STORE x17, 15*REGBYTES(sp)
|
||||
STORE x28, 16*REGBYTES(sp)
|
||||
STORE x29, 17*REGBYTES(sp)
|
||||
STORE x30, 18*REGBYTES(sp)
|
||||
STORE x31, 19*REGBYTES(sp)
|
||||
#endif /* __riscv_32e */
|
||||
.endm
|
||||
|
||||
/**
|
||||
* \brief Macro for restore caller registers
|
||||
* \details
|
||||
* This macro restore ABI defined caller saved registers from stack.
|
||||
* \remarks
|
||||
* - You could use this macro to restore context before you want return
|
||||
* from interrupt or exeception
|
||||
*/
|
||||
/* Restore caller registers */
|
||||
.macro RESTORE_CONTEXT
|
||||
LOAD x1, 0*REGBYTES(sp)
|
||||
LOAD x4, 1*REGBYTES(sp)
|
||||
LOAD x5, 2*REGBYTES(sp)
|
||||
LOAD x6, 3*REGBYTES(sp)
|
||||
LOAD x7, 4*REGBYTES(sp)
|
||||
LOAD x10, 5*REGBYTES(sp)
|
||||
LOAD x11, 6*REGBYTES(sp)
|
||||
LOAD x12, 7*REGBYTES(sp)
|
||||
LOAD x13, 8*REGBYTES(sp)
|
||||
LOAD x14, 9*REGBYTES(sp)
|
||||
LOAD x15, 10*REGBYTES(sp)
|
||||
#ifndef __riscv_32e
|
||||
LOAD x16, 14*REGBYTES(sp)
|
||||
LOAD x17, 15*REGBYTES(sp)
|
||||
LOAD x28, 16*REGBYTES(sp)
|
||||
LOAD x29, 17*REGBYTES(sp)
|
||||
LOAD x30, 18*REGBYTES(sp)
|
||||
LOAD x31, 19*REGBYTES(sp)
|
||||
|
||||
/* De-allocate the stack space */
|
||||
addi sp, sp, 20*REGBYTES
|
||||
#else
|
||||
/* De-allocate the stack space */
|
||||
addi sp, sp, 14*REGBYTES
|
||||
#endif /* __riscv_32e */
|
||||
csrrw sp, CSR_MSCRATCHCSWL, sp
|
||||
.endm
|
||||
|
||||
/**
|
||||
* \brief Macro for save necessary CSRs to stack
|
||||
* \details
|
||||
* This macro store MCAUSE, MEPC, MSUBM to stack.
|
||||
*/
|
||||
.macro SAVE_CSR_CONTEXT
|
||||
/* Store CSR mcause to stack using pushmcause */
|
||||
csrrwi x0, CSR_PUSHMCAUSE, 11
|
||||
/* Store CSR mepc to stack using pushmepc */
|
||||
csrrwi x0, CSR_PUSHMEPC, 12
|
||||
/* Store CSR msub to stack using pushmsub */
|
||||
csrrwi x0, CSR_PUSHMSUBM, 13
|
||||
.endm
|
||||
|
||||
/**
|
||||
* \brief Macro for restore necessary CSRs from stack
|
||||
* \details
|
||||
* This macro restore MSUBM, MEPC, MCAUSE from stack.
|
||||
*/
|
||||
.macro RESTORE_CSR_CONTEXT
|
||||
LOAD x5, 13*REGBYTES(sp)
|
||||
csrw CSR_MSUBM, x5
|
||||
LOAD x5, 12*REGBYTES(sp)
|
||||
csrw CSR_MEPC, x5
|
||||
LOAD x5, 11*REGBYTES(sp)
|
||||
csrw CSR_MCAUSE, x5
|
||||
.endm
|
||||
|
||||
/**
|
||||
* \brief Exception/NMI Entry
|
||||
* \details
|
||||
* This function provide common entry functions for exception/nmi.
|
||||
* \remarks
|
||||
* This function provide a default exception/nmi entry.
|
||||
* ABI defined caller save register and some CSR registers
|
||||
* to be saved before enter interrupt handler and be restored before return.
|
||||
*/
|
||||
.section .text.trap
|
||||
/* In CLIC mode, the exeception entry must be 64bytes aligned */
|
||||
.align 6
|
||||
.global exc_entry
|
||||
exc_entry:
|
||||
/* Save the caller saving registers (context) */
|
||||
SAVE_CONTEXT
|
||||
/* Save the necessary CSR registers */
|
||||
SAVE_CSR_CONTEXT
|
||||
|
||||
/*
|
||||
* Set the exception handler function arguments
|
||||
* argument 1: mcause value
|
||||
* argument 2: current stack point(SP) value
|
||||
*/
|
||||
csrr a0, mcause
|
||||
mv a1, sp
|
||||
/*
|
||||
* TODO: Call the exception handler function
|
||||
* By default, the function template is provided in
|
||||
* system_Device.c, you can adjust it as you want
|
||||
*/
|
||||
call core_exception_handler
|
||||
|
||||
/* Restore the necessary CSR registers */
|
||||
RESTORE_CSR_CONTEXT
|
||||
/* Restore the caller saving registers (context) */
|
||||
RESTORE_CONTEXT
|
||||
|
||||
/* Return to regular code */
|
||||
mret
|
||||
|
||||
/**
|
||||
* \brief Non-Vector Interrupt Entry
|
||||
* \details
|
||||
* This function provide common entry functions for handling
|
||||
* non-vector interrupts
|
||||
* \remarks
|
||||
* This function provide a default non-vector interrupt entry.
|
||||
* ABI defined caller save register and some CSR registers need
|
||||
* to be saved before enter interrupt handler and be restored before return.
|
||||
*/
|
||||
.section .text.irq
|
||||
/* In CLIC mode, the interrupt entry must be 4bytes aligned */
|
||||
.align 2
|
||||
.global irq_entry
|
||||
/* This label will be set to MTVT2 register */
|
||||
irq_entry:
|
||||
/* Save the caller saving registers (context) */
|
||||
SAVE_CONTEXT
|
||||
/* Save the necessary CSR registers */
|
||||
SAVE_CSR_CONTEXT
|
||||
|
||||
/* This special CSR read/write operation, which is actually
|
||||
* claim the CLIC to find its pending highest ID, if the ID
|
||||
* is not 0, then automatically enable the mstatus.MIE, and
|
||||
* jump to its vector-entry-label, and update the link register
|
||||
*/
|
||||
csrrw ra, CSR_JALMNXTI, ra
|
||||
|
||||
/* Critical section with interrupts disabled */
|
||||
DISABLE_MIE
|
||||
|
||||
/* Restore the necessary CSR registers */
|
||||
RESTORE_CSR_CONTEXT
|
||||
/* Restore the caller saving registers (context) */
|
||||
RESTORE_CONTEXT
|
||||
|
||||
/* Return to regular code */
|
||||
mret
|
||||
|
||||
/* Default Handler for Exceptions / Interrupts */
|
||||
.global default_intexc_handler
|
||||
Undef_Handler:
|
||||
default_intexc_handler:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
Reference in new issue
Block a user