sdio+fatfs创建
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@@ -0,0 +1,14 @@
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# RT-Thread building script for component
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from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
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CPPPATH = [cwd]
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ASFLAGS = ''
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group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
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Return('group')
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@@ -0,0 +1,307 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting implementation
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* 2018/12/27 Jesven Add SMP support
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* 2021/02/02 lizhirui Add userspace support
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*/
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#include "cpuport.h"
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#ifdef RT_USING_SMP
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#define rt_hw_interrupt_disable rt_hw_local_irq_disable
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#define rt_hw_interrupt_enable rt_hw_local_irq_enable
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#endif
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/*
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* rt_base_t rt_hw_interrupt_disable(void);
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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#ifdef RISCV_S_MODE
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csrrci a0, sstatus, 2
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#else
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csrrci a0, mstatus, 8
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#endif
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ret
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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csrw SRC_XSTATUS, a0
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ret
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch_to(rt_ubase_t to);
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* #endif
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* a0 --> to
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* a1 --> to_thread
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LOAD sp, (a0)
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#ifdef RT_USING_SMP
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mv a0, a1
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call rt_cpus_lock_status_restore
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#endif
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LOAD a0, 2 * REGBYTES(sp)
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csrw SRC_XSTATUS, a0
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j rt_hw_context_switch_exit
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
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* #endif
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*
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* a0 --> from
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* a1 --> to
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* a2 --> to_thread
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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/* saved from thread context
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* x1/ra -> sp(0)
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* x1/ra -> sp(1)
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* mstatus.mie -> sp(2)
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* x(i) -> sp(i-4)
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*/
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#ifdef ARCH_RISCV_FPU
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addi sp, sp, -32 * FREGBYTES
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FSTORE f0, 0 * FREGBYTES(sp)
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FSTORE f1, 1 * FREGBYTES(sp)
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FSTORE f2, 2 * FREGBYTES(sp)
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FSTORE f3, 3 * FREGBYTES(sp)
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FSTORE f4, 4 * FREGBYTES(sp)
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FSTORE f5, 5 * FREGBYTES(sp)
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FSTORE f6, 6 * FREGBYTES(sp)
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FSTORE f7, 7 * FREGBYTES(sp)
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FSTORE f8, 8 * FREGBYTES(sp)
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FSTORE f9, 9 * FREGBYTES(sp)
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FSTORE f10, 10 * FREGBYTES(sp)
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FSTORE f11, 11 * FREGBYTES(sp)
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FSTORE f12, 12 * FREGBYTES(sp)
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FSTORE f13, 13 * FREGBYTES(sp)
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FSTORE f14, 14 * FREGBYTES(sp)
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FSTORE f15, 15 * FREGBYTES(sp)
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FSTORE f16, 16 * FREGBYTES(sp)
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FSTORE f17, 17 * FREGBYTES(sp)
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FSTORE f18, 18 * FREGBYTES(sp)
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FSTORE f19, 19 * FREGBYTES(sp)
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FSTORE f20, 20 * FREGBYTES(sp)
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FSTORE f21, 21 * FREGBYTES(sp)
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FSTORE f22, 22 * FREGBYTES(sp)
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FSTORE f23, 23 * FREGBYTES(sp)
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FSTORE f24, 24 * FREGBYTES(sp)
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FSTORE f25, 25 * FREGBYTES(sp)
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FSTORE f26, 26 * FREGBYTES(sp)
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FSTORE f27, 27 * FREGBYTES(sp)
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FSTORE f28, 28 * FREGBYTES(sp)
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FSTORE f29, 29 * FREGBYTES(sp)
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FSTORE f30, 30 * FREGBYTES(sp)
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FSTORE f31, 31 * FREGBYTES(sp)
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#endif
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addi sp, sp, -32 * REGBYTES
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STORE sp, (a0)
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STORE x1, 0 * REGBYTES(sp)
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STORE x1, 1 * REGBYTES(sp)
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csrr a0, SRC_XSTATUS
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#ifdef RISCV_S_MODE
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andi a0, a0, 2
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beqz a0, save_spie
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li a0, 0x20
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save_spie:
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STORE a0, 2 * REGBYTES(sp)
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#else
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andi a0, a0, 8
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beqz a0, save_mpie
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li a0, 0x80
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save_mpie:
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STORE a0, 2 * REGBYTES(sp)
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#endif
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STORE x4, 4 * REGBYTES(sp)
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STORE x5, 5 * REGBYTES(sp)
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STORE x6, 6 * REGBYTES(sp)
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STORE x7, 7 * REGBYTES(sp)
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STORE x8, 8 * REGBYTES(sp)
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STORE x9, 9 * REGBYTES(sp)
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STORE x10, 10 * REGBYTES(sp)
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STORE x11, 11 * REGBYTES(sp)
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STORE x12, 12 * REGBYTES(sp)
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STORE x13, 13 * REGBYTES(sp)
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STORE x14, 14 * REGBYTES(sp)
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STORE x15, 15 * REGBYTES(sp)
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STORE x16, 16 * REGBYTES(sp)
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STORE x17, 17 * REGBYTES(sp)
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STORE x18, 18 * REGBYTES(sp)
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STORE x19, 19 * REGBYTES(sp)
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STORE x20, 20 * REGBYTES(sp)
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STORE x21, 21 * REGBYTES(sp)
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STORE x22, 22 * REGBYTES(sp)
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STORE x23, 23 * REGBYTES(sp)
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STORE x24, 24 * REGBYTES(sp)
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STORE x25, 25 * REGBYTES(sp)
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STORE x26, 26 * REGBYTES(sp)
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STORE x27, 27 * REGBYTES(sp)
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STORE x28, 28 * REGBYTES(sp)
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STORE x29, 29 * REGBYTES(sp)
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STORE x30, 30 * REGBYTES(sp)
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STORE x31, 31 * REGBYTES(sp)
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/* restore to thread context
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* sp(0) -> epc;
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* sp(1) -> ra;
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* sp(i) -> x(i+2)
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*/
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LOAD sp, (a1)
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#ifdef RT_USING_SMP
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mv a0, a2
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call rt_cpus_lock_status_restore
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#endif /*RT_USING_SMP*/
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j rt_hw_context_switch_exit
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#ifdef RT_USING_SMP
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/*
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* void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
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*
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* a0 --> context
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* a1 --> from
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* a2 --> to
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* a3 --> to_thread
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*/
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.globl rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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STORE a0, 0(a1)
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LOAD sp, 0(a2)
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move a0, a3
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call rt_cpus_lock_status_restore
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j rt_hw_context_switch_exit
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#endif
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.global rt_hw_context_switch_exit
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rt_hw_context_switch_exit:
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#ifdef RT_USING_SMP
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#ifdef RT_USING_SIGNALS
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mv a0, sp
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csrr t0, mhartid
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/* switch interrupt stack of current cpu */
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la sp, __stack_start__
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addi t1, t0, 1
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li t2, __STACKSIZE__
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mul t1, t1, t2
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add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
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call rt_signal_check
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mv sp, a0
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#endif
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#endif
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/* resw ra to mepc */
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LOAD a0, 0 * REGBYTES(sp)
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csrw SRC_XEPC, a0
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LOAD x1, 1 * REGBYTES(sp)
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#ifdef RISCV_S_MODE
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li t0, 0x00000120
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csrw sstatus, t0
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LOAD a0, 2 * REGBYTES(sp)
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csrs sstatus, a0
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#else
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li t0, 0x00007800
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csrw mstatus, t0
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LOAD a0, 2 * REGBYTES(sp)
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csrs mstatus, a0
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#endif
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LOAD x4, 4 * REGBYTES(sp)
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LOAD x5, 5 * REGBYTES(sp)
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LOAD x6, 6 * REGBYTES(sp)
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LOAD x7, 7 * REGBYTES(sp)
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LOAD x8, 8 * REGBYTES(sp)
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LOAD x9, 9 * REGBYTES(sp)
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LOAD x10, 10 * REGBYTES(sp)
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LOAD x11, 11 * REGBYTES(sp)
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LOAD x12, 12 * REGBYTES(sp)
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LOAD x13, 13 * REGBYTES(sp)
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LOAD x14, 14 * REGBYTES(sp)
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LOAD x15, 15 * REGBYTES(sp)
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LOAD x16, 16 * REGBYTES(sp)
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LOAD x17, 17 * REGBYTES(sp)
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LOAD x18, 18 * REGBYTES(sp)
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LOAD x19, 19 * REGBYTES(sp)
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LOAD x20, 20 * REGBYTES(sp)
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LOAD x21, 21 * REGBYTES(sp)
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LOAD x22, 22 * REGBYTES(sp)
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LOAD x23, 23 * REGBYTES(sp)
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LOAD x24, 24 * REGBYTES(sp)
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LOAD x25, 25 * REGBYTES(sp)
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LOAD x26, 26 * REGBYTES(sp)
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LOAD x27, 27 * REGBYTES(sp)
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LOAD x28, 28 * REGBYTES(sp)
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LOAD x29, 29 * REGBYTES(sp)
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LOAD x30, 30 * REGBYTES(sp)
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LOAD x31, 31 * REGBYTES(sp)
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addi sp, sp, 32 * REGBYTES
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#ifdef ARCH_RISCV_FPU
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FLOAD f0, 0 * FREGBYTES(sp)
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FLOAD f1, 1 * FREGBYTES(sp)
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FLOAD f2, 2 * FREGBYTES(sp)
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FLOAD f3, 3 * FREGBYTES(sp)
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FLOAD f4, 4 * FREGBYTES(sp)
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FLOAD f5, 5 * FREGBYTES(sp)
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FLOAD f6, 6 * FREGBYTES(sp)
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FLOAD f7, 7 * FREGBYTES(sp)
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FLOAD f8, 8 * FREGBYTES(sp)
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FLOAD f9, 9 * FREGBYTES(sp)
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FLOAD f10, 10 * FREGBYTES(sp)
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FLOAD f11, 11 * FREGBYTES(sp)
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FLOAD f12, 12 * FREGBYTES(sp)
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FLOAD f13, 13 * FREGBYTES(sp)
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FLOAD f14, 14 * FREGBYTES(sp)
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FLOAD f15, 15 * FREGBYTES(sp)
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FLOAD f16, 16 * FREGBYTES(sp)
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FLOAD f17, 17 * FREGBYTES(sp)
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FLOAD f18, 18 * FREGBYTES(sp)
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FLOAD f19, 19 * FREGBYTES(sp)
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FLOAD f20, 20 * FREGBYTES(sp)
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FLOAD f21, 21 * FREGBYTES(sp)
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FLOAD f22, 22 * FREGBYTES(sp)
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FLOAD f23, 23 * FREGBYTES(sp)
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FLOAD f24, 24 * FREGBYTES(sp)
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FLOAD f25, 25 * FREGBYTES(sp)
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FLOAD f26, 26 * FREGBYTES(sp)
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FLOAD f27, 27 * FREGBYTES(sp)
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FLOAD f28, 28 * FREGBYTES(sp)
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FLOAD f29, 29 * FREGBYTES(sp)
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FLOAD f30, 30 * FREGBYTES(sp)
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FLOAD f31, 31 * FREGBYTES(sp)
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addi sp, sp, 32 * FREGBYTES
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#endif
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XRET
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@@ -0,0 +1,123 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting code.
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* 2021-02-11 lizhirui add gp support
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*/
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#include <stddef.h>
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#include <rthw.h>
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#include <rtthread.h>
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#include "cpuport.h"
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#include "stack.h"
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/**
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* @brief from thread used interrupt context switch
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*
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*/
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volatile rt_ubase_t rt_interrupt_from_thread = 0;
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/**
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* @brief to thread used interrupt context switch
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*
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*/
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volatile rt_ubase_t rt_interrupt_to_thread = 0;
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/**
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* @brief flag to indicate context switch in interrupt or not
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*
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*/
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volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
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/**
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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rt_uint8_t *rt_hw_stack_init(void *tentry,
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void *parameter,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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struct rt_hw_stack_frame *frame;
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rt_uint8_t *stk;
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int i;
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extern int __global_pointer$;
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stk = stack_addr + sizeof(rt_ubase_t);
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stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
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stk -= sizeof(struct rt_hw_stack_frame);
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frame = (struct rt_hw_stack_frame *)stk;
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for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
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{
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((rt_ubase_t *)frame)[i] = 0xdeadbeef;
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}
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frame->ra = (rt_ubase_t)texit;
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frame->gp = (rt_ubase_t)&__global_pointer$;
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frame->a0 = (rt_ubase_t)parameter;
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frame->epc = (rt_ubase_t)tentry;
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frame->user_sp_exc_stack = (rt_ubase_t)(((rt_ubase_t)stk) + sizeof(struct rt_hw_stack_frame));
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||||
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#ifndef RISCV_S_MODE
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frame->xstatus = 0x00007880;
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#else
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frame->xstatus = 0x00040120;
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#endif
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return stk;
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}
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
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* #endif
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*/
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#ifndef RT_USING_SMP
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void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
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{
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||||
if (rt_thread_switch_interrupt_flag == 0)
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rt_interrupt_from_thread = from;
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||||
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||||
rt_interrupt_to_thread = to;
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||||
rt_thread_switch_interrupt_flag = 1;
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||||
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return ;
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||||
}
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||||
#endif /* end of RT_USING_SMP */
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||||
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||||
/** shutdown CPU */
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||||
void rt_hw_cpu_shutdown()
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||||
{
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||||
rt_uint32_t level;
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||||
rt_kprintf("shutdown...\n");
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||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
while (level)
|
||||
{
|
||||
RT_ASSERT(0);
|
||||
}
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||||
}
|
||||
|
||||
rt_thread_t rt_thread_sp_to_thread(void *spmember_addr)
|
||||
{
|
||||
return (rt_thread_t)(((rt_ubase_t)spmember_addr) - (offsetof(struct rt_thread,sp)));
|
||||
}
|
||||
|
||||
void *get_thread_kernel_stack_top(rt_thread_t thread)
|
||||
{
|
||||
return (void *)(((rt_size_t)thread -> stack_addr) + ((rt_size_t)thread -> stack_size));
|
||||
}
|
||||
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-03 Bernard The first version
|
||||
*/
|
||||
|
||||
#ifndef CPUPORT_H__
|
||||
#define CPUPORT_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
/* bytes of register width */
|
||||
#ifdef ARCH_CPU_64BIT
|
||||
#define STORE sd
|
||||
#define LOAD ld
|
||||
#define REGBYTES 8
|
||||
#else
|
||||
// error here, not portable
|
||||
#endif
|
||||
|
||||
#ifdef RISCV_U_MODE
|
||||
#define RISCV_USER_ENTRY 0xFFFFFFE000000000ULL
|
||||
#endif
|
||||
|
||||
#ifdef RISCV_S_MODE
|
||||
//csr in s-mode
|
||||
// M/U/S Interrupt Registers
|
||||
#define SRC_XIE sie
|
||||
#define SRC_XIP sip
|
||||
#define SRC_XTVEC stvec
|
||||
#define SRC_XSTATUS sstatus
|
||||
#define SRC_XSCRATCH sscratch
|
||||
#define SRC_XEPC sepc
|
||||
#define SRC_XCAUSE scause
|
||||
#define SRC_XTVAL stval
|
||||
#define XRET sret
|
||||
#else
|
||||
//csr in m-mode
|
||||
// M/U/S Interrupt Registers
|
||||
#define SRC_XIE mie
|
||||
#define SRC_XIP mip
|
||||
#define SRC_XTVEC mtvec
|
||||
#define SRC_XSTATUS mstatus
|
||||
#define SRC_XSCRATCH mscratch
|
||||
#define SRC_XEPC mepc
|
||||
#define SRC_XCAUSE mcause
|
||||
#define SRC_XTVAL mtval
|
||||
#define XRET mret
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,278 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/01 Bernard The first version
|
||||
* 2018/12/27 Jesven Change irq enable/disable to cpu0
|
||||
*/
|
||||
#include "tick.h"
|
||||
#include <plic.h>
|
||||
#include "encoding.h"
|
||||
#include "riscv.h"
|
||||
#include "interrupt.h"
|
||||
|
||||
#define MAX_HANDLERS 128
|
||||
|
||||
static struct rt_irq_desc irq_desc[MAX_HANDLERS];
|
||||
|
||||
static rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
|
||||
{
|
||||
rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector);
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
int rt_hw_clint_ipi_enable(void)
|
||||
{
|
||||
/* Set the Machine-Software bit in MIE */
|
||||
set_csr(mie, MIP_MSIP);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rt_hw_clint_ipi_disable(void)
|
||||
{
|
||||
/* Clear the Machine-Software bit in MIE */
|
||||
clear_csr(mie, MIP_MSIP);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rt_hw_plic_irq_enable(int irq_number)
|
||||
{
|
||||
plic_irq_enable(irq_number);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rt_hw_plic_irq_disable(int irq_number)
|
||||
{
|
||||
plic_irq_disable(irq_number);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
*/
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
int idx = 0;
|
||||
/* init exceptions table */
|
||||
for (idx = 0; idx < MAX_HANDLERS; idx++)
|
||||
{
|
||||
irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
|
||||
irq_desc[idx].param = RT_NULL;
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
|
||||
irq_desc[idx].counter = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
plic_set_threshold(0);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
rt_hw_plic_irq_disable(vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will un-mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
plic_set_priority(vector, 1);
|
||||
|
||||
rt_hw_plic_irq_enable(vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will install a interrupt service routine to a interrupt.
|
||||
* @param vector the interrupt number
|
||||
* @param new_handler the interrupt service routine to be installed
|
||||
* @param old_handler the old interrupt service routine
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
if(vector < MAX_HANDLERS)
|
||||
{
|
||||
old_handler = irq_desc[vector].handler;
|
||||
if (handler != RT_NULL)
|
||||
{
|
||||
irq_desc[vector].handler = (rt_isr_handler_t)handler;
|
||||
irq_desc[vector].param = param;
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
|
||||
irq_desc[vector].counter = 0;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
RT_WEAK
|
||||
void plic_irq_handle(int irq)
|
||||
{
|
||||
rt_kprintf("UN-handled interrupt %d occurred!!!\n", irq);
|
||||
return ;
|
||||
}
|
||||
|
||||
void dump_regs(struct rt_hw_stack_frame *regs)
|
||||
{
|
||||
rt_kprintf("--------------Dump Registers-----------------\n");
|
||||
|
||||
rt_kprintf("Function Registers:\n");
|
||||
rt_kprintf("\tra(x1) = 0x%p\tuser_sp = 0x%p\n",regs -> ra,regs -> user_sp_exc_stack);
|
||||
rt_kprintf("\tgp(x3) = 0x%p\ttp(x4) = 0x%p\n",regs -> gp,regs -> tp);
|
||||
rt_kprintf("Temporary Registers:\n");
|
||||
rt_kprintf("\tt0(x5) = 0x%p\tt1(x6) = 0x%p\n",regs -> t0,regs -> t1);
|
||||
rt_kprintf("\tt2(x7) = 0x%p\n",regs -> t2);
|
||||
rt_kprintf("\tt3(x28) = 0x%p\tt4(x29) = 0x%p\n",regs -> t3,regs -> t4);
|
||||
rt_kprintf("\tt5(x30) = 0x%p\tt6(x31) = 0x%p\n",regs -> t5,regs -> t6);
|
||||
rt_kprintf("Saved Registers:\n");
|
||||
rt_kprintf("\ts0/fp(x8) = 0x%p\ts1(x9) = 0x%p\n",regs -> s0_fp,regs -> s1);
|
||||
rt_kprintf("\ts2(x18) = 0x%p\ts3(x19) = 0x%p\n",regs -> s2,regs -> s3);
|
||||
rt_kprintf("\ts4(x20) = 0x%p\ts5(x21) = 0x%p\n",regs -> s4,regs -> s5);
|
||||
rt_kprintf("\ts6(x22) = 0x%p\ts7(x23) = 0x%p\n",regs -> s6,regs -> s7);
|
||||
rt_kprintf("\ts8(x24) = 0x%p\ts9(x25) = 0x%p\n",regs -> s8,regs -> s9);
|
||||
rt_kprintf("\ts10(x26) = 0x%p\ts11(x27) = 0x%p\n",regs -> s10,regs -> s11);
|
||||
rt_kprintf("Function Arguments Registers:\n");
|
||||
rt_kprintf("\ta0(x10) = 0x%p\ta1(x11) = 0x%p\n",regs -> a0,regs -> a1);
|
||||
rt_kprintf("\ta2(x12) = 0x%p\ta3(x13) = 0x%p\n",regs -> a2,regs -> a3);
|
||||
rt_kprintf("\ta4(x14) = 0x%p\ta5(x15) = 0x%p\n",regs -> a4,regs -> a5);
|
||||
rt_kprintf("\ta6(x16) = 0x%p\ta7(x17) = 0x%p\n",regs -> a6,regs -> a7);
|
||||
rt_kprintf("xstatus = 0x%p\n",regs -> xstatus);
|
||||
rt_kprintf("\t%s\n",(regs -> xstatus & SSTATUS_SIE) ? "Supervisor Interrupt Enabled" : "Supervisor Interrupt Disabled");
|
||||
rt_kprintf("\t%s\n",(regs -> xstatus & SSTATUS_SPIE) ? "Last Time Supervisor Interrupt Enabled" : "Last Time Supervisor Interrupt Disabled");
|
||||
rt_kprintf("\t%s\n",(regs -> xstatus & SSTATUS_SPP) ? "Last Privilege is Supervisor Mode" : "Last Privilege is User Mode");
|
||||
rt_kprintf("\t%s\n",(regs -> xstatus & SSTATUS_PUM) ? "Permit to Access User Page" : "Not Permit to Access User Page");
|
||||
rt_kprintf("\t%s\n",(regs -> xstatus & (1 << 19)) ? "Permit to Read Executable-only Page" : "Not Permit to Read Executable-only Page");
|
||||
rt_size_t satp_v = read_csr(satp);
|
||||
rt_kprintf("satp = 0x%p\n",satp_v);
|
||||
const char *mode_str = "Unknown Address Translation/Protection Mode";
|
||||
|
||||
switch(__MASKVALUE(satp_v >> 60,__MASK(4)))
|
||||
{
|
||||
case 0:
|
||||
mode_str = "No Address Translation/Protection Mode";
|
||||
break;
|
||||
|
||||
case 8:
|
||||
mode_str = "Page-based 39-bit Virtual Addressing Mode";
|
||||
break;
|
||||
|
||||
case 9:
|
||||
mode_str = "Page-based 48-bit Virtual Addressing Mode";
|
||||
break;
|
||||
}
|
||||
|
||||
rt_kprintf("\tMode = %s\n",mode_str);
|
||||
rt_kprintf("-----------------Dump OK---------------------\n");
|
||||
}
|
||||
|
||||
void handle_trap(rt_size_t xcause,rt_size_t xtval,rt_size_t xepc,struct rt_hw_stack_frame *sp)
|
||||
{
|
||||
int cause = (xcause & 0xFFFFFFFF);
|
||||
int plic_irq = 0;
|
||||
|
||||
if (xcause & (1UL << 63))
|
||||
{
|
||||
switch (cause)
|
||||
{
|
||||
case IRQ_M_SOFT:
|
||||
{
|
||||
|
||||
}
|
||||
break;
|
||||
case IRQ_M_TIMER:
|
||||
tick_isr();
|
||||
break;
|
||||
case IRQ_S_TIMER:
|
||||
tick_isr();
|
||||
break;
|
||||
|
||||
case IRQ_S_EXT:
|
||||
plic_irq = plic_claim();
|
||||
plic_complete(plic_irq);
|
||||
irq_desc[plic_irq].handler(plic_irq, irq_desc[plic_irq].param);
|
||||
break;
|
||||
|
||||
case IRQ_M_EXT:
|
||||
plic_irq = plic_claim();
|
||||
plic_complete(plic_irq);
|
||||
irq_desc[plic_irq].handler(plic_irq, irq_desc[plic_irq].param);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_thread_t tid;
|
||||
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
|
||||
extern long list_thread();
|
||||
#endif
|
||||
rt_hw_interrupt_disable();
|
||||
|
||||
rt_kprintf("xcause = %08x,xtval = %08x,xepc = %08x\n", xcause, xtval, xepc);
|
||||
tid = rt_thread_self();
|
||||
rt_kprintf("\nException:\n");
|
||||
switch (cause)
|
||||
{
|
||||
case CAUSE_MISALIGNED_FETCH:
|
||||
rt_kprintf("Instruction address misaligned");
|
||||
break;
|
||||
case CAUSE_FAULT_FETCH:
|
||||
rt_kprintf("Instruction access fault");
|
||||
break;
|
||||
case CAUSE_ILLEGAL_INSTRUCTION:
|
||||
rt_kprintf("Illegal instruction");
|
||||
break;
|
||||
case CAUSE_BREAKPOINT:
|
||||
rt_kprintf("Breakpoint");
|
||||
break;
|
||||
case CAUSE_MISALIGNED_LOAD:
|
||||
rt_kprintf("Load address misaligned");
|
||||
break;
|
||||
case CAUSE_FAULT_LOAD:
|
||||
rt_kprintf("Load access fault");
|
||||
break;
|
||||
case CAUSE_MISALIGNED_STORE:
|
||||
rt_kprintf("Store address misaligned");
|
||||
break;
|
||||
case CAUSE_FAULT_STORE:
|
||||
rt_kprintf("Store access fault");
|
||||
break;
|
||||
case CAUSE_USER_ECALL:
|
||||
rt_kprintf("Environment call from U-mode");
|
||||
break;
|
||||
case CAUSE_SUPERVISOR_ECALL:
|
||||
rt_kprintf("Environment call from S-mode");
|
||||
break;
|
||||
case CAUSE_HYPERVISOR_ECALL:
|
||||
rt_kprintf("Environment call from H-mode");
|
||||
break;
|
||||
case CAUSE_MACHINE_ECALL:
|
||||
rt_kprintf("Environment call from M-mode");
|
||||
break;
|
||||
default:
|
||||
rt_kprintf("Uknown exception : %08lX", cause);
|
||||
break;
|
||||
}
|
||||
rt_kprintf("\n");
|
||||
dump_regs(sp);
|
||||
rt_kprintf("exception pc => 0x%08x\n", xepc);
|
||||
rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, tid->name);
|
||||
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
|
||||
list_thread();
|
||||
#endif
|
||||
while(1);
|
||||
}
|
||||
rt_hw_interrupt_enable(0);
|
||||
}
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-05-20 bigmagic The first version
|
||||
*/
|
||||
|
||||
#ifndef INTERRUPT_H__
|
||||
#define INTERRUPT_H__
|
||||
|
||||
#include <rthw.h>
|
||||
#include "stack.h"
|
||||
|
||||
int rt_hw_clint_ipi_enable(void);
|
||||
int rt_hw_clint_ipi_disable(void);
|
||||
int rt_hw_plic_irq_enable(int irq_number);
|
||||
int rt_hw_plic_irq_disable(int irq_number);
|
||||
void rt_hw_interrupt_init(void);
|
||||
void rt_hw_interrupt_mask(int vector);
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name);
|
||||
void handle_trap(rt_size_t xcause,rt_size_t xtval,rt_size_t xepc,struct rt_hw_stack_frame *sp);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,151 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/02 Bernard The first version
|
||||
* 2018/12/27 Jesven Add SMP schedule
|
||||
* 2021/02/02 lizhirui Add userspace support
|
||||
*/
|
||||
|
||||
#include "cpuport.h"
|
||||
|
||||
.section .text.entry
|
||||
.align 2
|
||||
.global trap_entry
|
||||
trap_entry:
|
||||
#ifdef ARCH_RISCV_FPU
|
||||
addi sp, sp, -32 * FREGBYTES
|
||||
|
||||
FSTORE f0, 0 * FREGBYTES(sp)
|
||||
FSTORE f1, 1 * FREGBYTES(sp)
|
||||
FSTORE f2, 2 * FREGBYTES(sp)
|
||||
FSTORE f3, 3 * FREGBYTES(sp)
|
||||
FSTORE f4, 4 * FREGBYTES(sp)
|
||||
FSTORE f5, 5 * FREGBYTES(sp)
|
||||
FSTORE f6, 6 * FREGBYTES(sp)
|
||||
FSTORE f7, 7 * FREGBYTES(sp)
|
||||
FSTORE f8, 8 * FREGBYTES(sp)
|
||||
FSTORE f9, 9 * FREGBYTES(sp)
|
||||
FSTORE f10, 10 * FREGBYTES(sp)
|
||||
FSTORE f11, 11 * FREGBYTES(sp)
|
||||
FSTORE f12, 12 * FREGBYTES(sp)
|
||||
FSTORE f13, 13 * FREGBYTES(sp)
|
||||
FSTORE f14, 14 * FREGBYTES(sp)
|
||||
FSTORE f15, 15 * FREGBYTES(sp)
|
||||
FSTORE f16, 16 * FREGBYTES(sp)
|
||||
FSTORE f17, 17 * FREGBYTES(sp)
|
||||
FSTORE f18, 18 * FREGBYTES(sp)
|
||||
FSTORE f19, 19 * FREGBYTES(sp)
|
||||
FSTORE f20, 20 * FREGBYTES(sp)
|
||||
FSTORE f21, 21 * FREGBYTES(sp)
|
||||
FSTORE f22, 22 * FREGBYTES(sp)
|
||||
FSTORE f23, 23 * FREGBYTES(sp)
|
||||
FSTORE f24, 24 * FREGBYTES(sp)
|
||||
FSTORE f25, 25 * FREGBYTES(sp)
|
||||
FSTORE f26, 26 * FREGBYTES(sp)
|
||||
FSTORE f27, 27 * FREGBYTES(sp)
|
||||
FSTORE f28, 28 * FREGBYTES(sp)
|
||||
FSTORE f29, 29 * FREGBYTES(sp)
|
||||
FSTORE f30, 30 * FREGBYTES(sp)
|
||||
FSTORE f31, 31 * FREGBYTES(sp)
|
||||
|
||||
#endif
|
||||
|
||||
/* save thread context to thread stack */
|
||||
addi sp, sp, -32 * REGBYTES
|
||||
|
||||
STORE x1, 1 * REGBYTES(sp)
|
||||
|
||||
csrr x1, SRC_XSTATUS
|
||||
STORE x1, 2 * REGBYTES(sp)
|
||||
|
||||
csrr x1, SRC_XEPC
|
||||
STORE x1, 0 * REGBYTES(sp)
|
||||
|
||||
STORE x4, 4 * REGBYTES(sp)
|
||||
STORE x5, 5 * REGBYTES(sp)
|
||||
STORE x6, 6 * REGBYTES(sp)
|
||||
STORE x7, 7 * REGBYTES(sp)
|
||||
STORE x8, 8 * REGBYTES(sp)
|
||||
STORE x9, 9 * REGBYTES(sp)
|
||||
STORE x10, 10 * REGBYTES(sp)
|
||||
STORE x11, 11 * REGBYTES(sp)
|
||||
STORE x12, 12 * REGBYTES(sp)
|
||||
STORE x13, 13 * REGBYTES(sp)
|
||||
STORE x14, 14 * REGBYTES(sp)
|
||||
STORE x15, 15 * REGBYTES(sp)
|
||||
STORE x16, 16 * REGBYTES(sp)
|
||||
STORE x17, 17 * REGBYTES(sp)
|
||||
STORE x18, 18 * REGBYTES(sp)
|
||||
STORE x19, 19 * REGBYTES(sp)
|
||||
STORE x20, 20 * REGBYTES(sp)
|
||||
STORE x21, 21 * REGBYTES(sp)
|
||||
STORE x22, 22 * REGBYTES(sp)
|
||||
STORE x23, 23 * REGBYTES(sp)
|
||||
STORE x24, 24 * REGBYTES(sp)
|
||||
STORE x25, 25 * REGBYTES(sp)
|
||||
STORE x26, 26 * REGBYTES(sp)
|
||||
STORE x27, 27 * REGBYTES(sp)
|
||||
STORE x28, 28 * REGBYTES(sp)
|
||||
STORE x29, 29 * REGBYTES(sp)
|
||||
STORE x30, 30 * REGBYTES(sp)
|
||||
STORE x31, 31 * REGBYTES(sp)
|
||||
|
||||
/* switch to interrupt stack */
|
||||
move s0, sp
|
||||
|
||||
#ifndef RISCV_S_MODE
|
||||
/* get cpu id */
|
||||
csrr t0, mhartid
|
||||
#else
|
||||
li t0, 0
|
||||
#endif
|
||||
|
||||
/* switch interrupt stack of current cpu */
|
||||
la sp, __stack_start__
|
||||
addi t1, t0, 1
|
||||
li t2, __STACKSIZE__
|
||||
mul t1, t1, t2
|
||||
add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
|
||||
|
||||
/* handle interrupt */
|
||||
call rt_interrupt_enter
|
||||
csrr a0, SRC_XCAUSE
|
||||
csrr a1, SRC_XEPC
|
||||
mv a2, s0
|
||||
call handle_trap
|
||||
call rt_interrupt_leave
|
||||
|
||||
#ifdef RT_USING_SMP
|
||||
/* s0 --> sp */
|
||||
mv sp, s0
|
||||
mv a0, s0
|
||||
call rt_scheduler_do_irq_switch
|
||||
tail rt_hw_context_switch_exit
|
||||
|
||||
#else
|
||||
|
||||
/* switch to from_thread stack */
|
||||
move sp, s0
|
||||
|
||||
/* need to switch new thread */
|
||||
la s0, rt_thread_switch_interrupt_flag
|
||||
lw s2, 0(s0)
|
||||
beqz s2, spurious_interrupt
|
||||
sw zero, 0(s0)
|
||||
|
||||
la s0, rt_interrupt_from_thread
|
||||
LOAD s1, 0(s0)
|
||||
STORE sp, 0(s1)
|
||||
|
||||
la s0, rt_interrupt_to_thread
|
||||
LOAD s1, 0(s0)
|
||||
LOAD sp, 0(s1)
|
||||
|
||||
#endif
|
||||
|
||||
spurious_interrupt:
|
||||
tail rt_hw_context_switch_exit
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-01-30 lizhirui first version
|
||||
*/
|
||||
|
||||
#ifndef __RISCV_H__
|
||||
#define __RISCV_H__
|
||||
|
||||
#include <encoding.h>
|
||||
|
||||
#define __SIZE(bit) (1UL << (bit))
|
||||
#define __MASK(bit) (__SIZE(bit) - 1UL)
|
||||
#define __UMASK(bit) (~(__MASK(bit)))
|
||||
#define __MASKVALUE(value,maskvalue) ((value) & (maskvalue))
|
||||
#define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue)))
|
||||
#define __CHECKUPBOUND(value,bit_count) (!(((rt_size_t)value) & (~__MASK(bit_count))))
|
||||
#define __CHECKALIGN(value,start_bit) (!(((rt_size_t)value) & (__MASK(start_bit))))
|
||||
|
||||
#define __PARTBIT(value,start_bit,length) (((value) >> (start_bit)) & __MASK(length))
|
||||
|
||||
#define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit))
|
||||
#define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit))
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,137 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __RISCV_IO_H__
|
||||
#define __RISCV_IO_H__
|
||||
|
||||
static inline uint32_t __raw_hartid(void)
|
||||
{
|
||||
#ifdef RISCV_S_MODE
|
||||
extern int boot_hartid;
|
||||
return boot_hartid;
|
||||
#else
|
||||
uint32_t x;
|
||||
asm volatile("csrr %0, mhartid" : "=r" (x) );
|
||||
return x;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void __raw_writeb(rt_uint8_t val, volatile void *addr)
|
||||
{
|
||||
asm volatile("sb %0, 0(%1)"
|
||||
:
|
||||
: "r"(val), "r"(addr));
|
||||
}
|
||||
|
||||
static inline void __raw_writew(rt_uint16_t val, volatile void *addr)
|
||||
{
|
||||
asm volatile("sh %0, 0(%1)"
|
||||
:
|
||||
: "r"(val), "r"(addr));
|
||||
}
|
||||
|
||||
static inline void __raw_writel(rt_uint32_t val, volatile void *addr)
|
||||
{
|
||||
asm volatile("sw %0, 0(%1)"
|
||||
:
|
||||
: "r"(val), "r"(addr));
|
||||
}
|
||||
|
||||
#if __riscv_xlen != 32
|
||||
static inline void __raw_writeq(rt_uint64_t val, volatile void *addr)
|
||||
{
|
||||
asm volatile("sd %0, 0(%1)"
|
||||
:
|
||||
: "r"(val), "r"(addr));
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline rt_uint8_t __raw_readb(const volatile void *addr)
|
||||
{
|
||||
rt_uint8_t val;
|
||||
|
||||
asm volatile("lb %0, 0(%1)"
|
||||
: "=r"(val)
|
||||
: "r"(addr));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline rt_uint16_t __raw_readw(const volatile void *addr)
|
||||
{
|
||||
rt_uint16_t val;
|
||||
|
||||
asm volatile("lh %0, 0(%1)"
|
||||
: "=r"(val)
|
||||
: "r"(addr));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline rt_uint32_t __raw_readl(const volatile void *addr)
|
||||
{
|
||||
rt_uint32_t val;
|
||||
|
||||
asm volatile("lw %0, 0(%1)"
|
||||
: "=r"(val)
|
||||
: "r"(addr));
|
||||
return val;
|
||||
}
|
||||
|
||||
#if __riscv_xlen != 32
|
||||
static inline rt_uint64_t __raw_readq(const volatile void *addr)
|
||||
{
|
||||
rt_uint64_t val;
|
||||
|
||||
asm volatile("ld %0, 0(%1)"
|
||||
: "=r"(val)
|
||||
: "r"(addr));
|
||||
return val;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* FIXME: These are now the same as asm-generic */
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
#define __io_rbr() do {} while (0)
|
||||
#define __io_rar() do {} while (0)
|
||||
#define __io_rbw() do {} while (0)
|
||||
#define __io_raw() do {} while (0)
|
||||
|
||||
#define readb_relaxed(c) ({ rt_uint8_t __v; __io_rbr(); __v = __raw_readb(c); __io_rar(); __v; })
|
||||
#define readw_relaxed(c) ({ rt_uint16_t __v; __io_rbr(); __v = __raw_readw(c); __io_rar(); __v; })
|
||||
#define readl_relaxed(c) ({ rt_uint32_t __v; __io_rbr(); __v = __raw_readl(c); __io_rar(); __v; })
|
||||
|
||||
#define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); })
|
||||
#define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); })
|
||||
#define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); })
|
||||
|
||||
#if __riscv_xlen != 32
|
||||
#define readq_relaxed(c) ({ rt_uint64_t __v; __io_rbr(); __v = __raw_readq(c); __io_rar(); __v; })
|
||||
#define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); })
|
||||
#endif
|
||||
|
||||
#define __io_br() do {} while (0)
|
||||
#define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory");
|
||||
#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
|
||||
#define __io_aw() do {} while (0)
|
||||
|
||||
#define readb(c) ({ rt_uint8_t __v; __io_br(); __v = __raw_readb(c); __io_ar(); __v; })
|
||||
#define readw(c) ({ rt_uint16_t __v; __io_br(); __v = __raw_readw(c); __io_ar(); __v; })
|
||||
#define readl(c) ({ rt_uint32_t __v; __io_br(); __v = __raw_readl(c); __io_ar(); __v; })
|
||||
|
||||
#define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); })
|
||||
#define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); })
|
||||
#define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); })
|
||||
|
||||
#if __riscv_xlen != 32
|
||||
#define readq(c) ({ rt_uint64_t __v; __io_br(); __v = __raw_readq(c); __io_ar(); __v; })
|
||||
#define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); })
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-01-30 lizhirui first version
|
||||
*/
|
||||
|
||||
#ifndef __STACK_H__
|
||||
#define __STACK_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
struct rt_hw_stack_frame
|
||||
{
|
||||
rt_ubase_t epc; /* epc - epc - program counter */
|
||||
rt_ubase_t ra; /* x1 - ra - return address for jumps */
|
||||
rt_ubase_t xstatus; /* - supervisor/machine/user status register */
|
||||
rt_ubase_t gp; /* x3 - gp - global pointer */
|
||||
rt_ubase_t tp; /* x4 - tp - thread pointer */
|
||||
rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
|
||||
rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
|
||||
rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
|
||||
rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
|
||||
rt_ubase_t s1; /* x9 - s1 - saved register 1 */
|
||||
rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
|
||||
rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
|
||||
rt_ubase_t a2; /* x12 - a2 - function argument 2 */
|
||||
rt_ubase_t a3; /* x13 - a3 - function argument 3 */
|
||||
rt_ubase_t a4; /* x14 - a4 - function argument 4 */
|
||||
rt_ubase_t a5; /* x15 - a5 - function argument 5 */
|
||||
rt_ubase_t a6; /* x16 - a6 - function argument 6 */
|
||||
rt_ubase_t a7; /* x17 - s7 - function argument 7 */
|
||||
rt_ubase_t s2; /* x18 - s2 - saved register 2 */
|
||||
rt_ubase_t s3; /* x19 - s3 - saved register 3 */
|
||||
rt_ubase_t s4; /* x20 - s4 - saved register 4 */
|
||||
rt_ubase_t s5; /* x21 - s5 - saved register 5 */
|
||||
rt_ubase_t s6; /* x22 - s6 - saved register 6 */
|
||||
rt_ubase_t s7; /* x23 - s7 - saved register 7 */
|
||||
rt_ubase_t s8; /* x24 - s8 - saved register 8 */
|
||||
rt_ubase_t s9; /* x25 - s9 - saved register 9 */
|
||||
rt_ubase_t s10; /* x26 - s10 - saved register 10 */
|
||||
rt_ubase_t s11; /* x27 - s11 - saved register 11 */
|
||||
rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
|
||||
rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
|
||||
rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
|
||||
rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
|
||||
rt_ubase_t user_sp_exc_stack; /* sscratch - user mode sp/exception stack */
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-02-02 lizhirui first version
|
||||
* 2021-02-11 lizhirui fixed gp save/store bug
|
||||
*/
|
||||
|
||||
#ifndef __STACKFRAME_H__
|
||||
#define __STACKFRAME_H__
|
||||
|
||||
#include "cpuport.h"
|
||||
|
||||
.macro SAVE_ALL
|
||||
addi sp, sp, -33 * REGBYTES
|
||||
|
||||
STORE x1, 1 * REGBYTES(sp)
|
||||
|
||||
csrr x1, SRC_XSTATUS
|
||||
STORE x1, 2 * REGBYTES(sp)
|
||||
|
||||
csrr x1, SRC_XEPC
|
||||
STORE x1, 0 * REGBYTES(sp)
|
||||
|
||||
STORE x3, 3 * REGBYTES(sp)
|
||||
STORE x4, 4 * REGBYTES(sp)
|
||||
STORE x5, 5 * REGBYTES(sp)
|
||||
STORE x6, 6 * REGBYTES(sp)
|
||||
STORE x7, 7 * REGBYTES(sp)
|
||||
STORE x8, 8 * REGBYTES(sp)
|
||||
STORE x9, 9 * REGBYTES(sp)
|
||||
STORE x10, 10 * REGBYTES(sp)
|
||||
STORE x11, 11 * REGBYTES(sp)
|
||||
STORE x12, 12 * REGBYTES(sp)
|
||||
STORE x13, 13 * REGBYTES(sp)
|
||||
STORE x14, 14 * REGBYTES(sp)
|
||||
STORE x15, 15 * REGBYTES(sp)
|
||||
STORE x16, 16 * REGBYTES(sp)
|
||||
STORE x17, 17 * REGBYTES(sp)
|
||||
STORE x18, 18 * REGBYTES(sp)
|
||||
STORE x19, 19 * REGBYTES(sp)
|
||||
STORE x20, 20 * REGBYTES(sp)
|
||||
STORE x21, 21 * REGBYTES(sp)
|
||||
STORE x22, 22 * REGBYTES(sp)
|
||||
STORE x23, 23 * REGBYTES(sp)
|
||||
STORE x24, 24 * REGBYTES(sp)
|
||||
STORE x25, 25 * REGBYTES(sp)
|
||||
STORE x26, 26 * REGBYTES(sp)
|
||||
STORE x27, 27 * REGBYTES(sp)
|
||||
STORE x28, 28 * REGBYTES(sp)
|
||||
STORE x29, 29 * REGBYTES(sp)
|
||||
STORE x30, 30 * REGBYTES(sp)
|
||||
STORE x31, 31 * REGBYTES(sp)
|
||||
csrr t0, SRC_XSCRATCH
|
||||
STORE t0, 32 * REGBYTES(sp)
|
||||
.endm
|
||||
|
||||
.macro RESTORE_ALL_ONLY
|
||||
/* resw ra to sepc */
|
||||
LOAD x1, 0 * REGBYTES(sp)
|
||||
csrw SRC_XEPC, x1
|
||||
|
||||
LOAD x1, 2 * REGBYTES(sp)
|
||||
csrw SRC_XSTATUS, x1
|
||||
|
||||
LOAD x1, 1 * REGBYTES(sp)
|
||||
|
||||
LOAD x3, 3 * REGBYTES(sp)
|
||||
LOAD x4, 4 * REGBYTES(sp)
|
||||
LOAD x5, 5 * REGBYTES(sp)
|
||||
LOAD x6, 6 * REGBYTES(sp)
|
||||
LOAD x7, 7 * REGBYTES(sp)
|
||||
LOAD x8, 8 * REGBYTES(sp)
|
||||
LOAD x9, 9 * REGBYTES(sp)
|
||||
LOAD x10, 10 * REGBYTES(sp)
|
||||
LOAD x11, 11 * REGBYTES(sp)
|
||||
LOAD x12, 12 * REGBYTES(sp)
|
||||
LOAD x13, 13 * REGBYTES(sp)
|
||||
LOAD x14, 14 * REGBYTES(sp)
|
||||
LOAD x15, 15 * REGBYTES(sp)
|
||||
LOAD x16, 16 * REGBYTES(sp)
|
||||
LOAD x17, 17 * REGBYTES(sp)
|
||||
LOAD x18, 18 * REGBYTES(sp)
|
||||
LOAD x19, 19 * REGBYTES(sp)
|
||||
LOAD x20, 20 * REGBYTES(sp)
|
||||
LOAD x21, 21 * REGBYTES(sp)
|
||||
LOAD x22, 22 * REGBYTES(sp)
|
||||
LOAD x23, 23 * REGBYTES(sp)
|
||||
LOAD x24, 24 * REGBYTES(sp)
|
||||
LOAD x25, 25 * REGBYTES(sp)
|
||||
LOAD x26, 26 * REGBYTES(sp)
|
||||
LOAD x27, 27 * REGBYTES(sp)
|
||||
LOAD x28, 28 * REGBYTES(sp)
|
||||
LOAD x29, 29 * REGBYTES(sp)
|
||||
LOAD x30, 30 * REGBYTES(sp)
|
||||
LOAD x31, 31 * REGBYTES(sp)
|
||||
|
||||
addi sp, sp, 33 * REGBYTES
|
||||
.endm
|
||||
|
||||
.macro RESTORE_ALL
|
||||
/* resw ra to sepc */
|
||||
LOAD x1, 0 * REGBYTES(sp)
|
||||
csrw SRC_XEPC, x1
|
||||
|
||||
LOAD x1, 2 * REGBYTES(sp)
|
||||
csrw SRC_XSTATUS, x1
|
||||
|
||||
LOAD x1, 1 * REGBYTES(sp)
|
||||
|
||||
LOAD x3, 3 * REGBYTES(sp)
|
||||
LOAD x4, 4 * REGBYTES(sp)
|
||||
LOAD x5, 5 * REGBYTES(sp)
|
||||
LOAD x6, 6 * REGBYTES(sp)
|
||||
LOAD x7, 7 * REGBYTES(sp)
|
||||
LOAD x8, 8 * REGBYTES(sp)
|
||||
LOAD x9, 9 * REGBYTES(sp)
|
||||
LOAD x10, 10 * REGBYTES(sp)
|
||||
LOAD x11, 11 * REGBYTES(sp)
|
||||
LOAD x12, 12 * REGBYTES(sp)
|
||||
LOAD x13, 13 * REGBYTES(sp)
|
||||
LOAD x14, 14 * REGBYTES(sp)
|
||||
LOAD x15, 15 * REGBYTES(sp)
|
||||
LOAD x16, 16 * REGBYTES(sp)
|
||||
LOAD x17, 17 * REGBYTES(sp)
|
||||
LOAD x18, 18 * REGBYTES(sp)
|
||||
LOAD x19, 19 * REGBYTES(sp)
|
||||
LOAD x20, 20 * REGBYTES(sp)
|
||||
LOAD x21, 21 * REGBYTES(sp)
|
||||
LOAD x22, 22 * REGBYTES(sp)
|
||||
LOAD x23, 23 * REGBYTES(sp)
|
||||
LOAD x24, 24 * REGBYTES(sp)
|
||||
LOAD x25, 25 * REGBYTES(sp)
|
||||
LOAD x26, 26 * REGBYTES(sp)
|
||||
LOAD x27, 27 * REGBYTES(sp)
|
||||
LOAD x28, 28 * REGBYTES(sp)
|
||||
LOAD x29, 29 * REGBYTES(sp)
|
||||
LOAD x30, 30 * REGBYTES(sp)
|
||||
LOAD x31, 31 * REGBYTES(sp)
|
||||
|
||||
//restore user sp
|
||||
LOAD sp, 32 * REGBYTES(sp)
|
||||
.endm
|
||||
|
||||
.macro RESTORE_SYS_GP
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
.endm
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/01 Bernard The first version
|
||||
* 2018/12/27 Jesven Add SMP support
|
||||
* 2020/6/12 Xim Port to QEMU and remove SMP support
|
||||
*/
|
||||
|
||||
#define XSTATUS_FS (3 << 13) /* initial state of FPU, clear to disable */
|
||||
#define XSTATUS_PUM (1 << 18)
|
||||
#include <cpuport.h>
|
||||
|
||||
boot_hartid: .int
|
||||
.global boot_hartid
|
||||
|
||||
.global _start
|
||||
.section ".start", "ax"
|
||||
_start:
|
||||
#ifdef RISCV_S_MODE
|
||||
# save hartid
|
||||
la t0, boot_hartid # global varible rt_boot_hartid
|
||||
mv t1, a0 # get hartid in S-mode frome a0 register
|
||||
sw t1, (t0) # store t1 register low 4 bits in memory address which is stored in t0
|
||||
#else
|
||||
# setup stacks per hart
|
||||
csrr t0, mhartid # read current hart id
|
||||
slli t0, t0, 10 # shift left the hart id by 1024
|
||||
|
||||
# park harts with id != 0
|
||||
csrr a0, mhartid # read current hart id
|
||||
bnez a0, park # if we're not on the hart 0
|
||||
#endif
|
||||
|
||||
csrw SRC_XIE, 0 # clear Interrupt Registers
|
||||
csrw SRC_XIP, 0
|
||||
|
||||
la t0, trap_entry
|
||||
csrw SRC_XTVEC, t0 # set Trap Vector Base Address Register
|
||||
|
||||
/* set to disable FPU */
|
||||
li t0, XSTATUS_FS # close fpu
|
||||
csrc SRC_XSTATUS, t0
|
||||
#ifdef RISCV_S_MODE
|
||||
li t0, XSTATUS_PUM # PUM has no effect
|
||||
csrs SRC_XSTATUS, t0
|
||||
#endif
|
||||
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
|
||||
la sp, __stack_start__
|
||||
li t0, __STACKSIZE__
|
||||
add sp, sp, t0
|
||||
csrw SRC_XSCRATCH, sp
|
||||
j primary_cpu_entry
|
||||
|
||||
park:
|
||||
wfi
|
||||
j park
|
||||
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/28 Bernard The unify RISC-V porting code.
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "sbi.h"
|
||||
#include "tick.h"
|
||||
#include <riscv_io.h>
|
||||
#include <encoding.h>
|
||||
|
||||
#define VIRT_CLINT_TIMEBASE_FREQ (10000000)
|
||||
|
||||
static volatile uint64_t time_elapsed = 0;
|
||||
static volatile unsigned long tick_cycles = 0;
|
||||
|
||||
static uint64_t get_ticks()
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"rdtime %0"
|
||||
: "=r"(time_elapsed));
|
||||
return time_elapsed;
|
||||
}
|
||||
|
||||
int tick_isr(void)
|
||||
{
|
||||
int tick_cycles = VIRT_CLINT_TIMEBASE_FREQ / RT_TICK_PER_SECOND;
|
||||
rt_tick_increase();
|
||||
#ifdef RISCV_S_MODE
|
||||
sbi_set_timer(get_ticks() + tick_cycles);
|
||||
#else
|
||||
*(uint64_t*)CLINT_MTIMECMP(__raw_hartid()) = *(uint64_t*)CLINT_MTIME + tick_cycles;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Sets and enable the timer interrupt */
|
||||
int rt_hw_tick_init(void)
|
||||
{
|
||||
unsigned long interval = VIRT_CLINT_TIMEBASE_FREQ / RT_TICK_PER_SECOND;
|
||||
|
||||
#ifdef RISCV_S_MODE
|
||||
/* Clear the Supervisor-Timer bit in SIE */
|
||||
clear_csr(sie, SIP_STIP);
|
||||
|
||||
/* calculate the tick cycles */
|
||||
// tick_cycles = interval * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV / 1000ULL - 1;
|
||||
tick_cycles = 40000;
|
||||
/* Set timer */
|
||||
sbi_set_timer(get_ticks() + tick_cycles);
|
||||
|
||||
/* Enable the Supervisor-Timer bit in SIE */
|
||||
set_csr(sie, SIP_STIP);
|
||||
#else
|
||||
clear_csr(mie, MIP_MTIP);
|
||||
clear_csr(mip, MIP_MTIP);
|
||||
*(uint64_t*)CLINT_MTIMECMP(__raw_hartid()) = *(uint64_t*)CLINT_MTIME + interval;
|
||||
set_csr(mie, MIP_MTIP);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/28 Bernard The unify RISC-V porting code.
|
||||
*/
|
||||
|
||||
#ifndef TICK_H__
|
||||
#define TICK_H__
|
||||
|
||||
//ask the CLINT for a timer interrupt.
|
||||
#define CLINT (0x2000000L)
|
||||
#define CLINT_MTIMECMP(hartid) (CLINT + 0x4000 + 4*(hartid))
|
||||
#define CLINT_MTIME (CLINT + 0xBFF8) // cycles since boot.
|
||||
|
||||
int tick_isr(void);
|
||||
int rt_hw_tick_init(void);
|
||||
|
||||
#endif
|
||||
Reference in new issue
Block a user