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sc committed 2026-01-14 01:13:22 +08:00
1 parent b185a8ec12
commit 115d1d12c3
22 files changed
+3619 -1829
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.cproject
+1534 -1534
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.project
+1 -1
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@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>project</name>
<name>828F</name>
<comment />
<projects>
</projects>
applications/drv/memheap_alloc_align.c
+59
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@@ -0,0 +1,59 @@
#include <rtthread.h>
#include <rthw.h>
/**
* @brief Allocate aligned memory from a memheap
*
* @param heap Pointer to the memheap object
* @param size Requested user memory size (in bytes)
* @param align Alignment boundary (must be power of 2, e.g., 4, 8, 16)
* @return void* Aligned pointer on success, RT_NULL on failure
*
* @note The returned pointer must be freed with rt_memheap_free_align()
*/
void *rt_memheap_alloc_align(struct rt_memheap *heap, rt_size_t size, rt_size_t align)
{
void *raw_ptr;
void *aligned_ptr;
uintptr_t *header; // stores raw_ptr for free
RT_ASSERT(heap != RT_NULL);
RT_ASSERT(size > 0);
RT_ASSERT(align > 0 && (align & (align - 1)) == 0); // check power of 2
// Minimum space: user data + alignment padding + hidden header (sizeof(uintptr_t))
rt_size_t total_size = size + align - 1 + sizeof(uintptr_t);
raw_ptr = rt_memheap_alloc(heap, total_size);
if (raw_ptr == RT_NULL)
return RT_NULL;
// Calculate aligned address after hidden header
uintptr_t addr = (uintptr_t)raw_ptr + sizeof(uintptr_t);
aligned_ptr = (void *)((addr + align - 1) & ~(align - 1));
// Store raw_ptr just before aligned_ptr (in the hidden header)
header = (uintptr_t *)aligned_ptr - 1;
*header = (uintptr_t)raw_ptr;
return aligned_ptr;
}
/**
* @brief Free memory allocated by rt_memheap_alloc_align()
*
* @param heap Pointer to the memheap object
* @param ptr Pointer returned by rt_memheap_alloc_align()
*/
void rt_memheap_free_align(struct rt_memheap *heap, void *ptr)
{
if (ptr == RT_NULL)
return;
// Retrieve raw_ptr from hidden header
uintptr_t *header = (uintptr_t *)ptr - 1;
void *raw_ptr = (void *)(*header);
rt_memheap_free(raw_ptr);
}
applications/lvgl/guider/generated/gui_guider.h
+4 -3
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@@ -327,8 +327,7 @@ typedef struct
lv_obj_t *screen_do64;
lv_obj_t *screen_do65;
lv_obj_t *screen_do66;
lv_obj_t *screen_do67;
lv_obj_t *screen_name_do0;
lv_obj_t *screen_name_do0;
lv_obj_t *screen_name_do1;
lv_obj_t *screen_name_do2;
lv_obj_t *screen_name_do3;
@@ -337,7 +336,7 @@ typedef struct
lv_obj_t *screen_name_do6;
lv_obj_t *screen_name_do7;
lv_obj_t *screen_name_do8;
lv_obj_t *screen_name_do9;
lv_obj_t *screen_name_do09;
lv_obj_t *screen_name_do10;
lv_obj_t *screen_name_do11;
lv_obj_t *screen_name_do12;
@@ -418,6 +417,7 @@ typedef struct
lv_obj_t *screen_sys_name;
lv_obj_t *screen_machine_id;
lv_obj_t *screen_sys_id;
lv_obj_t *screen_sys_var;
lv_obj_t *g_kb_top_layer;
}lv_ui;
@@ -462,6 +462,7 @@ LV_FONT_DECLARE(lv_font_Alatsi_Regular_20)
LV_FONT_DECLARE(lv_font_simsun_21)
LV_FONT_DECLARE(lv_font_Acme_Regular_16)
LV_FONT_DECLARE(lv_font_Alatsi_Regular_18)
LV_FONT_DECLARE(lv_font_simsun_14)
LV_FONT_DECLARE(lv_font_montserratMedium_14)
LV_FONT_DECLARE(lv_font_simsun_32)
LV_FONT_DECLARE(lv_font_montserratMedium_30)
applications/lvgl/guider/generated/guider_fonts/lv_font_simsun_14.c
+1677
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applications/lvgl/guider/generated/setup_scr_screen.c
+221 -193
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applications/lvgl/lv__user_gui.c
+4 -1
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@@ -287,7 +287,7 @@ void ui_init_dio_leds(lv_ui *ui) {
do_name_array[6] = ui->screen_name_do6;
do_name_array[7] = ui->screen_name_do7;
do_name_array[8] = ui->screen_name_do8;
do_name_array[9] = ui->screen_name_do9;
do_name_array[9] = ui->screen_name_do09;
do_name_array[10] = ui->screen_name_do10;
do_name_array[11] = ui->screen_name_do11;
do_name_array[12] = ui->screen_name_do12;
@@ -357,6 +357,9 @@ void setup_user_screen(lv_ui *ui)
//lv_label_set_text(di_name_array[0], lang_get_str(0));
//lv_label_set_text(di_name_array[i], lang_get_str(di_table[i].name));
//lv_label_set_text(di_name_array[i], lang_get_str(di_table[i].name));
for (int i = 0; i < DI_TABLE_SIZE; i++)
{
applications/lvgl/lv_port_disp.c
+58 -18
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@@ -30,7 +30,9 @@
/**********************
* TYPEDEFS
**********************/
#define DBG_TAG "LVGLd"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
/**********************
* STATIC PROTOTYPES
**********************/
@@ -47,7 +49,15 @@ static void disp_flush(lv_disp_drv_t * disp_drv, const lv_area_t * area, lv_colo
/**********************
* MACROS
**********************/
static lv_disp_draw_buf_t draw_buf_dsc_1;
static lv_disp_draw_buf_t draw_buf_dsc_2;
static lv_disp_draw_buf_t draw_buf_dsc_3;
static lv_color_t *buf_1 = RT_NULL;
static lv_color_t *buf_2_1 = RT_NULL;
static lv_color_t *buf_2_2 = RT_NULL;
static lv_color_t *buf_3_1 = RT_NULL;
static lv_color_t *buf_3_2 = RT_NULL;
/**********************
* GLOBAL FUNCTIONS
**********************/
@@ -85,35 +95,65 @@ void lv_port_disp_init(void)
*/
/* Example for 1) */
static lv_disp_draw_buf_t draw_buf_dsc_1 __attribute__((aligned(4)));
static lv_color_t *buf_1 __attribute__((aligned(4))) = RT_NULL;
//static lv_disp_draw_buf_t draw_buf_dsc_1 __attribute__((aligned(8)));
//static lv_color_t *buf_1 __attribute__((aligned(8))) = RT_NULL;
//static lv_color_t buf_1[MY_DISP_HOR_RES * 10] __attribute__((section(".sdram"))); /*A buffer for 10 rows*/
buf_1 = (lv_color_t *)rt_memheap_alloc(&sdram_heap, sizeof(lv_color_t) * MY_DISP_HOR_RES * 10);
//buf_1 = (lv_color_t *)rt_memheap_alloc(&sdram_heap, sizeof(lv_color_t) * MY_DISP_HOR_RES * 10);
lv_disp_draw_buf_init(&draw_buf_dsc_1, buf_1, NULL, MY_DISP_HOR_RES * 10); /*Initialize the display buffer*/
//lv_disp_draw_buf_init(&draw_buf_dsc_1, buf_1, NULL, MY_DISP_HOR_RES * 10); /*Initialize the display buffer*/
/* Example for 2) */
static lv_disp_draw_buf_t draw_buf_dsc_2 __attribute__((aligned(4)));
static lv_color_t *buf_2_1 __attribute__((aligned(4)))= RT_NULL;
static lv_color_t *buf_2_2 __attribute__((aligned(4)))= RT_NULL;
//static lv_disp_draw_buf_t draw_buf_dsc_2 __attribute__((aligned(8)));
//static lv_color_t *buf_2_1 __attribute__((aligned(8)))= RT_NULL;
//static lv_color_t *buf_2_2 __attribute__((aligned(8)))= RT_NULL;
//static lv_color_t buf_2_1[MY_DISP_HOR_RES * 10] __attribute__((section(".sdram"))); /*A buffer for 10 rows*/
//static lv_color_t buf_2_2[MY_DISP_HOR_RES * 10] __attribute__((section(".sdram"))); /*An other buffer for 10 rows*/
buf_2_1 = (lv_color_t *)rt_memheap_alloc(&sdram_heap, sizeof(lv_color_t) * MY_DISP_HOR_RES * 10);
buf_2_2 = (lv_color_t *)rt_memheap_alloc(&sdram_heap, sizeof(lv_color_t) * MY_DISP_HOR_RES * 10);
//buf_2_1 = (lv_color_t *)rt_memheap_alloc(&sdram_heap, sizeof(lv_color_t) * MY_DISP_HOR_RES * 10);
//buf_2_2 = (lv_color_t *)rt_memheap_alloc(&sdram_heap, sizeof(lv_color_t) * MY_DISP_HOR_RES * 10);
lv_disp_draw_buf_init(&draw_buf_dsc_2, buf_2_1, buf_2_2, MY_DISP_HOR_RES * 10); /*Initialize the display buffer*/
//lv_disp_draw_buf_init(&draw_buf_dsc_2, buf_2_1, buf_2_2, MY_DISP_HOR_RES * 10); /*Initialize the display buffer*/
/* Example for 3) also set disp_drv.full_refresh = 1 below*/
static lv_disp_draw_buf_t draw_buf_dsc_3 __attribute__((aligned(4)));
static lv_color_t *buf_3_1 __attribute__((aligned(4)))= RT_NULL;
static lv_color_t *buf_3_2 __attribute__((aligned(4)))= RT_NULL;
//static lv_disp_draw_buf_t draw_buf_dsc_3 __attribute__((aligned(8)));
//static lv_color_t *buf_3_1 __attribute__((aligned(8)))= RT_NULL;
//static lv_color_t *buf_3_2 __attribute__((aligned(8)))= RT_NULL;
//static lv_color_t buf_3_1[MY_DISP_HOR_RES * MY_DISP_VER_RES] __attribute__((section(".sdram"))); /*A screen sized buffer*/
//static lv_color_t buf_3_2[MY_DISP_HOR_RES * MY_DISP_VER_RES] __attribute__((section(".sdram"))); /*Another screen sized buffer*/
buf_3_1 = (lv_color_t *)rt_memheap_alloc(&sdram_heap, sizeof(lv_color_t) * MY_DISP_VER_RES * 10);
buf_3_2 = (lv_color_t *)rt_memheap_alloc(&sdram_heap, sizeof(lv_color_t) * MY_DISP_VER_RES * 10);
//buf_3_1 = (lv_color_t *)rt_memheap_alloc(&sdram_heap, sizeof(lv_color_t) * MY_DISP_VER_RES * 10);
//buf_3_2 = (lv_color_t *)rt_memheap_alloc(&sdram_heap, sizeof(lv_color_t) * MY_DISP_VER_RES * 10);
lv_disp_draw_buf_init(&draw_buf_dsc_3, buf_3_1, buf_3_2, MY_DISP_HOR_RES * MY_DISP_VER_RES ); /*Initialize the display buffer*/
//lv_disp_draw_buf_init(&draw_buf_dsc_3, buf_3_1, buf_3_2, MY_DISP_HOR_RES * MY_DISP_VER_RES ); /*Initialize the display buffer*/
// 使用对齐分配函数
buf_1 = (lv_color_t *)rt_memheap_alloc_align(&sdram_heap,
sizeof(lv_color_t) * MY_DISP_HOR_RES * 10,
4); // ← 关键：对齐到 4 字节
buf_2_1 = (lv_color_t *)rt_memheap_alloc_align(&sdram_heap,
sizeof(lv_color_t) * MY_DISP_HOR_RES * 10,
4);
buf_2_2 = (lv_color_t *)rt_memheap_alloc_align(&sdram_heap,
sizeof(lv_color_t) * MY_DISP_HOR_RES * 10,
4);
buf_3_1 = (lv_color_t *)rt_memheap_alloc_align(&sdram_heap,
sizeof(lv_color_t) * MY_DISP_HOR_RES * MY_DISP_VER_RES,
4);
buf_3_2 = (lv_color_t *)rt_memheap_alloc_align(&sdram_heap,
sizeof(lv_color_t) * MY_DISP_HOR_RES * MY_DISP_VER_RES,
4);
if (!buf_1 || !buf_2_1 || !buf_2_2 || !buf_3_1 || !buf_3_2) {
LOG_E("Failed to alloc aligned draw buffers");
}
// 初始化 draw buffer
lv_disp_draw_buf_init(&draw_buf_dsc_1, buf_1, NULL, MY_DISP_HOR_RES * 10);
lv_disp_draw_buf_init(&draw_buf_dsc_2, buf_2_1, buf_2_2, MY_DISP_HOR_RES * 10);
lv_disp_draw_buf_init(&draw_buf_dsc_3, buf_3_1, buf_3_2, MY_DISP_HOR_RES * MY_DISP_VER_RES);
/*-----------------------------------
* Register the display in LVGL
*----------------------------------*/
@@ -131,7 +171,7 @@ void lv_port_disp_init(void)
disp_drv.flush_cb = disp_flush;
/*Set a display buffer*/
disp_drv.draw_buf = &draw_buf_dsc_1;
disp_drv.draw_buf = &draw_buf_dsc_2;
/*Required for Example 3)*/
//disp_drv.full_refresh = 1;
applications/main.c
+1
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@@ -18,6 +18,7 @@
#include <rtdbg.h>
extern rt_sem_t mount_sem; // 引用上面SD挂载线程定义的信号量
extern struct rt_memheap sram_DTCMRAM,sram_AXIRAM,sram_SRAM1,sram_SRAM2;
int main(void)
{
applications/sql/DB_SQLite.c
+2 -2
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@@ -293,8 +293,8 @@ static void db_sqlite(void *parameter) {
}
continue;
}else{
if(op_link>1000)
{//连续操作数据库1000次后强制关闭防止内存占用
if(op_link>255)
{//连续操作数据库255次后强制关闭防止内存占用
sqlite3_close(g_db);
g_db=RT_NULL;
op_link=0;
applications/wdt.c
+1 -1
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@@ -69,4 +69,4 @@ static int wdt_sample()
return ret;
}
INIT_APP_EXPORT(wdt_sample);
//INIT_APP_EXPORT(wdt_sample);
cubemx/Src/main.c
+2 -36
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@@ -797,49 +797,15 @@ void MPU_Config(void)
MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
MPU_InitStruct.SubRegionDisable = 0x0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Number = MPU_REGION_NUMBER1;
MPU_InitStruct.BaseAddress = 0x30000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Number = MPU_REGION_NUMBER2;
MPU_InitStruct.BaseAddress = 0x30020000;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Number = MPU_REGION_NUMBER4;
MPU_InitStruct.BaseAddress = 0x30040000;
MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Number = MPU_REGION_NUMBER5;
MPU_InitStruct.BaseAddress = 0xC0000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_32MB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* Enables the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
HAL_MPU_Enable(MPU_HFNMI_PRIVDEF);
}
cubemx/Src/stm32h7xx_hal_msp.c
-1
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@@ -127,7 +127,6 @@ void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
* @param hltdc: LTDC handle pointer
* @retval None
*/
/**
* @brief LTDC MSP De-Initialization
* This function freeze the hardware resources used in this example
cubemx/cubemx.ioc
+7 -24
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@@ -2,38 +2,21 @@
CAD.formats=
CAD.pinconfig=
CAD.provider=
CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_FULL_ACCESS
CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_FULL_ACCESS
CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=MPU_REGION_FULL_ACCESS
CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=0x30000000
CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=0x30020000
CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=0x30040000
CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=0xC0000000
CORTEX_M7.AccessPermission_Spec=MPU_REGION_FULL_ACCESS
CORTEX_M7.BaseAddress_Spec=0x24000000
CORTEX_M7.CPU_DCache=Enabled
CORTEX_M7.CPU_ICache=Enabled
CORTEX_M7.DisableExec_Spec=MPU_INSTRUCTION_ACCESS_ENABLE
CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_ENABLE
CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_ENABLE
CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=__NULL
CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=__NULL
CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=__NULL
CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_REGION_ENABLE
CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=MPU_REGION_ENABLE
CORTEX_M7.IPParameters=default_mode_Activation,CPU_ICache,CPU_DCache,Size_Spec,BaseAddress_Spec,DisableExec_Spec,IsCacheable_Spec,IsBufferable_Spec,IsShareable_Spec,SubRegionDisable_Spec,Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region5_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region5_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region5_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S
CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_ACCESS_BUFFERABLE
CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_BUFFERABLE
CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_ACCESS_BUFFERABLE
CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=MPU_ACCESS_BUFFERABLE
CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=__NULL
CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=__NULL
CORTEX_M7.IPParameters=default_mode_Activation,CPU_ICache,CPU_DCache,Size_Spec,BaseAddress_Spec,DisableExec_Spec,IsCacheable_Spec,IsBufferable_Spec,IsShareable_Spec,SubRegionDisable_Spec,Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S,MPU_Control,AccessPermission_Spec
CORTEX_M7.IsBufferable_Spec=MPU_ACCESS_BUFFERABLE
CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_ACCESS_CACHEABLE
CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_CACHEABLE
CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_ACCESS_CACHEABLE
CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=MPU_ACCESS_CACHEABLE
CORTEX_M7.IsCacheable_Spec=MPU_ACCESS_CACHEABLE
CORTEX_M7.IsShareable_Spec=MPU_ACCESS_NOT_SHAREABLE
CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_SIZE_128KB
CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_SIZE_128KB
CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_REGION_SIZE_32KB
CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=MPU_REGION_SIZE_32MB
CORTEX_M7.MPU_Control=MPU_HFNMI_PRIVDEF
CORTEX_M7.Size_Spec=MPU_REGION_SIZE_512KB
CORTEX_M7.SubRegionDisable_Spec=0x0
CORTEX_M7.default_mode_Activation=1
drivers/board.c
+1 -1
View File
@@ -31,7 +31,7 @@ rt_weak void rt_hw_board_init()
rt_memheap_init(&sram_DTCMRAM, "DTCMRAM", (void *)DTCMRAM_START, DTCMRAM_SIZE);
//rt_memheap_init(&sram_AXIRAM, "AXIRAM", (void *)AXIRAM_START, AXIRAM_SIZE);
rt_memheap_init(&sram_SRAM1, "SRAM1", (void *)SRAM1_START, SRAM1_SIZE);
//rt_memheap_init(&sram_SRAM2, "SRAM2", (void *)SRAM2_START, SRAM2_SIZE);
rt_memheap_init(&sram_SRAM2, "SRAM2", (void *)SRAM2_START, SRAM2_SIZE);
hw_board_init(BSP_CLOCK_SOURCE, BSP_CLOCK_SOURCE_FREQ_MHZ, BSP_CLOCK_SYSTEM_FREQ_MHZ);
drivers/board.h
+4 -4
View File
@@ -46,12 +46,12 @@ extern "C"
#define DTCMRAM_END (DTCMRAM_START + DTCMRAM_SIZE)
#define SRAM1_START (0x30000000)
#define SRAM1_SIZE (288*1024)
#define SRAM1_SIZE (128*1024)
#define SRAM1_END (SRAM1_START + SRAM1_SIZE)
//#define SRAM2_START (0x30020000)
//#define SRAM2_SIZE (128*1024)
//#define SRAM2_END (SRAM2_START + SRAM2_SIZE)
#define SRAM2_START (0x30020000)
#define SRAM2_SIZE ((128+32)*1024)
#define SRAM2_END (SRAM2_START + SRAM2_SIZE)
//#define SRAM3_START (0x30040000)
//#define SRAM3_SIZE (32*1024)
linkscripts/STM32H743IITx/link.lds
+26 -1
View File
@@ -8,8 +8,9 @@ MEMORY
ROM (rx) : ORIGIN =0x08000000,LENGTH =2048k
TDCMRAM (rw) : ORIGIN =0x20000000,LENGTH =128k
RAM (rw) : ORIGIN =0x24000000,LENGTH =512k
SRAM (rw) : ORIGIN =0x30000000,LENGTH =288k
SRAM1 (rw) : ORIGIN =0x30000000,LENGTH =128k
SDRAM (rw) : ORIGIN =0xC0000000,LENGTH =32768k
SRAM2 (rw) : ORIGIN =0x30020000,LENGTH =160k
}
ENTRY(Reset_Handler)
_system_stack_size = 0x400;
@@ -94,6 +95,30 @@ SECTIONS
. = ALIGN(4);
} > SDRAM
.sram1(NOLOAD):
{
. = ALIGN(4);
_ssram1 = .;
*(.sram1)
*(.sram1.*)
. = ALIGN(4);
_esram1 = .;
} > SRAM1
.sram2(NOLOAD):
{
. = ALIGN(4);
_ssram2 = .;
*(.sram2)
*(.sram2.*)
. = ALIGN(4);
_esram2 = .;
} > SRAM2
.tdcmram(NOLOAD):
{
. = ALIGN(4);
packages/LVGL-v8.3.10/env_support/rt-thread/lv_rt_thread_port.c
Vendored
+5 -1
View File
@@ -64,12 +64,16 @@ static void lvgl_thread_entry(void *parameter)
}
}
extern struct rt_memheap sram_DTCMRAM;
static void *lvgl_stack_ __attribute__((aligned(8)))= RT_NULL ;
static int lvgl_thread_init(void)
{
rt_err_t err;
lvgl_stack_ = rt_memheap_alloc(&sram_DTCMRAM, sizeof(lvgl_thread_stack));
err = rt_thread_init(&lvgl_thread, "LVGL", lvgl_thread_entry, RT_NULL,
&lvgl_thread_stack[0], sizeof(lvgl_thread_stack), PKG_LVGL_THREAD_PRIO, 20);
lvgl_stack_, sizeof(lvgl_thread_stack), PKG_LVGL_THREAD_PRIO, 20);
if(err != RT_EOK)
{
LOG_E("Failed to create LVGL thread");
packages/LVGL-v8.3.10/lvgl.h
Vendored
+1
View File
@@ -18,6 +18,7 @@ extern "C" {
#define LVGL_VERSION_PATCH 10
#define LVGL_VERSION_INFO ""
/*********************
* INCLUDES
*********************/
packages/LVGL-v8.3.10/src/lv_conf_internal.h
Vendored
+1 -1
View File
@@ -2141,7 +2141,7 @@
#ifdef CONFIG_LV_USE_QRCODE
#define LV_USE_QRCODE CONFIG_LV_USE_QRCODE
#else
#define LV_USE_QRCODE 0
#define LV_USE_QRCODE 1
#endif
#endif
packages/sqlite/sqlite3.c
+7 -7
View File
@@ -20727,13 +20727,13 @@ static malloc_zone_t* _sqliteZone_;
** Use standard C library malloc and free on non-Apple systems.
** Also used by rt-thread systems if SQLITE_WITHOUT_ZONEMALLOC is defined.
*/
extern struct rt_memheap sdram_heap,sram_SRAM1,sram_DTCMRAM;
//#define SQLITE_MALLOC(x) rt_memheap_alloc(&sram_SRAM1,(rt_size_t)x)
//#define SQLITE_FREE(x) rt_memheap_free(x)
//#define SQLITE_REALLOC(x,y) rt_memheap_realloc(&sram_SRAM1,(x),(rt_size_t)(y))
#define SQLITE_MALLOC(x) rt_malloc((rt_size_t)x)
#define SQLITE_FREE(x) rt_free(x)
#define SQLITE_REALLOC(x,y) rt_realloc((x),(rt_size_t)(y))
extern struct rt_memheap sram_DTCMRAM;
#define SQLITE_MALLOC(x) rt_memheap_alloc(&sram_DTCMRAM,(rt_size_t)x)
#define SQLITE_FREE(x) rt_memheap_free(x)
#define SQLITE_REALLOC(x,y) rt_memheap_realloc(&sram_DTCMRAM,(x),(rt_size_t)(y))
//#define SQLITE_MALLOC(x) rt_malloc((rt_size_t)x)
//#define SQLITE_FREE(x) rt_free(x)
//#define SQLITE_REALLOC(x,y) rt_realloc((x),(rt_size_t)(y))
#if (!defined(SQLITE_WITHOUT_MSIZE)) \
&& (defined(HAVE_MALLOC_H) && defined(HAVE_MALLOC_USABLE_SIZE))
rt-thread/include/rtthread.h
+3
View File
@@ -349,6 +349,9 @@ void rt_memheap_info(struct rt_memheap *heap,
rt_size_t *total,
rt_size_t *used,
rt_size_t *max_used);
void *rt_memheap_alloc_align(struct rt_memheap *heap, rt_size_t size, rt_size_t align);
void rt_memheap_free_align(struct rt_memheap *heap, void *ptr);
#endif /* RT_USING_MEMHEAP */
#ifdef RT_USING_MEMHEAP_AS_HEAP