添加信息

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sc committed 2026-01-14 01:13:22 +08:00
1 parent b185a8ec12
commit 115d1d12c3
22 files changed
+3619 -1829

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+26 -1
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@@ -8,8 +8,9 @@ MEMORY
ROM (rx) : ORIGIN =0x08000000,LENGTH =2048k
TDCMRAM (rw) : ORIGIN =0x20000000,LENGTH =128k
RAM (rw) : ORIGIN =0x24000000,LENGTH =512k
SRAM (rw) : ORIGIN =0x30000000,LENGTH =288k
SRAM1 (rw) : ORIGIN =0x30000000,LENGTH =128k
SDRAM (rw) : ORIGIN =0xC0000000,LENGTH =32768k
SRAM2 (rw) : ORIGIN =0x30020000,LENGTH =160k
}
ENTRY(Reset_Handler)
_system_stack_size = 0x400;
@@ -94,6 +95,30 @@ SECTIONS
. = ALIGN(4);
} > SDRAM
.sram1(NOLOAD):
{
. = ALIGN(4);
_ssram1 = .;
*(.sram1)
*(.sram1.*)
. = ALIGN(4);
_esram1 = .;
} > SRAM1
.sram2(NOLOAD):
{
. = ALIGN(4);
_ssram2 = .;
*(.sram2)
*(.sram2.*)
. = ALIGN(4);
_esram2 = .;
} > SRAM2
.tdcmram(NOLOAD):
{
. = ALIGN(4);