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sqlite数据库读写实现

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系统堆修改为axi内存区域
This commit is contained in:
sc committed 2025-11-20 01:59:02 +08:00
1 parent 91c4751d7c
commit 879bd943a4
38 files changed
+6434 -66
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drivers/board.c
+5 -4
View File
@@ -12,7 +12,7 @@
#include <board.h>
#include <drv_common.h>
struct rt_memheap sdram_AXIRAM,sdram_SRAM1,sdram_SRAM2; // memheap 控制块
struct rt_memheap sram_DTCMRAM,sram_AXIRAM,sram_SRAM1,sram_SRAM2; // memheap 控制块
rt_weak void rt_hw_board_init()
{
@@ -23,9 +23,10 @@ rt_weak void rt_hw_board_init()
rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
#endif
rt_memheap_init(&sdram_AXIRAM, "AXIRAM", (void *)AXIRAM_START, AXIRAM_SIZE);
rt_memheap_init(&sdram_SRAM1, "SRAM1", (void *)SRAM1_START, SRAM1_SIZE);
rt_memheap_init(&sdram_SRAM2, "SRAM2", (void *)SRAM2_START, SRAM2_SIZE);
rt_memheap_init(&sram_DTCMRAM, "DTCMRAM", (void *)DTCMRAM_START, DTCMRAM_SIZE);
//rt_memheap_init(&sram_AXIRAM, "AXIRAM", (void *)AXIRAM_START, AXIRAM_SIZE);
rt_memheap_init(&sram_SRAM1, "SRAM1", (void *)SRAM1_START, SRAM1_SIZE);
//rt_memheap_init(&sram_SRAM2, "SRAM2", (void *)SRAM2_START, SRAM2_SIZE);
hw_board_init(BSP_CLOCK_SOURCE, BSP_CLOCK_SOURCE_FREQ_MHZ, BSP_CLOCK_SYSTEM_FREQ_MHZ);
drivers/board.h
+16 -12
View File
@@ -33,25 +33,29 @@ extern "C"
#define ROM_SIZE (1024 * 1024)
#define ROM_END ((uint32_t)(ROM_START + ROM_SIZE))
#define RAM_START (0x20000000)
#define RAM_SIZE (128 * 1024)
#define RAM_START (0x24000000)
#define RAM_SIZE (512 * 1024)
#define RAM_END (RAM_START + RAM_SIZE)
#define AXIRAM_START (0x24000000)
#define AXIRAM_SIZE (512*1024)
#define AXIRAM_END (AXIRAM_START + AXIRAM_SIZE)
//#define AXIRAM_START (0x24000000)
//#define AXIRAM_SIZE (512*1024)
//#define AXIRAM_END (AXIRAM_START + AXIRAM_SIZE)
#define DTCMRAM_START (0x20000000)
#define DTCMRAM_SIZE (128*1024)
#define DTCMRAM_END (DTCMRAM_START + DTCMRAM_SIZE)
#define SRAM1_START (0x30000000)
#define SRAM1_SIZE (128*1024)
#define SRAM1_SIZE (288*1024)
#define SRAM1_END (SRAM1_START + SRAM1_SIZE)
#define SRAM2_START (0x30020000)
#define SRAM2_SIZE (128*1024)
#define SRAM2_END (SRAM2_START + SRAM2_SIZE)
//#define SRAM2_START (0x30020000)
//#define SRAM2_SIZE (128*1024)
//#define SRAM2_END (SRAM2_START + SRAM2_SIZE)
#define SRAM3_START (0x30040000)
#define SRAM3_SIZE (32*1024)
#define SRAM3_END (SRAM3_START + SRAM3_SIZE)
//#define SRAM3_START (0x30040000)
//#define SRAM3_SIZE (32*1024)
//#define SRAM3_END (SRAM3_START + SRAM3_SIZE)
#define BSP_USING_SDRAM
#define SDRAM1_START (0xC0000000)
drivers/drv_common.c
+2 -1
View File
@@ -17,7 +17,8 @@ static void reboot(uint8_t argc, char **argv)
{
rt_hw_cpu_reset();
}
FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System);
//FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System);
MSH_CMD_EXPORT(reboot, Reboot System);
#endif /* RT_USING_FINSH */
/* SysTick configuration */
drivers/drv_sdio.c
+3 -1
View File
@@ -48,7 +48,9 @@ struct rthw_sdio
#ifndef ALIGN
#define ALIGN(SDIO_ALIGN_LEN) __attribute__((aligned(SDIO_ALIGN_LEN)))
//ALIGN(SDIO_ALIGN_LEN)
static __attribute__((section(".ram_d1"))) rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((aligned(32)));
//static __attribute__((section(".ram_d1"))) rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((aligned(32)));
static rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((aligned(32)));
//static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
/**
* @brief This function get order from sdio.