sqlite数据库读写实现

系统堆修改为axi内存区域
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sc committed 2025-11-20 01:59:02 +08:00
1 parent 91c4751d7c
commit 879bd943a4
38 files changed
+6434 -66

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+16 -15
View File
@@ -6,10 +6,9 @@
MEMORY
{
ROM (rx) : ORIGIN =0x08000000,LENGTH =2048k
AXIRAM (rw) : ORIGIN =0x24000000,LENGTH =512k
RAM (rw) : ORIGIN =0x20000000,LENGTH =128k
SRAM1 (rw) : ORIGIN =0x30000000,LENGTH =128k
SRAM2 (rw) : ORIGIN =0x30020000,LENGTH =128k
TDCMRAM (rw) : ORIGIN =0x20000000,LENGTH =128k
RAM (rw) : ORIGIN =0x24000000,LENGTH =512k
SRAM (rw) : ORIGIN =0x30000000,LENGTH =288k
SDRAM (rw) : ORIGIN =0xC0000000,LENGTH =32768k
}
ENTRY(Reset_Handler)
@@ -85,6 +84,18 @@ SECTIONS
} > ROM
__exidx_end = .;
.tdcmram(NOLOAD):
{
. = ALIGN(4);
_stdcmram = .;
*(.tdcmram)
*(.tdcmram.*)
. = ALIGN(4);
_etdcmram = .;
} > TDCMRAM
/* .data section which is used for initialized data */
.data : AT (_sidata)
@@ -106,17 +117,7 @@ SECTIONS
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
.ram_d1(NOLOAD) :
{
. = ALIGN(4);
_sram_dax = .;
*(.ram_d1)
*(.ram_d1.*)
. = ALIGN(4);
_eram_d1 = .;
} >AXIRAM
} > RAM
.stack :
{