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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
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/**
******************************************************************************
* @file stm32h7xx_hal_cortex.c
* @author MCD Application Team
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
function according to the following table.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
(#) please refer to programming manual for details in how to configure priority.
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest preemption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure Systick using CORTEX HAL driver ***
========================================================
[..]
Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
inside the stm32h7xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..]
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
Systick functionalities
@endverbatim
* @{
*/
/**
* @brief Sets the priority grouping field (preemption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
/**
* @brief Sets the priority of an interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @param PreemptPriority The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t prioritygroup;
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
/**
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiates a system reset request to reset the MCU.
* @retval None
*/
void HAL_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
#if (__MPU_PRESENT == 1)
/**
* @brief Disables the MPU
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0;
}
/**
* @brief Enables the MPU
* @param MPU_Control Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != 0UL)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00;
MPU->RASR = 0x00;
}
}
#endif /* __MPU_PRESENT */
/**
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
{
/* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping();
}
/**
* @brief Gets the priority of an interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @param PriorityGroup the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
* @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}
/**
* @brief Sets Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval status - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clears the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval status - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief Configures the SysTick clock source.
* @param CLKSource specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
{
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
}
else
{
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
}
}
/**
* @brief This function handles SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
HAL_SYSTICK_Callback();
}
/**
* @brief SYSTICK callback.
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file
*/
}
#if defined(DUAL_CORE)
/**
* @brief Returns the current CPU ID.
* @retval CPU identifier
*/
uint32_t HAL_GetCurrentCPUID(void)
{
if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)
{
return CM7_CPUID;
}
else
{
return CM4_CPUID;
}
}
#else
/**
* @brief Returns the current CPU ID.
* @retval CPU identifier
*/
uint32_t HAL_GetCurrentCPUID(void)
{
return CM7_CPUID;
}
#endif /*DUAL_CORE*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c
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/**
******************************************************************************
* @file stm32h7xx_hal_crc.c
* @author MCD Application Team
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
* + Peripheral State functions
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(+) Initialize CRC calculator
(++) specify generating polynomial (peripheral default or non-default one)
(++) specify initialization value (peripheral default or non-default one)
(++) specify input data format
(++) specify input or output data inversion mode if any
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
input data buffer starting with the previously computed CRC as
initialization value
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
input data buffer starting with the defined initialization value
(default or non-default) to initiate CRC calculation
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup CRC CRC
* @brief CRC HAL module driver.
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup CRC_Private_Functions CRC Private Functions
* @{
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the CRC according to the specified parameters
in the CRC_InitTypeDef and create the associated handle
(+) DeInitialize the CRC peripheral
(+) Initialize the CRC MSP (MCU Specific Package)
(+) DeInitialize the CRC MSP
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC according to the specified
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if (hcrc->State == HAL_CRC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
hcrc->State = HAL_CRC_STATE_BUSY;
/* check whether or not non-default generating polynomial has been
* picked up by user */
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
{
/* initialize peripheral with default generating polynomial */
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
}
else
{
/* initialize CRC peripheral with generating polynomial defined by user */
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
{
return HAL_ERROR;
}
}
/* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
{
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
}
else
{
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
}
/* set input data inversion mode */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
/* set output data inversion mode */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
/* makes sure the input data format (bytes, halfwords or words stream)
* is properly specified by user */
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the CRC peripheral.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
/* Check the CRC peripheral state */
if (hcrc->State == HAL_CRC_STATE_BUSY)
{
return HAL_BUSY;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC calculation unit */
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_RESET;
/* Process unlocked */
__HAL_UNLOCK(hcrc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions.
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
using combination of the previous CRC value and the new one.
[..] or
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
independently of the previous CRC value.
@endverbatim
* @{
*/
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with the previously computed CRC as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
switch (hcrc->InputDataFormat)
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter Data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
case CRC_INPUTDATA_FORMAT_BYTES:
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
default:
break;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
* written in hcrc->Instance->DR) */
__HAL_CRC_DR_RESET(hcrc);
switch (hcrc->InputDataFormat)
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter 32-bit input data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
case CRC_INPUTDATA_FORMAT_BYTES:
/* Specific 8-bit input data handling */
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
/* Specific 16-bit input data handling */
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
default:
break;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the CRC handle state.
* @param hcrc CRC handle
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
{
/* Return CRC handle state */
return hcrc->State;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup CRC_Private_Functions
* @{
*/
/**
* @brief Enter 8-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer
* @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{
uint32_t i; /* input data buffer index */
uint16_t data;
__IO uint16_t *pReg;
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
* handling by the peripheral */
for (i = 0U; i < (BufferLength / 4U); i++)
{
hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
(uint32_t)pBuffer[(4U * i) + 3U];
}
/* last bytes specific handling */
if ((BufferLength % 4U) != 0U)
{
if ((BufferLength % 4U) == 1U)
{
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
}
if ((BufferLength % 4U) == 2U)
{
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = data;
}
if ((BufferLength % 4U) == 3U)
{
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = data;
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
}
}
/* Return the CRC computed value */
return hcrc->Instance->DR;
}
/**
* @brief Enter 16-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer
* @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{
uint32_t i; /* input data buffer index */
__IO uint16_t *pReg;
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
* a correct type handling by the peripheral */
for (i = 0U; i < (BufferLength / 2U); i++)
{
hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
}
if ((BufferLength % 2U) != 0U)
{
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = pBuffer[2U * i];
}
/* Return the CRC computed value */
return hcrc->Instance->DR;
}
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c
+225
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/**
******************************************************************************
* @file stm32h7xx_hal_crc_ex.c
* @author MCD Application Team
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the CRC peripheral.
*
@verbatim
================================================================================
##### How to use this driver #####
================================================================================
[..]
(+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
(+) Configure Input or Output data inversion
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup CRCEx CRCEx
* @brief CRC Extended HAL module driver
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
* @{
*/
/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
* @brief Extended Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Extended configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the generating polynomial
(+) Configure the input data inversion
(+) Configure the output data inversion
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC polynomial if different from default one.
* @param hcrc CRC handle
* @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
* This parameter is written in normal representation, e.g.
* @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
* @param PolyLength CRC polynomial length.
* This parameter can be one of the following values:
* @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
* @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
/* check polynomial definition vs polynomial size:
* polynomial length must be aligned with polynomial
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
{
}
switch (PolyLength)
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
break;
}
if (status == HAL_OK)
{
/* set generating polynomial */
WRITE_REG(hcrc->Instance->POL, Pol);
/* set generating polynomial size */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
}
/* Return function status */
return status;
}
/**
* @brief Set the Reverse Input data mode.
* @param hcrc CRC handle
* @param InputReverseMode Input Data inversion mode.
* This parameter can be one of the following values:
* @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
* @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
* @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
* @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set input data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the Reverse Output data mode.
* @param hcrc CRC handle
* @param OutputReverseMode Output Data inversion mode.
* This parameter can be one of the following values:
* @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
* @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set output data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c
+5145
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c
+446
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/**
******************************************************************************
* @file stm32h7xx_hal_cryp_ex.c
* @author MCD Application Team
* @brief Extended CRYP HAL module driver
* This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
* + Extended AES processing functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The CRYP extension HAL driver can be used after AES-GCM or AES-CCM
Encryption/Decryption to get the authentication messages.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined (CRYP)
/** @defgroup CRYPEx CRYPEx
* @brief CRYP Extension HAL module driver.
* @{
*/
#ifdef HAL_CRYP_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup CRYPEx_Private_Defines
* @{
*/
#define CRYP_PHASE_INIT 0x00000000U
#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */
#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
/* CTR0 information to use in CCM algorithm */
#define CRYP_CCM_CTR0_0 0x07FFFFFFU
#define CRYP_CCM_CTR0_3 0xFFFFFF00U
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions---------------------------------------------------------*/
/** @addtogroup CRYPEx_Exported_Functions
* @{
*/
/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
* @brief CRYPEx Extended processing functions.
*
@verbatim
==============================================================================
##### Extended AES processing functions #####
==============================================================================
[..] This section provides functions allowing to generate the authentication
TAG in Polling mode
(+)HAL_CRYPEx_AESGCM_GenerateAuthTAG
(+)HAL_CRYPEx_AESCCM_GenerateAuthTAG
they should be used after Encrypt/Decrypt operation.
@endverbatim
* @{
*/
/**
* @brief generate the GCM authentication TAG.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param AuthTag: Pointer to the authentication buffer
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
uint32_t tickstart;
uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
uint32_t tagaddr = (uint32_t)AuthTag;
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process locked */
__HAL_LOCK(hcryp);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Check if initialization phase has already been performed */
if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
}
else /* Initialization phase has not been performed*/
{
/* Disable the Peripheral */
__HAL_CRYP_DISABLE(hcryp);
/* Sequence error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
/* Select final phase */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
/*ALGODIR bit must be set to ‘0’.*/
hcryp->Instance->CR &= ~CRYP_CR_ALGODIR;
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* Write the number of bits in header (64 bits) followed by the number of bits
in the payload */
#if !defined (CRYP_VER_2_2)
/* STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(headerlength);
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(inputlength);
}
#if !defined (CRYP_VER_2_2)
else/* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
}
else if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
}
else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
}
else if (hcryp->Init.DataType == CRYP_DATATYPE_32B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(headerlength);
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(inputlength);
}
else
{
/* Nothing to do */
}
}
#endif /*End of not defined CRYP_VER_2_2*/
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP Peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
/* Read the authentication TAG in the output FIFO */
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
/* Disable the peripheral */
__HAL_CRYP_DISABLE(hcryp);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
}
/**
* @brief AES CCM Authentication TAG generation.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param AuthTag: Pointer to the authentication buffer
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
uint32_t tagaddr = (uint32_t)AuthTag;
uint32_t ctr0 [4] = {0};
uint32_t ctr0addr = (uint32_t)ctr0;
uint32_t tickstart;
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process locked */
__HAL_LOCK(hcryp);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Check if initialization phase has already been performed */
if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
}
else /* Initialization phase has not been performed*/
{
/* Disable the peripheral */
__HAL_CRYP_DISABLE(hcryp);
/* Sequence error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
/* Select final phase & ALGODIR bit must be set to ‘0’. */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* Write the counter block in the IN FIFO, CTR0 information from B0
data has to be swapped according to the DATATYPE*/
ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
ctr0[1] = hcryp->Init.B0[1];
ctr0[2] = hcryp->Init.B0[2];
ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
#if !defined (CRYP_VER_2_2)
/*STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
}
#if !defined (CRYP_VER_2_2)
else /* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
}
else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
}
else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
}
else
{
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
}
}
#endif /*End of not defined CRYP_VER_2_2*/
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
/* Read the Auth TAG in the IN FIFO */
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
}
else
{
/* Busy error code field */
hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
#endif /* HAL_CRYP_MODULE_ENABLED */
/**
* @}
*/
#endif /* CRYP */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c
+1534
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c
+869
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@@ -0,0 +1,869 @@
/**
******************************************************************************
* @file stm32h7xx_hal_dac_ex.c
* @author MCD Application Team
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.
*
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** Dual mode IO operation ***
==============================
(+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
for dual mode operation.
If software trigger is selected, using HAL_DACEx_DualStart() will start
the conversion of the value previously set by HAL_DACEx_DualSetValue().
(+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
for dual mode operation.
(+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
for dual mode operation using DMA to feed DAC converters.
First issued trigger will start the conversion of the value previously
set by HAL_DACEx_DualSetValue().
The same callbacks that are used in single mode are called in dual mode to notify
transfer completion (half complete or complete), errors or underrun.
(+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
for dual mode operation using DMA to feed DAC converters.
(+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
Channel 1 and Channel 2.
*** Signal generation operation ***
===================================
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
(+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
(+) HAL_DACEx_SetUserTrimming to set user trimming value.
(+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
after reset, user setting if HAL_DACEx_SetUserTrimming have been used
at least one time after reset).
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_DAC_MODULE_ENABLED
#if defined(DAC1) || defined(DAC2)
/** @defgroup DACEx DACEx
* @brief DAC Extended HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
* @{
*/
/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
* @brief Extended IO operation functions
*
@verbatim
==============================================================================
##### Extended features functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Start conversion.
(+) Stop conversion.
(+) Start conversion and enable DMA transfer.
(+) Stop conversion and disable DMA transfer.
(+) Get result of conversion.
(+) Get result of dual mode conversion.
@endverbatim
* @{
*/
/**
* @brief Enables DAC and starts conversion of both channels.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
{
uint32_t tmp_swtrig = 0UL;
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
/* Check if software trigger enabled */
if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1)
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
}
if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2)
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
}
/* Enable the selected DAC software conversion*/
SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Disables DAC and stop conversion of both channels.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
{
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The DAC channel that will request data from DMA.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param pData The destination peripheral Buffer address.
* @param Length The length of data to be transferred from memory to DAC peripheral
* @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment)
{
HAL_StatusTypeDef status;
uint32_t tmpreg = 0UL;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
if (Channel == DAC_CHANNEL_1)
{
/* Set the DMA transfer complete callback for channel1 */
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
/* Set the DMA half transfer complete callback for channel1 */
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
/* Set the DMA error callback for channel1 */
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Enable the selected DAC channel1 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
}
else
{
/* Set the DMA transfer complete callback for channel2 */
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
/* Set the DMA half transfer complete callback for channel2 */
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
/* Set the DMA error callback for channel2 */
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
/* Enable the selected DAC channel2 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
}
switch (Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12RD;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12LD;
break;
case DAC_ALIGN_8B_R:
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8RD;
break;
default:
break;
}
/* Enable the DMA channel */
if (Channel == DAC_CHANNEL_1)
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
/* Enable the DMA channel */
status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
}
else
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
/* Enable the DMA channel */
status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
}
/* Process Unlocked */
__HAL_UNLOCK(hdac);
if (status == HAL_OK)
{
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
}
else
{
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
}
/* Return function status */
return status;
}
/**
* @brief Disables DAC and stop conversion both channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The DAC channel that requests data from DMA.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
HAL_StatusTypeDef status;
/* Disable the selected DAC channel DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
/* Disable the DMA channel */
/* Channel1 is used */
if (Channel == DAC_CHANNEL_1)
{
/* Disable the DMA channel */
status = HAL_DMA_Abort(hdac->DMA_Handle1);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
}
else
{
/* Disable the DMA channel */
status = HAL_DMA_Abort(hdac->DMA_Handle2);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
/* Check if DMA Channel effectively disabled */
if (status != HAL_OK)
{
/* Update DAC state machine to error */
hdac->State = HAL_DAC_STATE_ERROR;
}
else
{
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
}
/* Return function status */
return status;
}
/**
* @brief Enable or disable the selected DAC channel wave generation.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Amplitude Select max triangle amplitude.
* This parameter can be one of the following values:
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
* @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
* @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
* @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
* @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
* @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
* @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
* @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
* @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
* @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the triangle wave generation for the selected DAC channel */
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Enable or disable the selected DAC channel wave generation.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Amplitude Unmask DAC channel LFSR for noise wave generation.
* This parameter can be one of the following values:
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the noise wave generation for the selected DAC channel */
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the specified data holding register value for dual DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Alignment Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* DAC_ALIGN_8B_R: 8bit right data alignment selected
* DAC_ALIGN_12B_L: 12bit left data alignment selected
* DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
* @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register.
* @note In dual mode, a unique register access is required to write in both
* DAC channels at the same time.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
{
uint32_t data;
uint32_t tmp;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (Alignment == DAC_ALIGN_8B_R)
{
data = ((uint32_t)Data2 << 8U) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16U) | Data1;
}
tmp = (uint32_t)hdac->Instance;
tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
/* Return function status */
return HAL_OK;
}
/**
* @brief Conversion complete callback in non-blocking mode for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief Error DAC callback for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief DMA underrun DAC callback for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief Run the self calibration of one DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig DAC channel configuration structure.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
* @retval HAL status
* @note Calibration runs about 7 ms.
*/
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t tmp;
uint32_t trimmingvalue;
uint32_t delta;
/* store/restore channel configuration structure purpose */
uint32_t oldmodeconfiguration;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Check the DAC handle allocation */
/* Check if DAC running */
if (hdac == NULL)
{
status = HAL_ERROR;
}
else if (hdac->State == HAL_DAC_STATE_BUSY)
{
status = HAL_ERROR;
}
else
{
/* Process locked */
__HAL_LOCK(hdac);
/* Store configuration */
oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL)));
/* Disable the selected DAC channel */
CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
/* Set mode in MCR for calibration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
/* Set DAC Channel1 DHR register to the middle value */
tmp = (uint32_t)hdac->Instance;
if (Channel == DAC_CHANNEL_1)
{
tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
}
else
{
tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
}
*(__IO uint32_t *) tmp = 0x0800UL;
/* Enable the selected DAC channel calibration */
/* i.e. set DAC_CR_CENx bit */
SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
/* Init trimming counter */
/* Medium value */
trimmingvalue = 16UL;
delta = 8UL;
while (delta != 0UL)
{
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* i.e. minimum time needed between two calibration steps */
HAL_Delay(1);
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
{
/* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
trimmingvalue -= delta;
}
else
{
/* DAC_SR_CAL_FLAGx is LOW try lower trimming */
trimmingvalue += delta;
}
delta >>= 1UL;
}
/* Still need to check if right calibration is current value or one step below */
/* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* i.e. minimum time needed between two calibration steps */
HAL_Delay(1U);
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
/* Trimming is actually one value more */
trimmingvalue++;
/* Set right trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
}
/* Disable the selected DAC channel calibration */
/* i.e. clear DAC_CR_CENx bit */
CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
sConfig->DAC_TrimmingValue = trimmingvalue;
sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
/* Restore configuration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
/* Process unlocked */
__HAL_UNLOCK(hdac);
}
return status;
}
/**
* @brief Set the trimming mode and trimming value (user trimming mode applied).
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig DAC configuration structure updated with new DAC trimming value.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param NewTrimmingValue DAC new trimming value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
/* Check the DAC handle allocation */
if (hdac == NULL)
{
status = HAL_ERROR;
}
else
{
/* Process locked */
__HAL_LOCK(hdac);
/* Set new trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
/* Update trimming mode */
sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
sConfig->DAC_TrimmingValue = NewTrimmingValue;
/* Process unlocked */
__HAL_UNLOCK(hdac);
}
return status;
}
/**
* @brief Return the DAC trimming value.
* @param hdac DAC handle
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval Trimming value : range: 0->31
*
*/
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameter */
assert_param(IS_DAC_CHANNEL(Channel));
/* Retrieve trimming */
return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
}
/**
* @}
*/
/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Set the specified data holding register value for DAC channel.
@endverbatim
* @{
*/
/**
* @brief Return the last data output value of the selected DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
{
uint32_t tmp = 0UL;
tmp |= hdac->Instance->DOR1;
tmp |= hdac->Instance->DOR2 << 16UL;
/* Returns the DAC channel data output register value */
return tmp;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DACEx_Private_Functions DACEx private functions
* @brief Extended private functions
* @{
*/
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvCpltCallbackCh2(hdac);
#else
HAL_DACEx_ConvCpltCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @brief DMA half transfer complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Conversion complete callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvHalfCpltCallbackCh2(hdac);
#else
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA error callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ErrorCallbackCh2(hdac);
#else
HAL_DACEx_ErrorCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 || DAC2 */
#endif /* HAL_DAC_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm_ex.c
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/**
******************************************************************************
* @file stm32h7xx_hal_dfsdm_ex.c
* @author MCD Application Team
* @brief DFSDM Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionality of the DFSDM Peripheral Controller:
* + Set and get pulses skipping on channel.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_DFSDM_MODULE_ENABLED
#if defined(DFSDM_CHDLYR_PLSSKP)
/** @defgroup DFSDMEx DFSDMEx
* @brief DFSDM Extended HAL module driver
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions
* @{
*/
/** @defgroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions
* @brief DFSDM extended channel operation functions
*
@verbatim
===============================================================================
##### Extended channel operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Set and get value of pulses skipping on channel
@endverbatim
* @{
*/
/**
* @brief Set value of pulses skipping.
* @param hdfsdm_channel DFSDM channel handle.
* @param PulsesValue Value of pulses to be skipped.
* This parameter must be a number between Min_Data = 0 and Max_Data = 63.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check pulses value */
assert_param(IS_DFSDM_CHANNEL_SKIPPING_VALUE(PulsesValue));
/* Check DFSDM channel state */
if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY)
{
/* Set new value of pulses skipping */
hdfsdm_channel->Instance->CHDLYR = (PulsesValue & DFSDM_CHDLYR_PLSSKP);
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @brief Get value of pulses skipping.
* @param hdfsdm_channel DFSDM channel handle.
* @param PulsesValue Value of pulses to be skipped.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check DFSDM channel state */
if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY)
{
/* Get value of remaining pulses to be skipped */
*PulsesValue = (hdfsdm_channel->Instance->CHDLYR & DFSDM_CHDLYR_PLSSKP);
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DFSDM_CHDLYR_PLSSKP */
#endif /* HAL_DFSDM_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
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/**
******************************************************************************
* @file stm32h7xx_hal_dma_ex.c
* @author MCD Application Team
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
* + Extended features functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The DMA Extension HAL driver can be used as follows:
(+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator.
(+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
(exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
-@- In Multi (Double) buffer mode, it is possible to update the base address for
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
-@- Multi (Double) buffer mode is possible with DMA and BDMA instances.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup DMAEx DMAEx
* @brief DMA Extended HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private Constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup DMAEx_Private_Functions
* @{
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @addtogroup DMAEx_Exported_Functions
* @{
*/
/** @addtogroup DMAEx_Exported_Functions_Group1
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and
Start MultiBuffer DMA transfer
(+) Configure the source, destination address and data length and
Start MultiBuffer DMA transfer with interrupt
(+) Change on the fly the memory0 or memory1 address.
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
(+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator.
(+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
@endverbatim
* @{
*/
/**
* @brief Starts the multi_buffer DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* Memory-to-memory transfer not supported in double buffering mode */
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
}
else
{
/* Process Locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
/* Enable the Double buffer mode */
((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
/* Calculate the interrupt clear flag register (IFCR) base address */
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
/* Clear all flags */
*ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
}
else /* BDMA instance(s) */
{
/* Enable the Double buffer mode */
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
/* Configure DMA Stream destination address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;
/* Calculate the interrupt clear flag register (IFCR) base address */
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
/* Clear all flags */
*ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
}
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Return error status */
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* Memory-to-memory transfer not supported in double buffering mode */
if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
/* Enable the Double buffer mode */
((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
/* Calculate the interrupt clear flag register (IFCR) base address */
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
/* Clear all flags */
*ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
}
else /* BDMA instance(s) */
{
/* Enable the Double buffer mode */
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
/* Configure DMA Stream destination address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;
/* Calculate the interrupt clear flag register (IFCR) base address */
ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
/* Clear all flags */
*ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
}
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(hdma->DMAmuxRequestGen != 0U)
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
}
}
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
/* Enable Common interrupts*/
MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
{
/*Enable Half Transfer IT if corresponding Callback is set*/
((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;
}
}
else /* BDMA instance(s) */
{
/* Enable Common interrupts*/
MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
{
/*Enable Half Transfer IT if corresponding Callback is set*/
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE;
}
}
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
{
/* Check if DMAMUX Synchronization is enabled*/
if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
}
if(hdma->DMAmuxRequestGen != 0U)
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
}
}
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Change the memory0 or memory1 address on the fly.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param Address: The new address
* @param memory: the memory to be changed, This parameter can be one of
* the following values:
* MEMORY0 /
* MEMORY1
* @note The MEMORY0 address can be changed only when the current transfer use
* MEMORY1 and the MEMORY1 address can be changed only when the current
* transfer use MEMORY0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
{
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
if(memory == MEMORY0)
{
/* change the memory0 address */
((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address;
}
else
{
/* change the memory1 address */
((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address;
}
}
else /* BDMA instance(s) */
{
if(memory == MEMORY0)
{
/* change the memory0 address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address;
}
else
{
/* change the memory1 address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = Address;
}
}
return HAL_OK;
}
/**
* @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
{
uint32_t syncSignalID = 0;
uint32_t syncPolarity = 0;
/* Check the parameters */
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
if(pSyncConfig->SyncEnable == ENABLE)
{
assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
}
else
{
assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
}
syncSignalID = pSyncConfig->SyncSignalID;
syncPolarity = pSyncConfig->SyncPolarity;
}
/*Check if the DMA state is ready */
if(hdma->State == HAL_DMA_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Disable the synchronization and event generation before applying a new config */
CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
MODIFY_REG( hdma->DMAmuxChannel->CCR, \
(~DMAMUX_CxCR_DMAREQ_ID) , \
(syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \
((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
/* Process Locked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Return error status */
return HAL_ERROR;
}
}
/**
* @brief Configure the DMAMUX request generator block used by the given DMA stream (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
* contains the request generator parameters.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
{
HAL_StatusTypeDef status;
HAL_DMA_StateTypeDef temp_state = hdma->State;
/* Check the parameters */
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
}
else
{
assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
}
assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if(hdma->DMAmuxRequestGen == 0U)
{
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
/* error status */
status = HAL_ERROR;
}
else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
{
/* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the request generator new parameters */
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
pRequestGeneratorConfig->Polarity;
/* Process Locked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Enable the DMAMUX request generator block used by the given DMA stream (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block */
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
{
/* Enable the request generator*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Disable the DMAMUX request generator block used by the given DMA stream (instance).
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block */
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
{
/* Disable the request generator*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Handles DMAMUX interrupt request.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval None
*/
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
{
/* Check for DMAMUX Synchronization overrun */
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Disable the synchro overrun interrupt */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
if(hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
if(hdma->DMAmuxRequestGen != 0)
{
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{
/* Disable the request gen overrun interrupt */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
if(hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
}
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DMAEx_Private_Functions
* @{
*/
/**
* @brief Set the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
/* Configure DMA Stream data length */
((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Stream destination address */
((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
/* Configure DMA Stream source address */
((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
}
/* Memory to Peripheral */
else
{
/* Configure DMA Stream source address */
((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
/* Configure DMA Stream destination address */
((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
}
}
else /* BDMA instance(s) */
{
/* Configure DMA Stream data length */
((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Stream destination address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
/* Configure DMA Stream source address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
}
/* Memory to Peripheral */
else
{
/* Configure DMA Stream source address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
/* Configure DMA Stream destination address */
((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
}
}
}
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c
+2705
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c
+823
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@@ -0,0 +1,823 @@
/**
******************************************************************************
* @file stm32h7xx_hal_dts.c
* @author MCD Application Team
* @brief DTS HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DTS peripheral:
* + Initialization and de-initialization functions
* + Start/Stop operation functions in polling mode.
* + Start/Stop operation functions in interrupt mode.
* + Peripheral Control functions
* + Peripheral State functions
*
@verbatim
================================================================================
##### DTS Peripheral features #####
================================================================================
[..]
The STM32h7xx device family integrate one DTS sensor interface :
##### How to use this driver #####
================================================================================
[..]
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_DTS_MODULE_ENABLED
#if defined(DTS)
/** @defgroup DTS DTS
* @brief DTS HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup DTS_Private_Constants
* @{
*/
/* @brief Delay for DTS startup time
* @note Delay required to get ready for DTS Block.
* @note Unit: ms
*/
#define DTS_DELAY_STARTUP (1UL)
/* @brief DTS measure ready flag time out value.
* @note Maximal measurement time is when LSE is selected as ref_clock and
* maximal sampling time is used, taking calibration into account this
* is equivalent to ~620 us. Use 5 ms as arbitrary timeout
* @note Unit: ms
*/
#define TS_TIMEOUT_MS (5UL)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
static void DTS_ResetCallback(DTS_HandleTypeDef *hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
/* Exported functions --------------------------------------------------------*/
/** @defgroup DTS_Exported_Functions DTS Exported Functions
* @{
*/
/** @defgroup DTS_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and de-initialization functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions to initialize and de-initialize comparators
@endverbatim
* @{
*/
/**
* @brief Initialize the DTS according to the specified
* parameters in the DTS_InitTypeDef and initialize the associated handle.
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts)
{
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
assert_param(IS_DTS_QUICKMEAS(hdts->Init.QuickMeasure));
assert_param(IS_DTS_REFCLK(hdts->Init.RefClock));
assert_param(IS_DTS_TRIGGERINPUT(hdts->Init.TriggerInput));
assert_param(IS_DTS_SAMPLINGTIME(hdts->Init.SamplingTime));
assert_param(IS_DTS_THRESHOLD(hdts->Init.HighThreshold));
assert_param(IS_DTS_THRESHOLD(hdts->Init.LowThreshold));
if (hdts->State == HAL_DTS_STATE_RESET)
{
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
/* Reset interrupt callbacks to legacy weak callbacks */
DTS_ResetCallback(hdts);
if (hdts->MspInitCallback == NULL)
{
hdts->MspInitCallback = HAL_DTS_MspInit;
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hdts->MspInitCallback(hdts);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_DTS_MspInit(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Change the DTS state */
hdts->State = HAL_DTS_STATE_BUSY;
/* Check ramp coefficient */
if (hdts->Instance->RAMPVALR == 0UL)
{
return HAL_ERROR;
}
/* Check factory calibration temperature */
if (hdts->Instance->T0VALR1 == 0UL)
{
return HAL_ERROR;
}
/* Check Quick Measure option is enabled or disabled */
if (hdts->Init.QuickMeasure == DTS_QUICKMEAS_DISABLE)
{
/* Check Reference clock selection */
if (hdts->Init.RefClock == DTS_REFCLKSEL_PCLK)
{
assert_param(IS_DTS_DIVIDER_RATIO_NUMBER(hdts->Init.Divider));
}
/* Quick measurement mode disabled */
CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_Q_MEAS_OPT);
}
else
{
/* DTS_QUICKMEAS_ENABLE shall be used only when the LSE clock is
selected as reference clock */
if (hdts->Init.RefClock != DTS_REFCLKSEL_LSE)
{
return HAL_ERROR;
}
/* Quick measurement mode enabled - no calibration needed */
SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_Q_MEAS_OPT);
}
/* set the DTS clk source */
if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
{
SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_REFCLK_SEL);
}
else
{
CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_REFCLK_SEL);
}
MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_HSREF_CLK_DIV, (hdts->Init.Divider << DTS_CFGR1_HSREF_CLK_DIV_Pos));
MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_TS1_SMP_TIME, hdts->Init.SamplingTime);
MODIFY_REG(hdts->Instance->CFGR1, DTS_CFGR1_TS1_INTRIG_SEL, hdts->Init.TriggerInput);
MODIFY_REG(hdts->Instance->ITR1, DTS_ITR1_TS1_HITTHD, (hdts->Init.HighThreshold << DTS_ITR1_TS1_HITTHD_Pos));
MODIFY_REG(hdts->Instance->ITR1, DTS_ITR1_TS1_LITTHD, hdts->Init.LowThreshold);
/* Change the DTS state */
hdts->State = HAL_DTS_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitialize the DTS peripheral.
* @note Deinitialization cannot be performed if the DTS configuration is locked.
* To unlock the configuration, perform a system reset.
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts)
{
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
/* Set DTS_CFGR register to reset value */
CLEAR_REG(hdts->Instance->CFGR1);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
if (hdts->MspDeInitCallback == NULL)
{
hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
}
/* DeInit the low level hardware: CLOCK, NVIC.*/
hdts->MspDeInitCallback(hdts);
#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_DTS_MspDeInit(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
hdts->State = HAL_DTS_STATE_RESET;
return HAL_OK;
}
/**
* @brief Initialize the DTS MSP.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize the DTS MSP.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DTS_Exported_Functions_Group2 Start-Stop operation functions
* @brief Start-Stop operation functions.
*
@verbatim
===============================================================================
##### DTS Start Stop operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Start a DTS Sensor without interrupt.
(+) Stop a DTS Sensor without interrupt.
(+) Start a DTS Sensor with interrupt generation.
(+) Stop a DTS Sensor with interrupt generation.
@endverbatim
* @{
*/
/**
* @brief Start the DTS sensor.
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts)
{
uint32_t Ref_Time;
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
if (hdts->State == HAL_DTS_STATE_READY)
{
hdts->State = HAL_DTS_STATE_BUSY;
/* Enable DTS sensor */
__HAL_DTS_ENABLE(hdts);
/* Get Start Tick*/
Ref_Time = HAL_GetTick();
/* Wait till TS1_RDY flag is set */
while (__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_RDY) == RESET)
{
if ((HAL_GetTick() - Ref_Time) > DTS_DELAY_STARTUP)
{
return HAL_TIMEOUT;
}
}
if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
{
/* Start continuous measures */
SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
/* Ensure start is taken into account */
HAL_Delay(TS_TIMEOUT_MS);
}
hdts->State = HAL_DTS_STATE_READY;
}
else
{
return HAL_BUSY;
}
return HAL_OK;
}
/**
* @brief Stop the DTS Sensor.
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts)
{
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
if (hdts->State == HAL_DTS_STATE_READY)
{
hdts->State = HAL_DTS_STATE_BUSY;
if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
{
CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
}
/* Disable the selected DTS sensor */
__HAL_DTS_DISABLE(hdts);
hdts->State = HAL_DTS_STATE_READY;
}
else
{
return HAL_BUSY;
}
return HAL_OK;
}
/**
* @brief Enable the interrupt(s) and start the DTS sensor
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts)
{
uint32_t Ref_Time;
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
if (hdts->State == HAL_DTS_STATE_READY)
{
hdts->State = HAL_DTS_STATE_BUSY;
/* On Asynchronous mode enable the asynchronous IT */
if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
{
__HAL_DTS_ENABLE_IT(hdts, DTS_IT_TS1_AITE | DTS_IT_TS1_AITL | DTS_IT_TS1_AITH);
}
else
{
/* Enable the IT(s) */
__HAL_DTS_ENABLE_IT(hdts, DTS_IT_TS1_ITE | DTS_IT_TS1_ITL | DTS_IT_TS1_ITH);
}
/* Enable the selected DTS sensor */
__HAL_DTS_ENABLE(hdts);
/* Get Start Tick*/
Ref_Time = HAL_GetTick();
/* Wait till TS1_RDY flag is set */
while (__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_RDY) == RESET)
{
if ((HAL_GetTick() - Ref_Time) > DTS_DELAY_STARTUP)
{
return HAL_TIMEOUT;
}
}
if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
{
/* Start continuous measures */
SET_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
/* Ensure start is taken into account */
HAL_Delay(TS_TIMEOUT_MS);
}
hdts->State = HAL_DTS_STATE_READY;
}
else
{
return HAL_BUSY;
}
return HAL_OK;
}
/**
* @brief Disable the interrupt(s) and stop the DTS sensor.
* @param hdts DTS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts)
{
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_ERROR;
}
if (hdts->State == HAL_DTS_STATE_READY)
{
hdts->State = HAL_DTS_STATE_BUSY;
/* On Asynchronous mode disable the asynchronous IT */
if (hdts->Init.RefClock == DTS_REFCLKSEL_LSE)
{
__HAL_DTS_DISABLE_IT(hdts, DTS_IT_TS1_AITE | DTS_IT_TS1_AITL | DTS_IT_TS1_AITH);
}
else
{
/* Disable the IT(s) */
__HAL_DTS_DISABLE_IT(hdts, DTS_IT_TS1_ITE | DTS_IT_TS1_ITL | DTS_IT_TS1_ITH);
}
if (__HAL_DTS_GET_TRIGGER(hdts) == DTS_TRIGGER_HW_NONE)
{
CLEAR_BIT(hdts->Instance->CFGR1, DTS_CFGR1_TS1_START);
}
/* Disable the selected DTS sensor */
__HAL_DTS_DISABLE(hdts);
hdts->State = HAL_DTS_STATE_READY;
}
else
{
return HAL_BUSY;
}
return HAL_OK;
}
/**
* @brief Get temperature from DTS
* @param hdts DTS handle
* @param Temperature Temperature in deg C
* @note This function retrieves latest available measure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature)
{
uint32_t freq_meas;
uint32_t samples;
uint32_t t0_temp;
uint32_t t0_freq;
uint32_t ramp_coeff;
if (hdts->State == HAL_DTS_STATE_READY)
{
hdts->State = HAL_DTS_STATE_BUSY;
/* Get the total number of samples */
samples = (hdts->Instance->DR & DTS_DR_TS1_MFREQ);
if ((hdts->Init.SamplingTime == 0UL) || (samples == 0UL))
{
hdts->State = HAL_DTS_STATE_READY;
return HAL_ERROR;
}
if ((hdts->Init.RefClock) == DTS_REFCLKSEL_LSE)
{
freq_meas = (LSE_VALUE * samples) / (hdts->Init.SamplingTime >> DTS_CFGR1_TS1_SMP_TIME_Pos); /* On Hz */
}
else
{
freq_meas = (HAL_RCCEx_GetD3PCLK1Freq() * (hdts->Init.SamplingTime >> DTS_CFGR1_TS1_SMP_TIME_Pos)) / samples; /* On Hz */
}
/* Read factory settings */
t0_temp = hdts->Instance->T0VALR1 >> DTS_T0VALR1_TS1_T0_Pos;
if (t0_temp == 0UL)
{
t0_temp = 30UL; /* 30 deg C */
}
else if (t0_temp == 1UL)
{
t0_temp = 110UL; /* 110 deg C */
}
else
{
hdts->State = HAL_DTS_STATE_READY;
return HAL_ERROR;
}
t0_freq = (hdts->Instance->T0VALR1 & DTS_T0VALR1_TS1_FMT0) * 100UL; /* Hz */
ramp_coeff = hdts->Instance->RAMPVALR & DTS_RAMPVALR_TS1_RAMP_COEFF; /* deg C/Hz */
if (ramp_coeff == 0UL)
{
hdts->State = HAL_DTS_STATE_READY;
return HAL_ERROR;
}
/* Figure out the temperature deg C */
*Temperature = (int32_t)t0_temp + (((int32_t)freq_meas - (int32_t)t0_freq) / (int32_t)ramp_coeff);
hdts->State = HAL_DTS_STATE_READY;
}
else
{
return HAL_BUSY;
}
return HAL_OK;
}
/**
* @brief DTS sensor IRQ Handler.
* @param hdts DTS handle
* @retval None
*/
void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts)
{
/* Check end of measure Asynchronous IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITE)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITE);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->AsyncEndCallback(hdts);
#else
HAL_DTS_AsyncEndCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Check low threshold Asynchronous IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITL)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITL);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->AsyncLowCallback(hdts);
#else
HAL_DTS_AsyncLowCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Check high threshold Asynchronous IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_AITH)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_AITH);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->AsyncHighCallback(hdts);
#else
HAL_DTS_AsyncHighCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Check end of measure IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITE)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITE);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->EndCallback(hdts);
#else
HAL_DTS_EndCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Check low threshold IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITL)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITL);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->LowCallback(hdts);
#else
HAL_DTS_LowCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
/* Check high threshold IT */
if ((__HAL_DTS_GET_FLAG(hdts, DTS_FLAG_TS1_ITH)) != RESET)
{
__HAL_DTS_CLEAR_FLAG(hdts, DTS_FLAG_TS1_ITH);
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
hdts->HighCallback(hdts);
#else
HAL_DTS_HighCallback(hdts);
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
}
}
/**
* @brief DTS Sensor End measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_EndCallback should be implemented in the user file
*/
}
/**
* @brief DTS Sensor low threshold measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_LowCallback should be implemented in the user file
*/
}
/**
* @brief DTS Sensor high threshold measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_HighCallback should be implemented in the user file
*/
}
/**
* @brief DTS Sensor asynchronous end measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_AsyncEndCallback should be implemented in the user file
*/
}
/**
* @brief DTS Sensor asynchronous low threshold measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_AsyncLowCallback should be implemented in the user file
*/
}
/**
* @brief DTS Sensor asynchronous high threshold measure callback.
* @param hdts DTS handle
* @retval None
*/
__weak void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdts);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DTS_AsyncHighCallback should be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DTS_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the DTS handle state.
* @param hdts DTS handle
* @retval HAL state
*/
HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts)
{
/* Check the DTS handle allocation */
if (hdts == NULL)
{
return HAL_DTS_STATE_RESET;
}
/* Return DTS handle state */
return hdts->State;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DTS_Private_Functions DTS Private Functions
* @{
*/
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
/**
* @brief Reset interrupt callbacks to the legacy weak callbacks.
* @param hdts pointer to a DTS_HandleTypeDef structure that contains
* the configuration information for DTS module.
* @retval None
*/
static void DTS_ResetCallback(DTS_HandleTypeDef *hdts)
{
/* Reset the DTS callback to the legacy weak callbacks */
hdts->DTS_EndCallback = HAL_DTS_EndCallback; /* End measure Callback */
hdts->DTS_LowCallback = HAL_DTS_LowCallback; /* low threshold Callback */
hdts->DTS_HighCallback = HAL_DTS_HighCallback; /* high threshold Callback */
hdts->DTS_AsyncEndCallback = HAL_DTS_AsyncEndCallback; /* Asynchronous end of measure Callback */
hdts->DTS_AsyncLowCallback = HAL_DTS_AsyncLowCallback; /* Asynchronous low threshold Callback */
hdts->DTS_AsyncHighCallback = HAL_DTS_AsyncHighCallback; /* Asynchronous high threshold Callback */
}
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
#endif /* DTS */
#endif /* HAL_DTS_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c
+2998
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c
+559
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@@ -0,0 +1,559 @@
/**
******************************************************************************
* @file stm32h7xx_hal_eth_ex.c
* @author MCD Application Team
* @brief ETH HAL Extended module driver.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_ETH_MODULE_ENABLED
#if defined(ETH)
/** @defgroup ETHEx ETHEx
* @brief ETH HAL Extended module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup ETHEx_Private_Constants ETHEx Private Constants
* @{
*/
#define ETH_MACL4CR_MASK (ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \
ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \
ETH_MACL3L4CR_L4DPIM)
#define ETH_MACL3CR_MASK (ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \
ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \
ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \
ETH_MACL3L4CR_L3HDBM)
#define ETH_MACRXVLAN_MASK (ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \
ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \
ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \
ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \
ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \
ETH_MACVTR_VTIM | ETH_MACVTR_ETV)
#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
ETH_MACVIR_VLP | ETH_MACVIR_VLC)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions
* @{
*/
/** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure ARP offload module
(+) Configure L3 and L4 filters
(+) Configure Extended VLAN features
(+) Configure Energy Efficient Ethernet module
@endverbatim
* @{
*/
/**
* @brief Enables ARP Offload.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
{
SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
}
/**
* @brief Disables ARP Offload.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth)
{
CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
}
/**
* @brief Set the ARP Match IP address
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param IpAddress: IP Address to be matched for incoming ARP requests
* @retval None
*/
void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
{
WRITE_REG(heth->Instance->MACARPAR, IpAddress);
}
/**
* @brief Configures the L4 Filter, this function allow to:
* set the layer 4 protocol to be matched (TCP or UDP)
* enable/disable L4 source/destination port perfect/inverse match.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param Filter: L4 filter to configured, this parameter must be one of the following
* ETH_L4_FILTER_0
* ETH_L4_FILTER_1
* @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
* that contains L4 filter configuration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef *pL4FilterConfig)
{
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
if(pL4FilterConfig == NULL)
{
return HAL_ERROR;
}
/* Write configuration to (MACL3L4C0R + filter )register */
MODIFY_REG(*configreg, ETH_MACL4CR_MASK ,(pL4FilterConfig->Protocol |
pL4FilterConfig->SrcPortFilterMatch |
pL4FilterConfig->DestPortFilterMatch));
configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
/* Write configuration to (MACL4A0R + filter )register */
MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , (pL4FilterConfig->SourcePort |
(pL4FilterConfig->DestinationPort << 16)));
/* Enable L4 filter */
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
return HAL_OK;
}
/**
* @brief Configures the L4 Filter, this function allow to:
* set the layer 4 protocol to be matched (TCP or UDP)
* enable/disable L4 source/destination port perfect/inverse match.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param Filter: L4 filter to configured, this parameter must be one of the following
* ETH_L4_FILTER_0
* ETH_L4_FILTER_1
* @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
* that contains L4 filter configuration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
{
if(pL4FilterConfig == NULL)
{
return HAL_ERROR;
}
/* Get configuration to (MACL3L4C0R + filter )register */
pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L4PEN);
pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
/* Get configuration to (MACL3L4C0R + filter )register */
pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4DP) >> 16);
pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
return HAL_OK;
}
/**
* @brief Configures the L3 Filter, this function allow to:
* set the layer 3 protocol to be matched (IPv4 or IPv6)
* enable/disable L3 source/destination port perfect/inverse match.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param Filter: L3 filter to configured, this parameter must be one of the following
* ETH_L3_FILTER_0
* ETH_L3_FILTER_1
* @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
* that contains L3 filter configuration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
{
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
if(pL3FilterConfig == NULL)
{
return HAL_ERROR;
}
/* Write configuration to (MACL3L4C0R + filter )register */
MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
pL3FilterConfig->SrcAddrFilterMatch |
pL3FilterConfig->DestAddrFilterMatch |
(pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
(pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
/* Check if IPv6 protocol is selected */
if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
{
/* Set the IPv6 address match */
/* Set Bits[31:0] of 128-bit IP addr */
*((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
/* Set Bits[63:32] of 128-bit IP addr */
*((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
/* update Bits[95:64] of 128-bit IP addr */
*((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
/* update Bits[127:96] of 128-bit IP addr */
*((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
}
else /* IPv4 protocol is selected */
{
/* Set the IPv4 source address match */
*((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
/* Set the IPv4 destination address match */
*((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
}
return HAL_OK;
}
/**
* @brief Configures the L3 Filter, this function allow to:
* set the layer 3 protocol to be matched (IPv4 or IPv6)
* enable/disable L3 source/destination port perfect/inverse match.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param Filter: L3 filter to configured, this parameter must be one of the following
* ETH_L3_FILTER_0
* ETH_L3_FILTER_1
* @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
* that will contain the L3 filter configuration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
{
if(pL3FilterConfig == NULL)
{
return HAL_ERROR;
}
pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN);
pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HSBM) >> 6);
pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11);
if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
{
pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
}
else
{
pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
}
return HAL_OK;
}
/**
* @brief Enables L3 and L4 filtering process.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None.
*/
void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth)
{
/* Enable L3/L4 filter */
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
}
/**
* @brief Disables L3 and L4 filtering process.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None.
*/
void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
{
/* Disable L3/L4 filter */
CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
}
/**
* @brief Get the VLAN Configuration for Receive Packets.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
* that will contain the VLAN filter configuration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
{
if(pVlanConfig == NULL)
{
return HAL_ERROR;
}
pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) ? DISABLE : ENABLE;
return HAL_OK;
}
/**
* @brief Set the VLAN Configuration for Receive Packets.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
* that contains VLAN filter configuration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
{
if(pVlanConfig == NULL)
{
return HAL_ERROR;
}
/* Write config to MACVTR */
MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) |
pVlanConfig->StripInnerVLANTag |
((uint32_t)pVlanConfig->InnerVLANTag << 27) |
((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
pVlanConfig->StripVLANTag |
pVlanConfig->VLANTypeCheck |
((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
return HAL_OK;
}
/**
* @brief Set the VLAN Hash Table
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param VLANHashTable: VLAN hash table 16 bit value
* @retval None
*/
void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
{
MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable);
}
/**
* @brief Get the VLAN Configuration for Transmit Packets.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param VLANTag: Selects the vlan tag, this parameter must be one of the following
* ETH_OUTER_TX_VLANTAG
* ETH_INNER_TX_VLANTAG
* @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
* that will contain the Tx VLAN filter configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
{
if (pVlanConfig == NULL)
{
return HAL_ERROR;
}
if(VLANTag == ETH_INNER_TX_VLANTAG)
{
pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACIVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
}
else
{
pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
}
return HAL_OK;;
}
/**
* @brief Set the VLAN Configuration for Transmit Packets.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param VLANTag: Selects the vlan tag, this parameter must be one of the following
* ETH_OUTER_TX_VLANTAG
* ETH_INNER_TX_VLANTAG
* @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
* that contains Tx VLAN filter configuration.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
{
if(VLANTag == ETH_INNER_TX_VLANTAG)
{
MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
((uint32_t)pVlanConfig->SVLANType << 19) |
pVlanConfig->VLANTagControl));
/* Enable Double VLAN processing */
SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
}
else
{
MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
((uint32_t)pVlanConfig->SVLANType << 19) |
pVlanConfig->VLANTagControl));
}
return HAL_OK;
}
/**
* @brief Set the VLAN Tag Identifier for Transmit Packets.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param VLANTag: Selects the vlan tag, this parameter must be one of the following
* ETH_OUTER_TX_VLANTAG
* ETH_INNER_TX_VLANTAG
* @param VLANIdentifier: VLAN Identifier 16 bit value
* @retval None
*/
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier)
{
if(VLANTag == ETH_INNER_TX_VLANTAG)
{
MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
}
else
{
MODIFY_REG(heth->Instance->MACVIR, ETH_MACVIR_VLT, VLANIdentifier);
}
}
/**
* @brief Enables the VLAN Tag Filtering process.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None.
*/
void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth)
{
/* Enable VLAN processing */
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
}
/**
* @brief Disables the VLAN Tag Filtering process.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None.
*/
void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth)
{
/* Disable VLAN processing */
CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
}
/**
* @brief Enters the Low Power Idle (LPI) mode
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param TxAutomate: Enable/Disbale automate enter/exit LPI mode.
* @param TxClockStop: Enable/Disbale Tx clock stop in LPI mode.
* @retval None
*/
void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
{
/* Enable LPI Interrupts */
__HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
/* Write to LPI Control register: Enter low power mode */
MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), (((uint32_t)TxAutomate << 19) |
((uint32_t)TxClockStop << 21) |
ETH_MACLCSR_LPIEN));
}
/**
* @brief Exits the Low Power Idle (LPI) mode.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
{
/* Clear the LPI Config and exit low power mode */
CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE));
/* Enable LPI Interrupts */
__HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
}
/**
* @brief Returns the ETH MAC LPI event
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval ETH MAC WakeUp event
*/
uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
{
return heth->MACLPIEvent;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* ETH */
#endif /* HAL_ETH_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c
+877
View File
@@ -0,0 +1,877 @@
/**
******************************************************************************
* @file stm32h7xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt (CORE1 or CORE2 in case of dual core line )
(++) Event (CORE1 or CORE2 in case of dual core line )
(++) a combination of the previous
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two diffenrents
interrupt pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected throught multiplexer.
(+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear soure.
It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain).
Value can be one of the following:
(++) EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selcted :
In this case corresponding bit of D2PMRx register is set to 0
(+++) On a configurable Line : the D3 domain wakeup signal is
automatically cleared after after the Delay + Rising Edge detect
(+++) On a direct Line : the D3 domain wakeup signal is
cleared after the direct event input signal is cleared
(++) EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selcted :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b00 :
DMA ch6 event selected as D3 domain pendclear source
(++) EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selcted :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b01 :
DMA ch7 event selected as D3 domain pendclear source
(++) EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selcted :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b10 :
LPTIM4 out selected as D3 domain pendclear source
(++) EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selcted :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b11 :
LPTIM5 out selected as D3 domain pendclear source
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain),
choose gpio D3 PendClearSource using PendClearSource
member from EXTI_PendClear_Source structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
#define EXTI_MODE_OFFSET 0x04U /* 0x10: offset between CPU IMR/EMR registers */
#define EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between CPU Rising/Falling configuration registers */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
uint32_t pcrlinepos;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
{
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store rising trigger mode */
*regaddr = regval;
/* Configure falling trigger */
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store falling trigger mode */
*regaddr = regval;
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
}
}
/* Configure interrupt mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* The event mode cannot be configured if the line does not support it */
assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
/* Configure event mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
#if defined (DUAL_CORE)
/* Configure interrupt mode for Core2 : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* The event mode cannot be configured if the line does not support it */
assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != EXTI_MODE_CORE2_EVENT));
/* Configure event mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
#endif /* DUAL_CORE */
/* Configure the D3 PendClear source in case of Wakeup target is Any */
if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
{
assert_param(IS_EXTI_D3_PENDCLR_SRC(pExtiConfig->PendClearSource));
/*Calc the PMR register address for the given line */
regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
if(pExtiConfig->PendClearSource == EXTI_D3_PENDCLR_SRC_NONE)
{
/* Clear D3PMRx register for the given line */
regval &= ~maskline;
/* Store D3PMRx register value */
*regaddr = regval;
}
else
{
/* Set D3PMRx register to 1 for the given line */
regval |= maskline;
/* Store D3PMRx register value */
*regaddr = regval;
if(linepos < 16UL)
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << linepos;
}
else
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << (linepos - 16UL);
}
regval = (*regaddr & (~(pcrlinepos * pcrlinepos * 3UL))) | (pcrlinepos * pcrlinepos * (pExtiConfig->PendClearSource - 1UL));
*regaddr = regval;
}
}
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
uint32_t pcrlinepos;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* 1] Get core mode : interrupt */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
pExtiConfig->Mode = EXTI_MODE_NONE;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
/* Get event mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
#if defined (DUAL_CORE)
regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT;
}
/* Get event mode */
regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT;
}
#endif /*DUAL_CORE*/
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
{
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
}
/* Get falling configuration */
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U);
}
else
{
pExtiConfig->GPIOSel = 0x00U;
}
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00U;
}
/* 3] Get D3 Pend Clear source */
if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
{
regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
if(((*regaddr) & linepos) == 0UL)
{
/* if PMR unset, then no pend clear source is used */
pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
}
else
{
/* if wakeup target is any and PMR set, the read pend clear source from D3PCRxL/H */
if(linepos < 16UL)
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << linepos;
}
else
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << (linepos - 16UL);
}
pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos));
}
}
else
{
/* if line wakeup target is not any, then no pend clear source is used */
pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
uint32_t pcrlinepos;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* 1] Clear interrupt mode */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear event mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
#if defined (DUAL_CORE)
/* 1] Clear CM4 interrupt mode */
regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear CM4 event mode */
regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
#endif /* DUAL_CORE */
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0x00U)
{
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL)));
SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
}
}
/* 4] Clear D3 Config lines */
if ((hexti->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
{
regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
*regaddr = (*regaddr & ~maskline);
if(linepos < 16UL)
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << linepos;
}
else
{
regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
pcrlinepos = 1UL << (linepos - 16UL);
}
/*Clear D3 PendClear source */
*regaddr &= (~(pcrlinepos * pcrlinepos * 3UL));
}
return HAL_OK;
}
/**
* @brief Register callback for a dedicated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->PendingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t maskline;
uint32_t offset;
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
}
else /* Cortex-M4*/
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
}
#else
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
#endif /* DUAL_CORE */
/* Get pending bit */
regval = (*regaddr & maskline);
if (regval != 0x00U)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call callback */
if (hexti->PendingCallback != NULL)
{
hexti->PendingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
}
else /* Cortex-M4 */
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
}
#else
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
#endif /* DUAL_CORE */
/* return 1 if bit is set else 0 */
regval = ((*regaddr & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
}
else /* Cortex-M4 */
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
}
#else
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
#endif /* DUAL_CORE */
/* Clear Pending bit */
*regaddr = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
*regaddr = maskline;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
+6169
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
+1099
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
+1709
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c
+893
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@@ -0,0 +1,893 @@
/**
******************************************************************************
* @file stm32h7xx_hal_gfxmmu.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* functionalities of the Graphic MMU (GFXMMU) peripheral:
* + Initialization and De-initialization.
* + LUT configuration.
* + Force flush and/or invalidate of cache.
* + Modify physical buffer adresses.
* + Modify cache and pre-fetch parameters.
* + Error management.
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** Initialization ***
======================
[..]
(#) As prerequisite, fill in the HAL_GFXMMU_MspInit() :
(++) Enable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
(++) If interrupts are used, enable and configure GFXMMU global
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#) Configure the number of blocks per line, default value, physical
buffer addresses, cache and pre-fetch parameters and interrupts
using the HAL_GFXMMU_Init() function.
*** LUT configuration ***
=========================
[..]
(#) Use HAL_GFXMMU_DisableLutLines() to deactivate all LUT lines (or a
range of lines).
(#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM.
(#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT.
*** Force flush and/or invalidate of cache ***
==============================================
[..]
(#) Use HAL_GFXMMU_ConfigForceCache() to flush and/or invalidate cache.
*** Modify physical buffer adresses ***
=======================================
[..]
(#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses.
*** Modify cache and pre-fetch parameters ***
=============================================
[..]
(#) Use HAL_GFXMMU_ModifyCachePrefetch() to modify cache and pre-fetch
parameters.
*** Error management ***
========================
[..]
(#) If interrupts are used, HAL_GFXMMU_IRQHandler() will be called when
an error occurs. This function will call HAL_GFXMMU_ErrorCallback().
Use HAL_GFXMMU_GetError() to get the error code.
*** De-initialization ***
=========================
[..]
(#) As prerequisite, fill in the HAL_GFXMMU_MspDeInit() :
(++) Disable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
(++) If interrupts has been used, disable GFXMMU global interrupt with
HAL_NVIC_DisableIRQ().
(#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function.
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions HAL_GFXMMU_RegisterCallback() to register a user callback.
[..]
Function HAL_GFXMMU_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : GFXMMU error.
(+) MspInitCallback : GFXMMU MspInit.
(+) MspDeInitCallback : GFXMMU MspDeInit.
[..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
[..]
Use function HAL_GFXMMU_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
HAL_GFXMMU_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
This function allows to reset following callbacks:
(+) ErrorCallback : GFXMMU error.
(+) MspInitCallback : GFXMMU MspInit.
(+) MspDeInitCallback : GFXMMU MspDeInit.
[..]
By default, after the HAL_GFXMMU_Init and if the state is HAL_GFXMMU_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples HAL_GFXMMU_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_GFXMMU_Init
and HAL_GFXMMU_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_GFXMMU_Init and HAL_GFXMMU_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_GFXMMU_RegisterCallback before calling HAL_GFXMMU_DeInit
or HAL_GFXMMU_Init function.
[..]
When the compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_GFXMMU_MODULE_ENABLED
#if defined(GFXMMU)
/** @defgroup GFXMMU GFXMMU
* @brief GFXMMU HAL driver module
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define GFXMMU_LUTXL_FVB_OFFSET 8U
#define GFXMMU_LUTXL_LVB_OFFSET 16U
#define GFXMMU_CR_ITS_MASK 0x1FU
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GFXMMU_Exported_Functions GFXMMU Exported Functions
* @{
*/
/** @defgroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize the GFXMMU.
(+) De-initialize the GFXMMU.
@endverbatim
* @{
*/
/**
* @brief Initialize the GFXMMU according to the specified parameters in the
* GFXMMU_InitTypeDef structure and initialize the associated handle.
* @param hgfxmmu GFXMMU handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check GFXMMU handle */
if(hgfxmmu == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_BLOCKS_PER_LINE(hgfxmmu->Init.BlocksPerLine));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf0Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf1Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf2Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address));
assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.CachePrefetch.Activation));
assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation));
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
/* Call GFXMMU MSP init function */
if(hgfxmmu->MspInitCallback == NULL)
{
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
}
hgfxmmu->MspInitCallback(hgfxmmu);
#else
/* Call GFXMMU MSP init function */
HAL_GFXMMU_MspInit(hgfxmmu);
#endif
/* Configure blocks per line, cache and interrupts parameters on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
GFXMMU_CR_AMEIE | GFXMMU_CR_192BM | GFXMMU_CR_CE | GFXMMU_CR_CL |
GFXMMU_CR_CLB | GFXMMU_CR_FC | GFXMMU_CR_PD | GFXMMU_CR_OC |
GFXMMU_CR_OB);
hgfxmmu->Instance->CR |= (hgfxmmu->Init.BlocksPerLine);
if(hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK(hgfxmmu->Init.CachePrefetch.CacheLock));
assert_param(IS_GFXMMU_PREFETCH(hgfxmmu->Init.CachePrefetch.Prefetch));
assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(hgfxmmu->Init.CachePrefetch.OutterBufferability));
assert_param(IS_GFXMMU_OUTTER_CACHABILITY(hgfxmmu->Init.CachePrefetch.OutterCachability));
hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
hgfxmmu->Init.CachePrefetch.CacheLock |
hgfxmmu->Init.CachePrefetch.Prefetch |
hgfxmmu->Init.CachePrefetch.OutterBufferability |
hgfxmmu->Init.CachePrefetch.OutterCachability);
if(hgfxmmu->Init.CachePrefetch.CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(hgfxmmu->Init.CachePrefetch.CacheLockBuffer));
assert_param(IS_GFXMMU_CACHE_FORCE(hgfxmmu->Init.CachePrefetch.CacheForce));
hgfxmmu->Instance->CR |= (hgfxmmu->Init.CachePrefetch.CacheLockBuffer |
hgfxmmu->Init.CachePrefetch.CacheForce);
}
}
if(hgfxmmu->Init.Interrupts.Activation == ENABLE)
{
assert_param(IS_GFXMMU_INTERRUPTS(hgfxmmu->Init.Interrupts.UsedInterrupts));
hgfxmmu->Instance->CR |= hgfxmmu->Init.Interrupts.UsedInterrupts;
}
/* Configure default value on GFXMMU_DVR register */
hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue;
/* Configure physical buffer adresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address;
hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address;
hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address;
hgfxmmu->Instance->B3CR = hgfxmmu->Init.Buffers.Buf3Address;
/* Force invalidate cache if cache is enabled */
if(hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
{
hgfxmmu->Instance->CCR |= GFXMMU_CACHE_FORCE_INVALIDATE;
}
/* Reset GFXMMU error code */
hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
/* Set GFXMMU to ready state */
hgfxmmu->State = HAL_GFXMMU_STATE_READY;
}
/* Return function status */
return status;
}
/**
* @brief De-initialize the GFXMMU.
* @param hgfxmmu GFXMMU handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check GFXMMU handle */
if(hgfxmmu == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
/* Disable all interrupts on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
GFXMMU_CR_AMEIE);
/* Call GFXMMU MSP de-init function */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
if(hgfxmmu->MspDeInitCallback == NULL)
{
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
}
hgfxmmu->MspDeInitCallback(hgfxmmu);
#else
HAL_GFXMMU_MspDeInit(hgfxmmu);
#endif
/* Set GFXMMU to reset state */
hgfxmmu->State = HAL_GFXMMU_STATE_RESET;
}
/* Return function status */
return status;
}
/**
* @brief Initialize the GFXMMU MSP.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_GFXMMU_MspInit could be implemented in the user file.
*/
}
/**
* @brief De-initialize the GFXMMU MSP.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_GFXMMU_MspDeInit could be implemented in the user file.
*/
}
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/**
* @brief Register a user GFXMMU callback
* to be used instead of the weak predefined callback.
* @param hgfxmmu GFXMMU handle.
* @param CallbackID ID of the callback to be registered.
* This parameter can be one of the following values:
* @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
* @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
* @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
* @param pCallback pointer to the callback function.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID,
pGFXMMU_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
else
{
if(HAL_GFXMMU_STATE_READY == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_ERROR_CB_ID :
hgfxmmu->ErrorCallback = pCallback;
break;
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = pCallback;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = pCallback;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Unregister a user GFXMMU callback.
* GFXMMU callback is redirected to the weak predefined callback.
* @param hgfxmmu GFXMMU handle.
* @param CallbackID ID of the callback to be unregistered.
* This parameter can be one of the following values:
* @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
* @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
* @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_GFXMMU_STATE_READY == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_ERROR_CB_ID :
hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
break;
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if(HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup GFXMMU_Exported_Functions_Group2 Operations functions
* @brief GFXMMU operation functions
*
@verbatim
==============================================================================
##### Operation functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Configure LUT.
(+) Force flush and/or invalidate of cache.
(+) Modify physical buffer adresses.
(+) Modify cache and pre-fetch parameters.
(+) Manage error.
@endverbatim
* @{
*/
/**
* @brief This function allows to copy LUT from flash to look up RAM.
* @param hgfxmmu GFXMMU handle.
* @param FirstLine First line enabled on LUT.
* This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
* @param LinesNumber Number of lines enabled on LUT.
* This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
* @param Address Start address of LUT in flash.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber,
uint32_t Address)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
/* Check GFXMMU state and coherent parameters */
if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
{
status = HAL_ERROR;
}
else
{
uint32_t current_address, current_line, lutxl_address, lutxh_address;
/* Initialize local variables */
current_address = Address;
current_line = 0U;
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
/* Copy LUT from flash to look up RAM */
while(current_line < LinesNumber)
{
*((uint32_t *)lutxl_address) = *((uint32_t *)current_address);
current_address += 4U;
*((uint32_t *)lutxh_address) = *((uint32_t *)current_address);
current_address += 4U;
lutxl_address += 8U;
lutxh_address += 8U;
current_line++;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to disable a range of LUT lines.
* @param hgfxmmu GFXMMU handle.
* @param FirstLine First line to disable on LUT.
* This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
* @param LinesNumber Number of lines to disable on LUT.
* This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
/* Check GFXMMU state and coherent parameters */
if((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
{
status = HAL_ERROR;
}
else
{
uint32_t current_line, lutxl_address, lutxh_address;
/* Initialize local variables */
current_line = 0U;
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
/* Disable LUT lines */
while(current_line < LinesNumber)
{
*((uint32_t *)lutxl_address) = 0U;
*((uint32_t *)lutxh_address) = 0U;
lutxl_address += 8U;
lutxh_address += 8U;
current_line++;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to configure one line of LUT.
* @param hgfxmmu GFXMMU handle.
* @param lutLine LUT line parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(lutLine->LineNumber));
assert_param(IS_GFXMMU_LUT_LINE_STATUS(lutLine->LineStatus));
assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->FirstVisibleBlock));
assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->LastVisibleBlock));
assert_param(IS_GFXMMU_LUT_LINE_OFFSET(lutLine->LineOffset));
/* Check GFXMMU state */
if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
uint32_t lutxl_address, lutxh_address;
/* Initialize local variables */
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * lutLine->LineNumber]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * lutLine->LineNumber) + 1U]);
/* Configure LUT line */
if(lutLine->LineStatus == GFXMMU_LUT_LINE_ENABLE)
{
/* Enable and configure LUT line */
*((uint32_t *)lutxl_address) = (lutLine->LineStatus |
(lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) |
(lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET));
*((uint32_t *)lutxh_address) = (uint32_t) lutLine->LineOffset;
}
else
{
/* Disable LUT line */
*((uint32_t *)lutxl_address) = 0U;
*((uint32_t *)lutxh_address) = 0U;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to force flush and/or invalidate of cache.
* @param hgfxmmu GFXMMU handle.
* @param ForceParam Force cache parameter.
* This parameter can be a values combination of @ref GFXMMU_CacheForceParam.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_CACHE_FORCE_ACTION(ForceParam));
/* Check GFXMMU state and cache status */
if(((hgfxmmu->Instance->CR & GFXMMU_CR_CE) != GFXMMU_CR_CE) || (hgfxmmu->State != HAL_GFXMMU_STATE_READY))
{
status = HAL_ERROR;
}
else
{
/* Force flush and/or invalidate cache on GFXMMU_CCR register */
hgfxmmu->Instance->CCR |= ForceParam;
}
/* Return function status */
return status;
}
/**
* @brief This function allows to modify physical buffer addresses.
* @param hgfxmmu GFXMMU handle.
* @param Buffers Buffers parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf0Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf1Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf2Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf3Address));
/* Check GFXMMU state */
if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
/* Modify physical buffer adresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = Buffers->Buf0Address;
hgfxmmu->Instance->B1CR = Buffers->Buf1Address;
hgfxmmu->Instance->B2CR = Buffers->Buf2Address;
hgfxmmu->Instance->B3CR = Buffers->Buf3Address;
}
/* Return function status */
return status;
}
/**
* @brief This function allows to modify cache and pre-fetch parameters.
* @param hgfxmmu GFXMMU handle.
* @param CachePrefetch Cache and pre-fetch parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,
GFXMMU_CachePrefetchTypeDef *CachePrefetch)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_FUNCTIONAL_STATE(CachePrefetch->Activation));
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
/* Check GFXMMU state */
if(hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
/* Modify cache and pre-fetch parameters on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_CE | GFXMMU_CR_CL | GFXMMU_CR_CLB | GFXMMU_CR_FC |
GFXMMU_CR_PD | GFXMMU_CR_OC | GFXMMU_CR_OB);
if(CachePrefetch->Activation == ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK(CachePrefetch->CacheLock));
assert_param(IS_GFXMMU_PREFETCH(CachePrefetch->Prefetch));
assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(CachePrefetch->OutterBufferability));
assert_param(IS_GFXMMU_OUTTER_CACHABILITY(CachePrefetch->OutterCachability));
hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
CachePrefetch->CacheLock |
CachePrefetch->Prefetch |
CachePrefetch->OutterBufferability |
CachePrefetch->OutterCachability);
if(CachePrefetch->CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(CachePrefetch->CacheLockBuffer));
assert_param(IS_GFXMMU_CACHE_FORCE(CachePrefetch->CacheForce));
hgfxmmu->Instance->CR |= (CachePrefetch->CacheLockBuffer |
CachePrefetch->CacheForce);
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function handles the GFXMMU interrupts.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu)
{
uint32_t flags, interrupts, error;
/* Read current flags and interrupts and determine which error occurs */
flags = hgfxmmu->Instance->SR;
interrupts = (hgfxmmu->Instance->CR & GFXMMU_CR_ITS_MASK);
error = (flags & interrupts);
if(error != 0U)
{
/* Clear flags on GFXMMU_FCR register */
hgfxmmu->Instance->FCR = error;
/* Update GFXMMU error code */
hgfxmmu->ErrorCode |= error;
/* Call GFXMMU error callback */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
hgfxmmu->ErrorCallback(hgfxmmu);
#else
HAL_GFXMMU_ErrorCallback(hgfxmmu);
#endif
}
}
/**
* @brief Error callback.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_GFXMMU_ErrorCallback could be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup GFXMMU_Exported_Functions_Group3 State functions
* @brief GFXMMU state functions
*
@verbatim
==============================================================================
##### State functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Get GFXMMU handle state.
(+) Get GFXMMU error code.
@endverbatim
* @{
*/
/**
* @brief This function allows to get the current GFXMMU handle state.
* @param hgfxmmu GFXMMU handle.
* @retval GFXMMU state.
*/
HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Return GFXMMU handle state */
return hgfxmmu->State;
}
/**
* @brief This function allows to get the current GFXMMU error code.
* @param hgfxmmu GFXMMU handle.
* @retval GFXMMU error code.
*/
uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu)
{
uint32_t error_code;
/* Enter in critical section */
__disable_irq();
/* Store and reset GFXMMU error code */
error_code = hgfxmmu->ErrorCode;
hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
/* Exit from critical section */
__enable_irq();
/* Return GFXMMU error code */
return error_code;
}
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
#endif /* GFXMMU */
#endif /* HAL_GFXMMU_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
+560
View File
@@ -0,0 +1,560 @@
/**
******************************************************************************
* @file stm32h7xx_hal_gpio.c
* @author MCD Application Team
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
[..]
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
(++) Input mode
(++) Analog mode
(++) Output mode
(++) Alternate function mode
(++) External interrupt/event lines
(+) During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
(+) All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
The external interrupt/event controller consists of up to 23 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure.
(++) In alternate mode is selection, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure.
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE (0x00000003U)
#define ANALOG_MODE (0x00000008U)
#define EXTI_MODE (0x10000000U)
#define GPIO_MODE_IT (0x00010000U)
#define GPIO_MODE_EVT (0x00020000U)
#define RISING_EDGE (0x00100000U)
#define FALLING_EDGE (0x00200000U)
#define GPIO_OUTPUT_TYPE (0x00000010U)
#if defined(DUAL_CORE)
#define EXTI_CPU1 (0x01000000U)
#define EXTI_CPU2 (0x02000000U)
#endif /*DUAL_CORE*/
#define GPIO_NUMBER (16U)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
This section provides functions allowing to initialize and de-initialize the GPIOs
to be ready for use.
@endverbatim
* @{
*/
/**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position = 0x00U;
uint32_t iocurrent;
uint32_t temp;
EXTI_Core_TypeDef *EXTI_CurrentCPU;
#if defined(DUAL_CORE) && defined(CORE_CM4)
EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
#else
EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
#endif
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00U)
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
if (iocurrent != 0x00U)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
temp &= ~(0xFU << ((position & 0x07U) * 4U));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
temp |= (GPIO_Init->Speed << (position * 2U));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT0 << position) ;
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
GPIOx->OTYPER = temp;
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2U];
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
SYSCFG->EXTICR[position >> 2U] = temp;
/* Clear EXTI line configuration */
temp = EXTI_CurrentCPU->IMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
temp |= iocurrent;
}
EXTI_CurrentCPU->IMR1 = temp;
temp = EXTI_CurrentCPU->EMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
temp |= iocurrent;
}
EXTI_CurrentCPU->EMR1 = temp;
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{
temp |= iocurrent;
}
EXTI->RTSR1 = temp;
temp = EXTI->FTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
{
temp |= iocurrent;
}
EXTI->FTSR1 = temp;
}
}
position++;
}
}
/**
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position = 0x00U;
uint32_t iocurrent;
uint32_t tmp;
EXTI_Core_TypeDef *EXTI_CurrentCPU;
#if defined(DUAL_CORE) && defined(CORE_CM4)
EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
#else
EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
#endif
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0x00U)
{
/* Get current io position */
iocurrent = GPIO_Pin & (1UL << position) ;
if (iocurrent != 0x00U)
{
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SYSCFG->EXTICR[position >> 2U];
tmp &= (0x0FUL << (4U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
tmp = 0x0FUL << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
/* Clear EXTI line configuration for Current CPU */
EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
/* Clear Rising Falling edge configuration */
EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO in Analog Mode */
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
}
position++;
}
}
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
{
bitstatus = GPIO_PIN_SET;
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
}
/**
* @brief Sets or clears the selected data port bit.
*
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
*
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
}
}
/**
* @brief Toggles the specified GPIO pins.
* @param GPIOx: Where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
}
else
{
GPIOx->BSRR = GPIO_Pin;
}
}
/**
* @brief Locks GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
* @param GPIO_Pin: specifies the port bit to be locked.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Apply lock key write sequence */
tmp |= GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK register. This read is mandatory to complete key lock sequence*/
tmp = GPIOx->LCKR;
/* read again in order to confirm lock is active */
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)
{
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
#if defined(DUAL_CORE) && defined(CORE_CM4)
if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U)
{
__HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
#else
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
#endif
}
/**
* @brief EXTI line detection callback.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_GPIO_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c
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/**
******************************************************************************
* @file stm32h7xx_hal_hsem.c
* @author MCD Application Team
* @brief HSEM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the semaphore peripheral:
* + Semaphore Take function (2-Step Procedure) , non blocking
* + Semaphore FastTake function (1-Step Procedure) , non blocking
* + Semaphore Status check
* + Semaphore Clear Key Set and Get
* + Release and release all functions
* + Semaphore notification enabling and disabling and callnack functions
* + IRQ handler management
*
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
(++) the semaphore ID from 0 to 31
(++) the process ID from 0 to 255
(#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
(++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
(#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
(++) the semaphore ID from 0_ID to 31
(++) It returns 1 if the given semaphore is taken otherwise (Free) zero
(#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
(++) the semaphore ID from 0 to 31
(++) the process ID from 0 to 255:
(++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
semaphore remains taken (locked)
(#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
This function takes as parameters :
(++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
(++) the Master ID:
(++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the
Key or the MasterID doesn't match, semaphores remains taken (locked)
(#)Semaphores Release all key functions:
(++) HAL_HSEM_SetClearKey() to set semaphore release all Key
(++) HAL_HSEM_GetClearKey() to get release all Key
(#)Semaphores notification functions :
(++) HAL_HSEM_ActivateNotification to activate a notification callback on
a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
semaphores (bitfield).
(++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
(++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
Used by the notification functions
*** HSEM HAL driver macros list ***
=============================================
[..] Below the list of most used macros in HSEM HAL driver.
(+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
[..] Example of use :
[..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
[..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example.
(+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
(+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
(+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
(+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
(+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup HSEM HSEM
* @brief HSEM HAL module driver
* @{
*/
#ifdef HAL_HSEM_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#if defined(DUAL_CORE)
#ifndef HSEM_R_MASTERID
#define HSEM_R_MASTERID HSEM_R_COREID
#endif
#ifndef HSEM_RLR_MASTERID
#define HSEM_RLR_MASTERID HSEM_RLR_COREID
#endif
#ifndef HSEM_CR_MASTERID
#define HSEM_CR_MASTERID HSEM_CR_COREID
#endif
#endif /* DUAL_CORE */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
* @{
*/
/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
* @brief HSEM Take and Release functions
*
@verbatim
==============================================================================
##### HSEM Take and Release functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Take a semaphore with 2 Step method
(+) Fast Take a semaphore with 1 Step method
(+) Check semaphore state Taken or not
(+) Release a semaphore
(+) Release all semaphore at once
@endverbatim
* @{
*/
/**
* @brief Take a semaphore in 2 Step mode.
* @param SemID: semaphore ID from 0 to 31
* @param ProcessID: Process ID from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
{
/* Check the parameters */
assert_param(IS_HSEM_SEMID(SemID));
assert_param(IS_HSEM_PROCESSID(ProcessID));
#if USE_MULTI_CORE_SHARED_CODE != 0U
/* First step write R register with MasterID, processID and take bit=1*/
HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
/* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
{
/*take success when MasterID and ProcessID match and take bit set*/
return HAL_OK;
}
#else
/* First step write R register with MasterID, processID and take bit=1*/
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
/* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
{
/*take success when MasterID and ProcessID match and take bit set*/
return HAL_OK;
}
#endif
/* Semaphore take fails*/
return HAL_ERROR;
}
/**
* @brief Fast Take a semaphore with 1 Step mode.
* @param SemID: semaphore ID from 0 to 31
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
{
/* Check the parameters */
assert_param(IS_HSEM_SEMID(SemID));
#if USE_MULTI_CORE_SHARED_CODE != 0U
/* Read the RLR register to take the semaphore */
if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
{
/*take success when MasterID match and take bit set*/
return HAL_OK;
}
#else
/* Read the RLR register to take the semaphore */
if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
{
/*take success when MasterID match and take bit set*/
return HAL_OK;
}
#endif
/* Semaphore take fails */
return HAL_ERROR;
}
/**
* @brief Check semaphore state Taken or not.
* @param SemID: semaphore ID
* @retval HAL HSEM state
*/
uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
{
return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
}
/**
* @brief Release a semaphore.
* @param SemID: semaphore ID from 0 to 31
* @param ProcessID: Process ID from 0 to 255
* @retval None
*/
void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
{
/* Check the parameters */
assert_param(IS_HSEM_SEMID(SemID));
assert_param(IS_HSEM_PROCESSID(ProcessID));
/* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */
#if USE_MULTI_CORE_SHARED_CODE != 0U
HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID));
#else
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
#endif
}
/**
* @brief Release All semaphore used by a given Master .
* @param Key: Semaphore Key , value from 0 to 0xFFFF
* @param CoreID: CoreID of the CPU that is using semaphores to be released
* @retval None
*/
void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
{
assert_param(IS_HSEM_KEY(Key));
assert_param(IS_HSEM_COREID(CoreID));
HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
}
/**
* @}
*/
/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
* @brief HSEM Set and Get Key functions.
*
@verbatim
==============================================================================
##### HSEM Set and Get Key functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Set semaphore Key
(+) Get semaphore Key
@endverbatim
* @{
*/
/**
* @brief Set semaphore Key .
* @param Key: Semaphore Key , value from 0 to 0xFFFF
* @retval None
*/
void HAL_HSEM_SetClearKey(uint32_t Key)
{
assert_param(IS_HSEM_KEY(Key));
MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
}
/**
* @brief Get semaphore Key .
* @retval Semaphore Key , value from 0 to 0xFFFF
*/
uint32_t HAL_HSEM_GetClearKey(void)
{
return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
}
/**
* @}
*/
/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
* @brief HSEM Notification functions.
*
@verbatim
==============================================================================
##### HSEM IRQ handler management and Notification functions #####
==============================================================================
[..] This section provides HSEM IRQ handler and Notification function.
@endverbatim
* @{
*/
/**
* @brief Activate Semaphore release Notification for a given Semaphores Mask .
* @param SemMask: Mask of Released semaphores
* @retval Semaphore Key
*/
void HAL_HSEM_ActivateNotification(uint32_t SemMask)
{
#if USE_MULTI_CORE_SHARED_CODE != 0U
/*enable the semaphore mask interrupts */
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/*Use interrupt line 0 for CPU1 Master */
HSEM->C1IER |= SemMask;
}
else /* HSEM_CPU2_COREID */
{
/*Use interrupt line 1 for CPU2 Master*/
HSEM->C2IER |= SemMask;
}
#else
HSEM_COMMON->IER |= SemMask;
#endif
}
/**
* @brief Deactivate Semaphore release Notification for a given Semaphores Mask .
* @param SemMask: Mask of Released semaphores
* @retval Semaphore Key
*/
void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
{
#if USE_MULTI_CORE_SHARED_CODE != 0U
/*enable the semaphore mask interrupts */
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/*Use interrupt line 0 for CPU1 Master */
HSEM->C1IER &= ~SemMask;
}
else /* HSEM_CPU2_COREID */
{
/*Use interrupt line 1 for CPU2 Master*/
HSEM->C2IER &= ~SemMask;
}
#else
HSEM_COMMON->IER &= ~SemMask;
#endif
}
/**
* @brief This function handles HSEM interrupt request
* @retval None
*/
void HAL_HSEM_IRQHandler(void)
{
uint32_t statusreg;
#if USE_MULTI_CORE_SHARED_CODE != 0U
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/* Get the list of masked freed semaphores*/
statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/
/*Disable Interrupts*/
HSEM->C1IER &= ~((uint32_t)statusreg);
/*Clear Flags*/
HSEM->C1ICR = ((uint32_t)statusreg);
}
else /* HSEM_CPU2_COREID */
{
/* Get the list of masked freed semaphores*/
statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/
/*Disable Interrupts*/
HSEM->C2IER &= ~((uint32_t)statusreg);
/*Clear Flags*/
HSEM->C2ICR = ((uint32_t)statusreg);
}
#else
/* Get the list of masked freed semaphores*/
statusreg = HSEM_COMMON->MISR;
/*Disable Interrupts*/
HSEM_COMMON->IER &= ~((uint32_t)statusreg);
/*Clear Flags*/
HSEM_COMMON->ICR = ((uint32_t)statusreg);
#endif
/* Call FreeCallback */
HAL_HSEM_FreeCallback(statusreg);
}
/**
* @brief Semaphore Released Callback.
* @param SemMask: Mask of Released semaphores
* @retval None
*/
__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(SemMask);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HSEM_FreeCallback can be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_HSEM_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
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/**
******************************************************************************
* @file stm32h7xx_hal_i2c_ex.c
* @author MCD Application Team
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Extended features functions
*
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32H7xx
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
(++) HAL_I2CEx_EnableWakeUp()
(++) HAL_I2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup I2CEx I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
(+) Configure Wake Up Feature
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Configure I2C Analog noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Enable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Enable fast mode plus driving capability for selected pin */
SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
}
/**
* @brief Disable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Disable fast mode plus driving capability for selected pin */
CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c
+1946
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s_ex.c
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/**
******************************************************************************
* @file stm32h7xx_hal_i2s_ex.c
* @author MCD Application Team
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S extension peripheral:
* + Extension features Functions
*
@verbatim
==============================================================================
##### I2S Extension features #####
==============================================================================
The I2S Full duplex feature is not supported by this HAL Driver
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c
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/**
******************************************************************************
* @file stm32h7xx_hal_iwdg.c
* @author MCD Application Team
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
* + Initialization and Start functions
* + IO operation functions
*
@verbatim
==============================================================================
##### IWDG Generic features #####
==============================================================================
[..]
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
if the main clock fails.
(+) Once the IWDG is started, the LSI is forced ON and both can not be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
(+) Debug mode : When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG1() or __HAL_DBGMCU_FREEZE2_IWDG2() and
__HAL_DBGMCU_UnFreeze_IWDG1 or __HAL_DBGMCU_UnFreeze2_IWDG2() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI frequency dispersion. STM32H7xx
devices provide the capability to measure the LSI frequency (LSI clock
connected internally to TIM16 CH1 input capture). The measured value
can be used to have an IWDG timeout with an acceptable accuracy.
##### How to use this driver #####
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts counting down.
(++) Enable write access to configuration registers:
IWDG_PR, IWDG_RLR and IWDG_WINR.
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(++) Wait for status flags to be reset.
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function with exact time base.
(+++) Else modify Window register. This will automatically reload
watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
*** IWDG HAL driver macros list ***
====================================
[..]
Below the list of most used macros in IWDG HAL driver:
(+) __HAL_IWDG_START: Enable the IWDG peripheral
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
the reload register
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_IWDG_MODULE_ENABLED
/** @addtogroup IWDG
* @brief IWDG HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to LSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IWDG_Exported_Functions
* @{
*/
/** @addtogroup IWDG_Exported_Functions_Group1
* @brief Initialization and Start functions.
*
@verbatim
===============================================================================
##### Initialization and Start functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the IWDG according to the specified parameters in the
IWDG_InitTypeDef of associated handle.
(+) Manage Window option.
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
is reloaded in order to exit function with correct time base.
@endverbatim
* @{
*/
/**
* @brief Initialize the IWDG according to the specified parameters in the
* IWDG_InitTypeDef and start watchdog. Before exiting function,
* watchdog is refreshed in order to have correct time base.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart;
/* Check the IWDG handle allocation */
if (hiwdg == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
/* Enable IWDG. LSI is turned on automatically */
__HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
0x5555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the Prescaler & Reload values to work with */
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
hiwdg->Instance->RLR = hiwdg->Init.Reload;
/* Check pending flag, if previous update not done, return timeout */
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while (hiwdg->Instance->SR != 0x00u)
{
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* If window parameter is different than current value, modify window
register */
if (hiwdg->Instance->WINR != hiwdg->Init.Window)
{
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
even if window feature is disabled, Watchdog will be reloaded by writing
windows register */
hiwdg->Instance->WINR = hiwdg->Init.Window;
}
else
{
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
}
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group2
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Refresh the IWDG.
@endverbatim
* @{
*/
/**
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
{
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_IWDG_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c
+4173
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c
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/**
******************************************************************************
* @file stm32h7xx_hal_ltdc_ex.c
* @author MCD Application Team
* @brief LTDC Extension HAL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
#if defined (LTDC) && defined (DSI)
/** @defgroup LTDCEx LTDCEx
* @brief LTDC HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
* @{
*/
/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the LTDC
@endverbatim
* @{
*/
/**
* @brief Retrieve common parameters from DSI Video mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
* the DSI video mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarity is inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
/* Retrieve vertical timing parameters from DSI */
hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U;
hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U;
hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
return HAL_OK;
}
/**
* @brief Retrieve common parameters from DSI Adapted command mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarities are inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC && DSI */
#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c
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/**
******************************************************************************
* @file stm32h7xx_hal_mdios.c
* @author MCD Application Team
* @brief MDIOS HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the MDIOS Peripheral.
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
*
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The MDIOS HAL driver can be used as follow:
(#) Declare a MDIOS_HandleTypeDef handle structure.
(#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API:
(##) Enable the MDIOS interface clock.
(##) MDIOS pins configuration:
(+++) Enable clocks for the MDIOS GPIOs.
(+++) Configure the MDIOS pins as alternate function.
(##) NVIC configuration if you need to use interrupt process:
(+++) Configure the MDIOS interrupt priority.
(+++) Enable the NVIC MDIOS IRQ handle.
(#) Program the Port Address and the Preamble Check in the Init structure.
(#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API.
(#) Perform direct slave read/write operations using the following APIs:
(##) Read the value of a DINn register: HAL_MDIOS_ReadReg()
(##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
(#) Get the Master read/write operations flags using the following APIs:
(##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
(##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
(#) Clear the read/write flags using the following APIs:
(##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress()
(##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()
(#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called
the MDIOS will generate an interrupt in the following cases:
(##) a DINn register written by the Master
(##) a DOUTn register read by the Master
(##) an error occur
(@) A callback is executed for each genereted interrupt, so the driver provide the following
HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()
(@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
and execute the previous callbacks
(#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
(##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
(GPIO, Clocks, NVIC configuration ...)
*** Callback registration ***
=============================================
The compilation define USE_HAL_MDIOS_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function @ref HAL_MDIOS_RegisterCallback() to register an interrupt callback.
Function @ref HAL_MDIOS_RegisterCallback() allows to register following callbacks:
(+) WriteCpltCallback : Write Complete Callback.
(+) ReadCpltCallback : Read Complete Callback.
(+) ErrorCallback : Error Callback.
(+) WakeUpCallback : Wake UP Callback
(+) MspInitCallback : MspInit Callback.
(+) MspDeInitCallback : MspDeInit Callback.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_MDIOS_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_MDIOS_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) WriteCpltCallback : Write Complete Callback.
(+) ReadCpltCallback : Read Complete Callback.
(+) ErrorCallback : Error Callback.
(+) WakeUpCallback : Wake UP Callback
(+) MspInitCallback : MspInit Callback.
(+) MspDeInitCallback : MspDeInit Callback.
By default, after the HAL_MDIOS_Init and when the state is HAL_MDIOS_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_MDIOS_WriteCpltCallback(), @ref HAL_MDIOS_ReadCpltCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak function in the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit only when
these callbacks are null (not registered beforehand).
if not, MspInit or MspDeInit are not null, the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_MDIOS_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_MDIOS_STATE_READY or HAL_MDIOS_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_MDIOS_RegisterCallback() before calling @ref HAL_MDIOS_DeInit
or HAL_MDIOS_Init function.
When The compilation define USE_HAL_MDIOS_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined (MDIOS)
/** @defgroup MDIOS MDIOS
* @brief HAL MDIOS module driver
* @{
*/
#ifdef HAL_MDIOS_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)
#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)
#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100U)
#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180U)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios);
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
* @{
*/
/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the MDIOS
(+) The following parameters can be configured:
(++) Port Address
(++) Preamble Check
@endverbatim
* @{
*/
/**
* @brief Initializes the MDIOS according to the specified parameters in
* the MDIOS_InitTypeDef and creates the associated handle .
* @param hmdios: pointer to a MDIOS_HandleTypeDef structure that contains
* the configuration information for MDIOS module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios)
{
uint32_t tmpcr;
/* Check the MDIOS handle allocation */
if(hmdios == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress));
assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck));
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
if(hmdios->State == HAL_MDIOS_STATE_RESET)
{
MDIOS_InitCallbacksToDefault(hmdios);
if(hmdios->MspInitCallback == NULL)
{
hmdios->MspInitCallback = HAL_MDIOS_MspInit;
}
/* Init the low level hardware */
hmdios->MspInitCallback(hmdios);
}
#else
if(hmdios->State == HAL_MDIOS_STATE_RESET)
{
/* Init the low level hardware */
HAL_MDIOS_MspInit(hmdios);
}
#endif /* (USE_HAL_MDIOS_REGISTER_CALLBACKS) */
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_BUSY;
/* Get the MDIOS CR value */
tmpcr = hmdios->Instance->CR;
/* Clear PORT_ADDRESS, DPC and EN bits */
tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS));
/* Set MDIOS control parametrs and enable the peripheral */
tmpcr |= (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT) |\
(hmdios->Init.PreambleCheck) | \
(MDIOS_CR_EN));
/* Write the MDIOS CR */
hmdios->Instance->CR = tmpcr;
hmdios->ErrorCode = HAL_MDIOS_ERROR_NONE;
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hmdios);
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitializes the MDIOS peripheral.
* @param hmdios: MDIOS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)
{
/* Check the MDIOS handle allocation */
if(hmdios == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_BUSY;
/* Disable the Peripheral */
__HAL_MDIOS_DISABLE(hmdios);
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
if(hmdios->MspDeInitCallback == NULL)
{
hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
}
/* DeInit the low level hardware */
hmdios->MspDeInitCallback(hmdios);
#else
/* DeInit the low level hardware */
HAL_MDIOS_MspDeInit(hmdios);
#endif /* (USE_HAL_MDIOS_REGISTER_CALLBACKS) */
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hmdios);
/* Return function status */
return HAL_OK;
}
/**
* @brief MDIOS MSP Init
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_MspInit can be implemented in the user file
*/
}
/**
* @brief MDIOS MSP DeInit
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_MspDeInit can be implemented in the user file
*/
}
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User MDIOS Callback
* To be used instead of the weak predefined callback
* @param hmdios mdios handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID
* @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID Read Complete Callback ID
* @arg @ref HAL_MDIOS_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_MDIOS_WAKEUP_CB_ID Wake Up Callback ID
* @arg @ref HAL_MDIOS_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, pMDIOS_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
/* Update the error code */
hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hmdios);
if(hmdios->State == HAL_MDIOS_STATE_READY)
{
switch (CallbackID)
{
case HAL_MDIOS_WRITE_COMPLETE_CB_ID :
hmdios->WriteCpltCallback = pCallback;
break;
case HAL_MDIOS_READ_COMPLETE_CB_ID :
hmdios->ReadCpltCallback = pCallback;
break;
case HAL_MDIOS_ERROR_CB_ID :
hmdios->ErrorCallback = pCallback;
break;
case HAL_MDIOS_WAKEUP_CB_ID :
hmdios->WakeUpCallback = pCallback;
break;
case HAL_MDIOS_MSPINIT_CB_ID :
hmdios->MspInitCallback = pCallback;
break;
case HAL_MDIOS_MSPDEINIT_CB_ID :
hmdios->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if(hmdios->State == HAL_MDIOS_STATE_RESET)
{
switch (CallbackID)
{
case HAL_MDIOS_MSPINIT_CB_ID :
hmdios->MspInitCallback = pCallback;
break;
case HAL_MDIOS_MSPDEINIT_CB_ID :
hmdios->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hmdios);
return status;
}
/**
* @brief Unregister an MDIOS Callback
* MDIOS callabck is redirected to the weak predefined callback
* @param hmdios mdios handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID
* @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID Read Complete Callback ID
* @arg @ref HAL_MDIOS_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_MDIOS_WAKEUP_CB_ID Wake Up Callback ID
* @arg @ref HAL_MDIOS_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hmdios);
if(hmdios->State == HAL_MDIOS_STATE_READY)
{
switch (CallbackID)
{
case HAL_MDIOS_WRITE_COMPLETE_CB_ID :
hmdios->WriteCpltCallback = HAL_MDIOS_WriteCpltCallback;
break;
case HAL_MDIOS_READ_COMPLETE_CB_ID :
hmdios->ReadCpltCallback = HAL_MDIOS_ReadCpltCallback;
break;
case HAL_MDIOS_ERROR_CB_ID :
hmdios->ErrorCallback = HAL_MDIOS_ErrorCallback;
break;
case HAL_MDIOS_WAKEUP_CB_ID :
hmdios->WakeUpCallback = HAL_MDIOS_WakeUpCallback;
break;
case HAL_MDIOS_MSPINIT_CB_ID :
hmdios->MspInitCallback = HAL_MDIOS_MspInit;
break;
case HAL_MDIOS_MSPDEINIT_CB_ID :
hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
break;
default :
/* Update the error code */
hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if(hmdios->State == HAL_MDIOS_STATE_RESET)
{
switch (CallbackID)
{
case HAL_MDIOS_MSPINIT_CB_ID :
hmdios->MspInitCallback = HAL_MDIOS_MspInit;
break;
case HAL_MDIOS_MSPDEINIT_CB_ID :
hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
break;
default :
/* Update the error code */
hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hmdios);
return status;
}
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions
* @brief MDIOS Read/Write functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
This subsection provides a set of functions allowing to manage the MDIOS
read and write operations.
(#) APIs that allow to the MDIOS to read/write from/to the
values of one of the DINn/DOUTn registers:
(+) Read the value of a DINn register: HAL_MDIOS_ReadReg()
(+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
(#) APIs that provide if there are some Slave registres have been
read or written by the Master:
(+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
(+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
(#) APIs that Clear the read/write flags:
(+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress()
(+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress()
(#) A set of Callbacks are provided:
(+) HAL_MDIOS_WriteCpltCallback()
(+) HAL_MDIOS_ReadCpltCallback()
(+) HAL_MDIOS_ErrorCallback()
@endverbatim
* @{
*/
/**
* @brief Writes to an MDIOS output register
* @param hmdios: mdios handle
* @param RegNum: MDIOS output register address
* @param Data: Data to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Get the addr of output register to be written by the MDIOS */
tmpreg = MDIOS_DOUT_BASE_ADDR + (4U * RegNum);
/* Write to DOUTn register */
*((uint32_t *)tmpreg) = Data;
/* Process Unlocked */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Reads an MDIOS input register
* @param hmdios: mdios handle
* @param RegNum: MDIOS input register address
* @param pData: pointer to Data
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Get the addr of input register to be read by the MDIOS */
tmpreg = MDIOS_DIN_BASE_ADDR + (4U * RegNum);
/* Read DINn register */
*pData = (uint16_t)(*((uint32_t *)tmpreg));
/* Process Unlocked */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Gets Written registers by MDIO master
* @param hmdios: mdios handle
* @retval bit map of written registers addresses
*/
uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios)
{
return hmdios->Instance->WRFR;
}
/**
* @brief Gets Read registers by MDIO master
* @param hmdios: mdios handle
* @retval bit map of read registers addresses
*/
uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios)
{
return hmdios->Instance->RDFR;
}
/**
* @brief Clears Write registers flag
* @param hmdios: mdios handle
* @param RegNum: registers addresses to be cleared
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
{
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Clear write registers flags */
hmdios->Instance->CWRFR |= (RegNum);
/* Release Lock */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Clears Read register flag
* @param hmdios: mdios handle
* @param RegNum: registers addresses to be cleared
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
{
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Clear read registers flags */
hmdios->Instance->CRDFR |= (RegNum);
/* Release Lock */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Enables Events for MDIOS peripheral
* @param hmdios: mdios handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)
{
/* Process Locked */
__HAL_LOCK(hmdios);
/* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */
__HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR));
/* Process Unlocked */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief This function handles MDIOS interrupt request.
* @param hmdios: MDIOS handle
* @retval None
*/
void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
{
/* Write Register Interrupt enabled ? */
if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != (uint32_t)RESET)
{
/* Write register flag */
if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != (uint32_t)RESET)
{
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
/*Call registered Write complete callback*/
hmdios->WriteCpltCallback(hmdios);
#else
/* Write callback function */
HAL_MDIOS_WriteCpltCallback(hmdios);
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/* Clear write register flag */
hmdios->Instance->CWRFR |= MDIOS_ALL_REG_FLAG;
}
}
/* Read Register Interrupt enabled ? */
if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != (uint32_t)RESET)
{
/* Read register flag */
if(HAL_MDIOS_GetReadRegAddress(hmdios) != (uint32_t)RESET)
{
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
/*Call registered Read complete callback*/
hmdios->ReadCpltCallback(hmdios);
#else
/* Read callback function */
HAL_MDIOS_ReadCpltCallback(hmdios);
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/* Clear read register flag */
hmdios->Instance->CRDFR |= MDIOS_ALL_REG_FLAG;
}
}
/* Error Interrupt enabled ? */
if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != (uint32_t)RESET)
{
/* All Errors Flag */
if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) != (uint32_t)RESET)
{
hmdios->ErrorCode |= HAL_MDIOS_ERROR_DATA;
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
/*Call registered Error callback*/
hmdios->ErrorCallback(hmdios);
#else
/* Error Callback */
HAL_MDIOS_ErrorCallback(hmdios);
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/* Clear errors flag */
__HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG);
}
hmdios->ErrorCode = HAL_MDIOS_ERROR_NONE;
}
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear MDIOS WAKEUP Exti pending bit */
__HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
/*Call registered WakeUp callback*/
hmdios->WakeUpCallback(hmdios);
#else
/* MDIOS WAKEUP callback */
HAL_MDIOS_WakeUpCallback(hmdios);
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
}
}
else
{
if(__HAL_MDIOS_WAKEUP_EXTID2_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear MDIOS WAKEUP Exti D2 pending bit */
__HAL_MDIOS_WAKEUP_EXTID2_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
/*Call registered WakeUp callback*/
hmdios->WakeUpCallback(hmdios);
#else
/* MDIOS WAKEUP callback */
HAL_MDIOS_WakeUpCallback(hmdios);
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
}
}
#else
/* check MDIOS WAKEUP exti flag */
if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear MDIOS WAKEUP Exti pending bit */
__HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
/*Call registered WakeUp callback*/
hmdios->WakeUpCallback(hmdios);
#else
/* MDIOS WAKEUP callback */
HAL_MDIOS_WakeUpCallback(hmdios);
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
}
#endif
}
/**
* @brief Write Complete Callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_WriteCpltCallback can be implemented in the user file
*/
}
/**
* @brief Read Complete Callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_ReadCpltCallback can be implemented in the user file
*/
}
/**
* @brief Error Callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_ErrorCallback can be implemented in the user file
*/
}
/**
* @brief MDIOS WAKEUP interrupt callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MDIOS_WakeUpCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions
* @brief MDIOS control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the MDIOS.
(+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
(+) HAL_MDIOS_GetError() API, returns the errors code of the HAL state machine.
@endverbatim
* @{
*/
/**
* @brief Gets MDIOS error code
* @param hmdios: mdios handle
* @retval mdios error code
*/
uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios)
{
/* return the error code */
return hmdios->ErrorCode;
}
/**
* @brief Return the MDIOS HAL state
* @param hmdios: mdios handle
* @retval HAL state
*/
HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios)
{
/* Return MDIOS state */
return hmdios->State;
}
/**
* @}
*/
/**
* @}
*/
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios)
{
/* Init the MDIOS Callback settings */
hmdios->WriteCpltCallback = HAL_MDIOS_WriteCpltCallback; /* Legacy weak WriteCpltCallback */
hmdios->ReadCpltCallback = HAL_MDIOS_ReadCpltCallback; /* Legacy weak ReadCpltCallback */
hmdios->ErrorCallback = HAL_MDIOS_ErrorCallback; /* Legacy weak ErrorCallback */
hmdios->WakeUpCallback = HAL_MDIOS_WakeUpCallback; /* Legacy weak WakeUpCallback */
}
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
/**
* @}
*/
#endif /* HAL_MDIOS_MODULE_ENABLED */
/**
* @}
*/
#endif /* MDIOS */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
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/**
******************************************************************************
* @file stm32h7xx_hal_mmc_ex.c
* @author MCD Application Team
* @brief MMC card Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
* + Extended features functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The MMC Extension HAL driver can be used as follows:
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
(+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup MMCEx MMCEx
* @brief MMC Extended HAL module driver
* @{
*/
#ifdef HAL_MMC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup MMCEx_Exported_Functions
* @{
*/
/** @addtogroup MMCEx_Exported_Functions_Group1
* @brief Multibuffer functions
*
@verbatim
==============================================================================
##### Multibuffer functions #####
==============================================================================
[..]
This section provides functions allowing to configure the multibuffer mode and start read and write
multibuffer mode for MMC HAL driver.
@endverbatim
* @{
*/
/**
* @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
* @param hmmc: MMC handle
* @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
* @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
* @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize)
{
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ;
hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ;
hmmc->Instance->IDMABSIZE= (uint32_t) (MMC_BLOCKSIZE * BufferSize);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
* @param hmmc: MMC handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t errorstate;
uint32_t add = BlockAdd;
if(hmmc->State == HAL_MMC_STATE_READY)
{
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_BUSY;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
/* Read Blocks in DMA mode */
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
* @param hmmc: MMC handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t add = BlockAdd;
if(hmmc->State == HAL_MMC_STATE_READY)
{
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_BUSY;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
/* Write Blocks in DMA mode */
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Change the DMA Buffer0 or Buffer1 address on the fly.
* @param hmmc: pointer to a MMC_HandleTypeDef structure.
* @param Buffer: the buffer to be changed, This parameter can be one of
* the following values: MMC_DMA_BUFFER0 or MMC_DMA_BUFFER1
* @param pDataBuffer: The new address
* @note The BUFFER0 address can be changed only when the current transfer use
* BUFFER1 and the BUFFER1 address can be changed only when the current
* transfer use BUFFER0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
{
if(Buffer == MMC_DMA_BUFFER0)
{
/* change the buffer0 address */
hmmc->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
}
else
{
/* change the memory1 address */
hmmc->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_MMC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32h7xx_hal_opamp_ex.c
* @author MCD Application Team
* @brief Extended OPAMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
* peripheral:
* + Extended Initialization and de-initialization functions
* + Extended Peripheral Control functions
*
@verbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup OPAMPEx OPAMPEx
* @brief OPAMP Extended HAL module driver
* @{
*/
#ifdef HAL_OPAMP_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
* @{
*/
/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
* @brief Extended operation functions
*
@verbatim
===============================================================================
##### Extended IO operation functions #####
===============================================================================
[..]
(+) OPAMP Self calibration.
@endverbatim
* @{
*/
/**
* @brief Run the self calibration of 2 OPAMPs in parallel.
* @note Trimming values (PMOS & NMOS) are updated and user trimming is
* enabled is calibration is successful.
* @note Calibration is performed in the mode specified in OPAMP init
* structure (mode normal or low power). To perform calibration for
* both modes, repeat this function twice after OPAMP init structure
* accordingly updated.
* @param hopamp1 handle
* @param hopamp2 handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t trimmingvaluen1;
uint32_t trimmingvaluep1;
uint32_t trimmingvaluen2;
uint32_t trimmingvaluep2;
/* Selection of register of trimming depending on power mode: OTR or HSOTR */
__IO uint32_t* tmp_opamp1_reg_trimming;
__IO uint32_t* tmp_opamp2_reg_trimming;
uint32_t delta;
uint32_t opampmode1;
uint32_t opampmode2;
if((hopamp1 == NULL) || (hopamp2 == NULL))
{
status = HAL_ERROR;
}
/* Check if OPAMP in calibration mode and calibration not yet enable */
else if(hopamp1->State != HAL_OPAMP_STATE_READY)
{
status = HAL_ERROR;
}
else if(hopamp2->State != HAL_OPAMP_STATE_READY)
{
status = HAL_ERROR;
}
else
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
/* Set Calibration mode */
/* Non-inverting input connected to calibration reference voltage. */
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
/* Save OPAMP mode */
opampmode1 = READ_BIT(hopamp1->Instance->CSR,OPAMP_CSR_VMSEL);
opampmode2 = READ_BIT(hopamp2->Instance->CSR,OPAMP_CSR_VMSEL);
/* Use of standalone mode */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
/* user trimming values are used for offset calibration */
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
/* Select trimming settings depending on power mode */
if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
{
tmp_opamp1_reg_trimming = &OPAMP1->OTR;
}
else
{
tmp_opamp1_reg_trimming = &OPAMP1->HSOTR;
}
if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
{
tmp_opamp2_reg_trimming = &OPAMP2->OTR;
}
else
{
tmp_opamp2_reg_trimming = &OPAMP2->HSOTR;
}
/* Enable calibration */
SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
/* 1st calibration - N */
/* Select 90U% VREF */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
/* Enable the selected opamp */
SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
/* Init trimming counter */
/* Medium value */
trimmingvaluen1 = 16U;
trimmingvaluen2 = 16U;
delta = 8U;
while (delta != 0U)
{
/* Set candidate trimming */
/* OPAMP_POWERMODE_NORMAL */
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
{
/* OPAMP_CSR_CALOUT is Low try higher trimming */
trimmingvaluen1 += delta;
}
else
{
/* OPAMP_CSR_CALOUT is High try lower trimming */
trimmingvaluen1 -= delta;
}
if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
{
/* OPAMP_CSR_CALOUT is Low try higher trimming */
trimmingvaluen2 += delta;
}
else
{
/* OPAMP_CSR_CALOUT is High try lower trimming */
trimmingvaluen2 -= delta;
}
/* Divide range by 2 to continue dichotomy sweep */
delta >>= 1U;
}
/* Still need to check if right calibration is current value or one step below */
/* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */
/* Set candidate trimming */
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) != 0U)
{
/* Trimming value is actually one value more */
trimmingvaluen1++;
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
}
if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) != 0U)
{
/* Trimming value is actually one value more */
trimmingvaluen2++;
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
}
/* 2nd calibration - P */
/* Select 10U% VREF */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
/* Init trimming counter */
/* Medium value */
trimmingvaluep1 = 16U;
trimmingvaluep2 = 16U;
delta = 8U;
while (delta != 0U)
{
/* Set candidate trimming */
/* OPAMP_POWERMODE_NORMAL */
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
{
/* OPAMP_CSR_CALOUT is Low try higher trimming */
trimmingvaluep1 += delta;
}
else
{
/* OPAMP_CSR_CALOUT is HIGH try lower trimming */
trimmingvaluep1 -= delta;
}
if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
{
/* OPAMP_CSR_CALOUT is Low try higher trimming */
trimmingvaluep2 += delta;
}
else
{
/* OPAMP_CSR_CALOUT is High try lower trimming */
trimmingvaluep2 -= delta;
}
/* Divide range by 2 to continue dichotomy sweep */
delta >>= 1U;
}
/* Still need to check if right calibration is current value or one step below */
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
/* Set candidate trimming */
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
{
/* Trimming value is actually one value more */
trimmingvaluep1++;
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVERTING));
}
if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
{
/* Trimming value is actually one value more */
trimmingvaluep2++;
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVERTING));
}
/* Disable calibration & set normal mode (operating mode) */
CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
/* Disable the OPAMPs */
CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
/* Self calibration is successful */
/* Store calibration (user trimming) results in init structure. */
/* Set user trimming mode */
hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
/* Affect calibration parameters depending on mode normal/high speed */
if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
{
/* Write calibration result N */
hopamp1->Init.TrimmingValueN = trimmingvaluen1;
/* Write calibration result P */
hopamp1->Init.TrimmingValueP = trimmingvaluep1;
}
else
{
/* Write calibration result N */
hopamp1->Init.TrimmingValueNHighSpeed = trimmingvaluen1;
/* Write calibration result P */
hopamp1->Init.TrimmingValuePHighSpeed = trimmingvaluep1;
}
if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_HIGHSPEED)
{
/* Write calibration result N */
hopamp2->Init.TrimmingValueN = trimmingvaluen2;
/* Write calibration result P */
hopamp2->Init.TrimmingValueP = trimmingvaluep2;
}
else
{
/* Write calibration result N */
hopamp2->Init.TrimmingValueNHighSpeed = trimmingvaluen2;
/* Write calibration result P */
hopamp2->Init.TrimmingValuePHighSpeed = trimmingvaluep2;
}
/* Update OPAMP state */
hopamp1->State = HAL_OPAMP_STATE_READY;
hopamp2->State = HAL_OPAMP_STATE_READY;
/* Restore OPAMP mode after calibration */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_VMSEL, opampmode1);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_VMSEL, opampmode2);
}
return status;
}
/**
* @}
*/
/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
(+) OPAMP unlock.
@endverbatim
* @{
*/
/**
* @brief Unlock the selected OPAMP configuration.
* @note This function must be called only when OPAMP is in state "locked".
* @param hopamp: OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
if(hopamp == NULL)
{
status = HAL_ERROR;
}
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
/* OPAMP state changed to locked */
hopamp->State = HAL_OPAMP_STATE_BUSY;
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_OPAMP_MODULE_ENABLED */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c
+3006
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c
+998
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@@ -0,0 +1,998 @@
/**
******************************************************************************
* @file stm32h7xx_hal_otfdec.c
* @author MCD Application Team
* @brief OTFDEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the On-The-Fly Decryption (OTFDEC) peripheral:
* + Initialization and de-initialization functions
* + Region setting/enable functions
* + Peripheral State functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The OTFDEC HAL driver can be used as follows:
(#) Declare an OTFDEC_HandleTypeDef handle structure (eg. OTFDEC_HandleTypeDef hotfdec).
(#) Initialize the OTFDEC low level resources by implementing the HAL_OTFDEC_MspInit() API:
(++) Enable the OTFDEC interface clock.
(++) NVIC configuration if interrupts are used
(+++) Configure the OTFDEC interrupt priority.
(+++) Enable the NVIC OTFDEC IRQ handle.
(#) Initialize the OTFDEC peripheral by calling the HAL_OTFDEC_Init() API.
(#) For each region,
(++) Configure the region deciphering mode by calling the HAL_OTFDEC_RegionSetMode() API.
(++) Write the region Key by calling the HAL_OTFDEC_RegionSetKey() API. If desired,
read the key CRC by calling HAL_OTFDEC_RegionGetKeyCRC() API and compare the
result with the theoretically expected CRC.
(++) Initialize the OTFDEC region config structure with the Nonce, protected
region start and end addresses and firmware version, and wrap-up the region
configuration by calling HAL_OTFDEC_RegionConfig() API.
(#) At this point, the OTFDEC region configuration is done and the deciphering
is enabled. The region can be deciphered on the fly after having made sure
the OctoSPI is configured in memory-mapped mode.
[..]
(@) Warning: the OTFDEC deciphering is based on a different endianness compared
to the AES-CTR as implemented in the AES peripheral. E.g., if the OTFEC
resorts to the Key (B0, B1, B2, B3) where Bi are 32-bit longwords and B0
is the Least Significant Word, the AES has to be configured with the Key
(B3, B2, B1, B0) to report the same result (with the same swapping applied
to the Initialization Vector).
[..]
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_OTFDEC_RegisterCallback()
to register an interrupt callback.
[..]
Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : OTFDEC error callback
(+) MspInitCallback : OTFDEC Msp Init callback
(+) MspDeInitCallback : OTFDEC Msp DeInit callback
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default
weak function.
[..]
@ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : OTFDEC error callback
(+) MspInitCallback : OTFDEC Msp Init callback
(+) MspDeInitCallback : OTFDEC Msp DeInit callback
[..]
By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET
all callbacks are set to the corresponding weak functions:
example @ref HAL_OTFDEC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit()
or @ref HAL_OTFDEC_Init() function.
[..]
When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup OTFDEC OTFDEC
* @brief OTFDEC HAL module driver.
* @{
*/
#ifdef HAL_OTFDEC_MODULE_ENABLED
#if defined(OTFDEC1)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup OTFDEC_Exported_Functions
* @{
*/
/** @defgroup OTFDEC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Initialize the OTFDEC peripheral and create the associated handle.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec)
{
/* Check the OTFDEC handle allocation */
if(hotfdec == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
if(hotfdec->State == HAL_OTFDEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
__HAL_UNLOCK(hotfdec);
#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
/* Init the OTFDEC Callback settings */
hotfdec->ErrorCallback = HAL_OTFDEC_ErrorCallback; /* Legacy weak callback */
if (hotfdec->MspInitCallback == NULL)
{
hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware */
hotfdec->MspInitCallback(hotfdec);
#else
/* Init the low level hardware */
HAL_OTFDEC_MspInit(hotfdec);
#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
}
/* Change the OTFDEC state */
hotfdec->State = HAL_OTFDEC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the OTFDEC peripheral.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OTFDEC_DeInit(OTFDEC_HandleTypeDef *hotfdec)
{
/* Check the OTFDEC handle allocation */
if(hotfdec == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
/* Change the OTFDEC state */
hotfdec->State = HAL_OTFDEC_STATE_BUSY;
#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
if (hotfdec->MspDeInitCallback == NULL)
{
hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: CLOCK, NVIC */
hotfdec->MspDeInitCallback(hotfdec);
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_OTFDEC_MspDeInit(hotfdec);
#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
/* Change the OTFDEC state */
hotfdec->State = HAL_OTFDEC_STATE_RESET;
/* Reset OTFDEC error status */
hotfdec->ErrorCode = HAL_OTFDEC_ERROR_NONE;
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the OTFDEC MSP.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval None
*/
__weak void HAL_OTFDEC_MspInit(OTFDEC_HandleTypeDef *hotfdec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hotfdec);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_OTFDEC_MspInit can be implemented in the user file.
*/
}
/**
* @brief DeInitialize OTFDEC MSP.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval None
*/
__weak void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hotfdec);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_OTFDEC_MspDeInit can be implemented in the user file.
*/
}
#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User OTFDEC Callback
* To be used instead of the weak predefined callback
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_OTFDEC_ERROR_CB_ID OTFDEC error callback ID
* @arg @ref HAL_OTFDEC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_OTFDEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID, pOTFDEC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hotfdec->State == HAL_OTFDEC_STATE_READY)
{
switch (CallbackID)
{
case HAL_OTFDEC_ERROR_CB_ID :
hotfdec->ErrorCallback = pCallback;
break;
case HAL_OTFDEC_MSPINIT_CB_ID :
hotfdec->MspInitCallback = pCallback;
break;
case HAL_OTFDEC_MSPDEINIT_CB_ID :
hotfdec->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_OTFDEC_STATE_RESET == hotfdec->State)
{
switch (CallbackID)
{
case HAL_OTFDEC_MSPINIT_CB_ID :
hotfdec->MspInitCallback = pCallback;
break;
case HAL_OTFDEC_MSPDEINIT_CB_ID :
hotfdec->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a OTFDEC Callback
* OTFDEC callback is redirected to the weak predefined callback
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_OTFDEC_ERROR_CB_ID OTFDEC error callback ID
* @arg @ref HAL_OTFDEC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_OTFDEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (hotfdec->State == HAL_OTFDEC_STATE_READY)
{
switch (CallbackID)
{
case HAL_OTFDEC_ERROR_CB_ID :
hotfdec->ErrorCallback = HAL_OTFDEC_ErrorCallback;
break;
case HAL_OTFDEC_MSPINIT_CB_ID :
hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
break;
case HAL_OTFDEC_MSPDEINIT_CB_ID :
hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_OTFDEC_STATE_RESET == hotfdec->State)
{
switch (CallbackID)
{
case HAL_OTFDEC_MSPINIT_CB_ID :
hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
break;
case HAL_OTFDEC_MSPDEINIT_CB_ID :
hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup OTFDEC_Exported_Functions_Group2 OTFDEC IRQ handler management
* @brief OTFDEC IRQ handler.
*
@verbatim
==============================================================================
##### OTFDEC IRQ handler management #####
==============================================================================
[..] This section provides OTFDEC IRQ handler function.
@endverbatim
* @{
*/
/**
* @brief Handle OTFDEC interrupt request.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval None
*/
void HAL_OTFDEC_IRQHandler(OTFDEC_HandleTypeDef *hotfdec)
{
uint32_t isr_reg;
isr_reg = READ_REG(hotfdec->Instance->ISR);
if ((isr_reg & OTFDEC_ISR_SEIF) == OTFDEC_ISR_SEIF)
{
SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_SEIF );
hotfdec->ErrorCode |= HAL_OTFDEC_SECURITY_ERROR;
}
if ((isr_reg & OTFDEC_ISR_XONEIF) == OTFDEC_ISR_XONEIF)
{
SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_XONEIF );
hotfdec->ErrorCode |= HAL_OTFDEC_EXECUTE_ERROR;
}
if ((isr_reg & OTFDEC_ISR_KEIF) == OTFDEC_ISR_KEIF)
{
SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_KEIF );
hotfdec->ErrorCode |= HAL_OTFDEC_KEY_ERROR;
}
#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
hotfdec->ErrorCallback(hotfdec);
#else
HAL_OTFDEC_ErrorCallback(hotfdec);
#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
}
/**
* @brief OTFDEC error callback.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval None
*/
__weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hotfdec);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_OTFDEC_ErrorCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral control functions.
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection permits to configure the OTFDEC peripheral
@endverbatim
* @{
*/
/**
* @brief Lock region keys.
* @note Writes to this region KEYRx registers are ignored until next OTFDEC reset.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the keys of which are locked
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
OTFDEC_Region_TypeDef * region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_KEYLOCK );
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @brief Set region keys.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the keys of which are set
* @param pKey pointer at set of keys
* @note The API reads the key CRC computed by the peripheral and compares it with thzt
* theoretically expected. An error is reported if they are different.
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey)
{
OTFDEC_Region_TypeDef * region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
if (pKey == NULL)
{
return HAL_ERROR;
}
else
{
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Set Key */
WRITE_REG( region->REG_KEYR0, pKey[0]);
__DSB();
__ISB();
WRITE_REG( region->REG_KEYR1, pKey[1]);
__DSB();
__ISB();
WRITE_REG( region->REG_KEYR2, pKey[2]);
__DSB();
__ISB();
WRITE_REG( region->REG_KEYR3, pKey[3]);
/* Compute theoretically expected CRC and compare it with that reported by the peripheral */
if (HAL_OTFDEC_KeyCRCComputation(pKey) != HAL_OTFDEC_RegionGetKeyCRC(hotfdec, RegionIndex))
{
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
}
/**
* @brief Set region mode.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the mode of which is set
* @param mode This parameter can be only:
* @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY Only instruction accesses are decrypted
* @arg @ref OTFDEC_REG_MODE_DATA_ACCESSES_ONLY Only data accesses are decrypted
* @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES All read accesses are decrypted (instruction or data)
* @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER Only instruction accesses are decrypted with proprietary cipher activated
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode)
{
OTFDEC_Region_TypeDef * region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
assert_param(IS_OTFDEC_REGION_OPERATING_MODE(mode));
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Set mode */
MODIFY_REG(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_MODE, mode);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @brief Set region configuration.
* @note Region deciphering is enabled at the end of this function
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region that is configured
* @param Config pointer on structure containing the region configuration parameters
* @param lock configuration lock enable or disable parameter
* This parameter can be one of the following values:
* @arg @ref OTFDEC_REG_CONFIGR_LOCK_DISABLE OTFDEC region configuration is not locked
* @arg @ref OTFDEC_REG_CONFIGR_LOCK_ENABLE OTFDEC region configuration is locked
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
{
OTFDEC_Region_TypeDef * region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
assert_param(IS_OTFDEC_REGION_CONFIG_LOCK(lock));
if (Config == NULL)
{
return HAL_ERROR;
}
else
{
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Set Nonce */
WRITE_REG( region->REG_NONCER0, Config->Nonce[0]);
WRITE_REG( region->REG_NONCER1, Config->Nonce[1]);
/* Write region protected area start and end addresses */
WRITE_REG( region->REG_START_ADDR, Config->StartAddress);
WRITE_REG( region->REG_END_ADDR, Config->EndAddress);
/* Write Version */
MODIFY_REG( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION, (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos );
/* Enable region deciphering or enciphering (depending of OTFDEC_CR ENC bit setting) */
SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
/* Lock the region configuration according to lock parameter value */
if (lock == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
{
SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE);
}
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
}
/**
* @brief Compute Key CRC
* @param pKey pointer at set of keys
* @retval CRC value
*/
uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey)
{
uint8_t crc7_poly = 0x7;
uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U};
uint8_t i;
uint8_t crc = 0;
uint32_t j, keyval, k;
uint32_t * temp = pKey;
for (j = 0U; j < 4U; j++)
{
keyval = *temp;
temp++;
if (j == 0U)
{
keyval ^= key_strobe[0];
}
else
{
keyval ^= (key_strobe[j] << 24) | ((uint32_t)crc << 16) | (key_strobe[j] << 8) | crc;
}
crc = 0;
for (i = 0; i < (uint8_t)32; i++)
{
k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31-i))&((uint8_t)0xF)))) & 1U;
crc <<= 1;
if (k != 0U)
{
crc ^= crc7_poly;
}
}
crc^=(uint8_t)0x55;
}
return (uint32_t) crc;
}
/**
* @brief Enable region deciphering.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the deciphering is enabled
* @note An error is reported when the configuration is locked.
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
OTFDEC_Region_TypeDef * region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
if (READ_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
{
/* Configuration is locked, REG_EN bit can't be modified */
__HAL_UNLOCK(hotfdec);
return HAL_ERROR;
}
/* Enable region processing */
SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @brief Disable region deciphering.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the deciphering is disabled
* @note An error is reported when the configuration is locked.
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
OTFDEC_Region_TypeDef * region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
if (READ_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
{
/* Configuration is locked, REG_EN bit can't be modified */
__HAL_UNLOCK(hotfdec);
return HAL_ERROR;
}
/* Disable region processing */
CLEAR_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions
* @brief Peripheral State functions.
*
@verbatim
==============================================================================
##### Peripheral State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the OTFDEC state.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval HAL state
*/
HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec)
{
return hotfdec->State;
}
/**
* @brief Return region keys CRC.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the keys CRC of which is read
* @retval Key CRC
*/
uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
OTFDEC_Region_TypeDef * region;
uint32_t address;
uint32_t keycrc;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
keycrc = (READ_REG( region->REG_CONFIGR )) & OTFDEC_REG_CONFIGR_KEYCRC;
keycrc >>= OTFDEC_REG_CONFIGR_KEYCRC_Pos;
return keycrc;
}
/**
* @brief Return region configuration parameters.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the configuration of which is read
* @param Config pointer on structure that will be filled up with the region configuration parameters
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config)
{
OTFDEC_Region_TypeDef * region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
if (Config == NULL)
{
return HAL_ERROR;
}
else
{
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Read Nonce */
Config->Nonce[0] = READ_REG(region->REG_NONCER0);
Config->Nonce[1] = READ_REG(region->REG_NONCER1);
/* Read Addresses */
Config->StartAddress = READ_REG(region->REG_START_ADDR);
Config->EndAddress = READ_REG(region->REG_END_ADDR);
/* Read Version */
Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) & OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos;
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* OTFDEC1 */
#endif /* HAL_OTFDEC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c
+2201
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c
+348
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/**
******************************************************************************
* @file stm32h7xx_hal_pcd_ex.c
* @author MCD Application Team
* @brief PCD Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Extended features functions
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup PCDEx PCDEx
* @brief PCD Extended HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Update FIFO configuration
@endverbatim
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief Set Tx FIFO
* @param hpcd PCD handle
* @param fifo The number of Tx fifo
* @param size Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
uint8_t i;
uint32_t Tx_Offset;
/* TXn min size = 16 words. (n : Transmit FIFO index)
When a TxFIFO is not used, the Configuration should be as follows:
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txm can use the space allocated for Txn.
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txn should be configured with the minimum space of 16 words
The FIFO is used optimally when used TxFIFOs are allocated in the top
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
Tx_Offset = hpcd->Instance->GRXFSIZ;
if (fifo == 0U)
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
}
else
{
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
for (i = 0U; i < (fifo - 1U); i++)
{
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
}
return HAL_OK;
}
/**
* @brief Set Rx FIFO
* @param hpcd PCD handle
* @param size Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
hpcd->Instance->GRXFSIZ = size;
return HAL_OK;
}
/**
* @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 1U;
hpcd->LPM_State = LPM_L0;
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
/**
* @brief Deactivate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 0U;
USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
/**
* @brief Handle BatteryCharging Process.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t tickstart = HAL_GetTick();
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
/* Wait Detect flag or a timeout is happen*/
while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > 1000U)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
}
}
/* Right response got */
HAL_Delay(200U);
/* Check Detect flag*/
if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
/*Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
{
/* Case of Standard Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
{
/* case Dedicated Charging Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* case Charging Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/* Battery Charging capability discovery finished */
(void)HAL_PCDEx_DeActivateBCD(hpcd);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
/**
* @brief Activate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
/* Power Down USB tranceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
/* Enable Battery charging */
USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
hpcd->battery_charging_active = 1U;
return HAL_OK;
}
/**
* @brief Deactivate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
/* Disable Battery charging */
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
hpcd->battery_charging_active = 0U;
return HAL_OK;
}
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @brief Send LPM message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_LPM_Callback could be implemented in the user file
*/
}
/**
* @brief Send BatteryCharging message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_BCD_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c
+1781
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
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/**
******************************************************************************
* @file stm32h7xx_hal_pwr.c
* @author MCD Application Team
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Initialization and de-initialization functions.
* + Peripheral Control functions.
* + Interrupt Handling functions.
@verbatim
==============================================================================
##### PWR peripheral overview #####
==============================================================================
[..]
(#) The Power control (PWR) provides an overview of the supply architecture
for the different power domains and of the supply configuration
controller.
In the H7 family, the number of power domains is different between
device lines. This difference is due to characteristics of each device.
(#) Domain architecture overview for the different H7 lines:
(+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
These devices have 3 power domains (D1, D2 and D3).
The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
peripherals. The D2 domain contains peripherals and a CPU
(Cortex-M4). The D3 domain contains the system control, I/O logic
and low-power peripherals.
(+) STM32H743, STM32H753, STM32H742 and STM32H750 devices have 3 power
domains (D1, D2 and D3).
The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
peripherals. The D2 domain contains peripherals. The D3 domains
contains the system control, I/O logic and low-power peripherals.
(+) STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx devices have 2
power domains (CD and SRD).
The core domain (CD) contains a CPU (Cortex-M7), a Flash
memory and peripherals. The SmartRun domain contains the system
control, I/O logic and low-power peripherals.
(#) Every entity have low power mode as decribed below :
(#) The CPU low power modes are :
(+) CPU CRUN.
(+) CPU CSLEEP.
(+) CPU CSTOP.
(#) The domain low power modes are :
(+) DRUN.
(+) DSTOP.
(+) DSTANDBY.
(#) The SYSTEM low power modes are :
(+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
Standby. In Run* mode, the performance is limited and the
system supply configuration shall be programmed. The system
enters Run mode only when the ACTVOSRDY bit in PWR control
status register 1 (PWR_CSR1) is set to 1.
(+) RUN.
(+) STOP.
(+) STANDBY.
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Power management peripheral is active by default at startup level in
STM32h7xx lines.
(#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
to enable/disable access to the backup domain (RTC registers, RTC backup
data registers and backup SRAM).
(#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
mode and voltage threshold) in order to set up the Power Voltage Detector,
then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() functions to start
and stop the PVD detection.
(+) PVD level could be one of the following values :
(++) 1V95
(++) 2V1
(++) 2V25
(++) 2V4
(++) 2V55
(++) 2V7
(++) 2V85
(++) External voltage level
(#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
with the right parameter to configure the wake up pin polarity (Low or
High) and to enable and disable it.
(#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
mode. Wake-up from SLEEP mode could be following to an event or an
interrupt according to low power mode intrinsic request called (__WFI()
or __WFE()).
Please ensure to clear all CPU pending events by calling
HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
in SLEEP mode with __WFE() entry.
(#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
mode for single core devices. For dual core devices, this API will enter
the domain (containing Cortex-Mx that executing this function) in DSTOP
mode. According to the used parameter, user could select the regulator to
be kept actif in low power mode and wake-up event type.
Please ensure to clear all CPU pending events by calling
HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
in CSTOP mode with __WFE() entry.
(#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
STANDBY mode for single core devices. For dual core devices, this API
will enter the domain (containing Cortex-Mx that executing this function)
in DSTANDBY mode.
(#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
enable and disable the Cortex-Mx re-entring in SLEEP mode after an
interruption handling is over.
(#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
to configure the Cortex-Mx to wake-up after any pending event / interrupt
even if it's disabled or has insufficient priority to cause exception
entry.
(#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
request.
*** PWR HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in PWR HAL driver.
(+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
regulator output voltage.
(+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags.
(+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
#ifdef HAL_PWR_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup PWR_Private_Constants PWR Private Constants
* @{
*/
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#if !defined (DUAL_CORE)
#define PVD_MODE_IT (0x00010000U)
#define PVD_MODE_EVT (0x00020000U)
#endif /* !defined (DUAL_CORE) */
#define PVD_RISING_EDGE (0x00000001U)
#define PVD_FALLING_EDGE (0x00000002U)
#define PVD_RISING_FALLING_EDGE (0x00000003U)
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
* @brief Initialization and De-Initialization functions
*
@verbatim
===============================================================================
##### Initialization and De-Initialization Functions #####
===============================================================================
[..]
This section provides functions allowing to deinitialize power peripheral.
[..]
After system reset, the backup domain (RTC registers, RTC backup data
registers and backup SRAM) is protected against possible unwanted write
accesses.
The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
domain.
The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
domain.
@endverbatim
* @{
*/
/**
* @brief Deinitialize the HAL PWR peripheral registers to their default reset
* values.
* @note This functionality is not available in this product.
* The prototype is kept just to maintain compatibility with other
* products.
* @retval None.
*/
void HAL_PWR_DeInit (void)
{
}
/**
* @brief Enable access to the backup domain (RTC registers, RTC backup data
* registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None.
*/
void HAL_PWR_EnableBkUpAccess (void)
{
/* Enable access to RTC and backup registers */
SET_BIT (PWR->CR1, PWR_CR1_DBP);
}
/**
* @brief Disable access to the backup domain (RTC registers, RTC backup data
* registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None.
*/
void HAL_PWR_DisableBkUpAccess (void)
{
/* Disable access to RTC and backup registers */
CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
* @brief Power Control functions
*
@verbatim
===============================================================================
##### Peripheral Control Functions #####
===============================================================================
[..]
This section provides functions allowing to control power peripheral.
*** PVD configuration ***
=========================
[..]
(+) The PVD is used to monitor the VDD power supply by comparing it to a
threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
register).
(+) A PVDO flag is available to indicate if VDD is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line 16 to generate an interrupt if enabled.
It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD is stopped in STANDBY mode.
*** Wake-up pin configuration ***
=================================
[..]
(+) Wake-up pin is used to wake up the system from STANDBY mode.
The pin pull is configurable through the WKUPEPR register to be in
No-pull, Pull-up and Pull-down.
The pin polarity is configurable through the WKUPEPR register to be
active on rising or falling edges.
(+) There are up to six Wake-up pin in the STM32H7 devices family.
*** Low Power modes configuration ***
=====================================
[..]
The device present 3 principles low-power modes features:
(+) SLEEP mode : Cortex-Mx is stopped and all PWR domains are remaining
active (Powered and Clocked).
(+) STOP mode : Cortex-Mx is stopped, clocks are stopped and the
regulator is running. The Main regulator or the LP
regulator could be selected.
(+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
supply regulator is powered off.
*** SLEEP mode ***
==================
[..]
(+) Entry:
The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
SLEEPEntry) function.
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
-@@- The Regulator parameter is not used for the STM32H7 family
and is kept as parameter just to maintain compatibility with the
lower power families (STM32L).
(+) Exit:
Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) can wake up the device from SLEEP mode.
*** STOP mode ***
=================
[..]
In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
register contents are preserved.
The voltage regulator can be configured either in normal or low-power mode.
To minimize the consumption in STOP mode, FLASH can be powered off before
entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
It can be switched on again by software after exiting the STOP mode using
the HAL_PWREx_DisableFlashPowerDown() function.
(+) Entry:
The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
STOPEntry) function with:
(++) Regulator:
(+++) PWR_MAINREGULATOR_ON: Main regulator ON.
(+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
(++) STOPEntry:
(+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
(+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
(+) Exit:
Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
*** STANDBY mode ***
====================
[..]
(+)
The system STANDBY mode allows to achieve the lowest power consumption.
It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
disabled. The system is consequently powered off. The PLL, the HSI
oscillator and the HSE oscillator are also switched off. SRAM and register
contents are lost except for the RTC registers, RTC backup registers,
backup SRAM and standby circuitry.
[..]
The voltage regulator is OFF.
(++) Entry:
(+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
function.
(++) Exit:
(+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
RTC wakeup, tamper event, time stamp event, external reset in NRST
pin, IWDG reset.
*** Auto-wakeup (AWU) from low-power mode ***
=============================================
[..]
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
RTC Wakeup event, a tamper event or a time-stamp event, without
depending on an external interrupt (Auto-wakeup mode).
(+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
(++) To wake up from the STOP mode with an RTC alarm event, it is
necessary to configure the RTC to generate the RTC alarm using the
HAL_RTC_SetAlarm_IT() function.
(++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
it is necessary to configure the RTC to detect the tamper or time
stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
HAL_RTCEx_SetTamper_IT() functions.
(++) To wake up from the STOP mode with an RTC WakeUp event, it is
necessary to configure the RTC to generate the RTC WakeUp event
using the HAL_RTCEx_SetWakeUpTimer_IT() function.
@endverbatim
* @{
*/
/**
* @brief Configure the event mode and the voltage threshold detected by the
* Programmable Voltage Detector(PVD).
* @param sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains
* the configuration information for the PVD.
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage threshold corresponding to each
* detection level.
* @note For dual core devices, please ensure to configure the EXTI lines for
* the different Cortex-Mx through PWR_Exported_Macro provided by this
* driver. All combination are allowed: wake up only Cortex-M7, wake up
* only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
* @retval None.
*/
void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
{
/* Check the PVD configuration parameter */
if (sConfigPVD == NULL)
{
return;
}
/* Check the parameters */
assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
/* Set PLS[7:5] bits according to PVDLevel value */
MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
/* Clear previous config */
#if !defined (DUAL_CORE)
__HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
__HAL_PWR_PVD_EXTI_DISABLE_IT ();
#endif /* !defined (DUAL_CORE) */
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
#if !defined (DUAL_CORE)
/* Interrupt mode configuration */
if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
__HAL_PWR_PVD_EXTI_ENABLE_IT ();
}
/* Event mode configuration */
if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
}
#endif /* !defined (DUAL_CORE) */
/* Rising edge configuration */
if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
}
/* Falling edge configuration */
if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
}
}
/**
* @brief Enable the Programmable Voltage Detector (PVD).
* @retval None.
*/
void HAL_PWR_EnablePVD (void)
{
/* Enable the power voltage detector */
SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
}
/**
* @brief Disable the Programmable Voltage Detector (PVD).
* @retval None.
*/
void HAL_PWR_DisablePVD (void)
{
/* Disable the power voltage detector */
CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
}
/**
* @brief Enable the WakeUp PINx functionality.
* @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
* This parameter can be one of the following legacy values, which
* sets the default (rising edge):
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
* PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6.
* or one of the following values where the user can explicitly states
* the enabled pin and the chosen polarity:
* @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
* PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
* PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
* PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
* PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
* PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
* @retval None.
*/
void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
{
/* Check the parameters */
assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
/*
Enable and Specify the Wake-Up pin polarity and the pull configuration
for the event detection (rising or falling edge).
*/
MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
}
/**
* @brief Disable the WakeUp PINx functionality.
* @param WakeUpPinx : Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
* PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6,
* PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
* PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
* PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
* PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
* PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
* PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
* @retval None.
*/
void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
{
/* Check the parameters */
assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
/* Disable the wake up pin selected */
CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
}
/**
* @brief Enter the current core in SLEEP mode (CSLEEP).
* @param Regulator : Specifies the regulator state in SLEEP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON : SLEEP mode with regulator ON.
* @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power
* regulator ON.
* @note This parameter is not used for the STM32H7 family and is kept as
* parameter just to maintain compatibility with the lower power
* families.
* @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
* intrinsic instruction.
* This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
* @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
* @note Ensure to clear pending events before calling this API through
* HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
* @retval None.
*/
void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
{
/* Check the parameters */
assert_param (IS_PWR_REGULATOR (Regulator));
assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
/* Select SLEEP mode entry */
if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI ();
}
else
{
/* Request Wait For Event */
__WFE ();
}
}
/**
* @brief Enter STOP mode.
* @note For single core devices, this API will enter the system in STOP mode
* with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is
* cleared.
* For dual core devices, this API will enter the domain (containing
* Cortex-Mx that executing this function) in DSTOP mode. If all
* Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is
* cleared, all the system will enter in STOP mode.
* @param Regulator : Specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
* @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
* regulator ON.
* @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE
* intrinsic instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
* @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
* @note In System STOP mode, all I/O pins keep the same state as in Run mode.
* @note When exiting System STOP mode by issuing an interrupt or a wakeup
* event, the HSI RC oscillator is selected as default system wakeup
* clock.
* @note In System STOP mode, when the voltage regulator operates in low
* power mode, an additional startup delay is incurred when the system
* is waking up. By keeping the internal regulator ON during STOP mode,
* the consumption is higher although the startup time is reduced.
* @retval None.
*/
void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
{
/* Check the parameters */
assert_param (IS_PWR_REGULATOR (Regulator));
assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
/* Select the regulator state in STOP mode */
MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
/* Configure the PWR mode for the different Domains */
#if defined (DUAL_CORE)
/* Check CPU ID */
if (HAL_GetCurrentCPUID () == CM7_CPUID)
{
/* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
}
else
{
/* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
}
#else /* Single core devices */
/* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
#if defined (PWR_CPUCR_PDDS_D2)
/* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
#endif /* PWR_CPUCR_PDDS_D2 */
#endif /* defined (DUAL_CORE) */
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
/* Ensure that all instructions are done before entering STOP mode */
__DSB ();
__ISB ();
/* Select STOP mode entry */
if (STOPEntry == PWR_STOPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI ();
}
else
{
/* Request Wait For Event */
__WFE ();
}
/* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
}
/**
* @brief Enter STANDBY mode.
* @note For single core devices, this API will enter the system in STANDBY
* mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
* regiter is cleared.
* For dual core devices, this API will enter the domain (containing
* Cortex-Mx that executing this function) in DSTANDBY mode. If all
* Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
* is cleared, all the system will enter in STANDBY mode.
* @note The system enters Standby mode only when all domains are in DSTANDBY.
* @note When the System exit STANDBY mode by issuing an interrupt or a
* wakeup event, the HSI RC oscillator is selected as system clock.
* @retval None.
*/
void HAL_PWR_EnterSTANDBYMode (void)
{
/* Configure the PWR mode for the different Domains */
#if defined (DUAL_CORE)
/* Check CPU ID */
if (HAL_GetCurrentCPUID () == CM7_CPUID)
{
/* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
}
else
{
/* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
}
#else /* Single core devices */
/* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
#if defined (PWR_CPUCR_PDDS_D2)
/* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
#endif /* PWR_CPUCR_PDDS_D2 */
#endif /* defined (DUAL_CORE) */
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
/* Ensure that all instructions are done before entering STOP mode */
__DSB ();
__ISB ();
/* This option is used to ensure that store operations are completed */
#if defined (__CC_ARM)
__force_stores();
#endif /* defined (__CC_ARM) */
/* Request Wait For Interrupt */
__WFI ();
}
/**
* @brief Indicate Sleep-On-Exit feature when returning from Handler mode to
* Thread mode.
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
* processor re-enters SLEEP mode when an interruption handling is over.
* Setting this bit is useful when the processor is expected to run
* only on interruptions handling.
* @retval None.
*/
void HAL_PWR_EnableSleepOnExit (void)
{
/* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
/**
* @brief Disable Sleep-On-Exit feature when returning from Handler mode to
* Thread mode.
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
* processor re-enters SLEEP mode when an interruption handling is over.
* @retval None
*/
void HAL_PWR_DisableSleepOnExit (void)
{
/* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
/**
* @brief Enable CORTEX SEVONPEND feature.
* @note Sets SEVONPEND bit of SCR register. When this bit is set, any
* pending event / interrupt even if it's disabled or has insufficient
* priority to cause exception entry wakes up the Cortex-Mx.
* @retval None.
*/
void HAL_PWR_EnableSEVOnPend (void)
{
/* Set SEVONPEND bit of Cortex-Mx System Control Register */
SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
/**
* @brief Disable CORTEX SEVONPEND feature.
* @note Resets SEVONPEND bit of SCR register. When this bit is reset, only
* enabled pending causes exception entry wakes up the Cortex-Mx.
* @retval None.
*/
void HAL_PWR_DisableSEVOnPend (void)
{
/* Clear SEVONPEND bit of Cortex System Control Register */
CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions
* @brief Interrupt Handling functions
*
@verbatim
===============================================================================
##### Interrupt Handling Functions #####
===============================================================================
[..]
This section provides functions allowing to handle the PVD pending
interrupts.
@endverbatim
* @{
*/
/**
* @brief This function handles the PWR PVD interrupt request.
* @note This API should be called under the PVD_AVD_IRQHandler().
* @retval None.
*/
void HAL_PWR_PVD_IRQHandler (void)
{
#if defined (DUAL_CORE)
/* Check Cortex-Mx ID */
if (HAL_GetCurrentCPUID () == CM7_CPUID)
{
/* Check PWR EXTI D1 flag */
if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
{
/* Clear PWR EXTI D1 pending bit */
__HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback ();
}
}
else
{
/* Check PWR EXTI D2 flag */
if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
{
/* Clear PWR EXTI D2 pending bit */
__HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback ();
}
}
#else /* Single core devices */
/* PVD EXTI line interrupt detected */
if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
{
/* Clear PWR EXTI pending bit */
__HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback ();
}
#endif /* defined (DUAL_CORE) */
}
/**
* @brief PWR PVD interrupt callback.
* @retval None.
*/
__weak void HAL_PWR_PVDCallback (void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PWR_PVDCallback can be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PWR_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
+2100
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c
+2621
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c
+692
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@@ -0,0 +1,692 @@
/**
******************************************************************************
* @file stm32h7xx_hal_ramecc.c
* @author MCD Application Team
* @brief RAMECC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the RAM ECC monitoring (RAMECC) peripheral:
* + Initialization and de-initialization functions
* + Monitoring operation functions
* + Error informations functions
* + State and error functions
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Enable and latch error informations through HAL_RAMECC_Init().
(#) For a given Monitor, enable and disable interrupt through
HAL_RAMECC_EnableNotifiaction().
To enable a notification for a given RAMECC instance, use global
interrupts.
To enable a notification for only RAMECC monitor, use monitor interrupts.
All possible notifications are defined in the driver header file under
RAMECC_Interrupt group.
*** Silent mode ***
===================
[..]
(+) Use HAL_RAMECC_StartMonitor() to start RAMECC latch failing
information without enabling any notification.
*** Interrupt mode ***
======================
[..]
(+) Use HAL_RAMECC_EnableNotifiaction() to enable interrupts for a
given error.
(+) Configure the RAMECC interrupt priority using
HAL_NVIC_SetPriority().
(+) Enable the RAMECC IRQ handler using HAL_NVIC_EnableIRQ().
*** Failing informations ***
======================
[..]
(#) Use HAL_RAMECC_GetFailingAddress() function to return the RAMECC
failing address.
(#) Use HAL_RAMECC_GetFailingDataLow() function to return the RAMECC
failing data low.
(#) Use HAL_RAMECC_GetFailingDataHigh() function to return the RAMECC
failing data high.
(#) Use HAL_RAMECC_GetHammingErrorCode() function to return the RAMECC
Hamming bits injected.
(#) Use HAL_RAMECC_IsECCSingleErrorDetected() function to check if a single
error was detected and corrected.
(#) Use HAL_RAMECC_IsECCDoubleErrorDetected() function to check if a double
error was dedetected.
*** RAMECC HAL driver macros list ***
=============================================
[..]
Below the list of used macros in RAMECC HAL driver.
(+) __HAL_RAMECC_ENABLE_IT : Enable the specified ECCRAM Monitor
interrupts.
(+) __HAL_RAMECC_DISABLE_IT : Disable the specified ECCRAM Monitor
interrupts.
(+) __HAL_RAMECC_GET_FLAG : Return the current RAMECC Monitor selected
flag.
(+) __HAL_RAMECC_CLEAR_FLAG : Clear the current RAMECC Monitor selected
flag.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup RAMECC RAMECC
* @brief RAMECC HAL module driver
* @{
*/
#ifdef HAL_RAMECC_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RAMECC_Exported_Functions
* @{
*/
/** @addtogroup RAMECC_Exported_Functions_Group1
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
This section provides functions allowing to initialize the RAMECC Monitor.
[..]
The HAL_RAMECC_Init() function follows the RAMECC configuration procedures
as described in reference manual.
The HAL_RAMECC_DeInit() function allows to deinitialize the RAMECC monitor.
@endverbatim
* @{
*/
/**
* @brief Initialize the RAMECC by clearing flags and disabling interrupts.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc)
{
/* Check the RAMECC peripheral handle */
if (hramecc == NULL)
{
/* Return HAL status */
return HAL_ERROR;
}
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Change RAMECC peripheral state */
hramecc->State = HAL_RAMECC_STATE_BUSY;
/* Disable RAMECC monitor */
hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN;
/* Disable all global interrupts */
((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER &= \
~(RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE);
/* Disable all interrupts monitor */
hramecc->Instance->CR &= ~(RAMECC_CR_ECCSEIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCDEBWIE);
/* Clear RAMECC monitor flags */
__HAL_RAMECC_CLEAR_FLAG (hramecc, RAMECC_FLAGS_ALL);
/* Initialise the RAMECC error code */
hramecc->ErrorCode = HAL_RAMECC_ERROR_NONE;
/* Update the RAMECC state */
hramecc->State = HAL_RAMECC_STATE_READY;
/* Return HAL status */
return HAL_OK;
}
/**
* @brief DeInitializes the RAMECC peripheral.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc)
{
/* Check the RAMECC peripheral handle */
if (hramecc == NULL)
{
/* Return HAL status */
return HAL_ERROR;
}
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Disable RAMECC monitor */
hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN;
/* Disable all global interrupts */
((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER &= \
~(RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE);
/* Disable all interrupts monitor */
hramecc->Instance->CR &= ~(RAMECC_CR_ECCSEIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCDEBWIE);
/* Clear RAMECC monitor flags */
__HAL_RAMECC_CLEAR_FLAG (hramecc, RAMECC_FLAGS_ALL);
/* Clean callback */
hramecc->DetectErrorCallback = NULL;
/* Initialise the RAMECC error code */
hramecc->ErrorCode = HAL_RAMECC_ERROR_NONE;
/* Change RAMECC peripheral state */
hramecc->State = HAL_RAMECC_STATE_RESET;
/* Return HAL status */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup RAMECC_Exported_Functions_Group2
*
@verbatim
===============================================================================
##### Monitoring operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure latching error informations.
(+) Configure RAMECC Global/Monitor interrupts.
(+) Register and Unregister RAMECC callbacks
(+) Handle RAMECC interrupt request
@endverbatim
* @{
*/
/**
* @brief Starts the RAMECC latching error information.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Check RAMECC state */
if (hramecc->State == HAL_RAMECC_STATE_READY)
{
/* Change RAMECC peripheral state */
hramecc->State = HAL_RAMECC_STATE_BUSY;
/* Enable RAMECC monitor */
hramecc->Instance->CR |= RAMECC_CR_ECCELEN;
/* Change RAMECC peripheral state */
hramecc->State = HAL_RAMECC_STATE_READY;
}
else
{
/* Update the error code */
hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY;
/* Return HAL status */
return HAL_ERROR;
}
/* Return HAL status */
return HAL_OK;
}
/**
* @brief Stop the RAMECC latching error informations.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMECC_StopMonitor (RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Check RAMECC state */
if (hramecc->State == HAL_RAMECC_STATE_READY)
{
/* Change RAMECC peripheral state */
hramecc->State = HAL_RAMECC_STATE_BUSY;
/* Disable RAMECC monitor */
hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN;
/* Change RAMECC peripheral state */
hramecc->State = HAL_RAMECC_STATE_READY;
}
else
{
/* Update the error code */
hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY;
/* Return HAL status */
return HAL_ERROR;
}
/* Return HAL status */
return HAL_OK;
}
/**
* @brief Enable the RAMECC error interrupts.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMECC Monitor.
* @param Notifications Select the notification.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMECC_EnableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
assert_param (IS_RAMECC_INTERRUPT (Notifications));
/* Check RAMECC state */
if (hramecc->State == HAL_RAMECC_STATE_READY)
{
/* Change RAMECC peripheral state */
hramecc->State = HAL_RAMECC_STATE_BUSY;
/* Enable RAMECC interrupts */
__HAL_RAMECC_ENABLE_IT (hramecc, Notifications);
/* Change RAMECC peripheral state */
hramecc->State = HAL_RAMECC_STATE_READY;
}
else
{
/* Update the error code */
hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY;
/* Return HAL status */
return HAL_ERROR;
}
/* Return HAL status */
return HAL_OK;
}
/**
* @brief Disable the RAMECC error interrupts.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMECC Monitor.
* @param Notifications Select the notification.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
assert_param (IS_RAMECC_INTERRUPT (Notifications));
/* Check RAMECC state */
if (hramecc->State == HAL_RAMECC_STATE_READY)
{
/* Change RAMECC peripheral state */
hramecc->State = HAL_RAMECC_STATE_BUSY;
/* Disable RAMECC interrupts */
__HAL_RAMECC_DISABLE_IT (hramecc, Notifications);
/* Change RAMECC peripheral state */
hramecc->State = HAL_RAMECC_STATE_READY;
}
else
{
/* Update the error code */
hramecc->ErrorCode = HAL_RAMECC_ERROR_BUSY;
/* Return HAL status */
return HAL_ERROR;
}
/* Return HAL status */
return HAL_OK;
}
/**
* @brief Register callbacks.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @param pCallback pointer to private callbacsk function which has pointer to
* a RAMECC_HandleTypeDef structure as parameter.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMECC_RegisterCallback (RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc))
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hramecc->ErrorCode |= HAL_RAMECC_ERROR_INVALID_CALLBACK;
/* Return HAL status */
return HAL_ERROR;
}
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Check RAMECC state */
if (hramecc->State == HAL_RAMECC_STATE_READY)
{
hramecc->DetectErrorCallback = pCallback;
}
else
{
/* Update the error code */
hramecc->ErrorCode = HAL_RAMECC_ERROR_INVALID_CALLBACK;
/* Update HAL status */
status = HAL_ERROR;
}
/* Return HAL status */
return status;
}
/**
* @brief UnRegister callbacks.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Check RAMECC state */
if(hramecc->State == HAL_RAMECC_STATE_READY)
{
hramecc->DetectErrorCallback = NULL;
}
else
{
/* Update the error code */
hramecc->ErrorCode = HAL_RAMECC_ERROR_INVALID_CALLBACK;
/* Update HAL status */
status = HAL_ERROR;
}
/* Return HAL status */
return status;
}
/**
* @brief Handles RAMECC interrupt request.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval None.
*/
void HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc)
{
uint32_t ier_reg = ((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER;
uint32_t cr_reg = hramecc->Instance->CR >> 1U;
uint32_t sr_reg = hramecc->Instance->SR << 1U;
/* Update global interrupt variables */
if ((ier_reg & RAMECC_IER_GIE) == RAMECC_IER_GIE)
{
ier_reg = RAMECC_IT_GLOBAL_ALL;
}
/* Clear active flags */
__HAL_RAMECC_CLEAR_FLAG (hramecc, (((ier_reg | cr_reg) & sr_reg) >> 1U));
/* Check if a valid double error callback is registred */
if (hramecc->DetectErrorCallback != NULL)
{
/* Error detection callback */
hramecc->DetectErrorCallback(hramecc);
}
}
/** @addtogroup RAMECC_Exported_Functions_Group3
*
@verbatim
===============================================================================
##### Error informations functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Get failing address.
(+) Get failing data low.
(+) Get failing data high.
(+) Get hamming bits injected.
(+) Check single error flag.
(+) Check double error flag.
@endverbatim
* @{
*/
/**
* @brief Return the RAMECC failing address.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval Failing address offset.
*/
uint32_t HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Return failing address */
return hramecc->Instance->FAR;
}
/**
* @brief Return the RAMECC data low.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval Failing data low.
*/
uint32_t HAL_RAMECC_GetFailingDataLow (RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Return failing data low */
return hramecc->Instance->FDRL;
}
/**
* @brief Return the RAMECC data high.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval Failing data high.
*/
uint32_t HAL_RAMECC_GetFailingDataHigh (RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Return failing data high */
return hramecc->Instance->FDRH;
}
/**
* @brief Return the RAMECC Hamming bits injected.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval Hamming bits injected.
*/
uint32_t HAL_RAMECC_GetHammingErrorCode (RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Return hamming bits injected */
return hramecc->Instance->FECR;
}
/**
* @brief Check if an ECC single error was occured.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval State of bit (1 or 0).
*/
uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Return the state of SEDC flag */
return ((READ_BIT(hramecc->Instance->SR, RAMECC_SR_SEDCF) == (RAMECC_SR_SEDCF)) ? 1UL : 0UL);
}
/**
* @brief Check if an ECC double error was occured.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @retval State of bit (1 or 0).
*/
uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Return the state of DEDF | DEBWDF flags */
return ((READ_BIT(hramecc->Instance->SR, (RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)) != 0U) ? 1UL : 0UL);
}
/**
* @}
*/
/** @addtogroup RAMECC_Exported_Functions_Group4
*
@verbatim
===============================================================================
##### State and Error Functions #####
===============================================================================
[..]
This section provides functions allowing to check and get the RAMECC state
and the error code .
[..]
The HAL_RAMECC_GetState() function allows to get the RAMECC peripheral
state.
The HAL_RAMECC_GetError() function allows to Get the RAMECC peripheral error
code.
@endverbatim
* @{
*/
/**
* @brief Get the RAMECC peripheral state.
* @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMECC instance.
* @retval RAMECC state.
*/
HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc)
{
/* Return the RAMECC state */
return hramecc->State;
}
/**
* @brief Get the RAMECC peripheral error code.
* @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMECC instance.
* @retval RAMECC error code.
*/
uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc)
{
/* Return the RAMECC error code */
return hramecc->ErrorCode;
}
/**
* @}
*/
#endif /* HAL_RAMECC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
+1745
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c
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/**
******************************************************************************
* @file stm32h7xx_hal_rng.c
* @author MCD Application Team
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
* + Initialization and configuration functions
* + Peripheral Control functions
* + Peripheral State functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The RNG HAL driver can be used as follows:
(#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
in HAL_RNG_MspInit().
(#) Activate the RNG peripheral using HAL_RNG_Init() function.
(#) Wait until the 32 bit Random Number Generator contains a valid
random data using (polling/interrupt) mode.
(#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
##### Callback registration #####
==================================
[..]
The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : RNG Error Callback.
(+) MspInitCallback : RNG MspInit.
(+) MspDeInitCallback : RNG MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : RNG Error Callback.
(+) MspInitCallback : RNG MspInit.
(+) MspDeInitCallback : RNG MspDeInit.
[..]
For specific callback ReadyDataCallback, use dedicated register callbacks:
respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
[..]
By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
example @ref HAL_RNG_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
or @ref HAL_RNG_Init() function.
[..]
When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined (RNG)
/** @addtogroup RNG
* @brief RNG HAL module driver.
* @{
*/
#ifdef HAL_RNG_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup RNG_Private_Defines
* @{
*/
/* Health test control register information to use in CCM algorithm */
#define RNG_HTCFG_1 0x17590ABCU /*!< magic number */
#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
#define RNG_HTCFG 0x000CAA74U /*!< for best latency and To be compliant with NIST */
#else /*RNG_VER_3_2*/
#define RNG_HTCFG 0x00007274U /*!< for best latency and To be compliant with NIST */
#endif
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RNG_Private_Constants RNG Private Constants
* @{
*/
#define RNG_TIMEOUT_VALUE 2U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RNG_Exported_Functions
* @{
*/
/** @addtogroup RNG_Exported_Functions_Group1
* @brief Initialization and configuration functions
*
@verbatim
===============================================================================
##### Initialization and configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the RNG according to the specified parameters
in the RNG_InitTypeDef and create the associated handle
(+) DeInitialize the RNG peripheral
(+) Initialize the RNG MSP
(+) DeInitialize RNG MSP
@endverbatim
* @{
*/
/**
* @brief Initializes the RNG peripheral and creates the associated handle.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
uint32_t tickstart;
/* Check the RNG handle allocation */
if (hrng == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
if (hrng->State == HAL_RNG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */
hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
if (hrng->MspInitCallback == NULL)
{
hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware */
hrng->MspInitCallback(hrng);
}
#else
if (hrng->State == HAL_RNG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
#if defined(RNG_CR_CONDRST)
/* Disable RNG */
__HAL_RNG_DISABLE(hrng);
/* Clock Error Detection Configuration when CONDRT bit is set to 1 */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST);
#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
/*!< magic number must be written immediately before to RNG_HTCRG */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
/* for best latency and to be compliant with NIST */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
#endif
/* Writing bits CONDRST=0*/
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for conditioning reset process to be completed */
while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
hrng->State = HAL_RNG_STATE_READY;
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
#else
/* Clock Error Detection Configuration */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
#endif /* end of RNG_CR_CONDRST */
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
/* verify that no seed error */
if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
{
hrng->State = HAL_RNG_STATE_ERROR;
return HAL_ERROR;
}
/* Get tick */
tickstart = HAL_GetTick();
/* Check if data register contains valid random data */
while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
hrng->State = HAL_RNG_STATE_ERROR;
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
/* Initialise the error code */
hrng->ErrorCode = HAL_RNG_ERROR_NONE;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitializes the RNG peripheral.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
{
#if defined(RNG_CR_CONDRST)
uint32_t tickstart;
#endif /* RNG_CR_CONDRST */
/* Check the RNG handle allocation */
if (hrng == NULL)
{
return HAL_ERROR;
}
#if defined(RNG_CR_CONDRST)
/* Clear Clock Error Detection bit when CONDRT bit is set to 1 */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_CED_ENABLE | RNG_CR_CONDRST);
/* Writing bits CONDRST=0*/
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for conditioning reset process to be completed */
while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
hrng->State = HAL_RNG_STATE_READY;
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
return HAL_ERROR;
}
}
#else
/* Clear Clock Error Detection bit */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED);
#endif /* RNG_CR_CONDRST */
/* Disable the RNG Peripheral */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
/* Clear RNG interrupt status flags */
CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
if (hrng->MspDeInitCallback == NULL)
{
hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware */
hrng->MspDeInitCallback(hrng);
#else
/* DeInit the low level hardware */
HAL_RNG_MspDeInit(hrng);
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Update the RNG state */
hrng->State = HAL_RNG_STATE_RESET;
/* Initialise the error code */
hrng->ErrorCode = HAL_RNG_ERROR_NONE;
/* Release Lock */
__HAL_UNLOCK(hrng);
/* Return the function status */
return HAL_OK;
}
/**
* @brief Initializes the RNG MSP.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspInit must be implemented in the user file.
*/
}
/**
* @brief DeInitializes the RNG MSP.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspDeInit must be implemented in the user file.
*/
}
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User RNG Callback
* To be used instead of the weak predefined callback
* @param hrng RNG handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
* @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hrng);
if (HAL_RNG_STATE_READY == hrng->State)
{
switch (CallbackID)
{
case HAL_RNG_ERROR_CB_ID :
hrng->ErrorCallback = pCallback;
break;
case HAL_RNG_MSPINIT_CB_ID :
hrng->MspInitCallback = pCallback;
break;
case HAL_RNG_MSPDEINIT_CB_ID :
hrng->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_RNG_STATE_RESET == hrng->State)
{
switch (CallbackID)
{
case HAL_RNG_MSPINIT_CB_ID :
hrng->MspInitCallback = pCallback;
break;
case HAL_RNG_MSPDEINIT_CB_ID :
hrng->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hrng);
return status;
}
/**
* @brief Unregister an RNG Callback
* RNG callabck is redirected to the weak predefined callback
* @param hrng RNG handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
* @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hrng);
if (HAL_RNG_STATE_READY == hrng->State)
{
switch (CallbackID)
{
case HAL_RNG_ERROR_CB_ID :
hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_RNG_MSPINIT_CB_ID :
hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
break;
case HAL_RNG_MSPDEINIT_CB_ID :
hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_RNG_STATE_RESET == hrng->State)
{
switch (CallbackID)
{
case HAL_RNG_MSPINIT_CB_ID :
hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
break;
case HAL_RNG_MSPDEINIT_CB_ID :
hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */
break;
default :
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hrng);
return status;
}
/**
* @brief Register Data Ready RNG Callback
* To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
* @param hrng RNG handle
* @param pCallback pointer to the Data Ready Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hrng);
if (HAL_RNG_STATE_READY == hrng->State)
{
hrng->ReadyDataCallback = pCallback;
}
else
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hrng);
return status;
}
/**
* @brief UnRegister the Data Ready RNG Callback
* Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
* @param hrng RNG handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hrng);
if (HAL_RNG_STATE_READY == hrng->State)
{
hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */
}
else
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hrng);
return status;
}
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup RNG_Exported_Functions_Group2
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Get the 32 bit Random number
(+) Get the 32 bit Random number with interrupt enabled
(+) Handle RNG interrupt request
@endverbatim
* @{
*/
/**
* @brief Generates a 32-bit random number.
* @note This function checks value of RNG_FLAG_DRDY flag to know if valid
* random number is available in the DR register (RNG_FLAG_DRDY flag set
* whenever a random number is available through the RNG_DR register).
* After transitioning from 0 to 1 (random number available),
* RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
* four words from the RNG_DR register, i.e. further function calls
* will immediately return a new u32 random number (additional words are
* available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
* @note When no more random number data is available in DR register, RNG_FLAG_DRDY
* flag is automatically cleared.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param random32bit pointer to generated random number variable if successful.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
{
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(hrng);
/* Check RNG peripheral state */
if (hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Get tick */
tickstart = HAL_GetTick();
/* Check if data register contains valid random data */
while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
hrng->State = HAL_RNG_STATE_READY;
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
return HAL_ERROR;
}
}
/* Get a 32bit Random number */
hrng->RandomNumber = hrng->Instance->DR;
*random32bit = hrng->RandomNumber;
hrng->State = HAL_RNG_STATE_READY;
}
else
{
hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR;
}
/* Process Unlocked */
__HAL_UNLOCK(hrng);
return status;
}
/**
* @brief Generates a 32-bit random number in interrupt mode.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(hrng);
/* Check RNG peripheral state */
if (hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
__HAL_RNG_ENABLE_IT(hrng);
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hrng);
hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Handles RNG interrupt request.
* @note In the case of a clock error, the RNG is no more able to generate
* random numbers because the PLL48CLK clock is not correct. User has
* to check that the clock controller is correctly configured to provide
* the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
* The clock error has no impact on the previously generated
* random numbers, and the RNG_DR register contents can be used.
* @note In the case of a seed error, the generation of random numbers is
* interrupted as long as the SECS bit is '1'. If a number is
* available in the RNG_DR register, it must not be used because it may
* not have enough entropy. In this case, it is recommended to clear the
* SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
* the RNG peripheral to reinitialize and restart the RNG.
* @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
* or CEIS are set.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
uint32_t rngclockerror = 0U;
/* RNG clock error interrupt occurred */
if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
rngclockerror = 1U;
}
else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_SEED;
rngclockerror = 1U;
}
else
{
/* Nothing to do */
}
if (rngclockerror == 1U)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_ERROR;
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
/* Call registered Error callback */
hrng->ErrorCallback(hrng);
#else
/* Call legacy weak Error callback */
HAL_RNG_ErrorCallback(hrng);
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Clear the clock error flag */
__HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
}
/* Check RNG data ready interrupt occurred */
if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
{
/* Generate random number once, so disable the IT */
__HAL_RNG_DISABLE_IT(hrng);
/* Get the 32bit Random number (DRDY flag automatically cleared) */
hrng->RandomNumber = hrng->Instance->DR;
if (hrng->State != HAL_RNG_STATE_ERROR)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
/* Call registered Data Ready callback */
hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
#else
/* Call legacy weak Data Ready callback */
HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
}
}
}
/**
* @brief Read latest generated random number.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval random value
*/
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
{
return (hrng->RandomNumber);
}
/**
* @brief Data Ready callback in non-blocking mode.
* @note When RNG_FLAG_DRDY flag value is set, first random number has been read
* from DR register in IRQ Handler and is provided as callback parameter.
* Depending on valid data available in the conditioning output buffer,
* additional words can be read by the application from DR register till
* DRDY bit remains high.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param random32bit generated random number.
* @retval None
*/
__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
UNUSED(random32bit);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ReadyDataCallback must be implemented in the user file.
*/
}
/**
* @brief RNG error callbacks.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ErrorCallback must be implemented in the user file.
*/
}
/**
* @}
*/
/** @addtogroup RNG_Exported_Functions_Group3
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Returns the RNG state.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL state
*/
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
{
return hrng->State;
}
/**
* @brief Return the RNG handle error code.
* @param hrng: pointer to a RNG_HandleTypeDef structure.
* @retval RNG Error Code
*/
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
{
/* Return RNG Error Code */
return hrng->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_RNG_MODULE_ENABLED */
/**
* @}
*/
#endif /* RNG */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c
+299
View File
@@ -0,0 +1,299 @@
/**
******************************************************************************
* @file stm32h7xx_hal_rng_ex.c
* @author MCD Application Team
* @brief Extended RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
* + Lock configuration functions
* + Reset the RNG
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined (RNG)
/** @addtogroup RNGEx
* @brief RNG Extended HAL module driver.
* @{
*/
#ifdef HAL_RNG_MODULE_ENABLED
#if defined (RNG_CR_CONDRST)
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup RNGEx_Private_Defines
* @{
*/
/* Health test control register information to use in CCM algorithm */
#define RNG_HTCFG_1 0x17590ABCU /*!< magic number */
#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
#define RNG_HTCFG 0x000CAA74U /*!< for best latency and To be compliant with NIST */
#else /*RNG_VER_3_2*/
#define RNG_HTCFG 0x00007274U /*!< for best latency and To be compliant with NIST */
#endif
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RNGEx_Private_Constants RNG Private Constants
* @{
*/
#define RNG_TIMEOUT_VALUE 2U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RNGEx_Exported_Functions
* @{
*/
/** @addtogroup RNGEx_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration and lock functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the RNG with the specified parameters in the RNG_ConfigTypeDef
(+) Lock RNG configuration Allows user to lock a configuration until next reset.
@endverbatim
* @{
*/
/**
* @brief Configure the RNG with the specified parameters in the
* RNG_ConfigTypeDef.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param pConf: pointer to a RNG_ConfigTypeDef structure that contains
* the configuration information for RNG module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
{
uint32_t tickstart;
uint32_t cr_value;
HAL_StatusTypeDef status ;
/* Check the RNG handle allocation */
if ((hrng == NULL) || (pConf == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
assert_param(IS_RNG_CLOCK_DIVIDER(pConf->ClockDivider));
assert_param(IS_RNG_NIST_COMPLIANCE(pConf->NistCompliance));
assert_param(IS_RNG_CONFIG1(pConf->Config1));
assert_param(IS_RNG_CONFIG2(pConf->Config2));
assert_param(IS_RNG_CONFIG3(pConf->Config3));
/* Check RNG peripheral state */
if (hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Disable RNG */
__HAL_RNG_DISABLE(hrng);
/* RNG CR register configuration. Set value in CR register for :
- NIST Compliance setting
- Clock divider value
- CONFIG 1, CONFIG 2 and CONFIG 3 values */
cr_value = (uint32_t)(pConf->ClockDivider | pConf->NistCompliance
| (pConf->Config1 << RNG_CR_RNG_CONFIG1_Pos)
| (pConf->Config2 << RNG_CR_RNG_CONFIG2_Pos)
| (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos));
MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1
| RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3,
(uint32_t)(RNG_CR_CONDRST | cr_value));
#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
/*!< magic number must be written immediately before to RNG_HTCRG */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
/* for best latency and to be compliant with NIST */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
#endif
/* Writing bits CONDRST=0*/
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for conditioning reset process to be completed */
while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
hrng->State = HAL_RNG_STATE_READY;
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
/* Enable RNG */
__HAL_RNG_ENABLE(hrng);
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
/* function status */
status = HAL_OK;
}
else
{
hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR;
}
/* Return the function status */
return status;
}
/**
* @brief Get the RNG Configuration and fill parameters in the
* RNG_ConfigTypeDef.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param pConf: pointer to a RNG_ConfigTypeDef structure that contains
* the configuration information for RNG module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
{
HAL_StatusTypeDef status ;
/* Check the RNG handle allocation */
if ((hrng == NULL) || (pConf == NULL))
{
return HAL_ERROR;
}
/* Check RNG peripheral state */
if (hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Get RNG parameters */
pConf->Config1 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos) ;
pConf->Config2 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
pConf->Config3 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
pConf->ClockDivider = (hrng->Instance->CR & RNG_CR_CLKDIV);
pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC);
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
/* function status */
status = HAL_OK;
}
else
{
hrng->ErrorCode |= HAL_RNG_ERROR_BUSY;
status = HAL_ERROR;
}
/* Return the function status */
return status;
}
/**
* @brief RNG current configuration lock.
* @note This function allows to lock RNG peripheral configuration.
* Once locked, HW RNG reset has to be perfomed prior any further
* configuration update.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng)
{
HAL_StatusTypeDef status;
/* Check the RNG handle allocation */
if (hrng == NULL)
{
return HAL_ERROR;
}
/* Check RNG peripheral state */
if (hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Perform RNG configuration Lock */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CONFIGLOCK, RNG_CR_CONFIGLOCK);
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_READY;
/* function status */
status = HAL_OK;
}
else
{
hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR;
}
/* Return the function status */
return status;
}
/**
* @}
*/
/**
* @}
*/
#endif /* CONDRST */
#endif /* HAL_RNG_MODULE_ENABLED */
/**
* @}
*/
#endif /* RNG */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c
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/**
******************************************************************************
* @file stm32h7xx_hal_sai_ex.c
* @author MCD Application Team
* @brief SAI Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionality of the SAI Peripheral Controller:
* + Modify PDM microphone delays.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_SAI_MODULE_ENABLED
/** @defgroup SAIEx SAIEx
* @brief SAI Extended HAL module driver
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
#define SAI_PDM_DELAY_MASK 0x77U
#define SAI_PDM_DELAY_OFFSET 8U
#define SAI_PDM_RIGHT_DELAY_OFFSET 4U
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
* @{
*/
/** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
* @brief SAIEx control functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Modify PDM microphone delays
@endverbatim
* @{
*/
/**
* @brief Configure PDM microphone delays.
* @param hsai SAI handle.
* @param pdmMicDelay Microphone delays configuration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t offset;
SAI_TypeDef *SaiBaseAddress;
/* Get the SAI base address according to the SAI handle */
#if defined(SAI4)
SaiBaseAddress = ((hsai->Instance == SAI1_Block_A) ? SAI1 : \
(hsai->Instance == SAI4_Block_A) ? SAI4 : \
NULL);
#else
SaiBaseAddress = ((hsai->Instance == SAI1_Block_A) ? SAI1 : NULL);
#endif /* SAI4 */
/* Check that SAI sub-block is SAI sub-block A */
if (SaiBaseAddress == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check microphone delay parameters */
assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair));
assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay));
assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay));
/* Compute offset on PDMDLY register according mic pair number */
offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U);
/* Check SAI state and offset */
if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U))
{
/* Reset current delays for specified microphone */
SaiBaseAddress->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset);
/* Apply new microphone delays */
SaiBaseAddress->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset);
}
else
{
status = HAL_ERROR;
}
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_SAI_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c
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/**
******************************************************************************
* @file stm32h7xx_hal_sd_ex.c
* @author MCD Application Team
* @brief SD card Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
* + Extended features functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The SD Extension HAL driver can be used as follows:
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
(+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup SDEx SDEx
* @brief SD Extended HAL module driver
* @{
*/
#ifdef HAL_SD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SDEx_Exported_Functions
* @{
*/
/** @addtogroup SDEx_Exported_Functions_Group1
* @brief Multibuffer functions
*
@verbatim
==============================================================================
##### Multibuffer functions #####
==============================================================================
[..]
This section provides functions allowing to configure the multibuffer mode and start read and write
multibuffer mode for SD HAL driver.
@endverbatim
* @{
*/
/**
* @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
* @param hsd: SD handle
* @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
* @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
* @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
{
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->Instance->IDMABASE0= (uint32_t) pDataBuffer0;
hsd->Instance->IDMABASE1= (uint32_t) pDataBuffer1;
hsd->Instance->IDMABSIZE= (uint32_t) (BLOCKSIZE * BufferSize);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
* @param hsd: SD handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t add = BlockAdd;
if(hsd->State == HAL_SD_STATE_READY)
{
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
DmaBase0_reg = hsd->Instance->IDMABASE0;
DmaBase1_reg = hsd->Instance->IDMABASE1;
if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Initialize data control register */
hsd->Instance->DCTRL = 0;
/* Clear old Flags*/
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_BUSY;
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
__SDMMC_CMDTRANS_ENABLE( hsd->Instance);
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
/* Read Blocks in DMA mode */
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
return HAL_ERROR;
}
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
* @param hsd: SD handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t add = BlockAdd;
if(hsd->State == HAL_SD_STATE_READY)
{
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
DmaBase0_reg = hsd->Instance->IDMABASE0;
DmaBase1_reg = hsd->Instance->IDMABASE1;
if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Initialize data control register */
hsd->Instance->DCTRL = 0;
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_BUSY;
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
__SDMMC_CMDTRANS_ENABLE( hsd->Instance);
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
/* Write Blocks in DMA mode */
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
return HAL_ERROR;
}
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Change the DMA Buffer0 or Buffer1 address on the fly.
* @param hsd: pointer to a SD_HandleTypeDef structure.
* @param Buffer: the buffer to be changed, This parameter can be one of
* the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1
* @param pDataBuffer: The new address
* @note The BUFFER0 address can be changed only when the current transfer use
* BUFFER1 and the BUFFER1 address can be changed only when the current
* transfer use BUFFER0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
{
if(Buffer == SD_DMA_BUFFER0)
{
/* change the buffer0 address */
hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
}
else
{
/* change the memory1 address */
hsd->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_SD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c
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/**
******************************************************************************
* @file stm32h7xx_hal_smartcard_ex.c
* @author MCD Application Team
* @brief SMARTCARD HAL module driver.
* This file provides extended firmware functions to manage the following
* functionalities of the SmartCard.
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
@verbatim
=============================================================================
##### SMARTCARD peripheral extended features #####
=============================================================================
[..]
The Extended SMARTCARD HAL driver can be used as follows:
(#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
auto-retry counter,...) in the hsmartcard AdvancedInit structure.
(#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
-@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
starting RX/TX transfers. Also RX/TX FIFO thresholds must be
configured prior starting RX/TX transfers.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup SMARTCARDEx SMARTCARDEx
* @brief SMARTCARD Extended HAL module driver
* @{
*/
#ifdef HAL_SMARTCARD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants
* @{
*/
/* UART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
/* UART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard);
/* Exported functions --------------------------------------------------------*/
/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions
* @{
*/
/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
* @brief Extended control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the SMARTCARD.
(+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
(+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
(+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
(+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
@endverbatim
* @{
*/
/** @brief Update on the fly the SMARTCARD block length in RTOR register.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @param BlockLength SMARTCARD block length (8-bit long at most)
* @retval None
*/
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
{
MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
}
/** @brief Update on the fly the receiver timeout value in RTOR register.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
* value must be less or equal to 0x0FFFFFFFF.
* @retval None
*/
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
{
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
}
/** @brief Enable the SMARTCARD receiver timeout feature.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
{
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmartcard);
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
/* Set the USART RTOEN bit */
SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/** @brief Disable the SMARTCARD receiver timeout feature.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
{
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmartcard);
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
/* Clear the USART RTOEN bit */
CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
* @brief SMARTCARD Transmit and Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of FIFO mode related callback functions.
(#) TX/RX Fifos Callbacks:
(++) HAL_SMARTCARDEx_RxFifoFullCallback()
(++) HAL_SMARTCARDEx_TxFifoEmptyCallback()
@endverbatim
* @{
*/
/**
* @brief SMARTCARD RX Fifo full callback.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmartcard);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file.
*/
}
/**
* @brief SMARTCARD TX Fifo empty callback.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmartcard);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions
* @brief SMARTCARD control functions
*
@verbatim
===============================================================================
##### Peripheral FIFO Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the SMARTCARD
FIFO feature.
(+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
(+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
(+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
(+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold
@endverbatim
* @{
*/
/**
* @brief Enable the FIFO mode.
* @param hsmartcard SMARTCARD handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
/* Process Locked */
__HAL_LOCK(hsmartcard);
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
/* Save actual SMARTCARD configuration */
tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
/* Disable SMARTCARD */
__HAL_SMARTCARD_DISABLE(hsmartcard);
/* Enable FIFO mode */
SET_BIT(tmpcr1, USART_CR1_FIFOEN);
hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE;
/* Restore SMARTCARD configuration */
WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
/* Determine the number of data to process during RX/TX ISR execution */
SMARTCARDEx_SetNbDataToProcess(hsmartcard);
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
return HAL_OK;
}
/**
* @brief Disable the FIFO mode.
* @param hsmartcard SMARTCARD handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
/* Process Locked */
__HAL_LOCK(hsmartcard);
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
/* Save actual SMARTCARD configuration */
tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
/* Disable SMARTCARD */
__HAL_SMARTCARD_DISABLE(hsmartcard);
/* Enable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE;
/* Restore SMARTCARD configuration */
WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
return HAL_OK;
}
/**
* @brief Set the TXFIFO threshold.
* @param hsmartcard SMARTCARD handle.
* @param Threshold TX FIFO threshold value
* This parameter can be one of the following values:
* @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8
* @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4
* @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2
* @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4
* @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8
* @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(hsmartcard);
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
/* Save actual SMARTCARD configuration */
tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
/* Disable SMARTCARD */
__HAL_SMARTCARD_DISABLE(hsmartcard);
/* Update TX threshold configuration */
MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
/* Determine the number of data to process during RX/TX ISR execution */
SMARTCARDEx_SetNbDataToProcess(hsmartcard);
/* Restore SMARTCARD configuration */
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
return HAL_OK;
}
/**
* @brief Set the RXFIFO threshold.
* @param hsmartcard SMARTCARD handle.
* @param Threshold RX FIFO threshold value
* This parameter can be one of the following values:
* @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8
* @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4
* @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2
* @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4
* @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8
* @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(hsmartcard);
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
/* Save actual SMARTCARD configuration */
tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
/* Disable SMARTCARD */
__HAL_SMARTCARD_DISABLE(hsmartcard);
/* Update RX threshold configuration */
MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
/* Determine the number of data to process during RX/TX ISR execution */
SMARTCARDEx_SetNbDataToProcess(hsmartcard);
/* Restore SMARTCARD configuration */
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions
* @{
*/
/**
* @brief Calculate the number of data to process in RX/TX ISR.
* @note The RX FIFO depth and the TX FIFO depth is extracted from
* the USART configuration registers.
* @param hsmartcard SMARTCARD handle.
* @retval None
*/
static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
{
uint8_t rx_fifo_depth;
uint8_t tx_fifo_depth;
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
{
hsmartcard->NbTxDataToProcess = 1U;
hsmartcard->NbRxDataToProcess = 1U;
}
else
{
rx_fifo_depth = RX_FIFO_DEPTH;
tx_fifo_depth = TX_FIFO_DEPTH;
rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
}
}
/**
* @}
*/
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32h7xx_hal_spi_ex.c
* @author MCD Application Team
* @brief Extended SPI HAL module driver.
* This file provides firmware functions to manage the following
* SPI peripheral extended functionalities :
* + IO operation functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup SPIEx SPIEx
* @brief SPI Extended HAL module driver
* @{
*/
#ifdef HAL_SPI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
* @{
*/
/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
* @brief Data transfers functions
*
@verbatim
==============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of extended functions to manage the SPI
data transfers.
(#) SPIEx function:
(++) HAL_SPIEx_FlushRxFifo()
(++) HAL_SPIEx_FlushRxFifo()
(++) HAL_SPIEx_EnableLockConfiguration()
(++) HAL_SPIEx_ConfigureUnderrun()
@endverbatim
* @{
*/
/**
* @brief Flush the RX fifo.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
{
uint8_t count = 0;
uint32_t itflag = hspi->Instance->SR;
__IO uint32_t tmpreg;
while (((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) != 0UL))
{
count += (uint8_t)4UL;
tmpreg = hspi->Instance->RXDR;
UNUSED(tmpreg); /* To avoid GCC warning */
if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
{
if (count > SPI_HIGHEND_FIFO_SIZE)
{
return HAL_TIMEOUT;
}
}
else
{
if (count > SPI_LOWEND_FIFO_SIZE)
{
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @brief Enable the Lock for the AF configuration of associated IOs
* and write protect the Content of Configuration register 2
* when SPI is enabled
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode = HAL_OK;
/* Process Locked */
__HAL_LOCK(hspi);
if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
}
/* Check if the SPI is disabled to edit IOLOCK bit */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
}
else
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
}
/**
* @brief Configure the UNDERRUN condition and behavior of slave transmitter.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param UnderrunDetection : Detection of underrun condition at slave transmitter
* This parameter can be a value of @ref SPI_Underrun_Detection.
* @param UnderrunBehaviour : Behavior of slave transmitter at underrun condition
* This parameter can be a value of @ref SPI_Underrun_Behaviour.
* @retval None
*/
HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
{
HAL_StatusTypeDef errorcode = HAL_OK;
/* Process Locked */
__HAL_LOCK(hspi);
/* Check State and Insure that Underrun configuration is managed only by Salve */
if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE))
{
errorcode = HAL_BUSY;
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
}
/* Check the parameters */
assert_param(IS_SPI_UNDERRUN_DETECTION(UnderrunDetection));
assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour));
/* Check if the SPI is disabled to edit CFG1 register */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Configure Underrun fields */
MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
}
else
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
/* Configure Underrun fields */
MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_SPI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32h7xx_hal_uart_ex.c
* @author MCD Application Team
* @brief Extended UART HAL module driver.
* This file provides firmware functions to manage the following extended
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
*
@verbatim
==============================================================================
##### UART peripheral extended features #####
==============================================================================
(#) Declare a UART_HandleTypeDef handle structure.
(#) For the UART RS485 Driver Enable mode, initialize the UART registers
by calling the HAL_RS485Ex_Init() API.
(#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
-@- When UART operates in FIFO mode, FIFO mode must be enabled prior
starting RX/TX transfers. Also RX/TX FIFO thresholds must be
configured prior starting RX/TX transfers.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup UARTEx UARTEx
* @brief UART Extended HAL module driver
* @{
*/
#ifdef HAL_UART_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
* @{
*/
/* UART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
/* UART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
* @{
*/
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
* @{
*/
/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Extended Initialization and Configuration Functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
in asynchronous mode.
(+) For the asynchronous mode the parameters below can be configured:
(++) Baud Rate
(++) Word Length
(++) Stop Bit
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
(++) Hardware flow control
(++) Receiver/transmitter modes
(++) Over Sampling Method
(++) One-Bit Sampling Method
(+) For the asynchronous mode, the following advanced features can be configured as well:
(++) TX and/or RX pin level inversion
(++) data logical level inversion
(++) RX and TX pins swap
(++) RX overrun detection disabling
(++) DMA disabling on RX error
(++) MSB first on communication line
(++) auto Baud rate detection
[..]
The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
procedures (details for the procedures are available in reference manual).
@endverbatim
Depending on the frame length defined by the M1 and M0 bits (7-bit,
8-bit or 9-bit), the possible UART formats are listed in the
following table.
Table 1. UART frame format.
+-----------------------------------------------------------------------+
| M1 bit | M0 bit | PCE bit | UART frame |
|---------|---------|-----------|---------------------------------------|
| 0 | 0 | 0 | | SB | 8 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 1 | 0 | | SB | 9 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
|---------|---------|-----------|---------------------------------------|
| 1 | 0 | 0 | | SB | 7 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+-----------------------------------------------------------------------+
* @{
*/
/**
* @brief Initialize the RS485 Driver enable feature according to the specified
* parameters in the UART_InitTypeDef and creates the associated handle.
* @param huart UART handle.
* @param Polarity Select the driver enable polarity.
* This parameter can be one of the following values:
* @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
* @arg @ref UART_DE_POLARITY_LOW DE signal is active low
* @param AssertionTime Driver Enable assertion time:
* 5-bit value defining the time between the activation of the DE (Driver Enable)
* signal and the beginning of the start bit. It is expressed in sample time
* units (1/8 or 1/16 bit time, depending on the oversampling rate)
* @param DeassertionTime Driver Enable deassertion time:
* 5-bit value defining the time between the end of the last stop bit, in a
* transmitted message, and the de-activation of the DE (Driver Enable) signal.
* It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
* oversampling rate).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime)
{
uint32_t temp;
/* Check the UART handle allocation */
if (huart == NULL)
{
return HAL_ERROR;
}
/* Check the Driver Enable UART instance */
assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
/* Check the Driver Enable polarity */
assert_param(IS_UART_DE_POLARITY(Polarity));
/* Check the Driver Enable assertion time */
assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
/* Check the Driver Enable deassertion time */
assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
UART_InitCallbacksToDefault(huart);
if (huart->MspInitCallback == NULL)
{
huart->MspInitCallback = HAL_UART_MspInit;
}
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
HAL_UART_MspInit(huart);
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
/* Set the Driver Enable polarity */
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
/* Set the Driver Enable assertion and deassertion times */
temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
}
/**
* @}
*/
/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
* @brief Extended functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
This subsection provides a set of Wakeup and FIFO mode related callback functions.
(#) Wakeup from Stop mode Callback:
(+) HAL_UARTEx_WakeupCallback()
(#) TX/RX Fifos Callbacks:
(+) HAL_UARTEx_RxFifoFullCallback()
(+) HAL_UARTEx_TxFifoEmptyCallback()
@endverbatim
* @{
*/
/**
* @brief UART wakeup from Stop mode callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
*/
}
/**
* @brief UART RX Fifo full callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
*/
}
/**
* @brief UART TX Fifo empty callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides the following functions:
(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
detection length to more than 4 bits for multiprocessor address mark wake up.
(+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
trigger: address match, Start Bit detection or RXNE bit status.
(+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
(+) HAL_UARTEx_DisableStopMode() API disables the above functionality
(+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
(+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
(+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
(+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
@endverbatim
* @{
*/
/**
* @brief By default in multiprocessor mode, when the wake up method is set
* to address mark, the UART handles only 4-bit long addresses detection;
* this API allows to enable longer addresses detection (6-, 7- or 8-bit
* long).
* @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
* 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
* @param huart UART handle.
* @param AddressLength This parameter can be one of the following values:
* @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
* @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
{
/* Check the UART handle allocation */
if (huart == NULL)
{
return HAL_ERROR;
}
/* Check the address length parameter */
assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the address length */
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState to Ready */
return (UART_CheckIdleState(huart));
}
/**
* @brief Set Wakeup from Stop mode interrupt flag selection.
* @note It is the application responsibility to enable the interrupt used as
* usart_wkup interrupt source before entering low-power mode.
* @param huart UART handle.
* @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
* This parameter can be one of the following values:
* @arg @ref UART_WAKEUP_ON_ADDRESS
* @arg @ref UART_WAKEUP_ON_STARTBIT
* @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* check the wake-up from stop mode UART instance */
assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
/* check the wake-up selection parameter */
assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the wake-up selection scheme */
MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
{
UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
}
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
status = HAL_TIMEOUT;
}
else
{
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
return status;
}
/**
* @brief Enable UART Stop Mode.
* @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
/* Set UESM bit */
SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
/**
* @brief Disable UART Stop Mode.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
/* Clear UESM bit */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
/**
* @brief Enable the FIFO mode.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
/* Disable UART */
__HAL_UART_DISABLE(huart);
/* Enable FIFO mode */
SET_BIT(tmpcr1, USART_CR1_FIFOEN);
huart->FifoMode = UART_FIFOMODE_ENABLE;
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
/**
* @brief Disable the FIFO mode.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
/* Disable UART */
__HAL_UART_DISABLE(huart);
/* Enable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
huart->FifoMode = UART_FIFOMODE_DISABLE;
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
/**
* @brief Set the TXFIFO threshold.
* @param huart UART handle.
* @param Threshold TX FIFO threshold value
* This parameter can be one of the following values:
* @arg @ref UART_TXFIFO_THRESHOLD_1_8
* @arg @ref UART_TXFIFO_THRESHOLD_1_4
* @arg @ref UART_TXFIFO_THRESHOLD_1_2
* @arg @ref UART_TXFIFO_THRESHOLD_3_4
* @arg @ref UART_TXFIFO_THRESHOLD_7_8
* @arg @ref UART_TXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
/* Disable UART */
__HAL_UART_DISABLE(huart);
/* Update TX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
/**
* @brief Set the RXFIFO threshold.
* @param huart UART handle.
* @param Threshold RX FIFO threshold value
* This parameter can be one of the following values:
* @arg @ref UART_RXFIFO_THRESHOLD_1_8
* @arg @ref UART_RXFIFO_THRESHOLD_1_4
* @arg @ref UART_RXFIFO_THRESHOLD_1_2
* @arg @ref UART_RXFIFO_THRESHOLD_3_4
* @arg @ref UART_RXFIFO_THRESHOLD_7_8
* @arg @ref UART_RXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
uint32_t tmpcr1;
/* Check the parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
/* Disable UART */
__HAL_UART_DISABLE(huart);
/* Update RX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup UARTEx_Private_Functions
* @{
*/
/**
* @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
* @param huart UART handle.
* @param WakeUpSelection UART wake up from stop mode parameters.
* @retval None
*/
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
{
assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
/* Set the USART address length */
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
/* Set the USART address node */
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
}
/**
* @brief Calculate the number of data to process in RX/TX ISR.
* @note The RX FIFO depth and the TX FIFO depth is extracted from
* the UART configuration registers.
* @param huart UART handle.
* @retval None
*/
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
{
uint8_t rx_fifo_depth;
uint8_t tx_fifo_depth;
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
{
huart->NbTxDataToProcess = 1U;
huart->NbRxDataToProcess = 1U;
}
else
{
rx_fifo_depth = RX_FIFO_DEPTH;
tx_fifo_depth = TX_FIFO_DEPTH;
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
}
}
/**
* @}
*/
#endif /* HAL_UART_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c
+3675
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c
+538
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/**
******************************************************************************
* @file stm32h7xx_hal_usart_ex.c
* @author MCD Application Team
* @brief Extended USART HAL module driver.
* This file provides firmware functions to manage the following extended
* functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
* + Peripheral Control functions
*
*
@verbatim
==============================================================================
##### USART peripheral extended features #####
==============================================================================
(#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
-@- When USART operates in FIFO mode, FIFO mode must be enabled prior
starting RX/TX transfers. Also RX/TX FIFO thresholds must be
configured prior starting RX/TX transfers.
(#) Slave mode enabling/disabling and NSS pin configuration.
-@- When USART operates in Slave mode, Slave mode must be enabled prior
starting RX/TX transfers.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup USARTEx USARTEx
* @brief USART Extended HAL module driver
* @{
*/
#ifdef HAL_USART_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
* @{
*/
/* UART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
/* UART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
*/
/* Private define ------------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup USARTEx_Private_Functions USARTEx Private Functions
* @{
*/
static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions
* @{
*/
/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
* @brief Extended USART Transmit/Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
This subsection provides a set of FIFO mode related callback functions.
(#) TX/RX Fifos Callbacks:
(+) HAL_USARTEx_RxFifoFullCallback()
(+) HAL_USARTEx_TxFifoEmptyCallback()
@endverbatim
* @{
*/
/**
* @brief USART RX Fifo full callback.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file.
*/
}
/**
* @brief USART TX Fifo empty callback.
* @param husart USART handle.
* @retval None
*/
__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides the following functions:
(+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
(+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
(+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
(+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
(+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
(+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
(+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
@endverbatim
* @{
*/
/**
* @brief Enable the SPI slave mode.
* @note When the USART operates in SPI slave mode, it handles data flow using
* the serial interface clock derived from the external SCLK signal
* provided by the external master SPI device.
* @note In SPI slave mode, the USART must be enabled before starting the master
* communications (or between frames while the clock is stable). Otherwise,
* if the USART slave is enabled while the master is in the middle of a
* frame, it will become desynchronized with the master.
* @note The data register of the slave needs to be ready before the first edge
* of the communication clock or before the end of the ongoing communication,
* otherwise the SPI slave will transmit zeros.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
/* Process Locked */
__HAL_LOCK(husart);
husart->State = HAL_USART_STATE_BUSY;
/* Save actual USART configuration */
tmpcr1 = READ_REG(husart->Instance->CR1);
/* Disable USART */
__HAL_USART_DISABLE(husart);
/* In SPI slave mode mode, the following bits must be kept cleared:
- LINEN and CLKEN bit in the USART_CR2 register
- HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
/* Enable SPI slave mode */
SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
husart->SlaveMode = USART_SLAVEMODE_ENABLE;
husart->State = HAL_USART_STATE_READY;
/* Enable USART */
__HAL_USART_ENABLE(husart);
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
/**
* @brief Disable the SPI slave mode.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
/* Process Locked */
__HAL_LOCK(husart);
husart->State = HAL_USART_STATE_BUSY;
/* Save actual USART configuration */
tmpcr1 = READ_REG(husart->Instance->CR1);
/* Disable USART */
__HAL_USART_DISABLE(husart);
/* Disable SPI slave mode */
CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
husart->SlaveMode = USART_SLAVEMODE_ENABLE;
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
/**
* @brief Configure the Slave Select input pin (NSS).
* @note Software NSS management: SPI slave will always be selected and NSS
* input pin will be ignored.
* @note Hardware NSS management: the SPI slave selection depends on NSS
* input pin. The slave is selected when NSS is low and deselected when
* NSS is high.
* @param husart USART handle.
* @param NSSConfig NSS configuration.
* This parameter can be one of the following values:
* @arg @ref USART_NSS_HARD
* @arg @ref USART_NSS_SOFT
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
assert_param(IS_USART_NSS(NSSConfig));
/* Process Locked */
__HAL_LOCK(husart);
husart->State = HAL_USART_STATE_BUSY;
/* Save actual USART configuration */
tmpcr1 = READ_REG(husart->Instance->CR1);
/* Disable USART */
__HAL_USART_DISABLE(husart);
/* Program DIS_NSS bit in the USART_CR2 register */
MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig);
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
/**
* @brief Enable the FIFO mode.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
/* Process Locked */
__HAL_LOCK(husart);
husart->State = HAL_USART_STATE_BUSY;
/* Save actual USART configuration */
tmpcr1 = READ_REG(husart->Instance->CR1);
/* Disable USART */
__HAL_USART_DISABLE(husart);
/* Enable FIFO mode */
SET_BIT(tmpcr1, USART_CR1_FIFOEN);
husart->FifoMode = USART_FIFOMODE_ENABLE;
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
/* Determine the number of data to process during RX/TX ISR execution */
USARTEx_SetNbDataToProcess(husart);
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
/**
* @brief Disable the FIFO mode.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
/* Process Locked */
__HAL_LOCK(husart);
husart->State = HAL_USART_STATE_BUSY;
/* Save actual USART configuration */
tmpcr1 = READ_REG(husart->Instance->CR1);
/* Disable USART */
__HAL_USART_DISABLE(husart);
/* Enable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
husart->FifoMode = USART_FIFOMODE_DISABLE;
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
/**
* @brief Set the TXFIFO threshold.
* @param husart USART handle.
* @param Threshold TX FIFO threshold value
* This parameter can be one of the following values:
* @arg @ref USART_TXFIFO_THRESHOLD_1_8
* @arg @ref USART_TXFIFO_THRESHOLD_1_4
* @arg @ref USART_TXFIFO_THRESHOLD_1_2
* @arg @ref USART_TXFIFO_THRESHOLD_3_4
* @arg @ref USART_TXFIFO_THRESHOLD_7_8
* @arg @ref USART_TXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
{
uint32_t tmpcr1;
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(husart);
husart->State = HAL_USART_STATE_BUSY;
/* Save actual USART configuration */
tmpcr1 = READ_REG(husart->Instance->CR1);
/* Disable USART */
__HAL_USART_DISABLE(husart);
/* Update TX threshold configuration */
MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
/* Determine the number of data to process during RX/TX ISR execution */
USARTEx_SetNbDataToProcess(husart);
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
/**
* @brief Set the RXFIFO threshold.
* @param husart USART handle.
* @param Threshold RX FIFO threshold value
* This parameter can be one of the following values:
* @arg @ref USART_RXFIFO_THRESHOLD_1_8
* @arg @ref USART_RXFIFO_THRESHOLD_1_4
* @arg @ref USART_RXFIFO_THRESHOLD_1_2
* @arg @ref USART_RXFIFO_THRESHOLD_3_4
* @arg @ref USART_RXFIFO_THRESHOLD_7_8
* @arg @ref USART_RXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
{
uint32_t tmpcr1;
/* Check the parameters */
assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(husart);
husart->State = HAL_USART_STATE_BUSY;
/* Save actual USART configuration */
tmpcr1 = READ_REG(husart->Instance->CR1);
/* Disable USART */
__HAL_USART_DISABLE(husart);
/* Update RX threshold configuration */
MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
/* Determine the number of data to process during RX/TX ISR execution */
USARTEx_SetNbDataToProcess(husart);
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup USARTEx_Private_Functions
* @{
*/
/**
* @brief Calculate the number of data to process in RX/TX ISR.
* @note The RX FIFO depth and the TX FIFO depth is extracted from
* the USART configuration registers.
* @param husart USART handle.
* @retval None
*/
static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
{
uint8_t rx_fifo_depth;
uint8_t tx_fifo_depth;
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (husart->FifoMode == USART_FIFOMODE_DISABLE)
{
husart->NbTxDataToProcess = 1U;
husart->NbRxDataToProcess = 1U;
}
else
{
rx_fifo_depth = RX_FIFO_DEPTH;
tx_fifo_depth = TX_FIFO_DEPTH;
rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
}
}
/**
* @}
*/
#endif /* HAL_USART_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c
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/**
******************************************************************************
* @file stm32h7xx_hal_wwdg.c
* @author MCD Application Team
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
* + Initialization and Configuration functions
* + IO operation functions
@verbatim
==============================================================================
##### WWDG Specific features #####
==============================================================================
[..]
Once enabled the WWDG generates a system reset on expiry of a programmed
time period, unless the program refreshes the counter (T[6;0] downcounter)
before reaching 0x3F value (i.e. a reset is generated when the counter
value rolls down from 0x40 to 0x3F).
(+) An MCU reset is also generated if the counter value is refreshed
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
(+) Once enabled the WWDG cannot be disabled except by a system reset.
(+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
reset occurs.
(+) The WWDG counter input clock is derived from the APB clock divided
by a programmable prescaler.
(+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
(+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
where T[5;0] are the lowest 6 bits of Counter.
(+) WWDG Counter refresh is allowed between the following limits :
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
(++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
max timeout before reset: approximately 73.14µs
(++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
max timeout before reset: approximately 599.18ms
==============================================================================
##### How to use this driver #####
==============================================================================
*** Common driver usage ***
===========================
[..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window and counter value
using HAL_WWDG_Init() function.
(+) Start the WWDG using HAL_WWDG_Start() function.
When the WWDG is enabled the counter value should be configured to
a value greater than 0x40 to prevent generating an immediate reset.
(+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
generated when the counter reaches 0x40, and then start the WWDG using
HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
add his own code by customization of callback HAL_WWDG_WakeupCallback.
Once enabled, EWI interrupt cannot be disabled except by a system reset.
(+) Then the application program must refresh the WWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_WWDG_Refresh() function. This operation must occur only when
the counter is lower than the refresh window value already programmed.
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
@ref HAL_WWDG_RegisterCallback() to register a user callback.
(+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
callbacks:
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
takes as parameters the HAL peripheral handle and the Callback ID.
This function allows to reset following callbacks:
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
[..]
When calling @ref HAL_WWDG_Init function, callbacks are reset to the
corresponding legacy weak (surcharged) functions:
@ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
not been registered before.
[..]
When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
*** WWDG HAL driver macros list ***
===================================
[..]
Below the list of most used macros in WWDG HAL driver.
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
(+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_WWDG_MODULE_ENABLED
/** @defgroup WWDG WWDG
* @brief WWDG HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
* @{
*/
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions.
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and start the WWDG according to the specified parameters
in the WWDG_InitTypeDef of associated handle.
(+) Initialize the WWDG MSP.
@endverbatim
* @{
*/
/**
* @brief Initialize the WWDG according to the specified.
* parameters in the WWDG_InitTypeDef of associated handle.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
{
/* Check the WWDG handle allocation */
if (hwwdg == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers */
if (hwwdg->EwiCallback == NULL)
{
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
}
if (hwwdg->MspInitCallback == NULL)
{
hwwdg->MspInitCallback = HAL_WWDG_MspInit;
}
/* Init the low level hardware */
hwwdg->MspInitCallback(hwwdg);
#else
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
#endif
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
/* Set WWDG Prescaler and Window */
WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the WWDG MSP.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @note When rewriting this function in user file, mechanism may be added
* to avoid multiple initialize when HAL_WWDG_Init function is called
* again to change parameters.
* @retval None
*/
__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hwwdg);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_WWDG_MspInit could be implemented in the user file
*/
}
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User WWDG Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hwwdg WWDG handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
* @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
status = HAL_ERROR;
}
else
{
switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = pCallback;
break;
case HAL_WWDG_MSPINIT_CB_ID:
hwwdg->MspInitCallback = pCallback;
break;
default:
status = HAL_ERROR;
break;
}
}
return status;
}
/**
* @brief Unregister a WWDG Callback
* WWDG Callback is redirected to the weak (surcharged) predefined callback
* @param hwwdg WWDG handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
* @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
break;
case HAL_WWDG_MSPINIT_CB_ID:
hwwdg->MspInitCallback = HAL_WWDG_MspInit;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
#endif
/**
* @}
*/
/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
==============================================================================
##### IO operation functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Refresh the WWDG.
(+) Handle WWDG interrupt request and associated function callback.
@endverbatim
* @{
*/
/**
* @brief Refresh the WWDG.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
{
/* Write to WWDG CR the WWDG Counter value to refresh with */
WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
/* Return function status */
return HAL_OK;
}
/**
* @brief Handle WWDG interrupt request.
* @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
* or data logging must be performed before the actual reset is generated.
* The EWI interrupt is enabled by calling HAL_WWDG_Init function with
* EWIMode set to WWDG_EWI_ENABLE.
* When the downcounter reaches the value 0x40, and EWI interrupt is
* generated and the corresponding Interrupt Service Routine (ISR) can
* be used to trigger specific actions (such as communications or data
* logging), before resetting the device.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval None
*/
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
{
/* Check if Early Wakeup Interrupt is enable */
if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
/* Check if WWDG Early Wakeup Interrupt occurred */
if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
{
/* Clear the WWDG Early Wakeup flag */
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/* Early Wakeup registered callback */
hwwdg->EwiCallback(hwwdg);
#else
/* Early Wakeup callback */
HAL_WWDG_EarlyWakeupCallback(hwwdg);
#endif
}
}
}
/**
* @brief WWDG Early Wakeup callback.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval None
*/
__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hwwdg);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_WWDG_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c
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libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c
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