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@@ -0,0 +1,14 @@
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# RT-Thread building script for component
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from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
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src = src + ['../common/atomic_riscv.c']
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CPPPATH = [cwd]
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group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2006-2023 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-03-12 WangXiaoyao the first version
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*/
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#ifndef __ASM_GENERIC_H__
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#define __ASM_GENERIC_H__
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/* use to mark a start point where every task start from */
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#define START_POINT(funcname) \
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.global funcname; \
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.type funcname, %function; \
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funcname: \
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.cfi_sections .debug_frame, .eh_frame; \
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.cfi_startproc; \
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.cfi_undefined ra
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#define START_POINT_END(name) \
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.cfi_endproc; \
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.size name, .-name;
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#endif /* __ASM_GENERIC_H__ */
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@@ -0,0 +1,125 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-10-18 Shell Add backtrace support
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*/
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#define DBG_TAG "hw.backtrace"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#include <rtthread.h>
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#include <mm_aspace.h>
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#include "riscv_mmu.h"
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#define WORD sizeof(rt_base_t)
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#define ARCH_CONTEXT_FETCH(pctx, id) (*(((unsigned long *)pctx) + (id)))
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rt_inline rt_err_t _bt_kaddr(rt_ubase_t *fp, struct rt_hw_backtrace_frame *frame)
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{
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rt_err_t rc;
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frame->fp = *(fp - 2);
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frame->pc = *(fp - 1);
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if ((rt_ubase_t)fp == frame->fp)
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{
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rc = -RT_ERROR;
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}
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else
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{
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rc = RT_EOK;
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}
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return rc;
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}
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#ifdef RT_USING_SMART
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#include <lwp_arch.h>
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#include <lwp_user_mm.h>
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rt_inline rt_err_t _bt_uaddr(rt_lwp_t lwp, rt_ubase_t *fp, struct rt_hw_backtrace_frame *frame)
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{
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rt_err_t rc;
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if (lwp_data_get(lwp, &frame->fp, fp - 2, WORD) != WORD)
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{
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rc = -RT_EFAULT;
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}
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else if (lwp_data_get(lwp, &frame->pc, fp - 1, WORD) != WORD)
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{
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rc = -RT_EFAULT;
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}
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else if ((rt_ubase_t)fp == frame->fp)
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{
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rc = -RT_ERROR;
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}
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else
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{
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frame->pc -= 0;
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rc = RT_EOK;
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}
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return rc;
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}
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#endif /* RT_USING_SMART */
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rt_err_t rt_hw_backtrace_frame_unwind(rt_thread_t thread, struct rt_hw_backtrace_frame *frame)
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{
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rt_err_t rc = -RT_ERROR;
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rt_ubase_t *fp = (rt_ubase_t *)frame->fp;
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if (fp && !((long)fp & 0x7))
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{
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#ifdef RT_USING_SMART
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if (thread->lwp)
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{
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void *lwp = thread->lwp;
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void *this_lwp = lwp_self();
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if (this_lwp == lwp && rt_hw_mmu_v2p(((rt_lwp_t)lwp)->aspace, fp) != ARCH_MAP_FAILED)
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{
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rc = _bt_kaddr(fp, frame);
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}
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else if (lwp_user_accessible_ext(lwp, (void *)fp, WORD))
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{
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rc = _bt_uaddr(lwp, fp, frame);
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}
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else
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{
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rc = -RT_EFAULT;
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}
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}
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else
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#endif
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if ((rt_kmem_v2p(fp) != ARCH_MAP_FAILED))
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{
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rc = _bt_kaddr(fp, frame);
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}
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else
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{
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rc = -RT_EINVAL;
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}
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}
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else
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{
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rc = -RT_EFAULT;
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}
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return rc;
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}
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rt_err_t rt_hw_backtrace_frame_get(rt_thread_t thread, struct rt_hw_backtrace_frame *frame)
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{
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rt_err_t rc;
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if (!thread || !frame)
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{
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rc = -RT_EINVAL;
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}
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else
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{
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frame->pc = ARCH_CONTEXT_FETCH(thread->sp, 13);
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frame->fp = ARCH_CONTEXT_FETCH(thread->sp, 12);
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rc = RT_EOK;
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}
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return rc;
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}
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@@ -0,0 +1,59 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-29 lizhirui first version
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*/
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#include <rthw.h>
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#include <rtdef.h>
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#include <board.h>
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#include <riscv.h>
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#include <cache.h>
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rt_inline rt_uint32_t rt_cpu_icache_line_size()
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{
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return 0;
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}
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rt_inline rt_uint32_t rt_cpu_dcache_line_size()
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{
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return 0;
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}
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void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
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{
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if (ops == RT_HW_CACHE_INVALIDATE)
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{
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rt_hw_cpu_icache_invalidate(addr, size);
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}
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}
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void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
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{
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if (ops == RT_HW_CACHE_FLUSH)
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{
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rt_hw_cpu_dcache_clean(addr, size);
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}
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else
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{
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rt_hw_cpu_dcache_invalidate(addr, size);
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}
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}
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rt_base_t rt_hw_cpu_icache_status_local()
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{
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return 0;
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}
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rt_base_t rt_hw_cpu_dcache_status()
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{
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return 0;
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}
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void rt_hw_sync_cache_local(void *addr, int size)
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{
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}
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@@ -0,0 +1,88 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-11-09 RT-Thread The first version
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*/
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#ifndef __CACHE_H__
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#define __CACHE_H__
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#include <rtdef.h>
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/**
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* @brief These APIs may not be supported by a specified architecture
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* But we have to include to all the cases to be 'general purpose'
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*/
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rt_always_inline void rt_hw_cpu_dcache_clean_local(void *addr, int size)
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{
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RT_UNUSED(addr);
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RT_UNUSED(size);
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}
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rt_always_inline void rt_hw_cpu_dcache_invalidate_local(void *addr, int size)
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{
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RT_UNUSED(addr);
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RT_UNUSED(size);
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}
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rt_always_inline void rt_hw_cpu_dcache_clean_and_invalidate_local(void *addr, int size)
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{
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RT_UNUSED(addr);
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RT_UNUSED(size);
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}
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rt_always_inline void rt_hw_cpu_dcache_clean_all_local(void)
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{
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}
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rt_always_inline void rt_hw_cpu_dcache_invalidate_all_local(void)
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{
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}
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rt_always_inline void rt_hw_cpu_dcache_clean_and_invalidate_all_local(void)
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{
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}
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rt_always_inline void rt_hw_cpu_icache_invalidate_local(void *addr, int size)
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{
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RT_UNUSED(addr);
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RT_UNUSED(size);
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}
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rt_always_inline void rt_hw_cpu_icache_invalidate_all_local(void)
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{
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}
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/**
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* @brief Multi-core
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*/
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#define rt_hw_cpu_dcache_clean rt_hw_cpu_dcache_clean_local
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#define rt_hw_cpu_dcache_invalidate rt_hw_cpu_dcache_invalidate_local
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#define rt_hw_cpu_dcache_clean_and_invalidate rt_hw_cpu_dcache_clean_and_invalidate_local
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#define rt_hw_cpu_dcache_clean_all rt_hw_cpu_dcache_clean_all_local
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#define rt_hw_cpu_dcache_invalidate_all rt_hw_cpu_dcache_invalidate_all_local
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#define rt_hw_cpu_dcache_clean_and_invalidate_all rt_hw_cpu_dcache_clean_and_invalidate_all_local
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#define rt_hw_cpu_icache_invalidate rt_hw_cpu_icache_invalidate_local
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#define rt_hw_cpu_icache_invalidate_all rt_hw_cpu_icache_invalidate_all_local
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#define rt_hw_icache_invalidate_all rt_hw_cpu_icache_invalidate_all
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/** instruction barrier */
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static inline void rt_hw_cpu_sync(void) {}
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/**
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* @brief local cpu icahce & dcache synchronization
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*
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* @param addr
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* @param size
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*/
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void rt_hw_sync_cache_local(void *addr, int size);
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#endif /* __CACHE_H__ */
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@@ -0,0 +1,145 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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||||
* Change Logs:
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||||
* Date Author Notes
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||||
* 2018/10/28 Bernard The unify RISC-V porting implementation
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* 2018/12/27 Jesven Add SMP support
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* 2021/02/02 lizhirui Add userspace support
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* 2022/10/22 WangXiaoyao Support User mode RVV;
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* Trimming process switch context
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*/
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#include "cpuport.h"
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#include "stackframe.h"
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.macro PUSH_8 reg
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addi sp, sp, -8
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STORE \reg, (sp)
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.endm
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.macro POP_8 reg
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LOAD \reg, (sp)
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addi sp, sp, 8
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.endm
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.macro RESERVE_CONTEXT
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PUSH_8 tp
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PUSH_8 ra
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PUSH_8 s0
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PUSH_8 s1
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PUSH_8 s2
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PUSH_8 s3
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PUSH_8 s4
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PUSH_8 s5
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PUSH_8 s6
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PUSH_8 s7
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PUSH_8 s8
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PUSH_8 s9
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PUSH_8 s10
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PUSH_8 s11
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csrr s11, sstatus
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li s10, (SSTATUS_SPP)
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or s11, s11, s10
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PUSH_8 s11
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.endm
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.macro RESTORE_CONTEXT
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POP_8 s11
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csrw sstatus, s11
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POP_8 s11
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POP_8 s10
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POP_8 s9
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POP_8 s8
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POP_8 s7
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POP_8 s6
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POP_8 s5
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POP_8 s4
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POP_8 s3
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POP_8 s2
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POP_8 s1
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POP_8 s0
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POP_8 ra
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POP_8 tp
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csrw sepc, ra
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.endm
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/*
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* void rt_hw_context_switch_to(rt_ubase_t to);
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*
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* a0 --> to SP pointer
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LOAD sp, (a0)
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la s0, rt_current_thread
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LOAD s1, (s0)
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||||
|
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#ifdef RT_USING_SMART
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mv a0, s1
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jal lwp_aspace_switch
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#endif
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||||
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RESTORE_CONTEXT
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||||
sret
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||||
|
||||
/*
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||||
* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
|
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*
|
||||
* a0 --> from SP pointer
|
||||
* a1 --> to SP pointer
|
||||
*
|
||||
* It should only be used on local interrupt disable
|
||||
*/
|
||||
.globl rt_hw_context_switch
|
||||
rt_hw_context_switch:
|
||||
RESERVE_CONTEXT
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STORE sp, (a0)
|
||||
|
||||
// restore to thread SP
|
||||
LOAD sp, (a1)
|
||||
|
||||
// restore Address Space
|
||||
la s0, rt_current_thread
|
||||
LOAD s1, (s0)
|
||||
|
||||
#ifdef RT_USING_SMART
|
||||
mv a0, s1
|
||||
jal lwp_aspace_switch
|
||||
#endif
|
||||
|
||||
RESTORE_CONTEXT
|
||||
sret
|
||||
|
||||
#ifdef ENABLE_VECTOR
|
||||
/**
|
||||
* @param a0 pointer to frame bottom
|
||||
*/
|
||||
.global rt_hw_vector_ctx_save
|
||||
rt_hw_vector_ctx_save:
|
||||
SAVE_VECTOR a0
|
||||
ret
|
||||
|
||||
/**
|
||||
* @param a0 pointer to frame bottom
|
||||
*/
|
||||
.global rt_hw_vector_ctx_restore
|
||||
rt_hw_vector_ctx_restore:
|
||||
RESTORE_VECTOR a0
|
||||
ret
|
||||
|
||||
.global rt_hw_disable_vector
|
||||
rt_hw_disable_vector:
|
||||
li t0, SSTATUS_VS
|
||||
csrc sstatus, t0
|
||||
ret
|
||||
|
||||
.global rt_hw_enable_vector
|
||||
rt_hw_enable_vector:
|
||||
li t0, SSTATUS_VS
|
||||
csrs sstatus, t0
|
||||
ret
|
||||
#endif /* ENABLE_VECTOR */
|
||||
@@ -0,0 +1,132 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/28 Bernard The unify RISC-V porting code.
|
||||
* 2021-02-11 lizhirui add gp support
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "cpuport.h"
|
||||
#include "stack.h"
|
||||
#include <sbi.h>
|
||||
#include <encoding.h>
|
||||
|
||||
#define K_SSTATUS_DEFAULT (SSTATUS_SPP | SSTATUS_SPIE | SSTATUS_SUM | SSTATUS_FS)
|
||||
|
||||
/**
|
||||
* @brief from thread used interrupt context switch
|
||||
*
|
||||
*/
|
||||
volatile rt_ubase_t rt_interrupt_from_thread = 0;
|
||||
/**
|
||||
* @brief to thread used interrupt context switch
|
||||
*
|
||||
*/
|
||||
volatile rt_ubase_t rt_interrupt_to_thread = 0;
|
||||
/**
|
||||
* @brief flag to indicate context switch in interrupt or not
|
||||
*
|
||||
*/
|
||||
volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
|
||||
|
||||
void *_rt_hw_stack_init(rt_ubase_t *sp, rt_ubase_t ra, rt_ubase_t sstatus)
|
||||
{
|
||||
(*--sp) = 0; /* tp */
|
||||
(*--sp) = ra; /* ra */
|
||||
(*--sp) = 0; /* s0(fp) */
|
||||
(*--sp) = 0; /* s1 */
|
||||
(*--sp) = 0; /* s2 */
|
||||
(*--sp) = 0; /* s3 */
|
||||
(*--sp) = 0; /* s4 */
|
||||
(*--sp) = 0; /* s5 */
|
||||
(*--sp) = 0; /* s6 */
|
||||
(*--sp) = 0; /* s7 */
|
||||
(*--sp) = 0; /* s8 */
|
||||
(*--sp) = 0; /* s9 */
|
||||
(*--sp) = 0; /* s10 */
|
||||
(*--sp) = 0; /* s11 */
|
||||
(*--sp) = sstatus; /* sstatus */
|
||||
|
||||
return (void *)sp;
|
||||
}
|
||||
|
||||
int rt_hw_cpu_id(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack, we assuming
|
||||
* when scheduler restore this new thread, context will restore
|
||||
* an entry to user first application
|
||||
*
|
||||
* s0-s11, ra, sstatus, a0
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry,
|
||||
void *parameter,
|
||||
rt_uint8_t *stack_addr,
|
||||
void *texit)
|
||||
{
|
||||
rt_ubase_t *sp = (rt_ubase_t *)stack_addr;
|
||||
// we use a strict alignment requirement for Q extension
|
||||
sp = (rt_ubase_t *)RT_ALIGN_DOWN((rt_ubase_t)sp, 16);
|
||||
|
||||
(*--sp) = (rt_ubase_t)tentry;
|
||||
(*--sp) = (rt_ubase_t)parameter;
|
||||
(*--sp) = (rt_ubase_t)texit;
|
||||
|
||||
/* compatible to RESTORE_CONTEXT */
|
||||
extern void _rt_thread_entry(void);
|
||||
return (rt_uint8_t *)_rt_hw_stack_init(sp, (rt_ubase_t)_rt_thread_entry, K_SSTATUS_DEFAULT);
|
||||
}
|
||||
|
||||
/*
|
||||
* #ifdef RT_USING_SMP
|
||||
* void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
|
||||
* #else
|
||||
* void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
|
||||
* #endif
|
||||
*/
|
||||
#ifndef RT_USING_SMP
|
||||
void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread)
|
||||
{
|
||||
if (rt_thread_switch_interrupt_flag == 0)
|
||||
rt_interrupt_from_thread = from;
|
||||
|
||||
rt_interrupt_to_thread = to;
|
||||
rt_thread_switch_interrupt_flag = 1;
|
||||
|
||||
return;
|
||||
}
|
||||
#endif /* end of RT_USING_SMP */
|
||||
|
||||
/** shutdown CPU */
|
||||
void rt_hw_cpu_shutdown(void)
|
||||
{
|
||||
rt_uint32_t level;
|
||||
rt_kprintf("shutdown...\n");
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
|
||||
sbi_shutdown();
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
void rt_hw_set_process_id(int pid)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-03 Bernard The first version
|
||||
*/
|
||||
|
||||
#ifndef CPUPORT_H__
|
||||
#define CPUPORT_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
/* bytes of register width */
|
||||
#ifdef ARCH_CPU_64BIT
|
||||
#define STORE sd
|
||||
#define LOAD ld
|
||||
#define REGBYTES 8
|
||||
#else
|
||||
// error here, not portable
|
||||
#error "Not supported XLEN"
|
||||
#endif
|
||||
|
||||
/* 33 general register */
|
||||
#define CTX_GENERAL_REG_NR 33
|
||||
|
||||
#ifdef ENABLE_FPU
|
||||
/* 32 fpu register */
|
||||
#define CTX_FPU_REG_NR 32
|
||||
#else
|
||||
#define CTX_FPU_REG_NR 0
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_VECTOR
|
||||
|
||||
#if defined(ARCH_VECTOR_VLEN_128)
|
||||
#define CTX_VECTOR_REGS 64
|
||||
#elif defined(ARCH_VECTOR_VLEN_256)
|
||||
#define CTX_VECTOR_REGS 128
|
||||
#endif
|
||||
|
||||
#define CTX_VECTOR_REG_NR (CTX_VECTOR_REGS + 4)
|
||||
#else
|
||||
#define CTX_VECTOR_REG_NR 0
|
||||
#endif
|
||||
|
||||
/* all context registers */
|
||||
#define CTX_REG_NR (CTX_GENERAL_REG_NR + CTX_FPU_REG_NR + CTX_VECTOR_REG_NR)
|
||||
|
||||
#ifdef RT_USING_SMP
|
||||
typedef union {
|
||||
unsigned long slock;
|
||||
struct __arch_tickets {
|
||||
unsigned short owner;
|
||||
unsigned short next;
|
||||
} tickets;
|
||||
} rt_hw_spinlock_t;
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <rtdef.h>
|
||||
rt_inline void rt_hw_dsb(void)
|
||||
{
|
||||
asm volatile("fence":::"memory");
|
||||
}
|
||||
|
||||
rt_inline void rt_hw_dmb(void)
|
||||
{
|
||||
asm volatile("fence":::"memory");
|
||||
}
|
||||
|
||||
rt_inline void rt_hw_isb(void)
|
||||
{
|
||||
asm volatile(".long 0x0000100F":::"memory");
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#ifdef RISCV_U_MODE
|
||||
#define RISCV_USER_ENTRY 0xFFFFFFE000000000ULL
|
||||
#endif
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-10-19 RT-Thread the first version
|
||||
*/
|
||||
|
||||
#include "cpuport.h"
|
||||
#include "stackframe.h"
|
||||
#include "asm-generic.h"
|
||||
|
||||
START_POINT(_rt_thread_entry)
|
||||
LOAD ra, (sp) /* thread exit */
|
||||
addi sp, sp, 8
|
||||
LOAD a0, (sp) /* parameter */
|
||||
addi sp, sp, 8
|
||||
LOAD t0, (sp) /* tentry */
|
||||
addi sp, sp, 8
|
||||
mv s1, ra
|
||||
jalr t0
|
||||
jalr s1
|
||||
j . /* never here */
|
||||
START_POINT_END(_rt_thread_entry)
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-10-10 RT-Thread the first version,
|
||||
* compatible to riscv-v-spec-1.0
|
||||
*/
|
||||
#ifndef __EXT_CONTEXT_H__
|
||||
#define __EXT_CONTEXT_H__
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/**
|
||||
* extension context maintenance
|
||||
*/
|
||||
|
||||
#include "cpuport.h"
|
||||
#include "encoding.h"
|
||||
#include "vector_encoding.h"
|
||||
|
||||
/**
|
||||
* ==================================
|
||||
* FPU EXTENSION
|
||||
* ==================================
|
||||
*/
|
||||
|
||||
#ifdef ENABLE_FPU
|
||||
#define FPU_CTX_F0_OFF 0 /* offsetof(fpu_context_t, fpustatus.f[0]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F1_OFF 8 /* offsetof(fpu_context_t, fpustatus.f[1]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F2_OFF 16 /* offsetof(fpu_context_t, fpustatus.f[2]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F3_OFF 24 /* offsetof(fpu_context_t, fpustatus.f[3]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F4_OFF 32 /* offsetof(fpu_context_t, fpustatus.f[4]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F5_OFF 40 /* offsetof(fpu_context_t, fpustatus.f[5]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F6_OFF 48 /* offsetof(fpu_context_t, fpustatus.f[6]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F7_OFF 56 /* offsetof(fpu_context_t, fpustatus.f[7]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F8_OFF 64 /* offsetof(fpu_context_t, fpustatus.f[8]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F9_OFF 72 /* offsetof(fpu_context_t, fpustatus.f[9]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F10_OFF 80 /* offsetof(fpu_context_t, fpustatus.f[10]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F11_OFF 88 /* offsetof(fpu_context_t, fpustatus.f[11]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F12_OFF 96 /* offsetof(fpu_context_t, fpustatus.f[12]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F13_OFF 104 /* offsetof(fpu_context_t, fpustatus.f[13]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F14_OFF 112 /* offsetof(fpu_context_t, fpustatus.f[14]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F15_OFF 120 /* offsetof(fpu_context_t, fpustatus.f[15]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F16_OFF 128 /* offsetof(fpu_context_t, fpustatus.f[16]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F17_OFF 136 /* offsetof(fpu_context_t, fpustatus.f[17]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F18_OFF 144 /* offsetof(fpu_context_t, fpustatus.f[18]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F19_OFF 152 /* offsetof(fpu_context_t, fpustatus.f[19]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F20_OFF 160 /* offsetof(fpu_context_t, fpustatus.f[20]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F21_OFF 168 /* offsetof(fpu_context_t, fpustatus.f[21]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F22_OFF 176 /* offsetof(fpu_context_t, fpustatus.f[22]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F23_OFF 184 /* offsetof(fpu_context_t, fpustatus.f[23]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F24_OFF 192 /* offsetof(fpu_context_t, fpustatus.f[24]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F25_OFF 200 /* offsetof(fpu_context_t, fpustatus.f[25]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F26_OFF 208 /* offsetof(fpu_context_t, fpustatus.f[26]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F27_OFF 216 /* offsetof(fpu_context_t, fpustatus.f[27]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F28_OFF 224 /* offsetof(fpu_context_t, fpustatus.f[28]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F29_OFF 232 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F30_OFF 240 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#define FPU_CTX_F31_OFF 248 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */
|
||||
#endif /* ENABLE_FPU */
|
||||
|
||||
/**
|
||||
* ==================================
|
||||
* VECTOR EXTENSION
|
||||
* ==================================
|
||||
*/
|
||||
|
||||
#ifdef ENABLE_VECTOR
|
||||
|
||||
#define VEC_FRAME_VSTART (0 * REGBYTES)
|
||||
#define VEC_FRAME_VTYPE (1 * REGBYTES)
|
||||
#define VEC_FRAME_VL (2 * REGBYTES)
|
||||
#define VEC_FRAME_VCSR (3 * REGBYTES)
|
||||
#define VEC_FRAME_V0 (4 * REGBYTES)
|
||||
|
||||
.macro GET_VEC_FRAME_LEN, xreg
|
||||
csrr \xreg, vlenb
|
||||
slli \xreg, \xreg, 5
|
||||
addi \xreg, \xreg, 4 * REGBYTES
|
||||
.endm
|
||||
|
||||
/**
|
||||
* @brief save vector extension hardware state
|
||||
*
|
||||
* @param dst register storing bottom of storage block
|
||||
*
|
||||
*/
|
||||
.macro SAVE_VECTOR, dst
|
||||
mv t1, \dst
|
||||
|
||||
csrr t0, vstart
|
||||
STORE t0, VEC_FRAME_VSTART(t1)
|
||||
csrr t0, vtype
|
||||
STORE t0, VEC_FRAME_VTYPE(t1)
|
||||
csrr t0, vl
|
||||
STORE t0, VEC_FRAME_VL(t1)
|
||||
csrr t0, vcsr
|
||||
STORE t0, VEC_FRAME_VCSR(t1)
|
||||
|
||||
addi t1, t1, VEC_FRAME_V0
|
||||
|
||||
// config vector setting,
|
||||
// t2 is updated to length of a vector group in bytes
|
||||
VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8)
|
||||
|
||||
vse8.v v0, (t1)
|
||||
add t1, t1, t2
|
||||
vse8.v v8, (t1)
|
||||
add t1, t1, t2
|
||||
vse8.v v16, (t1)
|
||||
add t1, t1, t2
|
||||
vse8.v v24, (t1)
|
||||
.endm
|
||||
|
||||
/**
|
||||
* @brief restore vector extension hardware states
|
||||
*
|
||||
* @param dst register storing bottom of storage block
|
||||
*
|
||||
*/
|
||||
.macro RESTORE_VECTOR, dst
|
||||
// restore vector registers first since it will modify vector states
|
||||
mv t0, \dst
|
||||
addi t1, t0, VEC_FRAME_V0
|
||||
|
||||
VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8)
|
||||
|
||||
vle8.v v0, (t1)
|
||||
add t1, t1, t2
|
||||
vle8.v v8, (t1)
|
||||
add t1, t1, t2
|
||||
vle8.v v16, (t1)
|
||||
add t1, t1, t2
|
||||
vle8.v v24, (t1)
|
||||
|
||||
mv t1, t0
|
||||
|
||||
LOAD t0, VEC_FRAME_VSTART(t1)
|
||||
csrw vstart, t0
|
||||
LOAD t0, VEC_FRAME_VCSR(t1)
|
||||
csrw vcsr, t0
|
||||
|
||||
LOAD t0, VEC_FRAME_VTYPE(t1)
|
||||
LOAD t3, VEC_FRAME_VL(t1)
|
||||
VEC_CONFIG_SET_VL_VTYPE(t3, t0)
|
||||
.endm
|
||||
|
||||
#endif /* ENABLE_VECTOR */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __EXT_CONTEXT_H__ */
|
||||
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/01 Bernard The first version
|
||||
* 2018/12/27 Jesven Change irq enable/disable to cpu0
|
||||
*/
|
||||
#include <plic.h>
|
||||
#include <mmu.h>
|
||||
#include "tick.h"
|
||||
#include "encoding.h"
|
||||
#include "riscv.h"
|
||||
#include "interrupt.h"
|
||||
|
||||
struct rt_irq_desc irq_desc[MAX_HANDLERS];
|
||||
|
||||
static rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
|
||||
{
|
||||
rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector);
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
int rt_hw_plic_irq_enable(int irq_number)
|
||||
{
|
||||
plic_irq_enable(irq_number);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rt_hw_plic_irq_disable(int irq_number)
|
||||
{
|
||||
plic_irq_disable(irq_number);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will un-mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
plic_set_priority(vector, 1);
|
||||
|
||||
rt_hw_plic_irq_enable(vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will install a interrupt service routine to a interrupt.
|
||||
* @param vector the interrupt number
|
||||
* @param new_handler the interrupt service routine to be installed
|
||||
* @param old_handler the old interrupt service routine
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
if(vector < MAX_HANDLERS)
|
||||
{
|
||||
old_handler = irq_desc[vector].handler;
|
||||
if (handler != RT_NULL)
|
||||
{
|
||||
irq_desc[vector].handler = (rt_isr_handler_t)handler;
|
||||
irq_desc[vector].param = param;
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
|
||||
irq_desc[vector].counter = 0;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_init()
|
||||
{
|
||||
/* Enable machine external interrupts. */
|
||||
// set_csr(sie, SIP_SEIP);
|
||||
int idx = 0;
|
||||
/* init exceptions table */
|
||||
for (idx = 0; idx < MAX_HANDLERS; idx++)
|
||||
{
|
||||
irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
|
||||
irq_desc[idx].param = RT_NULL;
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
|
||||
irq_desc[idx].counter = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
plic_set_threshold(0);
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-05-20 bigmagic The first version
|
||||
*/
|
||||
|
||||
#ifndef INTERRUPT_H__
|
||||
#define INTERRUPT_H__
|
||||
|
||||
#define MAX_HANDLERS 128
|
||||
|
||||
#include <rthw.h>
|
||||
#include "stack.h"
|
||||
|
||||
enum
|
||||
{
|
||||
EP_INSTRUCTION_ADDRESS_MISALIGNED = 0,
|
||||
EP_INSTRUCTION_ACCESS_FAULT,
|
||||
EP_ILLEGAL_INSTRUCTION,
|
||||
EP_BREAKPOINT,
|
||||
EP_LOAD_ADDRESS_MISALIGNED,
|
||||
EP_LOAD_ACCESS_FAULT,
|
||||
EP_STORE_ADDRESS_MISALIGNED,
|
||||
EP_STORE_ACCESS_FAULT,
|
||||
EP_ENVIRONMENT_CALL_U_MODE,
|
||||
EP_ENVIRONMENT_CALL_S_MODE,
|
||||
EP_RESERVED10,
|
||||
EP_ENVIRONMENT_CALL_M_MODE,
|
||||
EP_INSTRUCTION_PAGE_FAULT, /* page attr */
|
||||
EP_LOAD_PAGE_FAULT, /* read data */
|
||||
EP_RESERVED14,
|
||||
EP_STORE_PAGE_FAULT, /* write data */
|
||||
};
|
||||
|
||||
int rt_hw_plic_irq_enable(int irq_number);
|
||||
int rt_hw_plic_irq_disable(int irq_number);
|
||||
void rt_hw_interrupt_init(void);
|
||||
void rt_hw_interrupt_mask(int vector);
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name);
|
||||
void handle_trap(rt_size_t xcause, rt_size_t xtval, rt_size_t xepc, struct rt_hw_stack_frame *sp);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/02 Bernard The first version
|
||||
* 2018/12/27 Jesven Add SMP schedule
|
||||
* 2021/02/02 lizhirui Add userspace support
|
||||
* 2021/12/24 JasonHu Add user setting save/restore
|
||||
* 2022/10/22 WangXiaoyao Support kernel mode RVV;
|
||||
* Rewrite trap handling routine
|
||||
*/
|
||||
|
||||
#include "cpuport.h"
|
||||
#include "encoding.h"
|
||||
#include "stackframe.h"
|
||||
|
||||
.align 2
|
||||
.global trap_entry
|
||||
.global debug_check_sp
|
||||
trap_entry:
|
||||
// distingush exception from kernel or user
|
||||
csrrw sp, sscratch, sp
|
||||
bnez sp, _save_context
|
||||
|
||||
// BE REALLY careful with sscratch,
|
||||
// if it's wrong, we could looping here forever
|
||||
// or accessing random memory and seeing things totally
|
||||
// messy after a long time and don't even know why
|
||||
_from_kernel:
|
||||
csrr sp, sscratch
|
||||
j _save_context
|
||||
|
||||
_save_context:
|
||||
SAVE_ALL
|
||||
// clear sscratch to say 'now in kernel mode'
|
||||
csrw sscratch, zero
|
||||
|
||||
RESTORE_SYS_GP
|
||||
|
||||
// now we are ready to enter interrupt / excepiton handler
|
||||
_distinguish_syscall:
|
||||
csrr t0, scause
|
||||
#ifdef RT_USING_SMART
|
||||
// TODO swap 8 with config macro name
|
||||
li t1, 8
|
||||
beq t0, t1, syscall_entry
|
||||
// syscall never return here
|
||||
#endif
|
||||
|
||||
_handle_interrupt_and_exception:
|
||||
mv a0, t0
|
||||
csrrc a1, stval, zero
|
||||
csrr a2, sepc
|
||||
// sp as exception frame pointer
|
||||
mv a3, sp
|
||||
call handle_trap
|
||||
|
||||
_interrupt_exit:
|
||||
la s0, rt_thread_switch_interrupt_flag
|
||||
lw s2, 0(s0)
|
||||
beqz s2, _resume_execution
|
||||
sw zero, 0(s0)
|
||||
|
||||
_context_switch:
|
||||
la t0, rt_interrupt_from_thread
|
||||
LOAD a0, 0(t0)
|
||||
la t0, rt_interrupt_to_thread
|
||||
LOAD a1, 0(t0)
|
||||
jal rt_hw_context_switch
|
||||
|
||||
_resume_execution:
|
||||
#ifdef RT_USING_SMART
|
||||
LOAD t0, FRAME_OFF_SSTATUS(sp)
|
||||
andi t0, t0, SSTATUS_SPP
|
||||
beqz t0, arch_ret_to_user
|
||||
#endif
|
||||
|
||||
_resume_kernel:
|
||||
RESTORE_ALL
|
||||
csrw sscratch, zero
|
||||
sret
|
||||
|
||||
.global rt_hw_interrupt_enable
|
||||
rt_hw_interrupt_enable:
|
||||
csrs sstatus, a0 /* restore to old csr */
|
||||
jr ra
|
||||
|
||||
.global rt_hw_interrupt_disable
|
||||
rt_hw_interrupt_disable:
|
||||
csrrci a0, sstatus, 2 /* clear SIE */
|
||||
jr ra
|
||||
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2020, Xim
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
*/
|
||||
#ifndef ARCH_IO_H
|
||||
#define ARCH_IO_H
|
||||
#include <rtthread.h>
|
||||
#define RISCV_FENCE(p, s) \
|
||||
__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
|
||||
|
||||
/* These barriers need to enforce ordering on both devices or memory. */
|
||||
#define mb() RISCV_FENCE(iorw,iorw)
|
||||
#define rmb() RISCV_FENCE(ir,ir)
|
||||
#define wmb() RISCV_FENCE(ow,ow)
|
||||
|
||||
#define __arch_getl(a) (*(unsigned int *)(a))
|
||||
#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
|
||||
|
||||
#define dmb() mb()
|
||||
#define __iormb() rmb()
|
||||
#define __iowmb() wmb()
|
||||
|
||||
static inline void writel(uint32_t val, volatile void *addr)
|
||||
{
|
||||
__iowmb();
|
||||
__arch_putl(val, addr);
|
||||
}
|
||||
|
||||
static inline uint32_t readl(const volatile void *addr)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = __arch_getl(addr);
|
||||
__iormb();
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void write_reg(
|
||||
uint32_t val, volatile void *addr, unsigned offset)
|
||||
{
|
||||
writel(val, addr + offset);
|
||||
}
|
||||
|
||||
static inline uint32_t read_reg(
|
||||
const volatile void *addr, unsigned offset)
|
||||
{
|
||||
return readl(addr + offset);
|
||||
}
|
||||
|
||||
#endif // ARCH_IO_H
|
||||
@@ -0,0 +1,512 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-01-30 lizhirui first version
|
||||
* 2022-12-13 WangXiaoyao Port to new mm
|
||||
* 2023-10-12 Shell Add permission control API
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#define DBG_TAG "hw.mmu"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
#include <board.h>
|
||||
#include <cache.h>
|
||||
#include <mm_aspace.h>
|
||||
#include <mm_page.h>
|
||||
#include <mmu.h>
|
||||
#include <riscv_mmu.h>
|
||||
#include <tlb.h>
|
||||
|
||||
#ifdef RT_USING_SMART
|
||||
#include <board.h>
|
||||
#include <ioremap.h>
|
||||
#include <lwp_user_mm.h>
|
||||
#endif
|
||||
|
||||
#ifndef RT_USING_SMART
|
||||
#define USER_VADDR_START 0
|
||||
#endif
|
||||
|
||||
static size_t _unmap_area(struct rt_aspace *aspace, void *v_addr, size_t size);
|
||||
|
||||
static void *current_mmu_table = RT_NULL;
|
||||
|
||||
volatile __attribute__((aligned(4 * 1024)))
|
||||
rt_ubase_t MMUTable[__SIZE(VPN2_BIT)];
|
||||
|
||||
void rt_hw_aspace_switch(rt_aspace_t aspace)
|
||||
{
|
||||
uintptr_t page_table = (uintptr_t)rt_kmem_v2p(aspace->page_table);
|
||||
current_mmu_table = aspace->page_table;
|
||||
|
||||
write_csr(satp, (((size_t)SATP_MODE) << SATP_MODE_OFFSET) |
|
||||
((rt_ubase_t)page_table >> PAGE_OFFSET_BIT));
|
||||
rt_hw_tlb_invalidate_all_local();
|
||||
}
|
||||
|
||||
void *rt_hw_mmu_tbl_get()
|
||||
{
|
||||
return current_mmu_table;
|
||||
}
|
||||
|
||||
static int _map_one_page(struct rt_aspace *aspace, void *va, void *pa,
|
||||
size_t attr)
|
||||
{
|
||||
rt_size_t l1_off, l2_off, l3_off;
|
||||
rt_size_t *mmu_l1, *mmu_l2, *mmu_l3;
|
||||
|
||||
l1_off = GET_L1((size_t)va);
|
||||
l2_off = GET_L2((size_t)va);
|
||||
l3_off = GET_L3((size_t)va);
|
||||
|
||||
mmu_l1 = ((rt_size_t *)aspace->page_table) + l1_off;
|
||||
|
||||
if (PTE_USED(*mmu_l1))
|
||||
{
|
||||
mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1), PV_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
mmu_l2 = (rt_size_t *)rt_pages_alloc(0);
|
||||
|
||||
if (mmu_l2)
|
||||
{
|
||||
rt_memset(mmu_l2, 0, PAGE_SIZE);
|
||||
rt_hw_cpu_dcache_clean(mmu_l2, PAGE_SIZE);
|
||||
*mmu_l1 = COMBINEPTE((rt_size_t)VPN_TO_PPN(mmu_l2, PV_OFFSET),
|
||||
PAGE_DEFAULT_ATTR_NEXT);
|
||||
rt_hw_cpu_dcache_clean(mmu_l1, sizeof(*mmu_l1));
|
||||
}
|
||||
else
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if (PTE_USED(*(mmu_l2 + l2_off)))
|
||||
{
|
||||
RT_ASSERT(!PAGE_IS_LEAF(*(mmu_l2 + l2_off)));
|
||||
mmu_l3 =
|
||||
(rt_size_t *)PPN_TO_VPN(GET_PADDR(*(mmu_l2 + l2_off)), PV_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
mmu_l3 = (rt_size_t *)rt_pages_alloc(0);
|
||||
|
||||
if (mmu_l3)
|
||||
{
|
||||
rt_memset(mmu_l3, 0, PAGE_SIZE);
|
||||
rt_hw_cpu_dcache_clean(mmu_l3, PAGE_SIZE);
|
||||
*(mmu_l2 + l2_off) =
|
||||
COMBINEPTE((rt_size_t)VPN_TO_PPN(mmu_l3, PV_OFFSET),
|
||||
PAGE_DEFAULT_ATTR_NEXT);
|
||||
rt_hw_cpu_dcache_clean(mmu_l2, sizeof(*mmu_l2));
|
||||
// declares a reference to parent page table
|
||||
rt_page_ref_inc((void *)mmu_l2, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
RT_ASSERT(!PTE_USED(*(mmu_l3 + l3_off)));
|
||||
// declares a reference to parent page table
|
||||
rt_page_ref_inc((void *)mmu_l3, 0);
|
||||
*(mmu_l3 + l3_off) = COMBINEPTE((rt_size_t)pa, attr);
|
||||
rt_hw_cpu_dcache_clean(mmu_l3 + l3_off, sizeof(*(mmu_l3 + l3_off)));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/** rt_hw_mmu_map will never override existed page table entry */
|
||||
void *rt_hw_mmu_map(struct rt_aspace *aspace, void *v_addr, void *p_addr,
|
||||
size_t size, size_t attr)
|
||||
{
|
||||
int ret = -1;
|
||||
void *unmap_va = v_addr;
|
||||
size_t npages = size >> ARCH_PAGE_SHIFT;
|
||||
|
||||
// TODO trying with HUGEPAGE here
|
||||
while (npages--)
|
||||
{
|
||||
MM_PGTBL_LOCK(aspace);
|
||||
ret = _map_one_page(aspace, v_addr, p_addr, attr);
|
||||
MM_PGTBL_UNLOCK(aspace);
|
||||
if (ret != 0)
|
||||
{
|
||||
/* error, undo map */
|
||||
while (unmap_va != v_addr)
|
||||
{
|
||||
MM_PGTBL_LOCK(aspace);
|
||||
_unmap_area(aspace, unmap_va, ARCH_PAGE_SIZE);
|
||||
MM_PGTBL_UNLOCK(aspace);
|
||||
unmap_va += ARCH_PAGE_SIZE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
v_addr += ARCH_PAGE_SIZE;
|
||||
p_addr += ARCH_PAGE_SIZE;
|
||||
}
|
||||
|
||||
if (ret == 0)
|
||||
{
|
||||
return unmap_va;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void _unmap_pte(rt_size_t *pentry, rt_size_t *lvl_entry[], int level)
|
||||
{
|
||||
int loop_flag = 1;
|
||||
while (loop_flag)
|
||||
{
|
||||
loop_flag = 0;
|
||||
*pentry = 0;
|
||||
rt_hw_cpu_dcache_clean(pentry, sizeof(*pentry));
|
||||
|
||||
// we don't handle level 0, which is maintained by caller
|
||||
if (level > 0)
|
||||
{
|
||||
void *page = (void *)((rt_ubase_t)pentry & ~ARCH_PAGE_MASK);
|
||||
|
||||
// decrease reference from child page to parent
|
||||
rt_pages_free(page, 0);
|
||||
|
||||
int free = rt_page_ref_get(page, 0);
|
||||
if (free == 1)
|
||||
{
|
||||
rt_pages_free(page, 0);
|
||||
pentry = lvl_entry[--level];
|
||||
loop_flag = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static size_t _unmap_area(struct rt_aspace *aspace, void *v_addr, size_t size)
|
||||
{
|
||||
rt_size_t loop_va = __UMASKVALUE((rt_size_t)v_addr, PAGE_OFFSET_MASK);
|
||||
size_t unmapped = 0;
|
||||
|
||||
int i = 0;
|
||||
rt_size_t lvl_off[3];
|
||||
rt_size_t *lvl_entry[3];
|
||||
lvl_off[0] = (rt_size_t)GET_L1(loop_va);
|
||||
lvl_off[1] = (rt_size_t)GET_L2(loop_va);
|
||||
lvl_off[2] = (rt_size_t)GET_L3(loop_va);
|
||||
unmapped = 1 << (ARCH_PAGE_SHIFT + ARCH_INDEX_WIDTH * 2ul);
|
||||
|
||||
rt_size_t *pentry;
|
||||
lvl_entry[i] = ((rt_size_t *)aspace->page_table + lvl_off[i]);
|
||||
pentry = lvl_entry[i];
|
||||
|
||||
// find leaf page table entry
|
||||
while (PTE_USED(*pentry) && !PAGE_IS_LEAF(*pentry))
|
||||
{
|
||||
i += 1;
|
||||
lvl_entry[i] = ((rt_size_t *)PPN_TO_VPN(GET_PADDR(*pentry), PV_OFFSET) +
|
||||
lvl_off[i]);
|
||||
pentry = lvl_entry[i];
|
||||
unmapped >>= ARCH_INDEX_WIDTH;
|
||||
}
|
||||
|
||||
// clear PTE & setup its
|
||||
if (PTE_USED(*pentry))
|
||||
{
|
||||
_unmap_pte(pentry, lvl_entry, i);
|
||||
}
|
||||
|
||||
return unmapped;
|
||||
}
|
||||
|
||||
/** unmap is different from map that it can handle multiple pages */
|
||||
void rt_hw_mmu_unmap(struct rt_aspace *aspace, void *v_addr, size_t size)
|
||||
{
|
||||
// caller guarantee that v_addr & size are page aligned
|
||||
if (!aspace->page_table)
|
||||
{
|
||||
return;
|
||||
}
|
||||
size_t unmapped = 0;
|
||||
|
||||
while (size > 0)
|
||||
{
|
||||
MM_PGTBL_LOCK(aspace);
|
||||
unmapped = _unmap_area(aspace, v_addr, size);
|
||||
MM_PGTBL_UNLOCK(aspace);
|
||||
|
||||
// when unmapped == 0, region not exist in pgtbl
|
||||
if (!unmapped || unmapped > size)
|
||||
break;
|
||||
|
||||
size -= unmapped;
|
||||
v_addr += unmapped;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef RT_USING_SMART
|
||||
static inline void _init_region(void *vaddr, size_t size)
|
||||
{
|
||||
rt_ioremap_start = vaddr;
|
||||
rt_ioremap_size = size;
|
||||
rt_mpr_start = rt_ioremap_start - rt_mpr_size;
|
||||
LOG_D("rt_ioremap_start: %p, rt_mpr_start: %p", rt_ioremap_start, rt_mpr_start);
|
||||
}
|
||||
#else
|
||||
static inline void _init_region(void *vaddr, size_t size)
|
||||
{
|
||||
rt_mpr_start = vaddr - rt_mpr_size;
|
||||
}
|
||||
#endif
|
||||
|
||||
int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, rt_size_t size,
|
||||
rt_size_t *vtable, rt_size_t pv_off)
|
||||
{
|
||||
size_t l1_off, va_s, va_e;
|
||||
rt_base_t level;
|
||||
|
||||
if ((!aspace) || (!vtable))
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
va_s = (rt_size_t)v_address;
|
||||
va_e = ((rt_size_t)v_address) + size - 1;
|
||||
|
||||
if (va_e < va_s)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
// convert address to PPN2 index
|
||||
va_s = GET_L1(va_s);
|
||||
va_e = GET_L1(va_e);
|
||||
|
||||
if (va_s == 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
// vtable initialization check
|
||||
for (l1_off = va_s; l1_off <= va_e; l1_off++)
|
||||
{
|
||||
size_t v = vtable[l1_off];
|
||||
|
||||
if (v)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
rt_aspace_init(&rt_kernel_space, (void *)0x1000, USER_VADDR_START - 0x1000,
|
||||
vtable);
|
||||
|
||||
_init_region(v_address, size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
const static int max_level =
|
||||
(ARCH_VADDR_WIDTH - ARCH_PAGE_SHIFT) / ARCH_INDEX_WIDTH;
|
||||
|
||||
static inline uintptr_t _get_level_size(int level)
|
||||
{
|
||||
return 1ul << (ARCH_PAGE_SHIFT + (max_level - level) * ARCH_INDEX_WIDTH);
|
||||
}
|
||||
|
||||
static rt_size_t *_query(struct rt_aspace *aspace, void *vaddr, int *level)
|
||||
{
|
||||
rt_size_t l1_off, l2_off, l3_off;
|
||||
rt_size_t *mmu_l1, *mmu_l2, *mmu_l3;
|
||||
rt_size_t pa;
|
||||
|
||||
l1_off = GET_L1((rt_size_t)vaddr);
|
||||
l2_off = GET_L2((rt_size_t)vaddr);
|
||||
l3_off = GET_L3((rt_size_t)vaddr);
|
||||
|
||||
if (!aspace)
|
||||
{
|
||||
LOG_W("%s: no aspace", __func__);
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
mmu_l1 = ((rt_size_t *)aspace->page_table) + l1_off;
|
||||
|
||||
if (PTE_USED(*mmu_l1))
|
||||
{
|
||||
if (*mmu_l1 & PTE_XWR_MASK)
|
||||
{
|
||||
*level = 1;
|
||||
return mmu_l1;
|
||||
}
|
||||
|
||||
mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1), PV_OFFSET);
|
||||
|
||||
if (PTE_USED(*(mmu_l2 + l2_off)))
|
||||
{
|
||||
if (*(mmu_l2 + l2_off) & PTE_XWR_MASK)
|
||||
{
|
||||
*level = 2;
|
||||
return mmu_l2 + l2_off;
|
||||
}
|
||||
|
||||
mmu_l3 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*(mmu_l2 + l2_off)),
|
||||
PV_OFFSET);
|
||||
|
||||
if (PTE_USED(*(mmu_l3 + l3_off)))
|
||||
{
|
||||
*level = 3;
|
||||
return mmu_l3 + l3_off;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
void *rt_hw_mmu_v2p(struct rt_aspace *aspace, void *vaddr)
|
||||
{
|
||||
int level;
|
||||
uintptr_t *pte = _query(aspace, vaddr, &level);
|
||||
uintptr_t paddr;
|
||||
|
||||
if (pte)
|
||||
{
|
||||
paddr = GET_PADDR(*pte);
|
||||
paddr |= ((intptr_t)vaddr & (_get_level_size(level) - 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
paddr = (uintptr_t)ARCH_MAP_FAILED;
|
||||
}
|
||||
return (void *)paddr;
|
||||
}
|
||||
|
||||
static int _noncache(uintptr_t *pte)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _cache(uintptr_t *pte)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int (*control_handler[MMU_CNTL_DUMMY_END])(uintptr_t *pte) = {
|
||||
[MMU_CNTL_CACHE] = _cache,
|
||||
[MMU_CNTL_NONCACHE] = _noncache,
|
||||
};
|
||||
|
||||
int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size,
|
||||
enum rt_mmu_cntl cmd)
|
||||
{
|
||||
int level;
|
||||
int err = -RT_EINVAL;
|
||||
void *vend = vaddr + size;
|
||||
|
||||
int (*handler)(uintptr_t * pte);
|
||||
if (cmd >= 0 && cmd < MMU_CNTL_DUMMY_END)
|
||||
{
|
||||
handler = control_handler[cmd];
|
||||
|
||||
while (vaddr < vend)
|
||||
{
|
||||
uintptr_t *pte = _query(aspace, vaddr, &level);
|
||||
void *range_end = vaddr + _get_level_size(level);
|
||||
RT_ASSERT(range_end <= vend);
|
||||
|
||||
if (pte)
|
||||
{
|
||||
err = handler(pte);
|
||||
RT_ASSERT(err == RT_EOK);
|
||||
}
|
||||
vaddr = range_end;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err = -RT_ENOSYS;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief setup Page Table for kernel space. It's a fixed map
|
||||
* and all mappings cannot be changed after initialization.
|
||||
*
|
||||
* Memory region in struct mem_desc must be page aligned,
|
||||
* otherwise is a failure and no report will be
|
||||
* returned.
|
||||
*
|
||||
* @param aspace
|
||||
* @param mdesc
|
||||
* @param desc_nr
|
||||
*/
|
||||
void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr)
|
||||
{
|
||||
void *err;
|
||||
for (size_t i = 0; i < desc_nr; i++)
|
||||
{
|
||||
size_t attr;
|
||||
switch (mdesc->attr)
|
||||
{
|
||||
case NORMAL_MEM:
|
||||
attr = MMU_MAP_K_RWCB;
|
||||
break;
|
||||
case NORMAL_NOCACHE_MEM:
|
||||
attr = MMU_MAP_K_RWCB;
|
||||
break;
|
||||
case DEVICE_MEM:
|
||||
attr = MMU_MAP_K_DEVICE;
|
||||
break;
|
||||
default:
|
||||
attr = MMU_MAP_K_DEVICE;
|
||||
}
|
||||
|
||||
struct rt_mm_va_hint hint = {.flags = MMF_MAP_FIXED,
|
||||
.limit_start = aspace->start,
|
||||
.limit_range_size = aspace->size,
|
||||
.map_size = mdesc->vaddr_end -
|
||||
mdesc->vaddr_start + 1,
|
||||
.prefer = (void *)mdesc->vaddr_start};
|
||||
|
||||
if (mdesc->paddr_start == (rt_size_t)ARCH_MAP_FAILED)
|
||||
mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET;
|
||||
|
||||
rt_aspace_map_phy_static(aspace, &mdesc->varea, &hint, attr,
|
||||
mdesc->paddr_start >> MM_PAGE_SHIFT, &err);
|
||||
mdesc++;
|
||||
}
|
||||
|
||||
rt_hw_aspace_switch(&rt_kernel_space);
|
||||
rt_page_cleanup();
|
||||
}
|
||||
|
||||
void *rt_hw_mmu_pgtbl_create(void)
|
||||
{
|
||||
size_t *mmu_table;
|
||||
mmu_table = (rt_ubase_t *)rt_pages_alloc_ext(0, PAGE_ANY_AVAILABLE);
|
||||
if (!mmu_table)
|
||||
{
|
||||
return RT_NULL;
|
||||
}
|
||||
rt_memcpy(mmu_table, rt_kernel_space.page_table, ARCH_PAGE_SIZE);
|
||||
rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_table, ARCH_PAGE_SIZE);
|
||||
|
||||
return mmu_table;
|
||||
}
|
||||
|
||||
void rt_hw_mmu_pgtbl_delete(void *pgtbl)
|
||||
{
|
||||
rt_pages_free(pgtbl, 0);
|
||||
}
|
||||
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-01-30 lizhirui first version
|
||||
* 2023-10-12 Shell Add permission control API
|
||||
*/
|
||||
|
||||
#ifndef __MMU_H__
|
||||
#define __MMU_H__
|
||||
|
||||
#include "riscv.h"
|
||||
#include "riscv_mmu.h"
|
||||
#include <mm_aspace.h>
|
||||
#include <stddef.h>
|
||||
|
||||
/* RAM, Flash, or ROM */
|
||||
#define NORMAL_MEM 0
|
||||
/* normal nocache memory mapping type */
|
||||
#define NORMAL_NOCACHE_MEM 1
|
||||
/* MMIO region */
|
||||
#define DEVICE_MEM 2
|
||||
|
||||
typedef size_t rt_pte_t;
|
||||
|
||||
struct mem_desc
|
||||
{
|
||||
rt_size_t vaddr_start;
|
||||
rt_size_t vaddr_end;
|
||||
rt_size_t paddr_start;
|
||||
rt_size_t attr;
|
||||
struct rt_varea varea;
|
||||
};
|
||||
|
||||
#define GET_PF_ID(addr) ((addr) >> PAGE_OFFSET_BIT)
|
||||
#define GET_PF_OFFSET(addr) __MASKVALUE(addr, PAGE_OFFSET_MASK)
|
||||
#define GET_L1(addr) __PARTBIT(addr, VPN2_SHIFT, VPN2_BIT)
|
||||
#define GET_L2(addr) __PARTBIT(addr, VPN1_SHIFT, VPN1_BIT)
|
||||
#define GET_L3(addr) __PARTBIT(addr, VPN0_SHIFT, VPN0_BIT)
|
||||
#define GET_PPN(pte) \
|
||||
(__PARTBIT(pte, PTE_PPN_SHIFT, PHYSICAL_ADDRESS_WIDTH_BITS - PTE_PPN_SHIFT))
|
||||
#define GET_PADDR(pte) (GET_PPN(pte) << PAGE_OFFSET_BIT)
|
||||
#define VPN_TO_PPN(vaddr, pv_off) (((rt_size_t)(vaddr)) + (pv_off))
|
||||
#define PPN_TO_VPN(paddr, pv_off) (((rt_size_t)(paddr)) - (pv_off))
|
||||
#define COMBINEVADDR(l1_off, l2_off, l3_off) \
|
||||
(((l1_off) << VPN2_SHIFT) | ((l2_off) << VPN1_SHIFT) | \
|
||||
((l3_off) << VPN0_SHIFT))
|
||||
#define COMBINEPTE(paddr, attr) \
|
||||
((((paddr) >> PAGE_OFFSET_BIT) << PTE_PPN_SHIFT) | (attr))
|
||||
|
||||
#define MMU_MAP_ERROR_VANOTALIGN -1
|
||||
#define MMU_MAP_ERROR_PANOTALIGN -2
|
||||
#define MMU_MAP_ERROR_NOPAGE -3
|
||||
#define MMU_MAP_ERROR_CONFLICT -4
|
||||
|
||||
void *rt_hw_mmu_tbl_get(void);
|
||||
int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, rt_size_t size,
|
||||
rt_size_t *vtable, rt_size_t pv_off);
|
||||
void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr);
|
||||
void rt_hw_mmu_kernel_map_init(rt_aspace_t aspace, rt_size_t vaddr_start,
|
||||
rt_size_t size);
|
||||
void *rt_hw_mmu_map(rt_aspace_t aspace, void *v_addr, void *p_addr, size_t size,
|
||||
size_t attr);
|
||||
void rt_hw_mmu_unmap(rt_aspace_t aspace, void *v_addr, size_t size);
|
||||
void rt_hw_aspace_switch(rt_aspace_t aspace);
|
||||
void *rt_hw_mmu_v2p(rt_aspace_t aspace, void *vaddr);
|
||||
|
||||
int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size,
|
||||
enum rt_mmu_cntl cmd);
|
||||
|
||||
void *rt_hw_mmu_pgtbl_create(void);
|
||||
void rt_hw_mmu_pgtbl_delete(void *pgtbl);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-05-20 bigmagic first version
|
||||
* 2022-09-16 WangXiaoyao Porting to rv64
|
||||
*/
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <stdint.h>
|
||||
#include "plic.h"
|
||||
#include <riscv_io.h>
|
||||
#include "encoding.h"
|
||||
|
||||
#include <riscv.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#ifdef RT_USING_SMART
|
||||
#include <ioremap.h>
|
||||
#else
|
||||
#define rt_ioremap(addr, ...) (addr)
|
||||
#endif
|
||||
|
||||
size_t plic_base = 0x0c000000L;
|
||||
|
||||
/*
|
||||
* Each PLIC interrupt source can be assigned a priority by writing
|
||||
* to its 32-bit memory-mapped priority register.
|
||||
* The QEMU-virt (the same as FU540-C000) supports 7 levels of priority.
|
||||
* A priority value of 0 is reserved to mean "never interrupt" and
|
||||
* effectively disables the interrupt.
|
||||
* Priority 1 is the lowest active priority, and priority 7 is the highest.
|
||||
* Ties between global interrupts of the same priority are broken by
|
||||
* the Interrupt ID; interrupts with the lowest ID have the highest
|
||||
* effective priority.
|
||||
*/
|
||||
void plic_set_priority(int irq, int priority)
|
||||
{
|
||||
*(uint32_t *)PLIC_PRIORITY(irq) = priority;
|
||||
}
|
||||
|
||||
/*
|
||||
* Each global interrupt can be enabled by setting the corresponding
|
||||
* bit in the enables registers.
|
||||
*/
|
||||
void plic_irq_enable(int irq)
|
||||
{
|
||||
int hart = __raw_hartid();
|
||||
*(uint32_t *)PLIC_ENABLE(hart) = ((*(uint32_t *)PLIC_ENABLE(hart)) | (1 << irq));
|
||||
#ifdef RISCV_S_MODE
|
||||
set_csr(sie, read_csr(sie) | MIP_SEIP);
|
||||
#else
|
||||
set_csr(mie, read_csr(mie) | MIP_MEIP);
|
||||
#endif
|
||||
}
|
||||
|
||||
void plic_irq_disable(int irq)
|
||||
{
|
||||
int hart = __raw_hartid();
|
||||
*(uint32_t *)PLIC_ENABLE(hart) = (((*(uint32_t *)PLIC_ENABLE(hart)) & (~(1 << irq))));
|
||||
}
|
||||
|
||||
/*
|
||||
* PLIC will mask all interrupts of a priority less than or equal to threshold.
|
||||
* Maximum threshold is 7.
|
||||
* For example, a threshold value of zero permits all interrupts with
|
||||
* non-zero priority, whereas a value of 7 masks all interrupts.
|
||||
* Notice, the threshold is global for PLIC, not for each interrupt source.
|
||||
*/
|
||||
void plic_set_threshold(int threshold)
|
||||
{
|
||||
int hart = __raw_hartid();
|
||||
*(uint32_t *)PLIC_THRESHOLD(hart) = threshold;
|
||||
}
|
||||
|
||||
/*
|
||||
* DESCRIPTION:
|
||||
* Query the PLIC what interrupt we should serve.
|
||||
* Perform an interrupt claim by reading the claim register, which
|
||||
* returns the ID of the highest-priority pending interrupt or zero if there
|
||||
* is no pending interrupt.
|
||||
* A successful claim also atomically clears the corresponding pending bit
|
||||
* on the interrupt source.
|
||||
* RETURN VALUE:
|
||||
* the ID of the highest-priority pending interrupt or zero if there
|
||||
* is no pending interrupt.
|
||||
*/
|
||||
int plic_claim(void)
|
||||
{
|
||||
int hart = __raw_hartid();
|
||||
int irq = *(uint32_t *)PLIC_CLAIM(hart);
|
||||
return irq;
|
||||
}
|
||||
|
||||
/*
|
||||
* DESCRIPTION:
|
||||
* Writing the interrupt ID it received from the claim (irq) to the
|
||||
* complete register would signal the PLIC we've served this IRQ.
|
||||
* The PLIC does not check whether the completion ID is the same as the
|
||||
* last claim ID for that target. If the completion ID does not match an
|
||||
* interrupt source that is currently enabled for the target, the completion
|
||||
* is silently ignored.
|
||||
* RETURN VALUE: none
|
||||
*/
|
||||
void plic_complete(int irq)
|
||||
{
|
||||
int hart = __raw_hartid();
|
||||
*(uint32_t *)PLIC_COMPLETE(hart) = irq;
|
||||
}
|
||||
|
||||
void plic_set_ie(rt_uint32_t word_index, rt_uint32_t val)
|
||||
{
|
||||
volatile void *plic_ie = (void *)(rt_size_t)(plic_base + PLIC_ENABLE_BASE + 0x80 + word_index * 4);
|
||||
writel(val, plic_ie);
|
||||
}
|
||||
|
||||
static void _set_sie(int hartid)
|
||||
{
|
||||
for (size_t i = hartid * WORD_CNT_BYTE; i < 32; i++)
|
||||
plic_set_ie(i, 0xffffffff);
|
||||
}
|
||||
|
||||
void plic_init()
|
||||
{
|
||||
// PLIC takes up 64 MB space
|
||||
plic_base = (size_t)rt_ioremap((void *)plic_base, 64 * 1024 * 1024);
|
||||
|
||||
plic_set_threshold(0);
|
||||
|
||||
for (int i = 0; i < CONFIG_IRQ_NR; i++)
|
||||
{
|
||||
plic_set_priority(i, 1);
|
||||
}
|
||||
|
||||
// in a single core system, only current context was set
|
||||
_set_sie(__raw_hartid());
|
||||
}
|
||||
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-05-20 bigmagic first version
|
||||
* 2021-10-20 bernard fix s-mode issue
|
||||
*/
|
||||
|
||||
#ifndef __PLIC_H__
|
||||
#define __PLIC_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
#include <rthw.h>
|
||||
|
||||
#define PLIC_PRIORITY_BASE 0x0
|
||||
#define PLIC_PENDING_BASE 0x1000
|
||||
#define PLIC_ENABLE_BASE 0x2000
|
||||
#define PLIC_CONTEXT_BASE 0x200000
|
||||
|
||||
extern size_t plic_base;
|
||||
|
||||
#define VIRT_PLIC_BASE (plic_base)
|
||||
|
||||
#define PLIC_PRIORITY_OFFSET (0x0)
|
||||
#define PLIC_PENDING_OFFSET (0x1000)
|
||||
|
||||
#define PLIC_ENABLE_STRIDE 0x80
|
||||
#define PLIC_CONTEXT_STRIDE 0x1000
|
||||
|
||||
#ifndef RISCV_S_MODE
|
||||
#define PLIC_MENABLE_OFFSET (0x2000)
|
||||
#define PLIC_MTHRESHOLD_OFFSET (0x200000)
|
||||
#define PLIC_MCLAIM_OFFSET (0x200004)
|
||||
#define PLIC_MCOMPLETE_OFFSET (0x200004)
|
||||
|
||||
#define PLIC_ENABLE(hart) (VIRT_PLIC_BASE + PLIC_MENABLE_OFFSET + (hart * 2) * PLIC_ENABLE_STRIDE)
|
||||
#define PLIC_THRESHOLD(hart) (VIRT_PLIC_BASE + PLIC_MTHRESHOLD_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE)
|
||||
#define PLIC_CLAIM(hart) (VIRT_PLIC_BASE + PLIC_MCLAIM_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE)
|
||||
#define PLIC_COMPLETE(hart) (VIRT_PLIC_BASE + PLIC_MCOMPLETE_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE)
|
||||
|
||||
#else
|
||||
#define PLIC_SENABLE_OFFSET (0x2000 + PLIC_ENABLE_STRIDE)
|
||||
#define PLIC_STHRESHOLD_OFFSET (0x200000 + PLIC_CONTEXT_STRIDE)
|
||||
#define PLIC_SCLAIM_OFFSET (0x200004 + PLIC_CONTEXT_STRIDE)
|
||||
#define PLIC_SCOMPLETE_OFFSET (0x200004 + PLIC_CONTEXT_STRIDE)
|
||||
|
||||
#define PLIC_ENABLE(hart) (VIRT_PLIC_BASE + PLIC_SENABLE_OFFSET + (hart * 2) * PLIC_ENABLE_STRIDE)
|
||||
#define PLIC_THRESHOLD(hart) (VIRT_PLIC_BASE + PLIC_STHRESHOLD_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE)
|
||||
#define PLIC_CLAIM(hart) (VIRT_PLIC_BASE + PLIC_SCLAIM_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE)
|
||||
#define PLIC_COMPLETE(hart) (VIRT_PLIC_BASE + PLIC_SCOMPLETE_OFFSET + (hart * 2) * PLIC_CONTEXT_STRIDE)
|
||||
#endif
|
||||
|
||||
#define PLIC_PRIORITY(id) (VIRT_PLIC_BASE + PLIC_PRIORITY_OFFSET + (id) * 4)
|
||||
#define PLIC_PENDING(id) (VIRT_PLIC_BASE + PLIC_PENDING_OFFSET + ((id) / 32))
|
||||
|
||||
#define WORD_CNT_BYTE (1024 / 8)
|
||||
|
||||
/* IRQ config in system, max 1024 (from 0 to 1023) */
|
||||
#define CONFIG_IRQ_NR (128)
|
||||
#define CONFIG_IRQ_WORD (CONFIG_IRQ_NR / 32)
|
||||
|
||||
void plic_set_priority(int irq, int priority);
|
||||
void plic_irq_enable(int irq);
|
||||
void plic_irq_disable(int irq);
|
||||
void plic_set_threshold(int mthreshold);
|
||||
int plic_claim(void);
|
||||
void plic_complete(int irq);
|
||||
|
||||
void plic_set_thresh(rt_uint32_t val);
|
||||
void plic_set_ie(rt_uint32_t word_index,rt_uint32_t val);
|
||||
void plic_init();
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-01-30 lizhirui first version
|
||||
*/
|
||||
|
||||
#ifndef __RISCV_H__
|
||||
#define __RISCV_H__
|
||||
|
||||
#include <encoding.h>
|
||||
|
||||
#define __SIZE(bit) (1UL << (bit))
|
||||
#define __MASK(bit) (__SIZE(bit) - 1UL)
|
||||
#define __UMASK(bit) (~(__MASK(bit)))
|
||||
#define __MASKVALUE(value,maskvalue) ((value) & (maskvalue))
|
||||
#define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue)))
|
||||
#define __CHECKUPBOUND(value,bit_count) (!(((rt_size_t)value) & (~__MASK(bit_count))))
|
||||
#define __CHECKALIGN(value,start_bit) (!(((rt_size_t)value) & (__MASK(start_bit))))
|
||||
|
||||
#define __PARTBIT(value,start_bit,length) (((value) >> (start_bit)) & __MASK(length))
|
||||
|
||||
#define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit))
|
||||
#define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit))
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,131 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __RISCV_IO_H__
|
||||
#define __RISCV_IO_H__
|
||||
|
||||
static inline uint32_t __raw_hartid(void)
|
||||
{
|
||||
extern int boot_hartid;
|
||||
return boot_hartid;
|
||||
}
|
||||
|
||||
static inline void __raw_writeb(rt_uint8_t val, volatile void *addr)
|
||||
{
|
||||
asm volatile("sb %0, 0(%1)"
|
||||
:
|
||||
: "r"(val), "r"(addr));
|
||||
}
|
||||
|
||||
static inline void __raw_writew(rt_uint16_t val, volatile void *addr)
|
||||
{
|
||||
asm volatile("sh %0, 0(%1)"
|
||||
:
|
||||
: "r"(val), "r"(addr));
|
||||
}
|
||||
|
||||
static inline void __raw_writel(rt_uint32_t val, volatile void *addr)
|
||||
{
|
||||
asm volatile("sw %0, 0(%1)"
|
||||
:
|
||||
: "r"(val), "r"(addr));
|
||||
}
|
||||
|
||||
#if __riscv_xlen != 32
|
||||
static inline void __raw_writeq(rt_uint64_t val, volatile void *addr)
|
||||
{
|
||||
asm volatile("sd %0, 0(%1)"
|
||||
:
|
||||
: "r"(val), "r"(addr));
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline rt_uint8_t __raw_readb(const volatile void *addr)
|
||||
{
|
||||
rt_uint8_t val;
|
||||
|
||||
asm volatile("lb %0, 0(%1)"
|
||||
: "=r"(val)
|
||||
: "r"(addr));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline rt_uint16_t __raw_readw(const volatile void *addr)
|
||||
{
|
||||
rt_uint16_t val;
|
||||
|
||||
asm volatile("lh %0, 0(%1)"
|
||||
: "=r"(val)
|
||||
: "r"(addr));
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline rt_uint32_t __raw_readl(const volatile void *addr)
|
||||
{
|
||||
rt_uint32_t val;
|
||||
|
||||
asm volatile("lw %0, 0(%1)"
|
||||
: "=r"(val)
|
||||
: "r"(addr));
|
||||
return val;
|
||||
}
|
||||
|
||||
#if __riscv_xlen != 32
|
||||
static inline rt_uint64_t __raw_readq(const volatile void *addr)
|
||||
{
|
||||
rt_uint64_t val;
|
||||
|
||||
asm volatile("ld %0, 0(%1)"
|
||||
: "=r"(val)
|
||||
: "r"(addr));
|
||||
return val;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* FIXME: These are now the same as asm-generic */
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
#define __io_rbr() do {} while (0)
|
||||
#define __io_rar() do {} while (0)
|
||||
#define __io_rbw() do {} while (0)
|
||||
#define __io_raw() do {} while (0)
|
||||
|
||||
#define readb_relaxed(c) ({ rt_uint8_t __v; __io_rbr(); __v = __raw_readb(c); __io_rar(); __v; })
|
||||
#define readw_relaxed(c) ({ rt_uint16_t __v; __io_rbr(); __v = __raw_readw(c); __io_rar(); __v; })
|
||||
#define readl_relaxed(c) ({ rt_uint32_t __v; __io_rbr(); __v = __raw_readl(c); __io_rar(); __v; })
|
||||
|
||||
#define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); })
|
||||
#define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); })
|
||||
#define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); })
|
||||
|
||||
#if __riscv_xlen != 32
|
||||
#define readq_relaxed(c) ({ rt_uint64_t __v; __io_rbr(); __v = __raw_readq(c); __io_rar(); __v; })
|
||||
#define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); })
|
||||
#endif
|
||||
|
||||
#define __io_br() do {} while (0)
|
||||
#define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory");
|
||||
#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
|
||||
#define __io_aw() do {} while (0)
|
||||
|
||||
#define readb(c) ({ rt_uint8_t __v; __io_br(); __v = __raw_readb(c); __io_ar(); __v; })
|
||||
#define readw(c) ({ rt_uint16_t __v; __io_br(); __v = __raw_readw(c); __io_ar(); __v; })
|
||||
#define readl(c) ({ rt_uint32_t __v; __io_br(); __v = __raw_readl(c); __io_ar(); __v; })
|
||||
|
||||
#define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); })
|
||||
#define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); })
|
||||
#define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); })
|
||||
|
||||
#if __riscv_xlen != 32
|
||||
#define readq(c) ({ rt_uint64_t __v; __io_br(); __v = __raw_readq(c); __io_ar(); __v; })
|
||||
#define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); })
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-01-30 lizhirui first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include <riscv.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "riscv_mmu.h"
|
||||
|
||||
void mmu_enable_user_page_access(void)
|
||||
{
|
||||
set_csr(sstatus, SSTATUS_SUM);
|
||||
}
|
||||
|
||||
void mmu_disable_user_page_access(void)
|
||||
{
|
||||
clear_csr(sstatus, SSTATUS_SUM);
|
||||
}
|
||||
@@ -0,0 +1,168 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-01-30 lizhirui first version
|
||||
* 2023-10-12 Shell Add permission control API
|
||||
*/
|
||||
|
||||
#ifndef __RISCV_MMU_H__
|
||||
#define __RISCV_MMU_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include "riscv.h"
|
||||
|
||||
#undef PAGE_SIZE
|
||||
|
||||
#define PAGE_OFFSET_SHIFT 0
|
||||
#define PAGE_OFFSET_BIT 12
|
||||
#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
|
||||
#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT)
|
||||
#define VPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
|
||||
#define VPN0_BIT 9
|
||||
#define VPN1_SHIFT (VPN0_SHIFT + VPN0_BIT)
|
||||
#define VPN1_BIT 9
|
||||
#define VPN2_SHIFT (VPN1_SHIFT + VPN1_BIT)
|
||||
#define VPN2_BIT 9
|
||||
|
||||
#define PPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
|
||||
#define PPN0_BIT 9
|
||||
#define PPN1_SHIFT (PPN0_SHIFT + PPN0_BIT)
|
||||
#define PPN1_BIT 9
|
||||
#define PPN2_SHIFT (PPN1_SHIFT + PPN1_BIT)
|
||||
#define PPN2_BIT 26
|
||||
|
||||
#define L1_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT + VPN1_BIT)
|
||||
#define L2_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT)
|
||||
#define L3_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
|
||||
|
||||
#define ARCH_ADDRESS_WIDTH_BITS 64
|
||||
|
||||
#define PHYSICAL_ADDRESS_WIDTH_BITS 56
|
||||
|
||||
#define PAGE_ATTR_NEXT_LEVEL (0)
|
||||
#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R)
|
||||
#define PAGE_ATTR_READONLY (PTE_R)
|
||||
#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R)
|
||||
|
||||
#define PAGE_ATTR_USER (PTE_U)
|
||||
#define PAGE_ATTR_SYSTEM (0)
|
||||
|
||||
#define PAGE_DEFAULT_ATTR_LEAF (PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G)
|
||||
#define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G)
|
||||
|
||||
#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX)
|
||||
|
||||
#define PTE_USED(pte) __MASKVALUE(pte, PTE_V)
|
||||
|
||||
/**
|
||||
* encoding of SATP (Supervisor Address Translation and Protection register)
|
||||
*/
|
||||
#define SATP_MODE_OFFSET 60
|
||||
#define SATP_MODE_BARE 0
|
||||
#define SATP_MODE_SV39 8
|
||||
#define SATP_MODE_SV48 9
|
||||
#define SATP_MODE_SV57 10
|
||||
#define SATP_MODE_SV64 11
|
||||
|
||||
#define ARCH_VADDR_WIDTH 39
|
||||
#define SATP_MODE SATP_MODE_SV39
|
||||
|
||||
#define MMU_MAP_K_DEVICE (PTE_G | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_K_RWCB (PTE_G | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_K_RW (PTE_G | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_U_RWCB (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_U_RWCB_XN (PTE_U | PTE_W | PTE_R | PTE_V)
|
||||
#define MMU_MAP_U_RW (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
|
||||
|
||||
#define PTE_XWR_MASK 0xe
|
||||
|
||||
#define ARCH_PAGE_SIZE PAGE_SIZE
|
||||
#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
|
||||
#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT
|
||||
#define ARCH_INDEX_WIDTH 9
|
||||
#define ARCH_INDEX_SIZE (1ul << ARCH_INDEX_WIDTH)
|
||||
#define ARCH_INDEX_MASK (ARCH_INDEX_SIZE - 1)
|
||||
|
||||
#define ARCH_MAP_FAILED ((void *)0x8000000000000000)
|
||||
|
||||
void mmu_set_pagetable(rt_ubase_t addr);
|
||||
void mmu_enable_user_page_access(void);
|
||||
void mmu_disable_user_page_access(void);
|
||||
|
||||
#define RT_HW_MMU_PROT_READ 1
|
||||
#define RT_HW_MMU_PROT_WRITE 2
|
||||
#define RT_HW_MMU_PROT_EXECUTE 4
|
||||
#define RT_HW_MMU_PROT_KERNEL 8
|
||||
#define RT_HW_MMU_PROT_USER 16
|
||||
#define RT_HW_MMU_PROT_CACHE 32
|
||||
|
||||
/**
|
||||
* @brief Remove permission from attribution
|
||||
*
|
||||
* @param attr architecture specified mmu attribution
|
||||
* @param prot protect that will be removed
|
||||
* @return size_t returned attribution
|
||||
*/
|
||||
rt_inline size_t rt_hw_mmu_attr_rm_perm(size_t attr, rt_base_t prot)
|
||||
{
|
||||
switch (prot)
|
||||
{
|
||||
/* remove write permission for user */
|
||||
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
|
||||
attr &= ~PTE_W;
|
||||
break;
|
||||
default:
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
return attr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Add permission from attribution
|
||||
*
|
||||
* @param attr architecture specified mmu attribution
|
||||
* @param prot protect that will be added
|
||||
* @return size_t returned attribution
|
||||
*/
|
||||
rt_inline size_t rt_hw_mmu_attr_add_perm(size_t attr, rt_base_t prot)
|
||||
{
|
||||
switch (prot)
|
||||
{
|
||||
/* add write permission for user */
|
||||
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
|
||||
attr |= PTE_W;
|
||||
break;
|
||||
default:
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
return attr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Test permission from attribution
|
||||
*
|
||||
* @param attr architecture specified mmu attribution
|
||||
* @param prot protect that will be test
|
||||
* @return rt_bool_t RT_TRUE if the prot is allowed, otherwise RT_FALSE
|
||||
*/
|
||||
rt_inline rt_bool_t rt_hw_mmu_attr_test_perm(size_t attr, rt_base_t prot)
|
||||
{
|
||||
rt_bool_t rc = 0;
|
||||
switch (prot)
|
||||
{
|
||||
/* test write permission for user */
|
||||
case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER:
|
||||
rc = !!(attr & PTE_W);
|
||||
break;
|
||||
default:
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,264 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-05-18 Bernard port from FreeBSD
|
||||
*/
|
||||
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
||||
*
|
||||
* Copyright (c) 2019 Mitchell Horne <mhorne@FreeBSD.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "sbi.h"
|
||||
#include <rtthread.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/* SBI Implementation-Specific Definitions */
|
||||
#define OPENSBI_VERSION_MAJOR_OFFSET 16
|
||||
#define OPENSBI_VERSION_MINOR_MASK 0xFFFF
|
||||
|
||||
unsigned long sbi_spec_version;
|
||||
unsigned long sbi_impl_id;
|
||||
unsigned long sbi_impl_version;
|
||||
|
||||
static bool has_time_extension = false;
|
||||
static bool has_ipi_extension = false;
|
||||
static bool has_rfnc_extension = false;
|
||||
|
||||
static struct sbi_ret sbi_get_spec_version(void)
|
||||
{
|
||||
return (SBI_CALL0(SBI_EXT_ID_BASE, SBI_BASE_GET_SPEC_VERSION));
|
||||
}
|
||||
|
||||
static struct sbi_ret sbi_get_impl_id(void)
|
||||
{
|
||||
return (SBI_CALL0(SBI_EXT_ID_BASE, SBI_BASE_GET_IMPL_ID));
|
||||
}
|
||||
|
||||
static struct sbi_ret sbi_get_impl_version(void)
|
||||
{
|
||||
return (SBI_CALL0(SBI_EXT_ID_BASE, SBI_BASE_GET_IMPL_VERSION));
|
||||
}
|
||||
|
||||
void sbi_print_version(void)
|
||||
{
|
||||
uint32_t major;
|
||||
uint32_t minor;
|
||||
|
||||
/* For legacy SBI implementations. */
|
||||
if (sbi_spec_version == 0)
|
||||
{
|
||||
rt_kprintf("SBI: Unknown (Legacy) Implementation\n");
|
||||
rt_kprintf("SBI Specification Version: 0.1\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (sbi_impl_id)
|
||||
{
|
||||
case (SBI_IMPL_ID_BBL):
|
||||
rt_kprintf("SBI: Berkely Boot Loader %lu\n", sbi_impl_version);
|
||||
break;
|
||||
case (SBI_IMPL_ID_XVISOR):
|
||||
rt_kprintf("SBI: eXtensible Versatile hypervISOR %lu\n",
|
||||
sbi_impl_version);
|
||||
break;
|
||||
case (SBI_IMPL_ID_KVM):
|
||||
rt_kprintf("SBI: Kernel-based Virtual Machine %lu\n", sbi_impl_version);
|
||||
break;
|
||||
case (SBI_IMPL_ID_RUSTSBI):
|
||||
rt_kprintf("SBI: RustSBI %lu\n", sbi_impl_version);
|
||||
break;
|
||||
case (SBI_IMPL_ID_DIOSIX):
|
||||
rt_kprintf("SBI: Diosix %lu\n", sbi_impl_version);
|
||||
break;
|
||||
case (SBI_IMPL_ID_OPENSBI):
|
||||
major = sbi_impl_version >> OPENSBI_VERSION_MAJOR_OFFSET;
|
||||
minor = sbi_impl_version & OPENSBI_VERSION_MINOR_MASK;
|
||||
rt_kprintf("SBI: OpenSBI v%u.%u\n", major, minor);
|
||||
break;
|
||||
default:
|
||||
rt_kprintf("SBI: Unrecognized Implementation: %lu\n", sbi_impl_id);
|
||||
break;
|
||||
}
|
||||
|
||||
major = (sbi_spec_version & SBI_SPEC_VERS_MAJOR_MASK) >>
|
||||
SBI_SPEC_VERS_MAJOR_OFFSET;
|
||||
minor = (sbi_spec_version & SBI_SPEC_VERS_MINOR_MASK);
|
||||
rt_kprintf("SBI Specification Version: %u.%u\n", major, minor);
|
||||
}
|
||||
|
||||
void sbi_set_timer(uint64_t val)
|
||||
{
|
||||
struct sbi_ret ret;
|
||||
|
||||
/* Use the TIME legacy replacement extension, if available. */
|
||||
if (has_time_extension)
|
||||
{
|
||||
ret = SBI_CALL1(SBI_EXT_ID_TIME, SBI_TIME_SET_TIMER, val);
|
||||
RT_ASSERT(ret.error == SBI_SUCCESS);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)SBI_CALL1(SBI_SET_TIMER, 0, val);
|
||||
}
|
||||
}
|
||||
|
||||
void sbi_send_ipi(const unsigned long *hart_mask)
|
||||
{
|
||||
struct sbi_ret ret;
|
||||
|
||||
/* Use the IPI legacy replacement extension, if available. */
|
||||
if (has_ipi_extension)
|
||||
{
|
||||
ret = SBI_CALL2(SBI_EXT_ID_IPI, SBI_IPI_SEND_IPI, *hart_mask, 0);
|
||||
RT_ASSERT(ret.error == SBI_SUCCESS);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)SBI_CALL1(SBI_SEND_IPI, 0, (uint64_t)hart_mask);
|
||||
}
|
||||
}
|
||||
|
||||
void sbi_remote_fence_i(const unsigned long *hart_mask)
|
||||
{
|
||||
struct sbi_ret ret;
|
||||
|
||||
/* Use the RFENCE legacy replacement extension, if available. */
|
||||
if (has_rfnc_extension)
|
||||
{
|
||||
ret =
|
||||
SBI_CALL2(SBI_EXT_ID_RFNC, SBI_RFNC_REMOTE_FENCE_I, *hart_mask, 0);
|
||||
RT_ASSERT(ret.error == SBI_SUCCESS);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)SBI_CALL1(SBI_REMOTE_FENCE_I, 0, (uint64_t)hart_mask);
|
||||
}
|
||||
}
|
||||
|
||||
int sbi_remote_sfence_vma(const unsigned long *hart_mask,
|
||||
const unsigned long hart_mask_base,
|
||||
unsigned long start, unsigned long size)
|
||||
{
|
||||
struct sbi_ret ret = {.error = SBI_SUCCESS};
|
||||
|
||||
/* Use the RFENCE legacy replacement extension, if available. */
|
||||
if (has_rfnc_extension)
|
||||
{
|
||||
ret = SBI_CALL4(SBI_EXT_ID_RFNC, SBI_RFNC_REMOTE_SFENCE_VMA, *hart_mask,
|
||||
hart_mask_base, start, size);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)SBI_CALL3(SBI_REMOTE_SFENCE_VMA, 0, (uint64_t)hart_mask, start,
|
||||
size);
|
||||
}
|
||||
return ret.error;
|
||||
}
|
||||
|
||||
void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
|
||||
unsigned long start, unsigned long size,
|
||||
unsigned long asid)
|
||||
{
|
||||
struct sbi_ret ret;
|
||||
|
||||
/* Use the RFENCE legacy replacement extension, if available. */
|
||||
if (has_rfnc_extension)
|
||||
{
|
||||
ret = SBI_CALL5(SBI_EXT_ID_RFNC, SBI_RFNC_REMOTE_SFENCE_VMA_ASID,
|
||||
*hart_mask, 0, start, size, asid);
|
||||
RT_ASSERT(ret.error == SBI_SUCCESS);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)SBI_CALL4(SBI_REMOTE_SFENCE_VMA_ASID, 0, (uint64_t)hart_mask,
|
||||
start, size, asid);
|
||||
}
|
||||
}
|
||||
|
||||
int sbi_hsm_hart_start(unsigned long hart, unsigned long start_addr,
|
||||
unsigned long priv)
|
||||
{
|
||||
struct sbi_ret ret;
|
||||
|
||||
ret = SBI_CALL3(SBI_EXT_ID_HSM, SBI_HSM_HART_START, hart, start_addr, priv);
|
||||
return (ret.error != 0 ? (int)ret.error : 0);
|
||||
}
|
||||
|
||||
void sbi_hsm_hart_stop(void)
|
||||
{
|
||||
(void)SBI_CALL0(SBI_EXT_ID_HSM, SBI_HSM_HART_STOP);
|
||||
}
|
||||
|
||||
int sbi_hsm_hart_status(unsigned long hart)
|
||||
{
|
||||
struct sbi_ret ret;
|
||||
|
||||
ret = SBI_CALL1(SBI_EXT_ID_HSM, SBI_HSM_HART_STATUS, hart);
|
||||
|
||||
return (ret.error != 0 ? (int)ret.error : (int)ret.value);
|
||||
}
|
||||
|
||||
void sbi_init(void)
|
||||
{
|
||||
struct sbi_ret sret;
|
||||
|
||||
/*
|
||||
* Get the spec version. For legacy SBI implementations this will
|
||||
* return an error, otherwise it is guaranteed to succeed.
|
||||
*/
|
||||
sret = sbi_get_spec_version();
|
||||
if (sret.error != 0)
|
||||
{
|
||||
/* We are running a legacy SBI implementation. */
|
||||
sbi_spec_version = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set the SBI implementation info. */
|
||||
sbi_spec_version = sret.value;
|
||||
sbi_impl_id = sbi_get_impl_id().value;
|
||||
sbi_impl_version = sbi_get_impl_version().value;
|
||||
|
||||
/* Probe for legacy replacement extensions. */
|
||||
if (sbi_probe_extension(SBI_EXT_ID_TIME) != 0)
|
||||
has_time_extension = true;
|
||||
if (sbi_probe_extension(SBI_EXT_ID_IPI) != 0)
|
||||
has_ipi_extension = true;
|
||||
if (sbi_probe_extension(SBI_EXT_ID_RFNC) != 0)
|
||||
has_rfnc_extension = true;
|
||||
}
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
{
|
||||
sbi_console_putchar(*str++);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,244 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-05-18 Bernard port from FreeBSD
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2016-2017 Ruslan Bukin <br@bsdpad.com>
|
||||
* All rights reserved.
|
||||
* Copyright (c) 2019 Mitchell Horne <mhorne@FreeBSD.org>
|
||||
*
|
||||
* Portions of this software were developed by SRI International and the
|
||||
* University of Cambridge Computer Laboratory under DARPA/AFRL contract
|
||||
* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
|
||||
*
|
||||
* Portions of this software were developed by the University of Cambridge
|
||||
* Computer Laboratory as part of the CTSRD Project, with support from the
|
||||
* UK Higher Education Innovation Fund (HEIF).
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _MACHINE_SBI_H_
|
||||
#define _MACHINE_SBI_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <rtdef.h>
|
||||
|
||||
/* SBI Specification Version */
|
||||
#define SBI_SPEC_VERS_MAJOR_OFFSET 24
|
||||
#define SBI_SPEC_VERS_MAJOR_MASK (0x7F << SBI_SPEC_VERS_MAJOR_OFFSET)
|
||||
#define SBI_SPEC_VERS_MINOR_OFFSET 0
|
||||
#define SBI_SPEC_VERS_MINOR_MASK (0xFFFFFF << SBI_SPEC_VERS_MINOR_OFFSET)
|
||||
|
||||
/* SBI Implementation IDs */
|
||||
#define SBI_IMPL_ID_BBL 0
|
||||
#define SBI_IMPL_ID_OPENSBI 1
|
||||
#define SBI_IMPL_ID_XVISOR 2
|
||||
#define SBI_IMPL_ID_KVM 3
|
||||
#define SBI_IMPL_ID_RUSTSBI 4
|
||||
#define SBI_IMPL_ID_DIOSIX 5
|
||||
|
||||
/* SBI Error Codes */
|
||||
#define SBI_SUCCESS 0
|
||||
#define SBI_ERR_FAILURE -1
|
||||
#define SBI_ERR_NOT_SUPPORTED -2
|
||||
#define SBI_ERR_INVALID_PARAM -3
|
||||
#define SBI_ERR_DENIED -4
|
||||
#define SBI_ERR_INVALID_ADDRESS -5
|
||||
#define SBI_ERR_ALREADY_AVAILABLE -6
|
||||
|
||||
/* SBI Base Extension */
|
||||
#define SBI_EXT_ID_BASE 0x10
|
||||
#define SBI_BASE_GET_SPEC_VERSION 0
|
||||
#define SBI_BASE_GET_IMPL_ID 1
|
||||
#define SBI_BASE_GET_IMPL_VERSION 2
|
||||
#define SBI_BASE_PROBE_EXTENSION 3
|
||||
#define SBI_BASE_GET_MVENDORID 4
|
||||
#define SBI_BASE_GET_MARCHID 5
|
||||
#define SBI_BASE_GET_MIMPID 6
|
||||
|
||||
/* Timer (TIME) Extension */
|
||||
#define SBI_EXT_ID_TIME 0x54494D45
|
||||
#define SBI_TIME_SET_TIMER 0
|
||||
|
||||
/* IPI (IPI) Extension */
|
||||
#define SBI_EXT_ID_IPI 0x735049
|
||||
#define SBI_IPI_SEND_IPI 0
|
||||
|
||||
/* RFENCE (RFNC) Extension */
|
||||
#define SBI_EXT_ID_RFNC 0x52464E43
|
||||
#define SBI_RFNC_REMOTE_FENCE_I 0
|
||||
#define SBI_RFNC_REMOTE_SFENCE_VMA 1
|
||||
#define SBI_RFNC_REMOTE_SFENCE_VMA_ASID 2
|
||||
#define SBI_RFNC_REMOTE_HFENCE_GVMA_VMID 3
|
||||
#define SBI_RFNC_REMOTE_HFENCE_GVMA 4
|
||||
#define SBI_RFNC_REMOTE_HFENCE_VVMA_ASID 5
|
||||
#define SBI_RFNC_REMOTE_HFENCE_VVMA 6
|
||||
|
||||
/* Hart State Management (HSM) Extension */
|
||||
#define SBI_EXT_ID_HSM 0x48534D
|
||||
#define SBI_HSM_HART_START 0
|
||||
#define SBI_HSM_HART_STOP 1
|
||||
#define SBI_HSM_HART_STATUS 2
|
||||
#define SBI_HSM_STATUS_STARTED 0
|
||||
#define SBI_HSM_STATUS_STOPPED 1
|
||||
#define SBI_HSM_STATUS_START_PENDING 2
|
||||
#define SBI_HSM_STATUS_STOP_PENDING 3
|
||||
|
||||
/* Legacy Extensions */
|
||||
#define SBI_SET_TIMER 0
|
||||
#define SBI_CONSOLE_PUTCHAR 1
|
||||
#define SBI_CONSOLE_GETCHAR 2
|
||||
#define SBI_CLEAR_IPI 3
|
||||
#define SBI_SEND_IPI 4
|
||||
#define SBI_REMOTE_FENCE_I 5
|
||||
#define SBI_REMOTE_SFENCE_VMA 6
|
||||
#define SBI_REMOTE_SFENCE_VMA_ASID 7
|
||||
#define SBI_SHUTDOWN 8
|
||||
|
||||
#define SBI_CALL0(e, f) SBI_CALL5(e, f, 0, 0, 0, 0, 0)
|
||||
#define SBI_CALL1(e, f, p1) SBI_CALL5(e, f, p1, 0, 0, 0, 0)
|
||||
#define SBI_CALL2(e, f, p1, p2) SBI_CALL5(e, f, p1, p2, 0, 0, 0)
|
||||
#define SBI_CALL3(e, f, p1, p2, p3) SBI_CALL5(e, f, p1, p2, p3, 0, 0)
|
||||
#define SBI_CALL4(e, f, p1, p2, p3, p4) SBI_CALL5(e, f, p1, p2, p3, p4, 0)
|
||||
#define SBI_CALL5(e, f, p1, p2, p3, p4, p5) sbi_call(e, f, p1, p2, p3, p4, p5)
|
||||
|
||||
/*
|
||||
* Documentation available at
|
||||
* https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
|
||||
*/
|
||||
|
||||
struct sbi_ret
|
||||
{
|
||||
long error;
|
||||
long value;
|
||||
};
|
||||
|
||||
static __inline struct sbi_ret
|
||||
sbi_call(uint64_t arg7, uint64_t arg6, uint64_t arg0, uint64_t arg1,
|
||||
uint64_t arg2, uint64_t arg3, uint64_t arg4)
|
||||
{
|
||||
struct sbi_ret ret;
|
||||
|
||||
register uintptr_t a0 __asm("a0") = (uintptr_t)(arg0);
|
||||
register uintptr_t a1 __asm("a1") = (uintptr_t)(arg1);
|
||||
register uintptr_t a2 __asm("a2") = (uintptr_t)(arg2);
|
||||
register uintptr_t a3 __asm("a3") = (uintptr_t)(arg3);
|
||||
register uintptr_t a4 __asm("a4") = (uintptr_t)(arg4);
|
||||
register uintptr_t a6 __asm("a6") = (uintptr_t)(arg6);
|
||||
register uintptr_t a7 __asm("a7") = (uintptr_t)(arg7);
|
||||
|
||||
__asm __volatile(\
|
||||
"ecall" \
|
||||
: "+r"(a0), "+r"(a1) \
|
||||
: "r"(a2), "r"(a3), "r"(a4), "r"(a6), "r"(a7) \
|
||||
: "memory");
|
||||
|
||||
ret.error = a0;
|
||||
ret.value = a1;
|
||||
return (ret);
|
||||
}
|
||||
|
||||
/* Base extension functions and variables. */
|
||||
extern unsigned long sbi_spec_version;
|
||||
extern unsigned long sbi_impl_id;
|
||||
extern unsigned long sbi_impl_version;
|
||||
|
||||
static __inline long
|
||||
sbi_probe_extension(long id)
|
||||
{
|
||||
return (SBI_CALL1(SBI_EXT_ID_BASE, SBI_BASE_PROBE_EXTENSION, id).value);
|
||||
}
|
||||
|
||||
/* TIME extension functions. */
|
||||
void sbi_set_timer(uint64_t val);
|
||||
|
||||
/* IPI extension functions. */
|
||||
void sbi_send_ipi(const unsigned long *hart_mask);
|
||||
|
||||
/* RFENCE extension functions. */
|
||||
void sbi_remote_fence_i(const unsigned long *hart_mask);
|
||||
int sbi_remote_sfence_vma(const unsigned long *hart_mask,
|
||||
const unsigned long hart_mask_base,
|
||||
unsigned long start, unsigned long size);
|
||||
void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long start,
|
||||
unsigned long size, unsigned long asid);
|
||||
|
||||
/* Hart State Management extension functions. */
|
||||
|
||||
/*
|
||||
* Start execution on the specified hart at physical address start_addr. The
|
||||
* register a0 will contain the hart's ID, and a1 will contain the value of
|
||||
* priv.
|
||||
*/
|
||||
int sbi_hsm_hart_start(unsigned long hart, unsigned long start_addr, unsigned long priv);
|
||||
|
||||
/*
|
||||
* Stop execution on the current hart. Interrupts should be disabled, or this
|
||||
* function may return.
|
||||
*/
|
||||
void sbi_hsm_hart_stop(void);
|
||||
|
||||
/*
|
||||
* Get the execution status of the specified hart. The status will be one of:
|
||||
* - SBI_HSM_STATUS_STARTED
|
||||
* - SBI_HSM_STATUS_STOPPED
|
||||
* - SBI_HSM_STATUS_START_PENDING
|
||||
* - SBI_HSM_STATUS_STOP_PENDING
|
||||
*/
|
||||
int sbi_hsm_hart_status(unsigned long hart);
|
||||
|
||||
/* Legacy extension functions. */
|
||||
static __inline void
|
||||
sbi_console_putchar(int ch)
|
||||
{
|
||||
(void)SBI_CALL1(SBI_CONSOLE_PUTCHAR, 0, ch);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
sbi_console_getchar(void)
|
||||
{
|
||||
/*
|
||||
* XXX: The "error" is returned here because legacy SBI functions
|
||||
* continue to return their value in a0.
|
||||
*/
|
||||
return (SBI_CALL0(SBI_CONSOLE_GETCHAR, 0).error);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
sbi_shutdown(void)
|
||||
{
|
||||
(void)SBI_CALL0(SBI_SHUTDOWN, 0);
|
||||
}
|
||||
|
||||
void sbi_print_version(void);
|
||||
void sbi_init(void);
|
||||
|
||||
#endif /* !_MACHINE_SBI_H_ */
|
||||
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-01-30 lizhirui first version
|
||||
*/
|
||||
|
||||
#ifndef __STACK_H__
|
||||
#define __STACK_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
struct rt_hw_stack_frame
|
||||
{
|
||||
rt_ubase_t epc; /* epc - epc - program counter */
|
||||
rt_ubase_t ra; /* x1 - ra - return address for jumps */
|
||||
rt_ubase_t sstatus; /* - supervisor status register */
|
||||
rt_ubase_t gp; /* x3 - gp - global pointer */
|
||||
rt_ubase_t tp; /* x4 - tp - thread pointer */
|
||||
rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
|
||||
rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
|
||||
rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
|
||||
rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
|
||||
rt_ubase_t s1; /* x9 - s1 - saved register 1 */
|
||||
rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
|
||||
rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
|
||||
rt_ubase_t a2; /* x12 - a2 - function argument 2 */
|
||||
rt_ubase_t a3; /* x13 - a3 - function argument 3 */
|
||||
rt_ubase_t a4; /* x14 - a4 - function argument 4 */
|
||||
rt_ubase_t a5; /* x15 - a5 - function argument 5 */
|
||||
rt_ubase_t a6; /* x16 - a6 - function argument 6 */
|
||||
rt_ubase_t a7; /* x17 - s7 - function argument 7 */
|
||||
rt_ubase_t s2; /* x18 - s2 - saved register 2 */
|
||||
rt_ubase_t s3; /* x19 - s3 - saved register 3 */
|
||||
rt_ubase_t s4; /* x20 - s4 - saved register 4 */
|
||||
rt_ubase_t s5; /* x21 - s5 - saved register 5 */
|
||||
rt_ubase_t s6; /* x22 - s6 - saved register 6 */
|
||||
rt_ubase_t s7; /* x23 - s7 - saved register 7 */
|
||||
rt_ubase_t s8; /* x24 - s8 - saved register 8 */
|
||||
rt_ubase_t s9; /* x25 - s9 - saved register 9 */
|
||||
rt_ubase_t s10; /* x26 - s10 - saved register 10 */
|
||||
rt_ubase_t s11; /* x27 - s11 - saved register 11 */
|
||||
rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
|
||||
rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
|
||||
rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
|
||||
rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
|
||||
rt_ubase_t user_sp_exc_stack; /* sscratch - user mode sp/exception stack */
|
||||
#ifdef ENABLE_FPU
|
||||
rt_ubase_t f[CTX_FPU_REG_NR]; /* f0~f31 */
|
||||
#endif
|
||||
#ifdef ENABLE_VECTOR
|
||||
rt_ubase_t v[CTX_VECTOR_REG_NR];
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,274 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-02-02 lizhirui first version
|
||||
* 2021-02-11 lizhirui fixed gp save/store bug
|
||||
* 2021-11-18 JasonHu add fpu registers save/restore
|
||||
* 2022/10/22 WangXiaoyao Support kernel mode RVV;
|
||||
*/
|
||||
|
||||
#ifndef __STACKFRAME_H__
|
||||
#define __STACKFRAME_H__
|
||||
|
||||
#include "cpuport.h"
|
||||
#include "encoding.h"
|
||||
#include "ext_context.h"
|
||||
|
||||
#define BYTES(idx) ((idx) * REGBYTES)
|
||||
#define FRAME_OFF_SSTATUS BYTES(2)
|
||||
#define FRAME_OFF_SP BYTES(32)
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
.macro SAVE_ALL
|
||||
|
||||
#ifdef ENABLE_FPU
|
||||
/* reserve float registers */
|
||||
addi sp, sp, -CTX_FPU_REG_NR * REGBYTES
|
||||
#endif /* ENABLE_FPU */
|
||||
#ifdef ENABLE_VECTOR
|
||||
/* reserve float registers */
|
||||
addi sp, sp, -CTX_VECTOR_REG_NR * REGBYTES
|
||||
#endif /* ENABLE_VECTOR */
|
||||
|
||||
/* save general registers */
|
||||
addi sp, sp, -CTX_GENERAL_REG_NR * REGBYTES
|
||||
STORE x1, 1 * REGBYTES(sp)
|
||||
|
||||
csrr x1, sstatus
|
||||
STORE x1, FRAME_OFF_SSTATUS(sp)
|
||||
|
||||
csrr x1, sepc
|
||||
STORE x1, 0 * REGBYTES(sp)
|
||||
|
||||
STORE x3, 3 * REGBYTES(sp)
|
||||
STORE x4, 4 * REGBYTES(sp) /* save tp */
|
||||
STORE x5, 5 * REGBYTES(sp)
|
||||
STORE x6, 6 * REGBYTES(sp)
|
||||
STORE x7, 7 * REGBYTES(sp)
|
||||
STORE x8, 8 * REGBYTES(sp)
|
||||
STORE x9, 9 * REGBYTES(sp)
|
||||
STORE x10, 10 * REGBYTES(sp)
|
||||
STORE x11, 11 * REGBYTES(sp)
|
||||
STORE x12, 12 * REGBYTES(sp)
|
||||
STORE x13, 13 * REGBYTES(sp)
|
||||
STORE x14, 14 * REGBYTES(sp)
|
||||
STORE x15, 15 * REGBYTES(sp)
|
||||
STORE x16, 16 * REGBYTES(sp)
|
||||
STORE x17, 17 * REGBYTES(sp)
|
||||
STORE x18, 18 * REGBYTES(sp)
|
||||
STORE x19, 19 * REGBYTES(sp)
|
||||
STORE x20, 20 * REGBYTES(sp)
|
||||
STORE x21, 21 * REGBYTES(sp)
|
||||
STORE x22, 22 * REGBYTES(sp)
|
||||
STORE x23, 23 * REGBYTES(sp)
|
||||
STORE x24, 24 * REGBYTES(sp)
|
||||
STORE x25, 25 * REGBYTES(sp)
|
||||
STORE x26, 26 * REGBYTES(sp)
|
||||
STORE x27, 27 * REGBYTES(sp)
|
||||
STORE x28, 28 * REGBYTES(sp)
|
||||
STORE x29, 29 * REGBYTES(sp)
|
||||
STORE x30, 30 * REGBYTES(sp)
|
||||
STORE x31, 31 * REGBYTES(sp)
|
||||
csrr t0, sscratch
|
||||
STORE t0, 32 * REGBYTES(sp)
|
||||
|
||||
#ifdef ENABLE_FPU
|
||||
/* backup sp and adjust sp to save float registers */
|
||||
mv t1, sp
|
||||
addi t1, t1, CTX_GENERAL_REG_NR * REGBYTES
|
||||
|
||||
li t0, SSTATUS_FS
|
||||
csrs sstatus, t0
|
||||
fsd f0, FPU_CTX_F0_OFF(t1)
|
||||
fsd f1, FPU_CTX_F1_OFF(t1)
|
||||
fsd f2, FPU_CTX_F2_OFF(t1)
|
||||
fsd f3, FPU_CTX_F3_OFF(t1)
|
||||
fsd f4, FPU_CTX_F4_OFF(t1)
|
||||
fsd f5, FPU_CTX_F5_OFF(t1)
|
||||
fsd f6, FPU_CTX_F6_OFF(t1)
|
||||
fsd f7, FPU_CTX_F7_OFF(t1)
|
||||
fsd f8, FPU_CTX_F8_OFF(t1)
|
||||
fsd f9, FPU_CTX_F9_OFF(t1)
|
||||
fsd f10, FPU_CTX_F10_OFF(t1)
|
||||
fsd f11, FPU_CTX_F11_OFF(t1)
|
||||
fsd f12, FPU_CTX_F12_OFF(t1)
|
||||
fsd f13, FPU_CTX_F13_OFF(t1)
|
||||
fsd f14, FPU_CTX_F14_OFF(t1)
|
||||
fsd f15, FPU_CTX_F15_OFF(t1)
|
||||
fsd f16, FPU_CTX_F16_OFF(t1)
|
||||
fsd f17, FPU_CTX_F17_OFF(t1)
|
||||
fsd f18, FPU_CTX_F18_OFF(t1)
|
||||
fsd f19, FPU_CTX_F19_OFF(t1)
|
||||
fsd f20, FPU_CTX_F20_OFF(t1)
|
||||
fsd f21, FPU_CTX_F21_OFF(t1)
|
||||
fsd f22, FPU_CTX_F22_OFF(t1)
|
||||
fsd f23, FPU_CTX_F23_OFF(t1)
|
||||
fsd f24, FPU_CTX_F24_OFF(t1)
|
||||
fsd f25, FPU_CTX_F25_OFF(t1)
|
||||
fsd f26, FPU_CTX_F26_OFF(t1)
|
||||
fsd f27, FPU_CTX_F27_OFF(t1)
|
||||
fsd f28, FPU_CTX_F28_OFF(t1)
|
||||
fsd f29, FPU_CTX_F29_OFF(t1)
|
||||
fsd f30, FPU_CTX_F30_OFF(t1)
|
||||
fsd f31, FPU_CTX_F31_OFF(t1)
|
||||
|
||||
/* clr FS domain */
|
||||
csrc sstatus, t0
|
||||
|
||||
/* clean status would clr sr_sd; */
|
||||
li t0, SSTATUS_FS_CLEAN
|
||||
csrs sstatus, t0
|
||||
|
||||
#endif /* ENABLE_FPU */
|
||||
|
||||
#ifdef ENABLE_VECTOR
|
||||
csrr t0, sstatus
|
||||
andi t0, t0, SSTATUS_VS
|
||||
beqz t0, 0f
|
||||
|
||||
/* push vector frame */
|
||||
addi t1, sp, (CTX_GENERAL_REG_NR + CTX_FPU_REG_NR) * REGBYTES
|
||||
|
||||
SAVE_VECTOR t1
|
||||
0:
|
||||
#endif /* ENABLE_VECTOR */
|
||||
.endm
|
||||
|
||||
/**
|
||||
* @brief Restore All General Registers, for interrupt handling
|
||||
*
|
||||
*/
|
||||
.macro RESTORE_ALL
|
||||
|
||||
#ifdef ENABLE_VECTOR
|
||||
// skip on close
|
||||
ld t0, 2 * REGBYTES(sp)
|
||||
// cannot use vector on initial
|
||||
andi t0, t0, SSTATUS_VS_CLEAN
|
||||
beqz t0, 0f
|
||||
|
||||
/* push vector frame */
|
||||
addi t1, sp, (CTX_GENERAL_REG_NR + CTX_FPU_REG_NR) * REGBYTES
|
||||
|
||||
RESTORE_VECTOR t1
|
||||
0:
|
||||
#endif /* ENABLE_VECTOR */
|
||||
|
||||
#ifdef ENABLE_FPU
|
||||
/* restore float register */
|
||||
addi t2, sp, CTX_GENERAL_REG_NR * REGBYTES
|
||||
|
||||
li t0, SSTATUS_FS
|
||||
csrs sstatus, t0
|
||||
fld f0, FPU_CTX_F0_OFF(t2)
|
||||
fld f1, FPU_CTX_F1_OFF(t2)
|
||||
fld f2, FPU_CTX_F2_OFF(t2)
|
||||
fld f3, FPU_CTX_F3_OFF(t2)
|
||||
fld f4, FPU_CTX_F4_OFF(t2)
|
||||
fld f5, FPU_CTX_F5_OFF(t2)
|
||||
fld f6, FPU_CTX_F6_OFF(t2)
|
||||
fld f7, FPU_CTX_F7_OFF(t2)
|
||||
fld f8, FPU_CTX_F8_OFF(t2)
|
||||
fld f9, FPU_CTX_F9_OFF(t2)
|
||||
fld f10, FPU_CTX_F10_OFF(t2)
|
||||
fld f11, FPU_CTX_F11_OFF(t2)
|
||||
fld f12, FPU_CTX_F12_OFF(t2)
|
||||
fld f13, FPU_CTX_F13_OFF(t2)
|
||||
fld f14, FPU_CTX_F14_OFF(t2)
|
||||
fld f15, FPU_CTX_F15_OFF(t2)
|
||||
fld f16, FPU_CTX_F16_OFF(t2)
|
||||
fld f17, FPU_CTX_F17_OFF(t2)
|
||||
fld f18, FPU_CTX_F18_OFF(t2)
|
||||
fld f19, FPU_CTX_F19_OFF(t2)
|
||||
fld f20, FPU_CTX_F20_OFF(t2)
|
||||
fld f21, FPU_CTX_F21_OFF(t2)
|
||||
fld f22, FPU_CTX_F22_OFF(t2)
|
||||
fld f23, FPU_CTX_F23_OFF(t2)
|
||||
fld f24, FPU_CTX_F24_OFF(t2)
|
||||
fld f25, FPU_CTX_F25_OFF(t2)
|
||||
fld f26, FPU_CTX_F26_OFF(t2)
|
||||
fld f27, FPU_CTX_F27_OFF(t2)
|
||||
fld f28, FPU_CTX_F28_OFF(t2)
|
||||
fld f29, FPU_CTX_F29_OFF(t2)
|
||||
fld f30, FPU_CTX_F30_OFF(t2)
|
||||
fld f31, FPU_CTX_F31_OFF(t2)
|
||||
|
||||
/* clr FS domain */
|
||||
csrc sstatus, t0
|
||||
|
||||
/* clean status would clr sr_sd; */
|
||||
li t0, SSTATUS_FS_CLEAN
|
||||
csrs sstatus, t0
|
||||
|
||||
#endif /* ENABLE_FPU */
|
||||
|
||||
/* restore general register */
|
||||
addi t0, sp, CTX_REG_NR * REGBYTES
|
||||
csrw sscratch, t0
|
||||
|
||||
/* resw ra to sepc */
|
||||
LOAD x1, 0 * REGBYTES(sp)
|
||||
csrw sepc, x1
|
||||
|
||||
LOAD x1, 2 * REGBYTES(sp)
|
||||
csrw sstatus, x1
|
||||
|
||||
LOAD x1, 1 * REGBYTES(sp)
|
||||
|
||||
LOAD x3, 3 * REGBYTES(sp)
|
||||
LOAD x4, 4 * REGBYTES(sp) /* restore tp */
|
||||
LOAD x5, 5 * REGBYTES(sp)
|
||||
LOAD x6, 6 * REGBYTES(sp)
|
||||
LOAD x7, 7 * REGBYTES(sp)
|
||||
LOAD x8, 8 * REGBYTES(sp)
|
||||
LOAD x9, 9 * REGBYTES(sp)
|
||||
LOAD x10, 10 * REGBYTES(sp)
|
||||
LOAD x11, 11 * REGBYTES(sp)
|
||||
LOAD x12, 12 * REGBYTES(sp)
|
||||
LOAD x13, 13 * REGBYTES(sp)
|
||||
LOAD x14, 14 * REGBYTES(sp)
|
||||
LOAD x15, 15 * REGBYTES(sp)
|
||||
LOAD x16, 16 * REGBYTES(sp)
|
||||
LOAD x17, 17 * REGBYTES(sp)
|
||||
LOAD x18, 18 * REGBYTES(sp)
|
||||
LOAD x19, 19 * REGBYTES(sp)
|
||||
LOAD x20, 20 * REGBYTES(sp)
|
||||
LOAD x21, 21 * REGBYTES(sp)
|
||||
LOAD x22, 22 * REGBYTES(sp)
|
||||
LOAD x23, 23 * REGBYTES(sp)
|
||||
LOAD x24, 24 * REGBYTES(sp)
|
||||
LOAD x25, 25 * REGBYTES(sp)
|
||||
LOAD x26, 26 * REGBYTES(sp)
|
||||
LOAD x27, 27 * REGBYTES(sp)
|
||||
LOAD x28, 28 * REGBYTES(sp)
|
||||
LOAD x29, 29 * REGBYTES(sp)
|
||||
LOAD x30, 30 * REGBYTES(sp)
|
||||
LOAD x31, 31 * REGBYTES(sp)
|
||||
|
||||
/* restore user sp */
|
||||
LOAD sp, 32 * REGBYTES(sp)
|
||||
.endm
|
||||
|
||||
.macro RESTORE_SYS_GP
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
.endm
|
||||
|
||||
.macro OPEN_INTERRUPT
|
||||
csrsi sstatus, 2
|
||||
.endm
|
||||
|
||||
.macro CLOSE_INTERRUPT
|
||||
csrci sstatus, 2
|
||||
.endm
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __STACKFRAME_H__ */
|
||||
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-12-07 RT-Thread the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
|
||||
void init_bss(void)
|
||||
{
|
||||
unsigned int *dst;
|
||||
|
||||
dst = &__bss_start;
|
||||
while (dst < &__bss_end)
|
||||
{
|
||||
*dst++ = 0;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,98 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/01 Bernard The first version
|
||||
* 2018/12/27 Jesven Add SMP support
|
||||
* 2020/6/12 Xim Port to QEMU and remove SMP support
|
||||
*/
|
||||
|
||||
#include <encoding.h>
|
||||
#include <cpuport.h>
|
||||
|
||||
.data
|
||||
.global boot_hartid /* global varible rt_boot_hartid in .data section */
|
||||
boot_hartid:
|
||||
.word 0xdeadbeef
|
||||
|
||||
.global _start
|
||||
.section ".start", "ax"
|
||||
_start:
|
||||
j 1f
|
||||
.word 0xdeadbeef
|
||||
.align 3
|
||||
.global g_wake_up
|
||||
g_wake_up:
|
||||
.dword 1
|
||||
.dword 0
|
||||
1:
|
||||
/* save hartid */
|
||||
la t0, boot_hartid /* global varible rt_boot_hartid */
|
||||
mv t1, a0 /* get hartid in S-mode frome a0 register */
|
||||
sw t1, (t0) /* store t1 register low 4 bits in memory address which is stored in t0 */
|
||||
|
||||
/* clear Interrupt Registers */
|
||||
csrw sie, 0
|
||||
csrw sip, 0
|
||||
/* set Trap Vector Base Address Register */
|
||||
la t0, trap_entry
|
||||
csrw stvec, t0
|
||||
|
||||
li x1, 0
|
||||
li x2, 0
|
||||
li x3, 0
|
||||
li x4, 0
|
||||
li x5, 0
|
||||
li x6, 0
|
||||
li x7, 0
|
||||
li x8, 0
|
||||
li x9, 0
|
||||
li x10,0
|
||||
li x11,0
|
||||
li x12,0
|
||||
li x13,0
|
||||
li x14,0
|
||||
li x15,0
|
||||
li x16,0
|
||||
li x17,0
|
||||
li x18,0
|
||||
li x19,0
|
||||
li x20,0
|
||||
li x21,0
|
||||
li x22,0
|
||||
li x23,0
|
||||
li x24,0
|
||||
li x25,0
|
||||
li x26,0
|
||||
li x27,0
|
||||
li x28,0
|
||||
li x29,0
|
||||
li x30,0
|
||||
li x31,0
|
||||
|
||||
/* set to disable FPU */
|
||||
li t0, SSTATUS_FS + SSTATUS_VS
|
||||
csrc sstatus, t0
|
||||
li t0, SSTATUS_SUM
|
||||
csrs sstatus, t0
|
||||
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
|
||||
/* removed SMP support here */
|
||||
la sp, __stack_start__
|
||||
li t0, __STACKSIZE__
|
||||
add sp, sp, t0
|
||||
|
||||
/**
|
||||
* sscratch is always zero on kernel mode
|
||||
*/
|
||||
csrw sscratch, zero
|
||||
call init_bss
|
||||
call sbi_init
|
||||
j primary_cpu_entry
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-02-03 lizhirui first version
|
||||
* 2022-11-10 WangXiaoyao Add readable syscall tracing
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef RT_USING_SMART
|
||||
|
||||
#define DBG_TAG "syscall"
|
||||
#define DBG_LVL DBG_WARNING
|
||||
#include <rtdbg.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <mmu.h>
|
||||
#include <page.h>
|
||||
#include <lwp_user_mm.h>
|
||||
|
||||
#include "riscv_mmu.h"
|
||||
#include "stack.h"
|
||||
|
||||
typedef rt_size_t (*syscallfunc_t)(rt_size_t, rt_size_t, rt_size_t, rt_size_t, rt_size_t, rt_size_t, rt_size_t);
|
||||
|
||||
void syscall_handler(struct rt_hw_stack_frame *regs)
|
||||
{
|
||||
const char *syscall_name;
|
||||
int syscallid = regs->a7;
|
||||
|
||||
if (syscallid == 0)
|
||||
{
|
||||
LOG_E("syscall id = 0!\n");
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
syscallfunc_t syscallfunc = (syscallfunc_t)lwp_get_sys_api(syscallid);
|
||||
|
||||
if (syscallfunc == RT_NULL)
|
||||
{
|
||||
LOG_E("unsupported syscall!\n");
|
||||
sys_exit_group(-1);
|
||||
}
|
||||
|
||||
#if DBG_LVL >= DBG_INFO
|
||||
syscall_name = lwp_get_syscall_name(syscallid);
|
||||
#endif
|
||||
|
||||
LOG_I("[0x%lx] %s(0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)", rt_thread_self(), syscall_name,
|
||||
regs->a0, regs->a1, regs->a2, regs->a3, regs->a4, regs->a5, regs->a6);
|
||||
regs->a0 = syscallfunc(regs->a0, regs->a1, regs->a2, regs->a3, regs->a4, regs->a5, regs->a6);
|
||||
regs->a7 = 0;
|
||||
regs->epc += 4; // skip ecall instruction
|
||||
LOG_I("[0x%lx] %s ret: 0x%lx", rt_thread_self(), syscall_name, regs->a0);
|
||||
}
|
||||
#endif /* RT_USING_SMART */
|
||||
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/28 Bernard The unify RISC-V porting code.
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include <encoding.h>
|
||||
#include "sbi.h"
|
||||
|
||||
#ifdef RT_USING_KTIME
|
||||
#include <ktime.h>
|
||||
#endif
|
||||
|
||||
static volatile uint64_t time_elapsed = 0;
|
||||
static volatile unsigned long tick_cycles = 0;
|
||||
|
||||
static uint64_t get_ticks()
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"rdtime %0"
|
||||
: "=r"(time_elapsed));
|
||||
return time_elapsed;
|
||||
}
|
||||
|
||||
int tick_isr(void)
|
||||
{
|
||||
// uint64_t core_id = current_coreid();
|
||||
// clint->mtimecmp[core_id] += tick_cycles;
|
||||
rt_tick_increase();
|
||||
sbi_set_timer(get_ticks() + tick_cycles);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Sets and enable the timer interrupt */
|
||||
int rt_hw_tick_init(void)
|
||||
{
|
||||
/* Read core id */
|
||||
// unsigned long core_id = current_coreid();
|
||||
|
||||
/* Clear the Supervisor-Timer bit in SIE */
|
||||
clear_csr(sie, SIP_STIP);
|
||||
|
||||
/* calculate the tick cycles */
|
||||
tick_cycles = CPUTIME_TIMER_FREQ / RT_TICK_PER_SECOND;
|
||||
/* Set timer */
|
||||
sbi_set_timer(get_ticks() + tick_cycles);
|
||||
|
||||
#ifdef RT_USING_KTIME
|
||||
rt_ktime_cputimer_init();
|
||||
#endif
|
||||
/* Enable the Supervisor-Timer bit in SIE */
|
||||
set_csr(sie, SIP_STIP);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/10/28 Bernard The unify RISC-V porting code.
|
||||
*/
|
||||
|
||||
#ifndef TICK_H__
|
||||
#define TICK_H__
|
||||
|
||||
int tick_isr(void);
|
||||
int rt_hw_tick_init(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-11-28 WangXiaoyao the first version
|
||||
*/
|
||||
#ifndef __TLB_H__
|
||||
#define __TLB_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <mm_aspace.h>
|
||||
#include "sbi.h"
|
||||
#include "riscv_mmu.h"
|
||||
|
||||
#define HANDLE_FAULT(ret) \
|
||||
if (__builtin_expect((ret) != SBI_SUCCESS, 0)) \
|
||||
LOG_W("%s failed", __FUNCTION__);
|
||||
|
||||
static inline void rt_hw_tlb_invalidate_all(void)
|
||||
{
|
||||
uintptr_t mask = -1ul;
|
||||
HANDLE_FAULT(sbi_remote_sfence_vma(&mask, -1ul, 0, mask));
|
||||
}
|
||||
|
||||
static inline void rt_hw_tlb_invalidate_all_local(void)
|
||||
{
|
||||
__asm__ volatile("sfence.vma" ::: "memory");
|
||||
}
|
||||
|
||||
static inline void rt_hw_tlb_invalidate_aspace(rt_aspace_t aspace)
|
||||
{
|
||||
// TODO ASID
|
||||
rt_hw_tlb_invalidate_all_local();
|
||||
}
|
||||
|
||||
static inline void rt_hw_tlb_invalidate_page(rt_aspace_t aspace, void *start)
|
||||
{
|
||||
__asm__ volatile("sfence.vma %0, zero" ::"r"(start) : "memory");
|
||||
}
|
||||
|
||||
static inline void rt_hw_tlb_invalidate_range(rt_aspace_t aspace, void *start,
|
||||
size_t size, size_t stride)
|
||||
{
|
||||
// huge page is taking as normal page
|
||||
if (size <= ARCH_PAGE_SIZE)
|
||||
{
|
||||
rt_hw_tlb_invalidate_page(aspace, start);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_hw_tlb_invalidate_aspace(aspace);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __TLB_H__ */
|
||||
@@ -0,0 +1,376 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-12-08 RT-Thread first version
|
||||
*/
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <mm_fault.h>
|
||||
#include "mmu.h"
|
||||
#include "encoding.h"
|
||||
#include "stack.h"
|
||||
#include "sbi.h"
|
||||
#include "riscv.h"
|
||||
#include "interrupt.h"
|
||||
#include "plic.h"
|
||||
#include "tick.h"
|
||||
|
||||
#ifdef RT_USING_SMART
|
||||
#include <lwp_arch.h>
|
||||
#else
|
||||
#define rt_hw_backtrace(...) (0)
|
||||
#endif
|
||||
|
||||
#define DBG_TAG "libcpu.trap"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
void dump_regs(struct rt_hw_stack_frame *regs)
|
||||
{
|
||||
rt_kprintf("--------------Dump Registers-----------------\n");
|
||||
|
||||
rt_kprintf("Function Registers:\n");
|
||||
rt_kprintf("\tra(x1) = 0x%p\tuser_sp = 0x%p\n", regs->ra, regs->user_sp_exc_stack);
|
||||
rt_kprintf("\tgp(x3) = 0x%p\ttp(x4) = 0x%p\n", regs->gp, regs->tp);
|
||||
rt_kprintf("Temporary Registers:\n");
|
||||
rt_kprintf("\tt0(x5) = 0x%p\tt1(x6) = 0x%p\n", regs->t0, regs->t1);
|
||||
rt_kprintf("\tt2(x7) = 0x%p\n", regs->t2);
|
||||
rt_kprintf("\tt3(x28) = 0x%p\tt4(x29) = 0x%p\n", regs->t3, regs->t4);
|
||||
rt_kprintf("\tt5(x30) = 0x%p\tt6(x31) = 0x%p\n", regs->t5, regs->t6);
|
||||
rt_kprintf("Saved Registers:\n");
|
||||
rt_kprintf("\ts0/fp(x8) = 0x%p\ts1(x9) = 0x%p\n", regs->s0_fp, regs->s1);
|
||||
rt_kprintf("\ts2(x18) = 0x%p\ts3(x19) = 0x%p\n", regs->s2, regs->s3);
|
||||
rt_kprintf("\ts4(x20) = 0x%p\ts5(x21) = 0x%p\n", regs->s4, regs->s5);
|
||||
rt_kprintf("\ts6(x22) = 0x%p\ts7(x23) = 0x%p\n", regs->s6, regs->s7);
|
||||
rt_kprintf("\ts8(x24) = 0x%p\ts9(x25) = 0x%p\n", regs->s8, regs->s9);
|
||||
rt_kprintf("\ts10(x26) = 0x%p\ts11(x27) = 0x%p\n", regs->s10, regs->s11);
|
||||
rt_kprintf("Function Arguments Registers:\n");
|
||||
rt_kprintf("\ta0(x10) = 0x%p\ta1(x11) = 0x%p\n", regs->a0, regs->a1);
|
||||
rt_kprintf("\ta2(x12) = 0x%p\ta3(x13) = 0x%p\n", regs->a2, regs->a3);
|
||||
rt_kprintf("\ta4(x14) = 0x%p\ta5(x15) = 0x%p\n", regs->a4, regs->a5);
|
||||
rt_kprintf("\ta6(x16) = 0x%p\ta7(x17) = 0x%p\n", regs->a6, regs->a7);
|
||||
rt_kprintf("sstatus = 0x%p\n", regs->sstatus);
|
||||
rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SIE) ? "Supervisor Interrupt Enabled" : "Supervisor Interrupt Disabled");
|
||||
rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SPIE) ? "Last Time Supervisor Interrupt Enabled" : "Last Time Supervisor Interrupt Disabled");
|
||||
rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SPP) ? "Last Privilege is Supervisor Mode" : "Last Privilege is User Mode");
|
||||
rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SUM) ? "Permit to Access User Page" : "Not Permit to Access User Page");
|
||||
rt_kprintf("\t%s\n", (regs->sstatus & (1 << 19)) ? "Permit to Read Executable-only Page" : "Not Permit to Read Executable-only Page");
|
||||
rt_size_t satp_v = read_csr(satp);
|
||||
rt_kprintf("satp = 0x%p\n", satp_v);
|
||||
rt_kprintf("\tCurrent Page Table(Physical) = 0x%p\n", __MASKVALUE(satp_v, __MASK(44)) << PAGE_OFFSET_BIT);
|
||||
rt_kprintf("\tCurrent ASID = 0x%p\n", __MASKVALUE(satp_v >> 44, __MASK(16)) << PAGE_OFFSET_BIT);
|
||||
const char *mode_str = "Unknown Address Translation/Protection Mode";
|
||||
|
||||
switch (__MASKVALUE(satp_v >> 60, __MASK(4)))
|
||||
{
|
||||
case 0:
|
||||
mode_str = "No Address Translation/Protection Mode";
|
||||
break;
|
||||
|
||||
case 8:
|
||||
mode_str = "Page-based 39-bit Virtual Addressing Mode";
|
||||
break;
|
||||
|
||||
case 9:
|
||||
mode_str = "Page-based 48-bit Virtual Addressing Mode";
|
||||
break;
|
||||
}
|
||||
|
||||
rt_kprintf("\tMode = %s\n", mode_str);
|
||||
rt_kprintf("-----------------Dump OK---------------------\n");
|
||||
}
|
||||
|
||||
static const char *Exception_Name[] =
|
||||
{
|
||||
"Instruction Address Misaligned",
|
||||
"Instruction Access Fault",
|
||||
"Illegal Instruction",
|
||||
"Breakpoint",
|
||||
"Load Address Misaligned",
|
||||
"Load Access Fault",
|
||||
"Store/AMO Address Misaligned",
|
||||
"Store/AMO Access Fault",
|
||||
"Environment call from U-mode",
|
||||
"Environment call from S-mode",
|
||||
"Reserved-10",
|
||||
"Reserved-11",
|
||||
"Instruction Page Fault",
|
||||
"Load Page Fault",
|
||||
"Reserved-14",
|
||||
"Store/AMO Page Fault"};
|
||||
|
||||
static const char *Interrupt_Name[] =
|
||||
{
|
||||
"User Software Interrupt",
|
||||
"Supervisor Software Interrupt",
|
||||
"Reversed-2",
|
||||
"Reversed-3",
|
||||
"User Timer Interrupt",
|
||||
"Supervisor Timer Interrupt",
|
||||
"Reversed-6",
|
||||
"Reversed-7",
|
||||
"User External Interrupt",
|
||||
"Supervisor External Interrupt",
|
||||
"Reserved-10",
|
||||
"Reserved-11",
|
||||
};
|
||||
|
||||
extern struct rt_irq_desc irq_desc[];
|
||||
|
||||
#ifndef RT_USING_SMP
|
||||
static volatile int nested = 0;
|
||||
#define ENTER_TRAP \
|
||||
nested += 1
|
||||
#define EXIT_TRAP \
|
||||
nested -= 1
|
||||
#define CHECK_NESTED_PANIC(cause, tval, epc, eframe) \
|
||||
if (nested != 1) \
|
||||
handle_nested_trap_panic(cause, tval, epc, eframe)
|
||||
#endif /* RT_USING_SMP */
|
||||
|
||||
static const char *get_exception_msg(int id)
|
||||
{
|
||||
const char *msg;
|
||||
if (id < sizeof(Exception_Name) / sizeof(const char *))
|
||||
{
|
||||
msg = Exception_Name[id];
|
||||
}
|
||||
else
|
||||
{
|
||||
msg = "Unknown Exception";
|
||||
}
|
||||
return msg;
|
||||
}
|
||||
|
||||
#ifdef RT_USING_SMART
|
||||
#include "lwp.h"
|
||||
void handle_user(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw_stack_frame *sp)
|
||||
{
|
||||
rt_size_t id = __MASKVALUE(scause, __MASK(63UL));
|
||||
struct rt_lwp *lwp;
|
||||
|
||||
/* user page fault */
|
||||
enum rt_mm_fault_op fault_op;
|
||||
enum rt_mm_fault_type fault_type;
|
||||
switch (id)
|
||||
{
|
||||
case EP_LOAD_PAGE_FAULT:
|
||||
fault_op = MM_FAULT_OP_READ;
|
||||
fault_type = MM_FAULT_TYPE_PAGE_FAULT;
|
||||
break;
|
||||
case EP_LOAD_ACCESS_FAULT:
|
||||
fault_op = MM_FAULT_OP_READ;
|
||||
fault_type = MM_FAULT_TYPE_ACCESS_FAULT;
|
||||
break;
|
||||
case EP_LOAD_ADDRESS_MISALIGNED:
|
||||
fault_op = MM_FAULT_OP_READ;
|
||||
fault_type = MM_FAULT_TYPE_BUS_ERROR;
|
||||
break;
|
||||
case EP_STORE_PAGE_FAULT:
|
||||
fault_op = MM_FAULT_OP_WRITE;
|
||||
fault_type = MM_FAULT_TYPE_PAGE_FAULT;
|
||||
break;
|
||||
case EP_STORE_ACCESS_FAULT:
|
||||
fault_op = MM_FAULT_OP_WRITE;
|
||||
fault_type = MM_FAULT_TYPE_ACCESS_FAULT;
|
||||
break;
|
||||
case EP_STORE_ADDRESS_MISALIGNED:
|
||||
fault_op = MM_FAULT_OP_WRITE;
|
||||
fault_type = MM_FAULT_TYPE_BUS_ERROR;
|
||||
break;
|
||||
case EP_INSTRUCTION_PAGE_FAULT:
|
||||
fault_op = MM_FAULT_OP_EXECUTE;
|
||||
fault_type = MM_FAULT_TYPE_PAGE_FAULT;
|
||||
break;
|
||||
case EP_INSTRUCTION_ACCESS_FAULT:
|
||||
fault_op = MM_FAULT_OP_EXECUTE;
|
||||
fault_type = MM_FAULT_TYPE_ACCESS_FAULT;
|
||||
break;
|
||||
case EP_INSTRUCTION_ADDRESS_MISALIGNED:
|
||||
fault_op = MM_FAULT_OP_EXECUTE;
|
||||
fault_type = MM_FAULT_TYPE_BUS_ERROR;
|
||||
break;
|
||||
default:
|
||||
fault_op = 0;
|
||||
}
|
||||
|
||||
if (fault_op)
|
||||
{
|
||||
rt_base_t saved_stat;
|
||||
lwp = lwp_self();
|
||||
struct rt_aspace_fault_msg msg = {
|
||||
.fault_op = fault_op,
|
||||
.fault_type = fault_type,
|
||||
.fault_vaddr = (void *)stval,
|
||||
};
|
||||
|
||||
__asm__ volatile ("csrrsi %0, sstatus, 2":"=r"(saved_stat));
|
||||
if (lwp && rt_aspace_fault_try_fix(lwp->aspace, &msg))
|
||||
{
|
||||
__asm__ volatile ("csrw sstatus, %0"::"r"(saved_stat));
|
||||
return;
|
||||
}
|
||||
__asm__ volatile ("csrw sstatus, %0"::"r"(saved_stat));
|
||||
}
|
||||
LOG_E("[FATAL ERROR] Exception %ld:%s\n", id, get_exception_msg(id));
|
||||
LOG_E("scause:0x%p,stval:0x%p,sepc:0x%p\n", scause, stval, sepc);
|
||||
dump_regs(sp);
|
||||
|
||||
rt_thread_t cur_thr = rt_thread_self();
|
||||
struct rt_hw_backtrace_frame frame = {
|
||||
.fp = sp->s0_fp,
|
||||
.pc = sepc
|
||||
};
|
||||
rt_kprintf("fp = %p\n", frame.fp);
|
||||
lwp_backtrace_frame(cur_thr, &frame);
|
||||
|
||||
LOG_E("User Fault, killing thread: %s", cur_thr->parent.name);
|
||||
|
||||
EXIT_TRAP;
|
||||
sys_exit_group(-1);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_VECTOR
|
||||
static void vector_enable(struct rt_hw_stack_frame *sp)
|
||||
{
|
||||
sp->sstatus |= SSTATUS_VS_INITIAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* detect V/D support, and do not distinguish V/D instruction
|
||||
*/
|
||||
static int illegal_inst_recoverable(rt_ubase_t stval, struct rt_hw_stack_frame *sp)
|
||||
{
|
||||
// first 7 bits is opcode
|
||||
int opcode = stval & 0x7f;
|
||||
int csr = (stval & 0xFFF00000) >> 20;
|
||||
// ref riscv-v-spec-1.0, [Vector Instruction Formats]
|
||||
int width = ((stval & 0x7000) >> 12) - 1;
|
||||
int flag = 0;
|
||||
|
||||
switch (opcode)
|
||||
{
|
||||
case 0x57: // V
|
||||
case 0x27: // scalar FLOAT
|
||||
case 0x07:
|
||||
case 0x73: // CSR
|
||||
flag = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
if (flag)
|
||||
{
|
||||
vector_enable(sp);
|
||||
}
|
||||
|
||||
return flag;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void handle_nested_trap_panic(
|
||||
rt_size_t cause,
|
||||
rt_size_t tval,
|
||||
rt_size_t epc,
|
||||
struct rt_hw_stack_frame *eframe)
|
||||
{
|
||||
LOG_E("\n-------- [SEVER ERROR] --------");
|
||||
LOG_E("Nested trap detected");
|
||||
LOG_E("scause:0x%p,stval:0x%p,sepc:0x%p\n", cause, tval, epc);
|
||||
dump_regs(eframe);
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
#define IN_USER_SPACE (stval >= USER_VADDR_START && stval < USER_VADDR_TOP)
|
||||
#define PAGE_FAULT (id == EP_LOAD_PAGE_FAULT || id == EP_STORE_PAGE_FAULT)
|
||||
|
||||
/* Trap entry */
|
||||
void handle_trap(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw_stack_frame *sp)
|
||||
{
|
||||
ENTER_TRAP;
|
||||
rt_size_t id = __MASKVALUE(scause, __MASK(63UL));
|
||||
const char *msg;
|
||||
|
||||
/* supervisor external interrupt */
|
||||
if (scause == (uint64_t)(0x8000000000000005))
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
tick_isr();
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
else if (scause == (uint64_t)(0x8000000000000009))
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
int plic_irq = plic_claim();
|
||||
plic_complete(plic_irq);
|
||||
irq_desc[plic_irq].handler(plic_irq, irq_desc[plic_irq].param);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
else
|
||||
{
|
||||
// trap cannot nested when handling another trap / interrupt
|
||||
CHECK_NESTED_PANIC(scause, stval, sepc, sp);
|
||||
rt_size_t id = __MASKVALUE(scause, __MASK(63UL));
|
||||
const char *msg;
|
||||
|
||||
if (scause >> 63)
|
||||
{
|
||||
if (id < sizeof(Interrupt_Name) / sizeof(const char *))
|
||||
{
|
||||
msg = Interrupt_Name[id];
|
||||
}
|
||||
else
|
||||
{
|
||||
msg = "Unknown Interrupt";
|
||||
}
|
||||
|
||||
rt_kprintf("Unhandled Interrupt %ld:%s\n", id, msg);
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef ENABLE_VECTOR
|
||||
if (scause == 0x2)
|
||||
{
|
||||
if (!(sp->sstatus & SSTATUS_VS) && illegal_inst_recoverable(stval, sp))
|
||||
goto _exit;
|
||||
}
|
||||
#endif /* ENABLE_VECTOR */
|
||||
#ifdef RT_USING_SMART
|
||||
if (!(sp->sstatus & 0x100) || (PAGE_FAULT && IN_USER_SPACE))
|
||||
{
|
||||
handle_user(scause, stval, sepc, sp);
|
||||
// if handle_user() return here, jump to u mode then
|
||||
goto _exit;
|
||||
}
|
||||
#endif
|
||||
|
||||
// handle kernel exception:
|
||||
rt_kprintf("Unhandled Exception %ld:%s\n", id, get_exception_msg(id));
|
||||
}
|
||||
|
||||
rt_kprintf("scause:0x%p,stval:0x%p,sepc:0x%p\n", scause, stval, sepc);
|
||||
dump_regs(sp);
|
||||
rt_kprintf("--------------Thread list--------------\n");
|
||||
rt_kprintf("current thread: %s\n", rt_thread_self()->parent.name);
|
||||
|
||||
extern struct rt_thread *rt_current_thread;
|
||||
rt_kprintf("--------------Backtrace--------------\n");
|
||||
struct rt_hw_backtrace_frame frame = {
|
||||
.fp = sp->s0_fp,
|
||||
.pc = sepc
|
||||
};
|
||||
rt_kprintf("fp = %p", frame.fp);
|
||||
rt_backtrace_frame(&frame);
|
||||
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
_exit:
|
||||
EXIT_TRAP;
|
||||
return ;
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-10-10 RT-Thread the first version,
|
||||
* compatible to riscv-v-spec-1.0
|
||||
*/
|
||||
|
||||
#ifndef __VECTOR_ENCODING_H__
|
||||
#define __VECTOR_ENCODING_H__
|
||||
|
||||
/**
|
||||
* assembler names used for vset{i}vli vtypei immediate
|
||||
*/
|
||||
|
||||
#define VEC_IMM_SEW_8 e8
|
||||
#define VEC_IMM_SEW_16 e16
|
||||
#define VEC_IMM_SEW_32 e32
|
||||
#define VEC_IMM_SEW_64 e64
|
||||
/* group setting, encoding by multiplier */
|
||||
#define VEC_IMM_LMUL_F8 mf8
|
||||
#define VEC_IMM_LMUL_F4 mf4
|
||||
#define VEC_IMM_LMUL_F2 mf2
|
||||
#define VEC_IMM_LMUL_1 m1
|
||||
#define VEC_IMM_LMUL_2 m2
|
||||
#define VEC_IMM_LMUL_4 m4
|
||||
#define VEC_IMM_LMUL_8 m8
|
||||
/* TAIL & MASK agnostic bits */
|
||||
#define VEC_IMM_TAIL_AGNOSTIC ta
|
||||
#define VEC_IMM_MASK_AGNOSTIC ma
|
||||
#define VEC_IMM_TAMA VEC_IMM_TAIL_AGNOSTIC, VEC_IMM_MASK_AGNOSTIC
|
||||
#define VEC_IMM_TAMU VEC_IMM_TAIL_AGNOSTIC
|
||||
#define VEC_IMM_TUMA VEC_IMM_MASK_AGNOSTIC
|
||||
|
||||
/**
|
||||
* configuration setting instruction
|
||||
*/
|
||||
#define VEC_CONFIG_SETVLI(xVl, xAvl, vtype...) vsetvli xVl, xAvl, ##vtype
|
||||
#define VEC_CONFIG_SET_VL_VTYPE(xVl, xVtype) vsetvl x0, xVl, xVtype
|
||||
|
||||
#endif /* __VECTOR_ENCODING_H__ */
|
||||
Reference in new issue
Block a user