From a53eb282d2c68a54f24f3918e0a9094a7a89f04e Mon Sep 17 00:00:00 2001 From: sc <2401809606@qq.com> Date: Thu, 27 Nov 2025 02:25:08 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E8=BF=9B=E7=A8=8B=E5=86=85?= =?UTF-8?q?=E5=AD=98=E4=BD=8D=E7=BD=AE=20=E5=90=AF=E7=94=A8mpu=E5=86=85?= =?UTF-8?q?=E5=AD=98=E4=BF=9D=E6=8A=A4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .cproject | 4 +-- .project | 2 +- .settings/projcfg.ini | 4 +-- applications/data/DATA_comm.c | 26 ++++++++------- applications/disk/QSPI_elmfatfs.c | 2 +- applications/disk/SDIO_elmfatfs.c | 6 ++-- applications/main.c | 11 ++++++- cubemx/Src/main.c | 53 +++++++++++++++++++++++++++---- cubemx/cubemx.ioc | 32 ++++++++++++++++++- exclude_list.json | 2 +- 10 files changed, 112 insertions(+), 30 deletions(-) diff --git a/.cproject b/.cproject index 6ea0783..69f0452 100644 --- a/.cproject +++ b/.cproject @@ -643,7 +643,7 @@ - + @@ -663,7 +663,7 @@ - + diff --git a/.project b/.project index 350c330..f059ea4 100644 --- a/.project +++ b/.project @@ -1,6 +1,6 @@ - project + 828F diff --git a/.settings/projcfg.ini b/.settings/projcfg.ini index 6fcde23..5cc1ef7 100644 --- a/.settings/projcfg.ini +++ b/.settings/projcfg.ini @@ -1,5 +1,5 @@ #RT-Thread Studio Project Configuration -#Sun Nov 16 13:49:37 CST 2025 +#Thu Nov 27 01:44:39 CST 2025 project_type=rtt chip_name=STM32H743IITx cpu_name=None @@ -18,5 +18,5 @@ uart_name=uart3 tx_pin_name=PB10 rtt_nano_path= output_project_path=C\:/RT-ThreadStudio/workspace -hardware_adapter=DAP-LINK +hardware_adapter=ST-LINK project_name=828F diff --git a/applications/data/DATA_comm.c b/applications/data/DATA_comm.c index b8454b6..eef7384 100644 --- a/applications/data/DATA_comm.c +++ b/applications/data/DATA_comm.c @@ -467,8 +467,12 @@ void proc_thread_entry(void *parameter) } } +extern struct rt_memheap sram_DTCMRAM; +static struct rt_thread dat_comm_thread; +static void *dat_comm_stack __attribute__((aligned(4)))= RT_NULL ; int data_comm_init(void) { + rt_err_t dat_err; proc_mq = rt_mq_create("proc_mq", sizeof(struct proc_request*), 5, RT_IPC_FLAG_FIFO); if (proc_mq == RT_NULL) { @@ -476,18 +480,18 @@ int data_comm_init(void) return -1; } - rt_thread_t tid = rt_thread_create("dat_comm", proc_thread_entry, RT_NULL, - 1024*6, 20, 10); - if (tid != RT_NULL) - { - rt_thread_startup(tid); - LOG_D("Create cJSON thread"); - } - else + dat_comm_stack = rt_memheap_alloc(&sram_DTCMRAM, 1024*6); + dat_err = rt_thread_init(&dat_comm_thread, "dat_comm", proc_thread_entry, RT_NULL, + dat_comm_stack, 1024*6, 15, 10); + + if(dat_err != RT_EOK) { - LOG_D("Failed to create cJSON thread!\n"); + LOG_E("Failed to create cJSON thread!"); + return -1; + }else{ + LOG_I("Create cJSON thread"); } - + rt_thread_startup(&dat_comm_thread); return 0; } -//INIT_COMPONENT_EXPORT(data_comm_init); +INIT_APP_EXPORT(data_comm_init); diff --git a/applications/disk/QSPI_elmfatfs.c b/applications/disk/QSPI_elmfatfs.c index 1844323..a635689 100644 --- a/applications/disk/QSPI_elmfatfs.c +++ b/applications/disk/QSPI_elmfatfs.c @@ -125,4 +125,4 @@ int qspi_fal(void) } return RT_EOK; } -INIT_APP_EXPORT(qspi_fal); +INIT_COMPONENT_EXPORT(qspi_fal); diff --git a/applications/disk/SDIO_elmfatfs.c b/applications/disk/SDIO_elmfatfs.c index 5053977..6c53c85 100644 --- a/applications/disk/SDIO_elmfatfs.c +++ b/applications/disk/SDIO_elmfatfs.c @@ -46,8 +46,8 @@ void sd_mount(void *parameter) LOG_D("SD device 'sd' not found, retrying..."); } - // 避免空转，延时 100ms 再试 - rt_thread_mdelay(100); + // 避免空转，延时 50ms 再试 + rt_thread_mdelay(50); retry++; } } @@ -92,4 +92,4 @@ int stm32_sdcard_mount(void) } // 使用 INIT_COMPONENTS_INIT 或 INIT_APP_EXPORT 自动启动 //INIT_COMPONENTS_INIT(stm32_sdcard_mount); // 在组件初始化阶段运行 -INIT_APP_EXPORT(stm32_sdcard_mount); +INIT_COMPONENT_EXPORT(stm32_sdcard_mount); diff --git a/applications/main.c b/applications/main.c index 5de58b6..563a451 100644 --- a/applications/main.c +++ b/applications/main.c @@ -23,9 +23,18 @@ extern rt_sem_t mount_sem; // 引用上面SD挂载线程定义的信号量 int main(void) { + /*volatile uint32_t *sdram_test = (uint32_t*)0xC0000000; + *sdram_test = 0xAABBCCDD; + rt_thread_mdelay(1); // 等待稳定 + if (*sdram_test != 0xAABBCCDD) + { + rt_kprintf("SDRAM init failed!\n"); + while (1); // 卡死，不要继续 + } + rt_kprintf("SDRAM test OK\n");*/ + rt_sem_take(mount_sem, rt_tick_from_millisecond(5000)); // 等待挂载完成，最多等待 5 秒 thread_DB_SQLite(); - data_comm_init(); //start_uart_thread(); thread_RUN_LED();//运行指示灯线程 return RT_EOK; diff --git a/cubemx/Src/main.c b/cubemx/Src/main.c index 870bf27..c3bc009 100644 --- a/cubemx/Src/main.c +++ b/cubemx/Src/main.c @@ -91,6 +91,14 @@ __WEAK int main(void) /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); + /* Enable the CPU Cache */ + + /* Enable I-Cache---------------------------------------------------------*/ + SCB_EnableICache(); + + /* Enable D-Cache---------------------------------------------------------*/ + SCB_EnableDCache(); + /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ @@ -534,15 +542,46 @@ void MPU_Config(void) */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; MPU_InitStruct.Number = MPU_REGION_NUMBER0; - MPU_InitStruct.BaseAddress = 0x0; - MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; - MPU_InitStruct.SubRegionDisable = 0x87; + MPU_InitStruct.BaseAddress = 0x24000000; + MPU_InitStruct.Size = MPU_REGION_SIZE_512KB; + MPU_InitStruct.SubRegionDisable = 0x0; MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; - MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; - MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; - MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; - MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; + MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Number = MPU_REGION_NUMBER1; + MPU_InitStruct.BaseAddress = 0x30000000; + MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Number = MPU_REGION_NUMBER2; + MPU_InitStruct.BaseAddress = 0x30020000; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Number = MPU_REGION_NUMBER3; + MPU_InitStruct.BaseAddress = 0x0; + MPU_InitStruct.Size = MPU_REGION_SIZE_32KB; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Number = MPU_REGION_NUMBER4; + MPU_InitStruct.BaseAddress = 0xC0000000; + MPU_InitStruct.Size = MPU_REGION_SIZE_32MB; HAL_MPU_ConfigRegion(&MPU_InitStruct); /* Enables the MPU */ diff --git a/cubemx/cubemx.ioc b/cubemx/cubemx.ioc index 425a7fb..5323e9a 100644 --- a/cubemx/cubemx.ioc +++ b/cubemx/cubemx.ioc @@ -2,7 +2,37 @@ CAD.formats= CAD.pinconfig= CAD.provider= -CORTEX_M7.IPParameters=default_mode_Activation +CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=0x30000000 +CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=0x30020000 +CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=0x0 +CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=0xC0000000 +CORTEX_M7.BaseAddress_Spec=0x24000000 +CORTEX_M7.CPU_DCache=Enabled +CORTEX_M7.CPU_ICache=Enabled +CORTEX_M7.DisableExec_Spec=MPU_INSTRUCTION_ACCESS_ENABLE +CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_ENABLE +CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_ENABLE +CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_REGION_ENABLE +CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_REGION_ENABLE +CORTEX_M7.IPParameters=default_mode_Activation,CPU_ICache,CPU_DCache,Size_Spec,BaseAddress_Spec,DisableExec_Spec,IsCacheable_Spec,IsBufferable_Spec,IsShareable_Spec,SubRegionDisable_Spec,Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,IsShareable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S +CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_ACCESS_BUFFERABLE +CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_BUFFERABLE +CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_ACCESS_BUFFERABLE +CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_ACCESS_BUFFERABLE +CORTEX_M7.IsBufferable_Spec=MPU_ACCESS_BUFFERABLE +CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_ACCESS_CACHEABLE +CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_CACHEABLE +CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_ACCESS_CACHEABLE +CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_ACCESS_CACHEABLE +CORTEX_M7.IsCacheable_Spec=MPU_ACCESS_CACHEABLE +CORTEX_M7.IsShareable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_ACCESS_NOT_SHAREABLE +CORTEX_M7.IsShareable_Spec=MPU_ACCESS_NOT_SHAREABLE +CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_SIZE_128KB +CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_SIZE_128KB +CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_REGION_SIZE_32KB +CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_REGION_SIZE_32MB +CORTEX_M7.Size_Spec=MPU_REGION_SIZE_512KB +CORTEX_M7.SubRegionDisable_Spec=0x0 CORTEX_M7.default_mode_Activation=1 Dma.Request0=USART1_RX Dma.RequestsNb=1 diff --git a/exclude_list.json b/exclude_list.json index 4320063..773c782 100644 --- a/exclude_list.json +++ b/exclude_list.json @@ -1 +1 @@ -[{"config_name":"Debug","exclude_files":["packages/sqlite-v3.19.3/dbhelper.c","packages/sqlite-v3.19.3/rtthread_vfs.c","applications/lvgl","packages/LVGL-v8.3.11"]}] \ No newline at end of file +[{"config_name":"Debug","exclude_files":["packages/sqlite-v3.19.3/dbhelper.c","packages/sqlite-v3.19.3/rtthread_vfs.c"]}] \ No newline at end of file