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/**
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****************************************************************************** |
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* @file stm32h7xx_hal_mmc.h |
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* @author MCD Application Team |
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* @brief Header file of MMC HAL module. |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2017 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file |
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* in the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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* |
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****************************************************************************** |
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*/ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef STM32H7xx_HAL_MMC_H |
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#define STM32H7xx_HAL_MMC_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32h7xx_ll_sdmmc.h" |
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/** @addtogroup STM32H7xx_HAL_Driver
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* @{ |
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*/ |
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#if defined (SDMMC1) || defined (SDMMC2) |
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/** @addtogroup MMC
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* @{ |
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*/ |
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/* Exported types ------------------------------------------------------------*/ |
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/** @defgroup MMC_Exported_Types MMC Exported Types
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* @{ |
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*/ |
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/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
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* @{ |
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*/ |
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typedef enum |
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{ |
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HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */ |
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HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */ |
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HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */ |
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HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */ |
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HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */ |
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HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */ |
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HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfer State */ |
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HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */ |
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} HAL_MMC_StateTypeDef; |
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/**
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* @} |
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*/ |
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/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
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* @{ |
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*/ |
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typedef uint32_t HAL_MMC_CardStateTypeDef; |
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#define HAL_MMC_CARD_IDLE 0x00000000U /*!< Card is in idle state (can't be checked by CMD13) */ |
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#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready (can't be checked by CMD13) */ |
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#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state (can't be checked by CMD13) */ |
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#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ |
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#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ |
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#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ |
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#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ |
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#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ |
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#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ |
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#define HAL_MMC_CARD_BUSTEST 0x00000009U /*!< Card is in bus test state */ |
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#define HAL_MMC_CARD_SLEEP 0x0000000AU /*!< Card is in sleep state (can't be checked by CMD13) */ |
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#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error (can't be checked by CMD13) */ |
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/**
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* @} |
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*/ |
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/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
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* @{ |
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*/ |
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#define MMC_InitTypeDef SDMMC_InitTypeDef |
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#define MMC_TypeDef SDMMC_TypeDef |
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/**
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* @brief MMC Card Information Structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t CardType; /*!< Specifies the card Type */ |
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uint32_t Class; /*!< Specifies the class of the card class */ |
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uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ |
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uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ |
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uint32_t BlockSize; /*!< Specifies one block size in bytes */ |
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uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ |
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uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ |
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} HAL_MMC_CardInfoTypeDef; |
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/**
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* @brief MMC handle Structure definition |
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*/ |
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#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
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typedef struct __MMC_HandleTypeDef |
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#else |
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typedef struct |
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#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ |
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{ |
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MMC_TypeDef *Instance; /*!< MMC registers base address */ |
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MMC_InitTypeDef Init; /*!< MMC required parameters */ |
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HAL_LockTypeDef Lock; /*!< MMC locking object */ |
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const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ |
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uint32_t TxXferSize; /*!< MMC Tx Transfer size */ |
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uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ |
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uint32_t RxXferSize; /*!< MMC Rx Transfer size */ |
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__IO uint32_t Context; /*!< MMC transfer context */ |
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__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ |
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__IO uint32_t ErrorCode; /*!< MMC Card Error codes */ |
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__IO uint16_t RPMBErrorCode; /*!< MMC RPMB Area Error codes */ |
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HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ |
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uint32_t CSD[4U]; /*!< MMC card specific data table */ |
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uint32_t CID[4U]; /*!< MMC card identification number table */ |
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uint32_t Ext_CSD[128]; |
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#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
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void (* TxCpltCallback)(struct __MMC_HandleTypeDef *hmmc); |
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void (* RxCpltCallback)(struct __MMC_HandleTypeDef *hmmc); |
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void (* ErrorCallback)(struct __MMC_HandleTypeDef *hmmc); |
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void (* AbortCpltCallback)(struct __MMC_HandleTypeDef *hmmc); |
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void (* Read_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc); |
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void (* Read_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc); |
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void (* Write_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc); |
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void (* Write_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc); |
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void (* MspInitCallback)(struct __MMC_HandleTypeDef *hmmc); |
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void (* MspDeInitCallback)(struct __MMC_HandleTypeDef *hmmc); |
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#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ |
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} MMC_HandleTypeDef; |
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/**
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* @} |
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*/ |
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/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
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* @{ |
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*/ |
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typedef struct |
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{ |
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__IO uint8_t CSDStruct; /*!< CSD structure */ |
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__IO uint8_t SysSpecVersion; /*!< System specification version */ |
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__IO uint8_t Reserved1; /*!< Reserved */ |
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__IO uint8_t TAAC; /*!< Data read access time 1 */ |
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__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ |
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__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ |
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__IO uint16_t CardComdClasses; /*!< Card command classes */ |
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__IO uint8_t RdBlockLen; /*!< Max. read data block length */ |
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__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ |
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__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ |
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__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ |
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__IO uint8_t DSRImpl; /*!< DSR implemented */ |
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__IO uint8_t Reserved2; /*!< Reserved */ |
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__IO uint32_t DeviceSize; /*!< Device Size */ |
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__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ |
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__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ |
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__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ |
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__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ |
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__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ |
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__IO uint8_t EraseGrSize; /*!< Erase group size */ |
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__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ |
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__IO uint8_t WrProtectGrSize; /*!< Write protect group size */ |
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__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ |
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__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ |
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__IO uint8_t WrSpeedFact; /*!< Write speed factor */ |
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__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ |
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__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ |
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__IO uint8_t Reserved3; /*!< Reserved */ |
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__IO uint8_t ContentProtectAppli; /*!< Content protection application */ |
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__IO uint8_t FileFormatGroup; /*!< File format group */ |
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__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ |
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__IO uint8_t PermWrProtect; /*!< Permanent write protection */ |
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__IO uint8_t TempWrProtect; /*!< Temporary write protection */ |
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__IO uint8_t FileFormat; /*!< File format */ |
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__IO uint8_t ECC; /*!< ECC code */ |
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__IO uint8_t CSD_CRC; /*!< CSD CRC */ |
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__IO uint8_t Reserved4; /*!< Always 1 */ |
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} HAL_MMC_CardCSDTypeDef; |
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/**
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* @} |
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*/ |
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/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
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* @{ |
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*/ |
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typedef struct |
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{ |
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__IO uint8_t ManufacturerID; /*!< Manufacturer ID */ |
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__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ |
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__IO uint32_t ProdName1; /*!< Product Name part1 */ |
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__IO uint8_t ProdName2; /*!< Product Name part2 */ |
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__IO uint8_t ProdRev; /*!< Product Revision */ |
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__IO uint32_t ProdSN; /*!< Product Serial Number */ |
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__IO uint8_t Reserved1; /*!< Reserved1 */ |
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__IO uint16_t ManufactDate; /*!< Manufacturing Date */ |
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__IO uint8_t CID_CRC; /*!< CID CRC */ |
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__IO uint8_t Reserved2; /*!< Always 1 */ |
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} HAL_MMC_CardCIDTypeDef; |
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/**
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* @} |
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*/ |
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#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
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/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
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* @{ |
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*/ |
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typedef enum |
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{ |
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HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */ |
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HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */ |
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HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */ |
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HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */ |
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HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, /*!< MMC Rx DMA Double Buffer 0 Complete Callback ID */ |
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HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, /*!< MMC Rx DMA Double Buffer 1 Complete Callback ID */ |
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HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, /*!< MMC Tx DMA Double Buffer 0 Complete Callback ID */ |
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HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U, /*!< MMC Tx DMA Double Buffer 1 Complete Callback ID */ |
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HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */ |
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HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */ |
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} HAL_MMC_CallbackIDTypeDef; |
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/**
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* @} |
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*/ |
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/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
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* @{ |
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*/ |
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typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); |
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/**
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* @} |
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*/ |
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#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ |
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/**
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* @} |
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*/ |
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/* Exported constants --------------------------------------------------------*/ |
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/** @defgroup MMC_Exported_Constants Exported Constants
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* @{ |
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*/ |
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#define MMC_BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */ |
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/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
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* @{ |
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*/ |
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#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ |
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#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ |
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#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ |
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#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ |
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#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ |
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#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ |
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#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ |
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#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ |
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#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ |
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/*!< number of transferred bytes does not match the block length */ |
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#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ |
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#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ |
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#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ |
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#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ |
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/*!< command or if there was an attempt to access a locked card */ |
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#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ |
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#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ |
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#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ |
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#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ |
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#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ |
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#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ |
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#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ |
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#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ |
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#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ |
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#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ |
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#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ |
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/*!< of erase sequence command was received */ |
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#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ |
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#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ |
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#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ |
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#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ |
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#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ |
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#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ |
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#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ |
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#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ |
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#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ |
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/*!< response results after operating with RPMB partition */ |
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#define HAL_MMC_ERROR_RPMB_OPERATION_OK 0x0000U /*!< Operation OK */ |
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#define HAL_MMC_ERROR_RPMB_GENERAL_FAILURE 0x0001U /*!< General failure */ |
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#define HAL_MMC_ERROR_RPMB_AUTHENTICATION_FAILURE 0x0002U /*!< Authentication failure */ |
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#define HAL_MMC_ERROR_RPMB_COUNTER_FAILURE 0x0003U /*!< Counter failure */ |
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#define HAL_MMC_ERROR_RPMB_ADDRESS_FAILURE 0x0004U /*!< Address failure */ |
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#define HAL_MMC_ERROR_RPMB_WRITE_FAILURE 0x0005U /*!< Write failure */ |
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#define HAL_MMC_ERROR_RPMB_READ_FAILURE 0x0006U /*!< Read failure */ |
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#define HAL_MMC_ERROR_RPMB_KEY_NOT_YET_PROG 0x0007U /*!< Authentication Key not yet programmed */ |
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#define HAL_MMC_ERROR_RPMB_COUNTER_EXPIRED 0x0080U /*!< Write Counter has expired i.e. reached its max value */ |
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#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
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#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ |
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#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ |
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/**
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* @} |
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*/ |
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/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
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* @{ |
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*/ |
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#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ |
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#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ |
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#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ |
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#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ |
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#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ |
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#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ |
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#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ |
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/**
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* @} |
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*/ |
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/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
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* @{ |
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*/ |
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/**
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* @brief |
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*/ |
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#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */ |
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#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */ |
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#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */ |
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#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ |
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#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ |
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#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ |
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#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U |
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/**
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* @} |
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*/ |
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/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
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* @{ |
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*/ |
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#define MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U) /*!< MMC Card Capacity <=2Gbytes */ |
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#define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U) /*!< MMC Card Capacity >2Gbytes and <2Tbytes */ |
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/**
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* @} |
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*/ |
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/** @defgroup MMC_Exported_Constansts_Group5 MMC Erase Type
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* @{ |
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*/ |
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#define HAL_MMC_ERASE 0x00000000U /*!< Erase the erase groups identified by CMD35 & 36 */ |
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#define HAL_MMC_TRIM 0x00000001U /*!< Erase the write blocks identified by CMD35 & 36 */ |
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#define HAL_MMC_DISCARD 0x00000003U /*!< Discard the write blocks identified by CMD35 & 36 */ |
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#define HAL_MMC_SECURE_ERASE 0x80000000U /*!< Perform a secure purge according SRT on the erase groups identified by CMD35 & 36 */ |
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#define HAL_MMC_SECURE_TRIM_STEP1 0x80000001U /*!< Mark the write blocks identified by CMD35 & 36 for secure erase */ |
|||
#define HAL_MMC_SECURE_TRIM_STEP2 0x80008000U /*!< Perform a secure purge according SRT on the write blocks previously identified */ |
|||
|
|||
#define IS_MMC_ERASE_TYPE(TYPE) (((TYPE) == HAL_MMC_ERASE) || \ |
|||
((TYPE) == HAL_MMC_TRIM) || \ |
|||
((TYPE) == HAL_MMC_DISCARD) || \ |
|||
((TYPE) == HAL_MMC_SECURE_ERASE) || \ |
|||
((TYPE) == HAL_MMC_SECURE_TRIM_STEP1) || \ |
|||
((TYPE) == HAL_MMC_SECURE_TRIM_STEP2)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Constansts_Group6 MMC Secure Removal Type
|
|||
* @{ |
|||
*/ |
|||
#define HAL_MMC_SRT_ERASE 0x00000001U /*!< Information removed by an erase */ |
|||
#define HAL_MMC_SRT_WRITE_CHAR_ERASE 0x00000002U /*!< Information removed by an overwriting with a character followed by an erase */ |
|||
#define HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM 0x00000004U /*!< Information removed by an overwriting with a character, its complement then a random character */ |
|||
#define HAL_MMC_SRT_VENDOR_DEFINED 0x00000008U /*!< Information removed using a vendor defined */ |
|||
|
|||
|
|||
#define IS_MMC_SRT_TYPE(TYPE) (((TYPE) == HAL_MMC_SRT_ERASE) || \ |
|||
((TYPE) == HAL_MMC_SRT_WRITE_CHAR_ERASE) || \ |
|||
((TYPE) == HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM) || \ |
|||
((TYPE) == HAL_MMC_SRT_VENDOR_DEFINED)) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Constansts_Group7 MMC Partitions types
|
|||
* @{ |
|||
*/ |
|||
typedef uint32_t HAL_MMC_PartitionTypeDef; |
|||
|
|||
#define HAL_MMC_USER_AREA_PARTITION 0x00000000U /*!< User area partition */ |
|||
#define HAL_MMC_BOOT_PARTITION1 0x00000100U /*!< Boot partition 1 */ |
|||
#define HAL_MMC_BOOT_PARTITION2 0x00000200U /*!< Boot partition 2 */ |
|||
#define HAL_MMC_RPMB_PARTITION 0x00000300U /*!< RPMB partition */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup MMC_Exported_macros MMC Exported Macros
|
|||
* @brief macros to handle interrupts and specific clock configurations |
|||
* @{ |
|||
*/ |
|||
/** @brief Reset MMC handle state.
|
|||
* @param __HANDLE__ MMC Handle. |
|||
* @retval None |
|||
*/ |
|||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
|||
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_MMC_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET) |
|||
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @brief Enable the MMC device interrupt. |
|||
* @param __HANDLE__ MMC Handle. |
|||
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt |
|||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt |
|||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt |
|||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt |
|||
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt |
|||
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt |
|||
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt |
|||
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt |
|||
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the MMC device interrupt. |
|||
* @param __HANDLE__ MMC Handle. |
|||
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt |
|||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt |
|||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt |
|||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt |
|||
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt |
|||
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt |
|||
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt |
|||
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt |
|||
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified MMC flag is set or not. |
|||
* @param __HANDLE__ MMC Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) |
|||
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
|||
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout |
|||
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout |
|||
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error |
|||
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error |
|||
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) |
|||
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) |
|||
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) |
|||
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold |
|||
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
|||
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 |
|||
* @arg SDMMC_FLAG_DPSMACT: Data path state machine active |
|||
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active |
|||
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
|||
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full |
|||
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full |
|||
* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full |
|||
* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty |
|||
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty |
|||
* @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) |
|||
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected |
|||
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received |
|||
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received |
|||
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout |
|||
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion |
|||
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure |
|||
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error |
|||
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete |
|||
* @retval The new state of MMC FLAG (SET or RESET). |
|||
*/ |
|||
#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Clear the MMC's pending flags. |
|||
* @param __HANDLE__ MMC Handle. |
|||
* @param __FLAG__ specifies the flag to clear. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) |
|||
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
|||
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout |
|||
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout |
|||
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error |
|||
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error |
|||
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) |
|||
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) |
|||
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) |
|||
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold |
|||
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
|||
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 |
|||
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected |
|||
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received |
|||
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received |
|||
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout |
|||
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion |
|||
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure |
|||
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error |
|||
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified MMC interrupt has occurred or not. |
|||
* @param __HANDLE__ MMC Handle. |
|||
* @param __INTERRUPT__ specifies the SDMMC interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt |
|||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt |
|||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt |
|||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt |
|||
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt |
|||
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt |
|||
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt |
|||
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt |
|||
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt |
|||
* @retval The new state of MMC IT (SET or RESET). |
|||
*/ |
|||
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Clear the MMC's interrupt pending bits. |
|||
* @param __HANDLE__ MMC Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt |
|||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt |
|||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt |
|||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt |
|||
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt |
|||
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt |
|||
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt |
|||
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt |
|||
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include MMC HAL Extension module */ |
|||
#include "stm32h7xx_hal_mmc_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup MMC_Exported_Functions MMC Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); |
|||
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); |
|||
HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
|
|||
* @{ |
|||
*/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); |
|||
/* Non-Blocking mode: IT */ |
|||
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks); |
|||
/* Non-Blocking mode: DMA */ |
|||
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks); |
|||
|
|||
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); |
|||
|
|||
/* Callback in non blocking modes (DMA) */ |
|||
void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); |
|||
|
|||
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) |
|||
/* MMC callback registering/unregistering */ |
|||
HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, |
|||
pMMC_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId); |
|||
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); |
|||
HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode); |
|||
HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
|
|||
* @{ |
|||
*/ |
|||
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); |
|||
HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); |
|||
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); |
|||
HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); |
|||
HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
|
|||
* @{ |
|||
*/ |
|||
HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc); |
|||
uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc); |
|||
uint32_t HAL_MMC_GetRPMBError(const MMC_HandleTypeDef *hmmc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); |
|||
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group7 Peripheral Erase management
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, |
|||
uint32_t BlockEndAdd); |
|||
HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc); |
|||
HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode); |
|||
HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group8 Peripheral Sleep management
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc); |
|||
HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup MMC_Exported_Functions_Group9 Replay Protected Memory Block management
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, |
|||
uint32_t Timeout); |
|||
uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout); |
|||
uint32_t HAL_MMC_RPMB_GetWriteCounter_IT(MMC_HandleTypeDef *hmmc, uint8_t *pNonce); |
|||
HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, |
|||
uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, |
|||
uint16_t NumberOfBlocks, const uint8_t *pMAC); |
|||
HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, |
|||
uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, |
|||
uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Types MMC Private Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private defines -----------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Defines MMC Private Defines
|
|||
* @{ |
|||
*/ |
|||
#define MMC_EXT_CSD_DATA_SEC_SIZE_INDEX 61 |
|||
#define MMC_EXT_CSD_DATA_SEC_SIZE_POS 8 |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Variables MMC Private Variables
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Constants MMC Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Macros MMC Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions prototypes ----------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup MMC_Private_Functions MMC Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* SDMMC1 || SDMMC2 */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* STM32H7xx_HAL_MMC_H */ |
|||
@ -0,0 +1,113 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32h7xx_hal_mmc_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SD HAL extended module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32H7xx_HAL_MMC_EX_H |
|||
#define STM32H7xx_HAL_MMC_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32h7xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32H7xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
#if defined (SDMMC1) || defined (SDMMC2) |
|||
/** @addtogroup MMCEx
|
|||
* @brief SD HAL extended module driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup MMCEx_Exported_Types MMCEx Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup MMCEx_Exported_Types_Group1 MMC Internal DMA Buffer structure
|
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
MMC_DMA_BUFFER0 = 0x00U, /*!< selects MMC internal DMA Buffer 0 */ |
|||
MMC_DMA_BUFFER1 = 0x01U, /*!< selects MMC internal DMA Buffer 1 */ |
|||
|
|||
} HAL_MMCEx_DMABuffer_MemoryTypeDef; |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, |
|||
uint32_t *pDataBuffer1, uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, |
|||
uint32_t *pDataBuffer); |
|||
|
|||
void HAL_MMCEx_Read_DMADoubleBuf0CpltCallback(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMCEx_Read_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMCEx_Write_DMADoubleBuf0CpltCallback(MMC_HandleTypeDef *hmmc); |
|||
void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private defines -----------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/* Private functions prototypes ----------------------------------------------*/ |
|||
/* Private functions ---------------------------------------------------------*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* SDMMC1 || SDMMC2 */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* STM32H7xx_HAL_MMCEx_H */ |
|||
@ -0,0 +1,802 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32h7xx_hal_sd.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SD HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32H7xx_HAL_SD_H |
|||
#define STM32H7xx_HAL_SD_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32h7xx_ll_sdmmc.h" |
|||
#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_SDMMC3) |
|||
#include "stm32h7xx_ll_delayblock.h" |
|||
#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */ |
|||
|
|||
/** @addtogroup STM32H7xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
#if defined (SDMMC1) || defined (SDMMC2) |
|||
|
|||
/** @defgroup SD SD
|
|||
* @brief SD HAL module driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup SD_Exported_Types SD Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
|
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */ |
|||
HAL_SD_STATE_READY = ((uint32_t)0x00000001U), /*!< SD initialized and ready for use */ |
|||
HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< SD Timeout state */ |
|||
HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */ |
|||
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */ |
|||
HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receiving State */ |
|||
HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfer State */ |
|||
HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */ |
|||
} HAL_SD_StateTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
|
|||
* @{ |
|||
*/ |
|||
typedef uint32_t HAL_SD_CardStateTypeDef; |
|||
|
|||
#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */ |
|||
#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ |
|||
#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ |
|||
#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ |
|||
#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ |
|||
#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ |
|||
#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ |
|||
#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ |
|||
#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
|
|||
* @{ |
|||
*/ |
|||
#define SD_InitTypeDef SDMMC_InitTypeDef |
|||
#define SD_TypeDef SDMMC_TypeDef |
|||
|
|||
/**
|
|||
* @brief SD Card Information Structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t CardType; /*!< Specifies the card Type */ |
|||
|
|||
uint32_t CardVersion; /*!< Specifies the card version */ |
|||
|
|||
uint32_t Class; /*!< Specifies the class of the card class */ |
|||
|
|||
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ |
|||
|
|||
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ |
|||
|
|||
uint32_t BlockSize; /*!< Specifies one block size in bytes */ |
|||
|
|||
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ |
|||
|
|||
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ |
|||
|
|||
uint32_t CardSpeed; /*!< Specifies the card Speed */ |
|||
|
|||
} HAL_SD_CardInfoTypeDef; |
|||
|
|||
/**
|
|||
* @brief SD handle Structure definition |
|||
*/ |
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
typedef struct __SD_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
{ |
|||
SD_TypeDef *Instance; /*!< SD registers base address */ |
|||
|
|||
SD_InitTypeDef Init; /*!< SD required parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< SD locking object */ |
|||
|
|||
const uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ |
|||
|
|||
uint32_t TxXferSize; /*!< SD Tx Transfer size */ |
|||
|
|||
uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ |
|||
|
|||
uint32_t RxXferSize; /*!< SD Rx Transfer size */ |
|||
|
|||
__IO uint32_t Context; /*!< SD transfer context */ |
|||
|
|||
__IO HAL_SD_StateTypeDef State; /*!< SD card State */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< SD Card Error codes */ |
|||
|
|||
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ |
|||
|
|||
uint32_t CSD[4]; /*!< SD card specific data table */ |
|||
|
|||
uint32_t CID[4]; /*!< SD card identification number table */ |
|||
|
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
void (* TxCpltCallback)(struct __SD_HandleTypeDef *hsd); |
|||
void (* RxCpltCallback)(struct __SD_HandleTypeDef *hsd); |
|||
void (* ErrorCallback)(struct __SD_HandleTypeDef *hsd); |
|||
void (* AbortCpltCallback)(struct __SD_HandleTypeDef *hsd); |
|||
void (* Read_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd); |
|||
void (* Read_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd); |
|||
void (* Write_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd); |
|||
void (* Write_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd); |
|||
#if (USE_SD_TRANSCEIVER != 0U) |
|||
void (* DriveTransceiver_1_8V_Callback)(FlagStatus status); |
|||
#endif /* USE_SD_TRANSCEIVER */ |
|||
|
|||
void (* MspInitCallback)(struct __SD_HandleTypeDef *hsd); |
|||
void (* MspDeInitCallback)(struct __SD_HandleTypeDef *hsd); |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
} SD_HandleTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
|
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
__IO uint8_t CSDStruct; /*!< CSD structure */ |
|||
__IO uint8_t SysSpecVersion; /*!< System specification version */ |
|||
__IO uint8_t Reserved1; /*!< Reserved */ |
|||
__IO uint8_t TAAC; /*!< Data read access time 1 */ |
|||
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ |
|||
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ |
|||
__IO uint16_t CardComdClasses; /*!< Card command classes */ |
|||
__IO uint8_t RdBlockLen; /*!< Max. read data block length */ |
|||
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ |
|||
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ |
|||
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ |
|||
__IO uint8_t DSRImpl; /*!< DSR implemented */ |
|||
__IO uint8_t Reserved2; /*!< Reserved */ |
|||
__IO uint32_t DeviceSize; /*!< Device Size */ |
|||
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ |
|||
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ |
|||
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ |
|||
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ |
|||
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ |
|||
__IO uint8_t EraseGrSize; /*!< Erase group size */ |
|||
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ |
|||
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */ |
|||
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ |
|||
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ |
|||
__IO uint8_t WrSpeedFact; /*!< Write speed factor */ |
|||
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ |
|||
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ |
|||
__IO uint8_t Reserved3; /*!< Reserved */ |
|||
__IO uint8_t ContentProtectAppli; /*!< Content protection application */ |
|||
__IO uint8_t FileFormatGroup; /*!< File format group */ |
|||
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ |
|||
__IO uint8_t PermWrProtect; /*!< Permanent write protection */ |
|||
__IO uint8_t TempWrProtect; /*!< Temporary write protection */ |
|||
__IO uint8_t FileFormat; /*!< File format */ |
|||
__IO uint8_t ECC; /*!< ECC code */ |
|||
__IO uint8_t CSD_CRC; /*!< CSD CRC */ |
|||
__IO uint8_t Reserved4; /*!< Always 1 */ |
|||
} HAL_SD_CardCSDTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
|
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */ |
|||
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ |
|||
__IO uint32_t ProdName1; /*!< Product Name part1 */ |
|||
__IO uint8_t ProdName2; /*!< Product Name part2 */ |
|||
__IO uint8_t ProdRev; /*!< Product Revision */ |
|||
__IO uint32_t ProdSN; /*!< Product Serial Number */ |
|||
__IO uint8_t Reserved1; /*!< Reserved1 */ |
|||
__IO uint16_t ManufactDate; /*!< Manufacturing Date */ |
|||
__IO uint8_t CID_CRC; /*!< CID CRC */ |
|||
__IO uint8_t Reserved2; /*!< Always 1 */ |
|||
|
|||
} HAL_SD_CardCIDTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
|
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
__IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */ |
|||
__IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */ |
|||
__IO uint16_t CardType; /*!< Carries information about card type */ |
|||
__IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */ |
|||
__IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */ |
|||
__IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */ |
|||
__IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */ |
|||
__IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */ |
|||
__IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */ |
|||
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */ |
|||
__IO uint8_t UhsSpeedGrade; /*!< Carries information about the speed grade of UHS card */ |
|||
__IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */ |
|||
__IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */ |
|||
} HAL_SD_CardStatusTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
|
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */ |
|||
HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */ |
|||
HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */ |
|||
HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */ |
|||
HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, /*!< SD Rx DMA Double Buffer 0 Complete Callback ID */ |
|||
HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, /*!< SD Rx DMA Double Buffer 1 Complete Callback ID */ |
|||
HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, /*!< SD Tx DMA Double Buffer 0 Complete Callback ID */ |
|||
HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U, /*!< SD Tx DMA Double Buffer 1 Complete Callback ID */ |
|||
|
|||
HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */ |
|||
HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */ |
|||
} HAL_SD_CallbackIDTypeDef; |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
|
|||
* @{ |
|||
*/ |
|||
typedef void (*pSD_CallbackTypeDef)(SD_HandleTypeDef *hsd); |
|||
#if (USE_SD_TRANSCEIVER != 0U) |
|||
typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); |
|||
#endif /* USE_SD_TRANSCEIVER */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup SD_Exported_Constants SD Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */ |
|||
|
|||
/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
|
|||
* @{ |
|||
*/ |
|||
#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ |
|||
#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ |
|||
#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ |
|||
#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ |
|||
#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ |
|||
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ |
|||
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ |
|||
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ |
|||
#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ |
|||
/*!< number of transferred bytes does not match the block length */ |
|||
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ |
|||
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ |
|||
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ |
|||
#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ |
|||
/*!< command or if there was an attempt to access a locked card */ |
|||
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ |
|||
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ |
|||
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ |
|||
#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ |
|||
#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ |
|||
#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ |
|||
#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ |
|||
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ |
|||
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ |
|||
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ |
|||
#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ |
|||
/*!< of erase sequence command was received */ |
|||
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ |
|||
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ |
|||
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ |
|||
#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ |
|||
#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ |
|||
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ |
|||
#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ |
|||
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ |
|||
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ |
|||
|
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
|
|||
* @{ |
|||
*/ |
|||
#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ |
|||
#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ |
|||
#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ |
|||
#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ |
|||
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ |
|||
#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ |
|||
#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
|
|||
* @{ |
|||
*/ |
|||
#define CARD_NORMAL_SPEED ((uint32_t)0x00000000U) /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01 */ |
|||
#define CARD_HIGH_SPEED ((uint32_t)0x00000100U) /*!< High Speed Card <25Mo/s , Spec version 2.00 */ |
|||
#define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U) /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards |
|||
and <104Mo/s for SDR104, Spec version 3.01 */ |
|||
|
|||
#define CARD_SDSC ((uint32_t)0x00000000U) /*!< SD Standard Capacity <2Go */ |
|||
#define CARD_SDHC_SDXC ((uint32_t)0x00000001U) /*!< SD High Capacity <32Go, SD Extended Capacity <2To */ |
|||
#define CARD_SECURED ((uint32_t)0x00000003U) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
|
|||
* @{ |
|||
*/ |
|||
#define CARD_V1_X ((uint32_t)0x00000000U) |
|||
#define CARD_V2_X ((uint32_t)0x00000001U) |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup SD_Exported_macros SD Exported Macros
|
|||
* @brief macros to handle interrupts and specific clock configurations |
|||
* @{ |
|||
*/ |
|||
/** @brief Reset SD handle state.
|
|||
* @param __HANDLE__ SD Handle. |
|||
* @retval None |
|||
*/ |
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \ |
|||
(__HANDLE__)->State = HAL_SD_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET) |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @brief Enable the SD device interrupt. |
|||
* @param __HANDLE__ SD Handle. |
|||
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt |
|||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt |
|||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt |
|||
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt |
|||
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt |
|||
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt |
|||
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt |
|||
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt |
|||
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Disable the SD device interrupt. |
|||
* @param __HANDLE__ SD Handle. |
|||
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt |
|||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt |
|||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt |
|||
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt |
|||
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt |
|||
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt |
|||
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt |
|||
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt |
|||
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified SD flag is set or not. |
|||
* @param __HANDLE__ SD Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) |
|||
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
|||
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout |
|||
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout |
|||
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error |
|||
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error |
|||
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) |
|||
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) |
|||
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) |
|||
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold |
|||
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
|||
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 |
|||
* @arg SDMMC_FLAG_DPSMACT: Data path state machine active |
|||
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active |
|||
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
|||
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full |
|||
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full |
|||
* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full |
|||
* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty |
|||
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty |
|||
* @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) |
|||
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected |
|||
* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received |
|||
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received |
|||
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout |
|||
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion |
|||
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure |
|||
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error |
|||
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete |
|||
* @retval The new state of SD FLAG (SET or RESET). |
|||
*/ |
|||
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Clear the SD's pending flags. |
|||
* @param __HANDLE__ SD Handle. |
|||
* @param __FLAG__ specifies the flag to clear. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) |
|||
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
|||
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout |
|||
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout |
|||
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error |
|||
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error |
|||
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) |
|||
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) |
|||
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) |
|||
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold |
|||
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
|||
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 |
|||
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected |
|||
* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received |
|||
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received |
|||
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout |
|||
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion |
|||
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure |
|||
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error |
|||
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) |
|||
|
|||
/**
|
|||
* @brief Check whether the specified SD interrupt has occurred or not. |
|||
* @param __HANDLE__ SD Handle. |
|||
* @param __INTERRUPT__ specifies the SDMMC interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt |
|||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt |
|||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt |
|||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt |
|||
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt |
|||
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt |
|||
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt |
|||
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt |
|||
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt |
|||
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt |
|||
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt |
|||
* @retval The new state of SD IT (SET or RESET). |
|||
*/ |
|||
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @brief Clear the SD's interrupt pending bits. |
|||
* @param __HANDLE__ SD Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
|||
* This parameter can be one or a combination of the following values: |
|||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt |
|||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt |
|||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt |
|||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt |
|||
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
|||
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt |
|||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|||
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt |
|||
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt |
|||
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt |
|||
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt |
|||
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt |
|||
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt |
|||
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt |
|||
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Include SD HAL Extension module */ |
|||
#include "stm32h7xx_hal_sd_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup SD_Exported_Functions SD Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd); |
|||
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd); |
|||
HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd); |
|||
void HAL_SD_MspInit(SD_HandleTypeDef *hsd); |
|||
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
|
|||
* @{ |
|||
*/ |
|||
/* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); |
|||
/* Non-Blocking mode: IT */ |
|||
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks); |
|||
/* Non-Blocking mode: DMA */ |
|||
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks); |
|||
|
|||
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); |
|||
|
|||
/* Callback in non blocking modes (DMA) */ |
|||
void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd); |
|||
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); |
|||
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); |
|||
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); |
|||
|
|||
#if (USE_SD_TRANSCEIVER != 0U) |
|||
/* Callback to switch in 1.8V mode */ |
|||
void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status); |
|||
#endif /* USE_SD_TRANSCEIVER */ |
|||
|
|||
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) |
|||
/* SD callback registering/unregistering */ |
|||
HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, |
|||
pSD_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID); |
|||
|
|||
#if (USE_SD_TRANSCEIVER != 0U) |
|||
HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd); |
|||
#endif /* USE_SD_TRANSCEIVER */ |
|||
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode); |
|||
HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group4 SD card related functions
|
|||
* @{ |
|||
*/ |
|||
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); |
|||
HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); |
|||
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); |
|||
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); |
|||
HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
|
|||
* @{ |
|||
*/ |
|||
HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd); |
|||
uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd); |
|||
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Types SD Private Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private defines -----------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Defines SD Private Defines
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Variables SD Private Variables
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Constants SD Private Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Macros SD Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions prototypes ----------------------------------------------*/ |
|||
/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup SD_Private_Functions SD Private Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* SDMMC1 || SDMMC2 */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* STM32H7xx_HAL_SD_H */ |
|||
@ -0,0 +1,112 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32h7xx_hal_sd_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of SD HAL extended module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32H7xx_HAL_SD_EX_H |
|||
#define STM32H7xx_HAL_SD_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32h7xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32H7xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
#if defined (SDMMC1) || defined (SDMMC2) |
|||
|
|||
/** @addtogroup SDEx
|
|||
* @brief SD HAL extended module driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup SDEx_Exported_Types SDEx Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
|
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */ |
|||
SD_DMA_BUFFER1 = 0x01U, /*!< selects SD internal DMA Buffer 1 */ |
|||
|
|||
} HAL_SDEx_DMABuffer_MemoryTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup SDEx_Exported_Functions SDEx Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SDEx_Exported_Functions_Group1 MultiBuffer functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, |
|||
uint32_t BufferSize); |
|||
HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks); |
|||
HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, |
|||
uint32_t *pDataBuffer); |
|||
|
|||
void HAL_SDEx_Read_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd); |
|||
void HAL_SDEx_Read_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd); |
|||
void HAL_SDEx_Write_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd); |
|||
void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private defines -----------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/* Private functions prototypes ----------------------------------------------*/ |
|||
/* Private functions ---------------------------------------------------------*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#endif /* SDMMC1 || SDMMC2 */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* stm32h7xx_HAL_SD_EX_H */ |
|||
File diff suppressed because it is too large
@ -0,0 +1,870 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32h7xx_hal_uart_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of UART HAL Extended module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32H7xx_HAL_UART_EX_H |
|||
#define STM32H7xx_HAL_UART_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32h7xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32H7xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup UARTEx
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief UART wake up from stop mode parameters |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
|
|||
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. |
|||
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must |
|||
be filled up. */ |
|||
|
|||
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
|
|||
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ |
|||
|
|||
uint8_t Address; /*!< UART/USART node address (7-bit long max). */ |
|||
} UART_WakeUpTypeDef; |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup UARTEx_Word_Length UARTEx Word Length
|
|||
* @{ |
|||
*/ |
|||
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ |
|||
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ |
|||
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
|
|||
* @{ |
|||
*/ |
|||
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ |
|||
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
|
|||
* @brief UART FIFO mode |
|||
* @{ |
|||
*/ |
|||
#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ |
|||
#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
|
|||
* @brief UART TXFIFO threshold level |
|||
* @{ |
|||
*/ |
|||
#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ |
|||
#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ |
|||
#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ |
|||
#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ |
|||
#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ |
|||
#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
|
|||
* @brief UART RXFIFO threshold level |
|||
* @{ |
|||
*/ |
|||
#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ |
|||
#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ |
|||
#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ |
|||
#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ |
|||
#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ |
|||
#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup UARTEx_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup UARTEx_Exported_Functions_Group1
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Initialization and de-initialization functions ****************************/ |
|||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, |
|||
uint32_t DeassertionTime); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup UARTEx_Exported_Functions_Group2
|
|||
* @{ |
|||
*/ |
|||
|
|||
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); |
|||
|
|||
void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); |
|||
void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup UARTEx_Exported_Functions_Group3
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Peripheral Control functions **********************************************/ |
|||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); |
|||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); |
|||
|
|||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); |
|||
|
|||
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); |
|||
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); |
|||
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); |
|||
|
|||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, |
|||
uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
|||
|
|||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Report the UART clock source.
|
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* @param __CLOCKSOURCE__ output variable. |
|||
* @retval UART clocking source, written in __CLOCKSOURCE__. |
|||
*/ |
|||
#if defined(UART9) && defined(USART10) |
|||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ |
|||
do { \ |
|||
if((__HANDLE__)->Instance == USART1) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_USART1_SOURCE()) \ |
|||
{ \ |
|||
case RCC_USART1CLKSOURCE_D2PCLK2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \ |
|||
break; \ |
|||
case RCC_USART1CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_USART1CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_USART1CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_USART1CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_USART1CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == USART2) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_USART2_SOURCE()) \ |
|||
{ \ |
|||
case RCC_USART2CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_USART2CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_USART2CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_USART2CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_USART2CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_USART2CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == USART3) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_USART3_SOURCE()) \ |
|||
{ \ |
|||
case RCC_USART3CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_USART3CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_USART3CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_USART3CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_USART3CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_USART3CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == UART4) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_UART4_SOURCE()) \ |
|||
{ \ |
|||
case RCC_UART4CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_UART4CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_UART4CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_UART4CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_UART4CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_UART4CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if ((__HANDLE__)->Instance == UART5) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_UART5_SOURCE()) \ |
|||
{ \ |
|||
case RCC_UART5CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_UART5CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_UART5CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_UART5CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_UART5CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_UART5CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == USART6) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_USART6_SOURCE()) \ |
|||
{ \ |
|||
case RCC_USART6CLKSOURCE_D2PCLK2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \ |
|||
break; \ |
|||
case RCC_USART6CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_USART6CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_USART6CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_USART6CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_USART6CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == UART7) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_UART7_SOURCE()) \ |
|||
{ \ |
|||
case RCC_UART7CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_UART7CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_UART7CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_UART7CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_UART7CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_UART7CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == UART8) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_UART8_SOURCE()) \ |
|||
{ \ |
|||
case RCC_UART8CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_UART8CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_UART8CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_UART8CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_UART8CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_UART8CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == UART9) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_UART9_SOURCE()) \ |
|||
{ \ |
|||
case RCC_UART9CLKSOURCE_D2PCLK2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \ |
|||
break; \ |
|||
case RCC_UART9CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_UART9CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_UART9CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_UART9CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_UART9CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == USART10) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_USART10_SOURCE()) \ |
|||
{ \ |
|||
case RCC_USART10CLKSOURCE_D2PCLK2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \ |
|||
break; \ |
|||
case RCC_USART10CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_USART10CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_USART10CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_USART10CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_USART10CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == LPUART1) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ |
|||
{ \ |
|||
case RCC_LPUART1CLKSOURCE_D3PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1; \ |
|||
break; \ |
|||
case RCC_LPUART1CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_LPUART1CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_LPUART1CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_LPUART1CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_LPUART1CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else \ |
|||
{ \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
} \ |
|||
} while(0U) |
|||
#else |
|||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ |
|||
do { \ |
|||
if((__HANDLE__)->Instance == USART1) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_USART1_SOURCE()) \ |
|||
{ \ |
|||
case RCC_USART1CLKSOURCE_D2PCLK2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \ |
|||
break; \ |
|||
case RCC_USART1CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_USART1CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_USART1CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_USART1CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_USART1CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == USART2) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_USART2_SOURCE()) \ |
|||
{ \ |
|||
case RCC_USART2CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_USART2CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_USART2CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_USART2CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_USART2CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_USART2CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == USART3) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_USART3_SOURCE()) \ |
|||
{ \ |
|||
case RCC_USART3CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_USART3CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_USART3CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_USART3CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_USART3CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_USART3CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == UART4) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_UART4_SOURCE()) \ |
|||
{ \ |
|||
case RCC_UART4CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_UART4CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_UART4CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_UART4CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_UART4CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_UART4CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if ((__HANDLE__)->Instance == UART5) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_UART5_SOURCE()) \ |
|||
{ \ |
|||
case RCC_UART5CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_UART5CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_UART5CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_UART5CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_UART5CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_UART5CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == USART6) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_USART6_SOURCE()) \ |
|||
{ \ |
|||
case RCC_USART6CLKSOURCE_D2PCLK2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \ |
|||
break; \ |
|||
case RCC_USART6CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_USART6CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_USART6CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_USART6CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_USART6CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == UART7) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_UART7_SOURCE()) \ |
|||
{ \ |
|||
case RCC_UART7CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_UART7CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_UART7CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_UART7CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_UART7CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_UART7CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == UART8) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_UART8_SOURCE()) \ |
|||
{ \ |
|||
case RCC_UART8CLKSOURCE_D2PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ |
|||
break; \ |
|||
case RCC_UART8CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_UART8CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_UART8CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_UART8CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_UART8CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else if((__HANDLE__)->Instance == LPUART1) \ |
|||
{ \ |
|||
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ |
|||
{ \ |
|||
case RCC_LPUART1CLKSOURCE_D3PCLK1: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1; \ |
|||
break; \ |
|||
case RCC_LPUART1CLKSOURCE_PLL2: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ |
|||
break; \ |
|||
case RCC_LPUART1CLKSOURCE_PLL3: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ |
|||
break; \ |
|||
case RCC_LPUART1CLKSOURCE_HSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ |
|||
break; \ |
|||
case RCC_LPUART1CLKSOURCE_CSI: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ |
|||
break; \ |
|||
case RCC_LPUART1CLKSOURCE_LSE: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ |
|||
break; \ |
|||
default: \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
break; \ |
|||
} \ |
|||
} \ |
|||
else \ |
|||
{ \ |
|||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ |
|||
} \ |
|||
} while(0U) |
|||
#endif /* UART9 && USART10 */ |
|||
|
|||
/** @brief Report the UART mask to apply to retrieve the received data
|
|||
* according to the word length and to the parity bits activation. |
|||
* @note If PCE = 1, the parity bit is not included in the data extracted |
|||
* by the reception API(). |
|||
* This masking operation is not carried out in the case of |
|||
* DMA transfers. |
|||
* @param __HANDLE__ specifies the UART Handle. |
|||
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. |
|||
*/ |
|||
#define UART_MASK_COMPUTATION(__HANDLE__) \ |
|||
do { \ |
|||
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ |
|||
{ \ |
|||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ |
|||
{ \ |
|||
(__HANDLE__)->Mask = 0x01FFU ; \ |
|||
} \ |
|||
else \ |
|||
{ \ |
|||
(__HANDLE__)->Mask = 0x00FFU ; \ |
|||
} \ |
|||
} \ |
|||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ |
|||
{ \ |
|||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ |
|||
{ \ |
|||
(__HANDLE__)->Mask = 0x00FFU ; \ |
|||
} \ |
|||
else \ |
|||
{ \ |
|||
(__HANDLE__)->Mask = 0x007FU ; \ |
|||
} \ |
|||
} \ |
|||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ |
|||
{ \ |
|||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ |
|||
{ \ |
|||
(__HANDLE__)->Mask = 0x007FU ; \ |
|||
} \ |
|||
else \ |
|||
{ \ |
|||
(__HANDLE__)->Mask = 0x003FU ; \ |
|||
} \ |
|||
} \ |
|||
else \ |
|||
{ \ |
|||
(__HANDLE__)->Mask = 0x0000U; \ |
|||
} \ |
|||
} while(0U) |
|||
|
|||
/**
|
|||
* @brief Ensure that UART frame length is valid. |
|||
* @param __LENGTH__ UART frame length. |
|||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) |
|||
*/ |
|||
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ |
|||
((__LENGTH__) == UART_WORDLENGTH_8B) || \ |
|||
((__LENGTH__) == UART_WORDLENGTH_9B)) |
|||
|
|||
/**
|
|||
* @brief Ensure that UART wake-up address length is valid. |
|||
* @param __ADDRESS__ UART wake-up address length. |
|||
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) |
|||
*/ |
|||
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ |
|||
((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) |
|||
|
|||
/**
|
|||
* @brief Ensure that UART TXFIFO threshold level is valid. |
|||
* @param __THRESHOLD__ UART TXFIFO threshold level. |
|||
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) |
|||
*/ |
|||
#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ |
|||
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ |
|||
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ |
|||
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ |
|||
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ |
|||
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) |
|||
|
|||
/**
|
|||
* @brief Ensure that UART RXFIFO threshold level is valid. |
|||
* @param __THRESHOLD__ UART RXFIFO threshold level. |
|||
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) |
|||
*/ |
|||
#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ |
|||
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ |
|||
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ |
|||
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ |
|||
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ |
|||
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32H7xx_HAL_UART_EX_H */ |
|||
|
|||
@ -0,0 +1,93 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32h7xx_ll_delayblock.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of Delay Block module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef STM32H7xx_LL_DLYB_H |
|||
#define STM32H7xx_LL_DLYB_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32h7xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32H7xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup DELAYBLOCK_LL
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup DELAYBLOCK_LL_Exported_Types DELAYBLOCK_LL Exported Types
|
|||
* @{ |
|||
*/ |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup DLYB_Exported_Constants Delay Block Exported Constants
|
|||
* @{ |
|||
*/ |
|||
|
|||
|
|||
#define DLYB_MAX_UNIT ((uint32_t)0x00000080U) /*!< Max UNIT value (128) */ |
|||
#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup DelayBlock_LL_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/* Peripheral Control functions ************************************************/ |
|||
/** @addtogroup HAL_DELAY_LL_Group1
|
|||
* @{ |
|||
*/ |
|||
HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *DLYBx); |
|||
HAL_StatusTypeDef DelayBlock_Disable(DLYB_TypeDef *DLYBx); |
|||
HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx, uint32_t PhaseSel, uint32_t Units); |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* STM32H7xx_LL_DLYB_H */ |
|||
|
|||
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
@ -0,0 +1,353 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32h7xx_hal_mmc_ex.c |
|||
* @author MCD Application Team |
|||
* @brief MMC card Extended HAL module driver. |
|||
* This file provides firmware functions to manage the following |
|||
* functionalities of the Secure Digital (MMC) peripheral: |
|||
* + Extended features functions |
|||
* |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
@verbatim |
|||
============================================================================== |
|||
##### How to use this driver ##### |
|||
============================================================================== |
|||
[..] |
|||
The MMC Extension HAL driver can be used as follows: |
|||
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function. |
|||
|
|||
(+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and |
|||
HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions. |
|||
|
|||
@endverbatim |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32h7xx_hal.h" |
|||
|
|||
/** @addtogroup STM32H7xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup MMCEx MMCEx
|
|||
* @brief MMC Extended HAL module driver |
|||
* @{ |
|||
*/ |
|||
|
|||
#if defined (SDMMC1) || defined (SDMMC2) |
|||
#ifdef HAL_MMC_MODULE_ENABLED |
|||
|
|||
/* Private typedef -----------------------------------------------------------*/ |
|||
/* Private define ------------------------------------------------------------*/ |
|||
/* Private macro -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private function prototypes -----------------------------------------------*/ |
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup MMCEx_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
|
|||
/** @addtogroup MMCEx_Exported_Functions_Group1
|
|||
* @brief Multibuffer functions |
|||
* |
|||
@verbatim |
|||
============================================================================== |
|||
##### Multibuffer functions ##### |
|||
============================================================================== |
|||
[..] |
|||
This section provides functions allowing to configure the multibuffer mode and start read and write |
|||
multibuffer mode for MMC HAL driver. |
|||
|
|||
@endverbatim |
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA. |
|||
* @param hmmc: MMC handle |
|||
* @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transferred data |
|||
* @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transferred data |
|||
* @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size. |
|||
* @retval HAL status |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, |
|||
uint32_t *pDataBuffer1, uint32_t BufferSize) |
|||
{ |
|||
if (hmmc->State == HAL_MMC_STATE_READY) |
|||
{ |
|||
hmmc->Instance->IDMABASE0 = (uint32_t) pDataBuffer0 ; |
|||
hmmc->Instance->IDMABASE1 = (uint32_t) pDataBuffer1 ; |
|||
hmmc->Instance->IDMABSIZE = (uint32_t)(MMC_BLOCKSIZE * BufferSize); |
|||
|
|||
return HAL_OK; |
|||
} |
|||
else |
|||
{ |
|||
return HAL_BUSY; |
|||
} |
|||
} |
|||
|
|||
/**
|
|||
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1. |
|||
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before |
|||
* call this function. |
|||
* @param hmmc: MMC handle |
|||
* @param BlockAdd: Block Address from where data is to be read |
|||
* @param NumberOfBlocks: Total number of blocks to read |
|||
* @retval HAL status |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks) |
|||
{ |
|||
SDMMC_DataInitTypeDef config; |
|||
uint32_t DmaBase0_reg; |
|||
uint32_t DmaBase1_reg; |
|||
uint32_t errorstate; |
|||
uint32_t add = BlockAdd; |
|||
|
|||
if (hmmc->State == HAL_MMC_STATE_READY) |
|||
{ |
|||
if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) |
|||
{ |
|||
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ |
|||
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) |
|||
{ |
|||
if ((NumberOfBlocks % 8U) != 0U) |
|||
{ |
|||
/* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ |
|||
hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
if ((BlockAdd % 8U) != 0U) |
|||
{ |
|||
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ |
|||
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; |
|||
return HAL_ERROR; |
|||
} |
|||
} |
|||
|
|||
DmaBase0_reg = hmmc->Instance->IDMABASE0; |
|||
DmaBase1_reg = hmmc->Instance->IDMABASE1; |
|||
|
|||
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) |
|||
{ |
|||
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
/* Initialize data control register */ |
|||
hmmc->Instance->DCTRL = 0; |
|||
|
|||
hmmc->ErrorCode = HAL_MMC_ERROR_NONE; |
|||
hmmc->State = HAL_MMC_STATE_BUSY; |
|||
|
|||
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) |
|||
{ |
|||
add *= 512U; |
|||
} |
|||
|
|||
/* Configure the MMC DPSM (Data Path State Machine) */ |
|||
config.DataTimeOut = SDMMC_DATATIMEOUT; |
|||
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; |
|||
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; |
|||
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; |
|||
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; |
|||
config.DPSM = SDMMC_DPSM_DISABLE; |
|||
(void)SDMMC_ConfigData(hmmc->Instance, &config); |
|||
|
|||
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; |
|||
|
|||
__SDMMC_CMDTRANS_ENABLE(hmmc->Instance); |
|||
|
|||
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; |
|||
|
|||
/* Read Blocks in DMA mode */ |
|||
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); |
|||
|
|||
/* Read Multi Block command */ |
|||
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); |
|||
if (errorstate != HAL_MMC_ERROR_NONE) |
|||
{ |
|||
hmmc->State = HAL_MMC_STATE_READY; |
|||
hmmc->ErrorCode |= errorstate; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | |
|||
SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); |
|||
|
|||
return HAL_OK; |
|||
} |
|||
else |
|||
{ |
|||
return HAL_BUSY; |
|||
} |
|||
|
|||
} |
|||
|
|||
/**
|
|||
* @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1. |
|||
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before |
|||
* call this function. |
|||
* @param hmmc: MMC handle |
|||
* @param BlockAdd: Block Address from where data is to be read |
|||
* @param NumberOfBlocks: Total number of blocks to read |
|||
* @retval HAL status |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, |
|||
uint32_t NumberOfBlocks) |
|||
{ |
|||
SDMMC_DataInitTypeDef config; |
|||
uint32_t errorstate; |
|||
uint32_t DmaBase0_reg; |
|||
uint32_t DmaBase1_reg; |
|||
uint32_t add = BlockAdd; |
|||
|
|||
if (hmmc->State == HAL_MMC_STATE_READY) |
|||
{ |
|||
if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) |
|||
{ |
|||
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ |
|||
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) |
|||
{ |
|||
if ((NumberOfBlocks % 8U) != 0U) |
|||
{ |
|||
/* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ |
|||
hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
if ((BlockAdd % 8U) != 0U) |
|||
{ |
|||
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ |
|||
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; |
|||
return HAL_ERROR; |
|||
} |
|||
} |
|||
|
|||
DmaBase0_reg = hmmc->Instance->IDMABASE0; |
|||
DmaBase1_reg = hmmc->Instance->IDMABASE1; |
|||
|
|||
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) |
|||
{ |
|||
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
/* Initialize data control register */ |
|||
hmmc->Instance->DCTRL = 0; |
|||
|
|||
hmmc->ErrorCode = HAL_MMC_ERROR_NONE; |
|||
|
|||
hmmc->State = HAL_MMC_STATE_BUSY; |
|||
|
|||
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) |
|||
{ |
|||
add *= 512U; |
|||
} |
|||
|
|||
/* Configure the MMC DPSM (Data Path State Machine) */ |
|||
config.DataTimeOut = SDMMC_DATATIMEOUT; |
|||
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; |
|||
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; |
|||
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; |
|||
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; |
|||
config.DPSM = SDMMC_DPSM_DISABLE; |
|||
(void)SDMMC_ConfigData(hmmc->Instance, &config); |
|||
|
|||
__SDMMC_CMDTRANS_ENABLE(hmmc->Instance); |
|||
|
|||
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; |
|||
|
|||
/* Write Blocks in DMA mode */ |
|||
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); |
|||
|
|||
/* Write Multi Block command */ |
|||
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); |
|||
if (errorstate != HAL_MMC_ERROR_NONE) |
|||
{ |
|||
hmmc->State = HAL_MMC_STATE_READY; |
|||
hmmc->ErrorCode |= errorstate; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | |
|||
SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); |
|||
|
|||
return HAL_OK; |
|||
} |
|||
else |
|||
{ |
|||
return HAL_BUSY; |
|||
} |
|||
} |
|||
|
|||
|
|||
/**
|
|||
* @brief Change the DMA Buffer0 or Buffer1 address on the fly. |
|||
* @param hmmc: pointer to a MMC_HandleTypeDef structure. |
|||
* @param Buffer: the buffer to be changed, This parameter can be one of |
|||
* the following values: MMC_DMA_BUFFER0 or MMC_DMA_BUFFER1 |
|||
* @param pDataBuffer: The new address |
|||
* @note The BUFFER0 address can be changed only when the current transfer use |
|||
* BUFFER1 and the BUFFER1 address can be changed only when the current |
|||
* transfer use BUFFER0. |
|||
* @retval HAL status |
|||
*/ |
|||
HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, |
|||
uint32_t *pDataBuffer) |
|||
{ |
|||
if (Buffer == MMC_DMA_BUFFER0) |
|||
{ |
|||
/* change the buffer0 address */ |
|||
hmmc->Instance->IDMABASE0 = (uint32_t)pDataBuffer; |
|||
} |
|||
else |
|||
{ |
|||
/* change the memory1 address */ |
|||
hmmc->Instance->IDMABASE1 = (uint32_t)pDataBuffer; |
|||
} |
|||
|
|||
return HAL_OK; |
|||
} |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* HAL_MMC_MODULE_ENABLED */ |
|||
#endif /* SDMMC1 || SDMMC2 */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
File diff suppressed because it is too large
@ -0,0 +1,315 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32h7xx_hal_sd_ex.c |
|||
* @author MCD Application Team |
|||
* @brief SD card Extended HAL module driver. |
|||
* This file provides firmware functions to manage the following |
|||
* functionalities of the Secure Digital (SD) peripheral: |
|||
* + Extended features functions |
|||
* |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
@verbatim |
|||
============================================================================== |
|||
##### How to use this driver ##### |
|||
============================================================================== |
|||
[..] |
|||
The SD Extension HAL driver can be used as follows: |
|||
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function. |
|||
(+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() |
|||
and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions. |
|||
|
|||
@endverbatim |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32h7xx_hal.h" |
|||
|
|||
/** @addtogroup STM32H7xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup SDEx SDEx
|
|||
* @brief SD Extended HAL module driver |
|||
* @{ |
|||
*/ |
|||
|
|||
#if defined (SDMMC1) || defined (SDMMC2) |
|||
#ifdef HAL_SD_MODULE_ENABLED |
|||
|
|||
/* Private typedef -----------------------------------------------------------*/ |
|||
/* Private define ------------------------------------------------------------*/ |
|||
/* Private macro -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private function prototypes -----------------------------------------------*/ |
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup SDEx_Exported_Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup SDEx_Exported_Functions_Group1
|
|||
* @brief Multibuffer functions |
|||
* |
|||
@verbatim |
|||
============================================================================== |
|||
##### Multibuffer functions ##### |
|||
============================================================================== |
|||
[..] |
|||
This section provides functions allowing to configure the multibuffer mode and start read and write |
|||
multibuffer mode for SD HAL driver. |
|||
|
|||
@endverbatim |
|||
* @{ |
|||
*/ |
|||
|
|||
/**
|
|||
* @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA. |
|||
* @param hsd: SD handle |
|||
* @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transferred data |
|||
* @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transferred data |
|||
* @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size. |
|||
* @retval HAL status |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, |
|||
uint32_t BufferSize) |
|||
{ |
|||
if (hsd->State == HAL_SD_STATE_READY) |
|||
{ |
|||
hsd->Instance->IDMABASE0 = (uint32_t) pDataBuffer0; |
|||
hsd->Instance->IDMABASE1 = (uint32_t) pDataBuffer1; |
|||
hsd->Instance->IDMABSIZE = (uint32_t)(BLOCKSIZE * BufferSize); |
|||
|
|||
return HAL_OK; |
|||
} |
|||
else |
|||
{ |
|||
return HAL_BUSY; |
|||
} |
|||
} |
|||
|
|||
/**
|
|||
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1. |
|||
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before |
|||
* call this function. |
|||
* @param hsd: SD handle |
|||
* @param BlockAdd: Block Address from where data is to be read |
|||
* @param NumberOfBlocks: Total number of blocks to read |
|||
* @retval HAL status |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) |
|||
{ |
|||
SDMMC_DataInitTypeDef config; |
|||
uint32_t errorstate; |
|||
uint32_t DmaBase0_reg; |
|||
uint32_t DmaBase1_reg; |
|||
uint32_t add = BlockAdd; |
|||
|
|||
if (hsd->State == HAL_SD_STATE_READY) |
|||
{ |
|||
if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) |
|||
{ |
|||
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
DmaBase0_reg = hsd->Instance->IDMABASE0; |
|||
DmaBase1_reg = hsd->Instance->IDMABASE1; |
|||
|
|||
if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) |
|||
{ |
|||
hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
/* Initialize data control register */ |
|||
hsd->Instance->DCTRL = 0; |
|||
/* Clear old Flags*/ |
|||
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); |
|||
|
|||
hsd->ErrorCode = HAL_SD_ERROR_NONE; |
|||
hsd->State = HAL_SD_STATE_BUSY; |
|||
|
|||
if (hsd->SdCard.CardType != CARD_SDHC_SDXC) |
|||
{ |
|||
add *= 512U; |
|||
} |
|||
|
|||
/* Configure the SD DPSM (Data Path State Machine) */ |
|||
config.DataTimeOut = SDMMC_DATATIMEOUT; |
|||
config.DataLength = BLOCKSIZE * NumberOfBlocks; |
|||
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; |
|||
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; |
|||
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; |
|||
config.DPSM = SDMMC_DPSM_DISABLE; |
|||
(void)SDMMC_ConfigData(hsd->Instance, &config); |
|||
|
|||
hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; |
|||
|
|||
__SDMMC_CMDTRANS_ENABLE(hsd->Instance); |
|||
|
|||
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; |
|||
|
|||
/* Read Blocks in DMA mode */ |
|||
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); |
|||
|
|||
/* Read Multi Block command */ |
|||
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); |
|||
if (errorstate != HAL_SD_ERROR_NONE) |
|||
{ |
|||
hsd->State = HAL_SD_STATE_READY; |
|||
hsd->ErrorCode |= errorstate; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | |
|||
SDMMC_IT_IDMABTC)); |
|||
|
|||
return HAL_OK; |
|||
} |
|||
else |
|||
{ |
|||
return HAL_BUSY; |
|||
} |
|||
|
|||
} |
|||
|
|||
/**
|
|||
* @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1. |
|||
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before |
|||
* call this function. |
|||
* @param hsd: SD handle |
|||
* @param BlockAdd: Block Address from where data is to be read |
|||
* @param NumberOfBlocks: Total number of blocks to read |
|||
* @retval HAL status |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) |
|||
{ |
|||
SDMMC_DataInitTypeDef config; |
|||
uint32_t errorstate; |
|||
uint32_t DmaBase0_reg; |
|||
uint32_t DmaBase1_reg; |
|||
uint32_t add = BlockAdd; |
|||
|
|||
if (hsd->State == HAL_SD_STATE_READY) |
|||
{ |
|||
if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) |
|||
{ |
|||
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
DmaBase0_reg = hsd->Instance->IDMABASE0; |
|||
DmaBase1_reg = hsd->Instance->IDMABASE1; |
|||
if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U)) |
|||
{ |
|||
hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
/* Initialize data control register */ |
|||
hsd->Instance->DCTRL = 0; |
|||
|
|||
hsd->ErrorCode = HAL_SD_ERROR_NONE; |
|||
|
|||
hsd->State = HAL_SD_STATE_BUSY; |
|||
|
|||
if (hsd->SdCard.CardType != CARD_SDHC_SDXC) |
|||
{ |
|||
add *= 512U; |
|||
} |
|||
|
|||
/* Configure the SD DPSM (Data Path State Machine) */ |
|||
config.DataTimeOut = SDMMC_DATATIMEOUT; |
|||
config.DataLength = BLOCKSIZE * NumberOfBlocks; |
|||
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; |
|||
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; |
|||
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; |
|||
config.DPSM = SDMMC_DPSM_DISABLE; |
|||
(void)SDMMC_ConfigData(hsd->Instance, &config); |
|||
|
|||
__SDMMC_CMDTRANS_ENABLE(hsd->Instance); |
|||
|
|||
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; |
|||
|
|||
/* Write Blocks in DMA mode */ |
|||
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); |
|||
|
|||
/* Write Multi Block command */ |
|||
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); |
|||
if (errorstate != HAL_SD_ERROR_NONE) |
|||
{ |
|||
hsd->State = HAL_SD_STATE_READY; |
|||
hsd->ErrorCode |= errorstate; |
|||
return HAL_ERROR; |
|||
} |
|||
|
|||
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | |
|||
SDMMC_IT_IDMABTC)); |
|||
|
|||
return HAL_OK; |
|||
} |
|||
else |
|||
{ |
|||
return HAL_BUSY; |
|||
} |
|||
} |
|||
|
|||
|
|||
/**
|
|||
* @brief Change the DMA Buffer0 or Buffer1 address on the fly. |
|||
* @param hsd: pointer to a SD_HandleTypeDef structure. |
|||
* @param Buffer: the buffer to be changed, This parameter can be one of |
|||
* the following values: SD_DMA_BUFFER0 or SD_DMA_BUFFER1 |
|||
* @param pDataBuffer: The new address |
|||
* @note The BUFFER0 address can be changed only when the current transfer use |
|||
* BUFFER1 and the BUFFER1 address can be changed only when the current |
|||
* transfer use BUFFER0. |
|||
* @retval HAL status |
|||
*/ |
|||
HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, |
|||
uint32_t *pDataBuffer) |
|||
{ |
|||
if (Buffer == SD_DMA_BUFFER0) |
|||
{ |
|||
/* change the buffer0 address */ |
|||
hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer; |
|||
} |
|||
else |
|||
{ |
|||
/* change the memory1 address */ |
|||
hsd->Instance->IDMABASE1 = (uint32_t)pDataBuffer; |
|||
} |
|||
|
|||
return HAL_OK; |
|||
} |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* HAL_SD_MODULE_ENABLED */ |
|||
#endif /* SDMMC1 || SDMMC2 */ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
File diff suppressed because it is too large
File diff suppressed because it is too large
@ -0,0 +1,214 @@ |
|||
/**
|
|||
****************************************************************************** |
|||
* @file stm32h7xx_ll_delayblock.c |
|||
* @author MCD Application Team |
|||
* @brief DelayBlock Low Layer HAL module driver. |
|||
* |
|||
* This file provides firmware functions to manage the following |
|||
* functionalities of the Delay Block peripheral: |
|||
* + input clock frequency range 25MHz to 208MHz |
|||
* + up to 12 oversampling phases |
|||
* |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
@verbatim |
|||
============================================================================== |
|||
##### DelayBlock peripheral features ##### |
|||
============================================================================== |
|||
[..] The Delay block is used to generate an Output clock which is de-phased from the Input |
|||
clock. The phase of the Output clock is programmed by FW. The Output clock is then used |
|||
to clock the receive data in i.e. a SDMMC or QSPI interface. |
|||
The delay is Voltage and Temperature dependent, which may require FW to do re-tuning |
|||
and recenter the Output clock phase to the receive data. |
|||
|
|||
[..] The Delay Block features include the following: |
|||
(+) Input clock frequency range 25MHz to 208MHz. |
|||
(+) Up to 12 oversampling phases. |
|||
|
|||
##### How to use this driver ##### |
|||
============================================================================== |
|||
[..] |
|||
This driver is a considered as a driver of service for external devices drivers |
|||
that interfaces with the DELAY peripheral. |
|||
The DelayBlock_Enable() function, enables the DelayBlock instance, configure the delay line length |
|||
and configure the Output clock phase. |
|||
The DelayBlock_Disable() function, disables the DelayBlock instance by setting DEN flag to 0. |
|||
|
|||
|
|||
@endverbatim |
|||
*/ |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32h7xx_hal.h" |
|||
|
|||
/** @addtogroup STM32H7xx_HAL_Driver
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup DELAYBLOCK_LL DELAYBLOCK_LL
|
|||
* @brief Low layer module for Delay Block |
|||
* @{ |
|||
*/ |
|||
|
|||
#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED) |
|||
|
|||
/* Private typedef -----------------------------------------------------------*/ |
|||
/* Private define ------------------------------------------------------------*/ |
|||
/** @defgroup DelayBlock_LL_Private_Defines Delay Block Low Layer Private Defines
|
|||
* @{ |
|||
*/ |
|||
#define DLYB_TIMEOUT 0xFFU |
|||
/**
|
|||
* @} |
|||
*/ |
|||
/* Private macro -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private function prototypes -----------------------------------------------*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
|
|||
/** @defgroup DelayBlock_LL_Exported_Functions Delay Block Low Layer Exported Functions
|
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup HAL_DELAY_LL_Group1 Initialization de-initialization functions
|
|||
* @brief Initialization and Configuration functions |
|||
* |
|||
@verbatim |
|||
=============================================================================== |
|||
##### Initialization and de-initialization functions ##### |
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=============================================================================== |
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[..] This section provides functions allowing to: |
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|
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@endverbatim |
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* @{ |
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*/ |
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|
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|
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/**
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* @brief Enable the Delay Block instance. |
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* @param DLYBx: Pointer to DLYB instance. |
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* @retval HAL status |
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*/ |
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HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *DLYBx) |
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{ |
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uint32_t unit = 0U; |
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uint32_t sel = 0U; |
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uint32_t sel_current; |
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uint32_t unit_current; |
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uint32_t tuning; |
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uint32_t lng_mask; |
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uint32_t tickstart; |
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|
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DLYBx->CR = DLYB_CR_DEN | DLYB_CR_SEN; |
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for (sel_current = 0U; sel_current < DLYB_MAX_SELECT; sel_current++) |
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{ |
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/* lng_mask is the mask bit for the LNG field to check the output of the UNITx*/ |
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lng_mask = DLYB_CFGR_LNG_0 << sel_current; |
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tuning = 0U; |
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for (unit_current = 0U; unit_current < DLYB_MAX_UNIT; unit_current++) |
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{ |
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/* Set the Delay of the UNIT(s)*/ |
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DLYBx->CFGR = DLYB_MAX_SELECT | (unit_current << DLYB_CFGR_UNIT_Pos); |
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|
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/* Waiting for a LNG valid value */ |
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tickstart = HAL_GetTick(); |
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while ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U) |
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{ |
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if((HAL_GetTick() - tickstart) >= DLYB_TIMEOUT) |
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{ |
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return HAL_TIMEOUT; |
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} |
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} |
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if (tuning == 0U) |
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{ |
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if ((DLYBx->CFGR & lng_mask) != 0U) |
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{ |
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/* 1/2 period HIGH is detected */ |
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tuning = 1U; |
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} |
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} |
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else |
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{ |
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/* 1/2 period LOW detected after the HIGH 1/2 period => FULL PERIOD passed*/ |
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if((DLYBx->CFGR & lng_mask ) == 0U) |
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{ |
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/* Save the first result */ |
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if( unit == 0U ) |
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{ |
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unit = unit_current; |
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sel = sel_current + 1U; |
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} |
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break; |
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} |
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} |
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} |
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} |
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|
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/* Apply the Tuning settings */ |
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DLYBx->CR = 0U; |
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DLYBx->CR = DLYB_CR_DEN | DLYB_CR_SEN; |
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DLYBx->CFGR = sel | (unit << DLYB_CFGR_UNIT_Pos); |
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DLYBx->CR = DLYB_CR_DEN; |
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|
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return HAL_OK; |
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} |
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|
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/**
|
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* @brief Disable the Delay Block instance. |
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* @param DLYBx: Pointer to DLYB instance. |
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* @retval HAL status |
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*/ |
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HAL_StatusTypeDef DelayBlock_Disable(DLYB_TypeDef *DLYBx) |
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{ |
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/* Disable DLYB */ |
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DLYBx->CR = 0U; |
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return HAL_OK; |
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} |
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|
|||
/**
|
|||
* @brief Configure the Delay Block instance. |
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* @param DLYBx: Pointer to DLYB instance. |
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* @param PhaseSel: Phase selection [0..11]. |
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* @param Units: Delay units[0..127]. |
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* @retval HAL status |
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*/ |
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HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx,uint32_t PhaseSel, uint32_t Units ) |
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{ |
|||
/* Apply the delay settings */ |
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|
|||
DLYBx->CR = 0U; |
|||
DLYBx->CR = DLYB_CR_DEN | DLYB_CR_SEN; |
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DLYBx->CFGR = PhaseSel | (Units << DLYB_CFGR_UNIT_Pos); |
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DLYBx->CR = DLYB_CR_DEN; |
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|
|||
return HAL_OK; |
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} |
|||
|
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* (HAL_SD_MODULE_ENABLED) & (HAL_QSPI_MODULE_ENABLED)*/ |
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
/**
|
|||
* @} |
|||
*/ |
|||
|
|||
File diff suppressed because it is too large
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Reference in new issue