mpu设置修改

.settings/language.settings.xml

@@ -5,7 +5,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1387597085481388379" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1122953909570767073" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>

Kconfig

@@ -18,7 +18,7 @@ config PKGS_DIR
 config PLATFORM_DIR
     string
     option env="PLATFORM_DIR"
-    default "D:/RT-ThreadStudio/workspace/828F/platform"
+    default "C:/RT-ThreadStudio/workspace/828F/platform"
 
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"

applications/sql/DB_SQLite.c

@@ -180,10 +180,6 @@ void close_db_immediately(void) {
 void db_sqlite_init_full(void)
 {
     LOG_D("[DataBase] Init SQLite");
-    if (sqlite3_init_with_sdram_heap() != 0)
-    {
-        LOG_E("Failed to set memory");
-    }else{ LOG_D("set memory");}
     sqlite3_initialize();
 
     if (access(DB_NAME, F_OK) != 0)

cubemx/Src/main.c

@@ -810,6 +810,7 @@ void MPU_Config(void)
   MPU_InitStruct.Number = MPU_REGION_NUMBER1;
   MPU_InitStruct.BaseAddress = 0x30000000;
   MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
+  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
 
   HAL_MPU_ConfigRegion(&MPU_InitStruct);
 
@@ -822,17 +823,19 @@ void MPU_Config(void)
 
   /** Initializes and configures the Region and the memory to be protected
   */
-  MPU_InitStruct.Number = MPU_REGION_NUMBER3;
+  MPU_InitStruct.Number = MPU_REGION_NUMBER4;
-  MPU_InitStruct.BaseAddress = 0x0;
+  MPU_InitStruct.BaseAddress = 0x30040000;
   MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
+  MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
 
   HAL_MPU_ConfigRegion(&MPU_InitStruct);
 
   /** Initializes and configures the Region and the memory to be protected
   */
-  MPU_InitStruct.Number = MPU_REGION_NUMBER4;
+  MPU_InitStruct.Number = MPU_REGION_NUMBER5;
   MPU_InitStruct.BaseAddress = 0xC0000000;
   MPU_InitStruct.Size = MPU_REGION_SIZE_32MB;
+  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
 
   HAL_MPU_ConfigRegion(&MPU_InitStruct);
   /* Enables the MPU */

cubemx/Src/stm32h7xx_hal_msp.c

@@ -127,6 +127,7 @@ void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
   * @param hltdc: LTDC handle pointer
   * @retval None
   */
+
 /**
   * @brief LTDC MSP De-Initialization
   * This function freeze the hardware resources used in this example
@@ -707,7 +708,7 @@ void HAL_HCD_MspInit(HCD_HandleTypeDef* hhcd)
     GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
     GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS;
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 

cubemx/cubemx.ioc

@@ -2,35 +2,38 @@
 CAD.formats=
 CAD.pinconfig=
 CAD.provider=
+CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_FULL_ACCESS
+CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_FULL_ACCESS
+CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=MPU_REGION_FULL_ACCESS
 CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=0x30000000
 CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=0x30020000
-CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=0x0
+CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=0x30040000
-CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=0xC0000000
+CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=0xC0000000
 CORTEX_M7.BaseAddress_Spec=0x24000000
 CORTEX_M7.CPU_DCache=Enabled
 CORTEX_M7.CPU_ICache=Enabled
 CORTEX_M7.DisableExec_Spec=MPU_INSTRUCTION_ACCESS_ENABLE
 CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_ENABLE
 CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_ENABLE
-CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_REGION_ENABLE
+CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=__NULL
 CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_REGION_ENABLE
-CORTEX_M7.IPParameters=default_mode_Activation,CPU_ICache,CPU_DCache,Size_Spec,BaseAddress_Spec,DisableExec_Spec,IsCacheable_Spec,IsBufferable_Spec,IsShareable_Spec,SubRegionDisable_Spec,Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,IsShareable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S
+CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=MPU_REGION_ENABLE
+CORTEX_M7.IPParameters=default_mode_Activation,CPU_ICache,CPU_DCache,Size_Spec,BaseAddress_Spec,DisableExec_Spec,IsCacheable_Spec,IsBufferable_Spec,IsShareable_Spec,SubRegionDisable_Spec,Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region5_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region5_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region5_Settings_S,IsCacheable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S
 CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_ACCESS_BUFFERABLE
 CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_BUFFERABLE
-CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_ACCESS_BUFFERABLE
 CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_ACCESS_BUFFERABLE
+CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=MPU_ACCESS_BUFFERABLE
 CORTEX_M7.IsBufferable_Spec=MPU_ACCESS_BUFFERABLE
 CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_ACCESS_CACHEABLE
 CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_CACHEABLE
-CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_ACCESS_CACHEABLE
 CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_ACCESS_CACHEABLE
+CORTEX_M7.IsCacheable_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=MPU_ACCESS_CACHEABLE
 CORTEX_M7.IsCacheable_Spec=MPU_ACCESS_CACHEABLE
-CORTEX_M7.IsShareable_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_ACCESS_NOT_SHAREABLE
 CORTEX_M7.IsShareable_Spec=MPU_ACCESS_NOT_SHAREABLE
 CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_SIZE_128KB
 CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_SIZE_128KB
-CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region3_Settings_S=MPU_REGION_SIZE_32KB
+CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_REGION_SIZE_32KB
-CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region4_Settings_S=MPU_REGION_SIZE_32MB
+CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region5_Settings_S=MPU_REGION_SIZE_32MB
 CORTEX_M7.Size_Spec=MPU_REGION_SIZE_512KB
 CORTEX_M7.SubRegionDisable_Spec=0x0
 CORTEX_M7.default_mode_Activation=1
@@ -65,7 +68,6 @@ LTDC.WindowY1_L0=600
 LTDC.WindowY1_L1=600
 MMTAppRegionsCount=0
 MMTConfigApplied=false
-MMTSectionSuffix=_Section
 Mcu.CPN=STM32H743IIT6
 Mcu.Family=STM32H7
 Mcu.IP0=CORTEX_M7
@@ -389,7 +391,6 @@ ProjectManager.DeletePrevious=true
 ProjectManager.DeviceId=STM32H743IITx
 ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.12.1
 ProjectManager.FreePins=false
-ProjectManager.FreePinsContext=
 ProjectManager.HalAssertFull=false
 ProjectManager.HeapSize=0x200
 ProjectManager.KeepUserCode=true

packages/sqlite/sqlite3.c

@@ -20728,9 +20728,9 @@ static malloc_zone_t* _sqliteZone_;
 ** Also used by rt-thread systems if SQLITE_WITHOUT_ZONEMALLOC is defined.
 */
 extern struct rt_memheap sdram_heap,sram_SRAM1,sram_DTCMRAM;
-//#define SQLITE_MALLOC(x)    rt_memheap_alloc(&sram_DTCMRAM,(rt_size_t)x)
+//#define SQLITE_MALLOC(x)    rt_memheap_alloc(&sram_SRAM1,(rt_size_t)x)
-//#define SQLITE_FREE(x)      rt_free(x)
+//#define SQLITE_FREE(x)      rt_memheap_free(x)
-//#define SQLITE_REALLOC(x,y) rt_memheap_realloc(&sram_DTCMRAM,(x),(rt_size_t)(y))
+//#define SQLITE_REALLOC(x,y) rt_memheap_realloc(&sram_SRAM1,(x),(rt_size_t)(y))
 #define SQLITE_MALLOC(x)    rt_malloc((rt_size_t)x)
 #define SQLITE_FREE(x)      rt_free(x)
 #define SQLITE_REALLOC(x,y) rt_realloc((x),(rt_size_t)(y))