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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2025-11-04 Administrator the first version
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*/
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#include <board.h>
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#ifdef BSP_USING_SDRAM
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#include <sdram_port.h>
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#define DRV_DEBUG
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#define LOG_TAG "drv.sdram"
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#include <drv_log.h>
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static SDRAM_HandleTypeDef hsdram1;
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static FMC_SDRAM_CommandTypeDef command;
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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struct rt_memheap sdram_heap;
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#endif
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/**
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* @brief Perform the SDRAM exernal memory inialization sequence
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* @param hsdram: SDRAM handle
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* @param Command: Pointer to SDRAM command structure
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* @retval None
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*/
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static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
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{
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__IO uint32_t tmpmrd = 0;
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uint32_t target_bank = 0;
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#if SDRAM_TARGET_BANK == 1
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target_bank = FMC_SDRAM_CMD_TARGET_BANK1;
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#else
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target_bank = FMC_SDRAM_CMD_TARGET_BANK2;
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#endif
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/* Configure a clock configuration enable command */
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Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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Command->CommandTarget = target_bank;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Insert 100 ms delay */
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/* interrupt is not enable, just to delay some time. */
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for (tmpmrd = 0; tmpmrd < 0xffffff; tmpmrd ++)
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;
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/* Configure a PALL (precharge all) command */
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Command->CommandMode = FMC_SDRAM_CMD_PALL;
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Command->CommandTarget = target_bank;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Configure a Auto-Refresh command */
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Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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Command->CommandTarget = target_bank;
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Command->AutoRefreshNumber = 8;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Program the external memory mode register */
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#if SDRAM_DATA_WIDTH == 8
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tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
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#elif SDRAM_DATA_WIDTH == 16
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tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
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#else
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tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_4 |
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#endif
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
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#if SDRAM_CAS_LATENCY == 3
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SDRAM_MODEREG_CAS_LATENCY_3 |
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#else
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SDRAM_MODEREG_CAS_LATENCY_2 |
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#endif
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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Command->CommandTarget = target_bank;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = tmpmrd;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Set the device refresh counter */
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HAL_SDRAM_ProgramRefreshRate(hsdram, SDRAM_REFRESH_COUNT);
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}
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static int SDRAM_Init(void)
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{
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int result = RT_EOK;
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FMC_SDRAM_TimingTypeDef SDRAM_Timing;
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/* SDRAM device configuration */
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hsdram1.Instance = FMC_SDRAM_DEVICE;
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SDRAM_Timing.LoadToActiveDelay = LOADTOACTIVEDELAY;
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SDRAM_Timing.ExitSelfRefreshDelay = EXITSELFREFRESHDELAY;
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SDRAM_Timing.SelfRefreshTime = SELFREFRESHTIME;
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SDRAM_Timing.RowCycleDelay = ROWCYCLEDELAY;
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SDRAM_Timing.WriteRecoveryTime = WRITERECOVERYTIME;
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SDRAM_Timing.RPDelay = RPDELAY;
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SDRAM_Timing.RCDDelay = RCDDELAY;
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#if SDRAM_TARGET_BANK == 1
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hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
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#else
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hsdram1.Init.SDBank = FMC_SDRAM_BANK2;
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#endif
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#if SDRAM_COLUMN_BITS == 8
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hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
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#elif SDRAM_COLUMN_BITS == 9
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hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
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#elif SDRAM_COLUMN_BITS == 10
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hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_10;
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#else
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hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_11;
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#endif
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#if SDRAM_ROW_BITS == 11
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hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_11;
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#elif SDRAM_ROW_BITS == 12
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hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
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#else
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hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
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#endif
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#if SDRAM_DATA_WIDTH == 8
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hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_8;
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#elif SDRAM_DATA_WIDTH == 16
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hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
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#else
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hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32;
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#endif
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hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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#if SDRAM_CAS_LATENCY == 1
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hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1;
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#elif SDRAM_CAS_LATENCY == 2
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hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
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#else
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hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
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#endif
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hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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#if SDCLOCK_PERIOD == 2
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hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
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#else
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hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_3;
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#endif
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hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
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#if SDRAM_RPIPE_DELAY == 0
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hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
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#elif SDRAM_RPIPE_DELAY == 1
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hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
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#else
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hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_2;
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#endif
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/* Initialize the SDRAM controller */
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if (HAL_SDRAM_Init(&hsdram1, &SDRAM_Timing) != HAL_OK)
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{
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LOG_E("SDRAM init failed!");
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result = -RT_ERROR;
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}
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else
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{
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/* Program the SDRAM external device */
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SDRAM_Initialization_Sequence(&hsdram1, &command);
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LOG_D("sdram init success, mapped at 0x%X, size is %d bytes, data width is %d", SDRAM_BANK_ADDR, SDRAM_SIZE, SDRAM_DATA_WIDTH);
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
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rt_memheap_init(&sdram_heap, "SDRAM", (void *)SDRAM1_START, SDRAM1_SIZE);
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#endif
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}
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return result;
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}
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INIT_BOARD_EXPORT(SDRAM_Init);
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#ifdef DRV_DEBUG
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#ifdef FINSH_USING_MSH
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int sdram_test(void)
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{
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int i = 0;
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uint32_t start_time = 0, time_cast = 0;
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#if SDRAM_DATA_WIDTH == 8
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char data_width = 1;
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uint8_t data = 0;
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#elif SDRAM_DATA_WIDTH == 16
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char data_width = 2;
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uint16_t data = 0;
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#else
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char data_width = 4;
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uint32_t data = 0;
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#endif
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/* write data */
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LOG_D("Writing the %ld bytes data, waiting....", SDRAM_SIZE);
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start_time = rt_tick_get();
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for (i = 0; i < SDRAM_SIZE / data_width; i++)
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{
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#if SDRAM_DATA_WIDTH == 8
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*(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint8_t)0x55;
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#elif SDRAM_DATA_WIDTH == 16
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*(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint16_t)(i % 65535);
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#else
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*(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint32_t)0x55555555;
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#endif
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}
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time_cast = rt_tick_get() - start_time;
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LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
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time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
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/* read data */
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LOG_D("start Reading and verifying data, waiting....");
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for (i = 0; i < SDRAM_SIZE / data_width; i++)
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{
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#if SDRAM_DATA_WIDTH == 8
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data = *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != 0x55)
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{
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LOG_E("SDRAM test failed!");
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break;
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}
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#elif SDRAM_DATA_WIDTH == 16
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data = *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != (i % 65535))
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{
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LOG_E("SDRAM test failed!");
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break;
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}
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#else
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data = *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != 0x55555555)
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{
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LOG_E("SDRAM test failed!");
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break;
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}
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#endif
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}
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if (i >= SDRAM_SIZE / data_width)
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{
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LOG_D("SDRAM test success!");
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}
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return RT_EOK;
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}
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MSH_CMD_EXPORT(sdram_test, sdram test)
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/* 从片内 RAM 和 片外 SDRAM 顺序申请测试 */
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void malloc_test(void)
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{
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int size = 50 * 1024; // 50KBytes
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rt_uint8_t * ptr = RT_NULL;
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ptr = rt_malloc(size);
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if(ptr != RT_NULL)
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{
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LOG_D("ptr = %p", ptr); // 打印申请到的空间的首地址
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}
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else
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{
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LOG_E("malloc failed");
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}
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}
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MSH_CMD_EXPORT(malloc_test, malloc test)
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#endif /* FINSH_USING_MSH */
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#endif /* DRV_DEBUG */
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#endif /* BSP_USING_SDRAM */
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@@ -0,0 +1,64 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2025-11-05 Administrator the first version
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*/
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#ifndef APPLICATIONS_SDRAM_PORT_H_
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#define APPLICATIONS_SDRAM_PORT_H_
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/* parameters for sdram peripheral */
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/* Bank1 or Bank2 */
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#define SDRAM_TARGET_BANK 1
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/* stm32f4 Bank1:0XC0000000 Bank2:0XD0000000 */
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#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
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/* data width: 8, 16, 32 */
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#define SDRAM_DATA_WIDTH 16
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/* column bit numbers: 8, 9, 10, 11 */
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#define SDRAM_COLUMN_BITS 9
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/* row bit numbers: 11, 12, 13 */
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#define SDRAM_ROW_BITS 13
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/* cas latency clock number: 1, 2, 3 */
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#define SDRAM_CAS_LATENCY 3
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/* read pipe delay: 0, 1, 2 */
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#define SDRAM_RPIPE_DELAY 1
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/* clock divid: 2, 3 */
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#define SDCLOCK_PERIOD 2
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/* refresh rate counter */
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//#define SDRAM_REFRESH_COUNT ((uint32_t)0x02AB)
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#define SDRAM_REFRESH_COUNT ((uint32_t)0x1000)
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#define SDRAM_SIZE ((uint32_t)0x2000000)
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/* Timing configuration for W9825G6KH-6 */
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/* 90 MHz of SD clock frequency (180MHz/2) */
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/* TMRD: 2 Clock cycles */
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#define LOADTOACTIVEDELAY 2
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/* TXSR: 7x11.90ns */
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#define EXITSELFREFRESHDELAY 12
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/* TRAS: 4x11.90ns */
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#define SELFREFRESHTIME 12
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/* TRC: 7x11.90ns */
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#define ROWCYCLEDELAY 10
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/* TWR: 2 Clock cycles */
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#define WRITERECOVERYTIME 2
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/* TRP: 2x11.90ns */
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#define RPDELAY 3
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/* TRCD: 2x11.90ns */
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#define RCDDELAY 3
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/* memory mode register */
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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#endif /* APPLICATIONS_SDRAM_PORT_H_ */
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