/*
 * Copyright (c) 2006-2025, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2025-11-16     RealThread   first version
 */

#include <rtthread.h>
#include <board.h>
#include <drv_common.h>

struct rt_memheap sram_DTCMRAM,sram_AXIRAM,sram_SRAM1,sram_SRAM2;                  // memheap 控制块

rt_weak void rt_hw_board_init()
{
    /* 允许未对齐访问（Cortex-M3/M4/M7 支持） */
    //SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; // ← 默认是 1（禁止）
    // 要允许，应该 CLEAR 这个位！
    //SCB->CCR &= ～SCB_CCR_UNALIGN_TRP_Msk;

    extern void hw_board_init(char *clock_src, int32_t clock_src_freq, int32_t clock_target_freq);

    /* Heap initialization */
#if defined(RT_USING_HEAP)
    rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
#endif

    rt_memheap_init(&sram_DTCMRAM, "DTCMRAM", (void *)DTCMRAM_START, DTCMRAM_SIZE);
    //rt_memheap_init(&sram_AXIRAM, "AXIRAM", (void *)AXIRAM_START, AXIRAM_SIZE);
    rt_memheap_init(&sram_SRAM1, "SRAM1", (void *)SRAM1_START, SRAM1_SIZE);
    //rt_memheap_init(&sram_SRAM2, "SRAM2", (void *)SRAM2_START, SRAM2_SIZE);

    hw_board_init(BSP_CLOCK_SOURCE, BSP_CLOCK_SOURCE_FREQ_MHZ, BSP_CLOCK_SYSTEM_FREQ_MHZ);

    /* Set the shell console output device */
#if defined(RT_USING_DEVICE) && defined(RT_USING_CONSOLE)
    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif

    /* Board underlying hardware initialization */
#ifdef RT_USING_COMPONENTS_INIT
    rt_components_board_init();
#endif

}