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48 lines
1.5 KiB
48 lines
1.5 KiB
/*
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* Copyright (c) 2006-2025, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2025-11-16 RealThread first version
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*/
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#include <rtthread.h>
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#include <board.h>
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#include <drv_common.h>
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struct rt_memheap sram_DTCMRAM,sram_AXIRAM,sram_SRAM1,sram_SRAM2; // memheap 控制块
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rt_weak void rt_hw_board_init()
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{
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/* 允许未对齐访问（Cortex-M3/M4/M7 支持） */
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//SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; // ← 默认是 1（禁止）
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// 要允许，应该 CLEAR 这个位！
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//SCB->CCR &= ～SCB_CCR_UNALIGN_TRP_Msk;
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extern void hw_board_init(char *clock_src, int32_t clock_src_freq, int32_t clock_target_freq);
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/* Heap initialization */
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#if defined(RT_USING_HEAP)
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rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
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#endif
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rt_memheap_init(&sram_DTCMRAM, "DTCMRAM", (void *)DTCMRAM_START, DTCMRAM_SIZE);
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//rt_memheap_init(&sram_AXIRAM, "AXIRAM", (void *)AXIRAM_START, AXIRAM_SIZE);
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rt_memheap_init(&sram_SRAM1, "SRAM1", (void *)SRAM1_START, SRAM1_SIZE);
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//rt_memheap_init(&sram_SRAM2, "SRAM2", (void *)SRAM2_START, SRAM2_SIZE);
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hw_board_init(BSP_CLOCK_SOURCE, BSP_CLOCK_SOURCE_FREQ_MHZ, BSP_CLOCK_SYSTEM_FREQ_MHZ);
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/* Set the shell console output device */
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#if defined(RT_USING_DEVICE) && defined(RT_USING_CONSOLE)
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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/* Board underlying hardware initialization */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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