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623 lines
20 KiB
623 lines
20 KiB
5 months ago
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/*
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* Copyright (c) 2006-2025, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-12-20 BruceOu the first version
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* 2025-10-10 WangShun compatible with RT-Studio
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*/
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#include "drv_i2c.h"
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#include "i2c_config.h"
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#ifdef RT_USING_I2C
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#define DBG_TAG "drv.i2c"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && \
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!defined(BSP_USING_I2C4) && !defined(BSP_USING_I2C5)
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#error "Please define at least one BSP_USING_I2Cx"
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/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
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#endif
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#if defined(BSP_USING_I2C0)
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struct rt_i2c_bus_device i2c0;
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#endif /* BSP_USING_I2C0 */
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#if defined(BSP_USING_I2C1)
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struct rt_i2c_bus_device i2c1;
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#endif /* BSP_USING_I2C1 */
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#if defined(BSP_USING_I2C2)
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struct rt_i2c_bus_device i2c2;
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#endif /* BSP_USING_I2C2 */
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#if defined(BSP_USING_I2C3)
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struct rt_i2c_bus_device i2c3;
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#endif /* BSP_USING_I2C3 */
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#if defined(BSP_USING_I2C4)
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struct rt_i2c_bus_device i2c4;
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#endif /* BSP_USING_I2C4 */
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#if defined(BSP_USING_I2C5)
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struct rt_i2c_bus_device i2c5;
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#endif /* BSP_USING_I2C5 */
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#if defined(SOC_SERIES_GD32F5xx)
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#define i2c_flag_get_gd i2c_add_flag_get
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#define i2c_timing_config_gd i2c_add_timing_config
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#define i2c_master_clock_config_gd i2c_add_master_clock_config
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#define i2c_enable_gd i2c_add_enable
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#define i2c_flag_clear_gd i2c_add_flag_clear
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#define i2c_stop_on_bus_gd i2c_add_stop_on_bus
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#define i2c_transfer_byte_number_config_gd i2c_add_transfer_byte_number_config
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#define i2c_start_on_bus_gd i2c_add_start_on_bus
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#define i2c_address10_enable_gd i2c_add_address10_enable
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#define i2c_address10_disable_gd i2c_add_address10_disable
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#define i2c_master_addressing_gd i2c_add_master_addressing
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#define i2c_data_transmit_gd i2c_add_data_transmit
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#define i2c_data_receive_gd i2c_add_data_receive
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#define I2C_FLAG_RBNE_GD I2C_ADD_FLAG_RBNE
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#define I2C_STAT_GD I2C_ADD_STAT
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#define I2C_STAT_TBE_GD I2C_ADD_STAT_TBE
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#define I2C_STAT_TI_GD I2C_ADD_STAT_TI
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#define I2C_MASTER_RECEIVE_GD I2C_ADD_MASTER_RECEIVE
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#define I2C_MASTER_TRANSMIT_GD I2C_ADD_MASTER_TRANSMIT
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#define I2C_FLAG_I2CBSY_GD I2C_ADD_FLAG_I2CBSY
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#define I2C_FLAG_TC_GD I2C_ADD_FLAG_TC
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#define I2C_FLAG_TI_GD I2C_ADD_FLAG_TI
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#define I2C_FLAG_STPDET_GD I2C_ADD_FLAG_STPDET
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#else
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#define i2c_flag_get_gd i2c_flag_get
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#define i2c_timing_config_gd i2c_timing_config
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#define i2c_master_clock_config_gd i2c_master_clock_config
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#define i2c_enable_gd i2c_enable
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#define i2c_flag_clear_gd i2c_flag_clear
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#define i2c_data_receive_gd i2c_data_receive
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#define i2c_data_transmit_gd i2c_data_transmit
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#define i2c_address10_enable_gd i2c_address10_enable
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#define i2c_address10_disable_gd i2c_address10_disable
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#define i2c_master_addressing_gd i2c_master_addressing
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#define i2c_transfer_byte_number_config_gd i2c_transfer_byte_number_config
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#define i2c_start_on_bus_gd i2c_start_on_bus
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#define i2c_stop_on_bus_gd i2c_stop_on_bus
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#if defined(SOC_SERIES_GD32E51x)
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#undef i2c_flag_get_gd
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#undef i2c_flag_clear_gd
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#undef i2c_master_addressing_gd
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#define i2c_flag_get_gd i2c2_flag_get
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#define i2c_flag_clear_gd i2c2_flag_clear
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#define i2c_master_addressing_gd i2c2_master_addressing
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#undef I2C_STAT_GD
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#undef I2C_STAT_TBE_GD
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#undef I2C_STAT_TI_GD
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#define I2C_STAT_GD I2C2_STAT
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#define I2C_STAT_TBE_GD I2C2_STAT_TBE
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#define I2C_STAT_TI_GD I2C2_STAT_TI
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#undef I2C_MASTER_RECEIVE_GD
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#undef I2C_MASTER_TRANSMIT_GD
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#define I2C_MASTER_RECEIVE_GD I2C2_MASTER_RECEIVE
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#define I2C_MASTER_TRANSMIT_GD I2C2_MASTER_TRANSMIT
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#undef I2C_FLAG_RBNE_GD
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#undef I2C_FLAG_I2CBSY_GD
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#undef I2C_FLAG_TC_GD
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#undef I2C_FLAG_TI_GD
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#undef I2C_FLAG_STPDET_GD
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#define I2C_FLAG_RBNE_GD I2C2_FLAG_RBNE
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#define I2C_FLAG_I2CBSY_GD I2C2_FLAG_I2CBSY
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#define I2C_FLAG_TC_GD I2C2_FLAG_TC
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#define I2C_FLAG_TI_GD I2C2_FLAG_TI
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#define I2C_FLAG_STPDET_GD I2C2_FLAG_STPDET
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/* also needed in write path */
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#define I2C_FLAG_TBE_GD I2C2_FLAG_TBE
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#else
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#define I2C_FLAG_RBNE_GD I2C_FLAG_RBNE
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#define I2C_STAT_GD I2C_STAT
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#define I2C_STAT_TBE_GD I2C_STAT_TBE
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#define I2C_STAT_TI_GD I2C_STAT_TI
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#define I2C_MASTER_RECEIVE_GD I2C_MASTER_RECEIVE
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#define I2C_MASTER_TRANSMIT_GD I2C_MASTER_TRANSMIT
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#define I2C_FLAG_I2CBSY_GD I2C_FLAG_I2CBSY
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#define I2C_FLAG_TC_GD I2C_FLAG_TC
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#define I2C_FLAG_TI_GD I2C_FLAG_TI
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#define I2C_FLAG_STPDET_GD I2C_FLAG_STPDET
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/* used in write path */
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#define I2C_FLAG_TBE_GD I2C_FLAG_TBE
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#endif
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#endif
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#if defined(SOC_SERIES_GD32F5xx)
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#define IS_I2C_LEGACY(periph) ((periph) == I2C0 || (periph) == I2C1 || (periph) == I2C2)
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#elif defined(SOC_SERIES_GD32F4xx)
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#define IS_I2C_LEGACY(periph) (1)
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#elif defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) || defined(SOC_SERIES_GD32L23x)
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#define IS_I2C_LEGACY(periph) (0)
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#elif defined(SOC_SERIES_GD32E51x)
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#define IS_I2C_LEGACY(periph) ((periph) == I2C0 || (periph) == I2C1)
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#endif
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static const struct gd32_i2c_bus gd_i2c_config[] = {
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#ifdef BSP_USING_I2C0
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I2C0_CONFIG,
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#endif
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#ifdef BSP_USING_I2C1
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I2C1_CONFIG,
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#endif
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#ifdef BSP_USING_I2C2
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I2C2_CONFIG,
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#endif
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#ifdef BSP_USING_I2C3
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I2C3_CONFIG,
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#endif
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#ifdef BSP_USING_I2C4
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I2C4_CONFIG,
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#endif
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#ifdef BSP_USING_I2C5
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I2C5_CONFIG,
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#endif
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};
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/**
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* @brief This function initializes the i2c pin.
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* @param i2c
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* @retval None
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*/
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static void gd32_i2c_gpio_init(const struct gd32_i2c_bus *i2c)
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{
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rt_uint32_t scl_port, sda_port;
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rt_uint32_t scl_pin, sda_pin;
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rt_uint32_t pin_af;
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rcu_periph_enum scl_periph, sda_periph;
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if (get_pin_config(i2c->scl_pin_name, &scl_port, &scl_pin, &scl_periph) == -RT_ERROR)
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{
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return;
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}
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if (get_pin_config(i2c->sda_pin_name, &sda_port, &sda_pin, &sda_periph) == -RT_ERROR)
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{
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return;
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}
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pin_alternate_config(i2c->alternate, &pin_af);
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/* enable I2C and GPIO clock */
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rcu_periph_clock_enable(scl_periph);
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rcu_periph_clock_enable(sda_periph);
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rcu_periph_clock_enable(i2c->per_clk);
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/* configure I2C_SCL as alternate function push-pull */
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#if defined(SOC_SERIES_GD32E51x)
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gpio_init(scl_port, GPIO_MODE_AF_OD, GPIO_OSPEED_10MHZ, scl_pin);
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gpio_init(sda_port, GPIO_MODE_AF_OD, GPIO_OSPEED_10MHZ, sda_pin);
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if (!IS_I2C_LEGACY(i2c->i2c_periph))
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{
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rcu_periph_clock_enable(RCU_AF);
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gpio_afio_port_config(AFIO_PA8_I2C2_CFG, ENABLE);
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gpio_afio_port_config(AFIO_PC9_I2C2_CFG, ENABLE);
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}
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else
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{
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i2c_deinit(i2c->i2c_periph);
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}
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/* configure remap function */
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if (i2c->i2c_remap != 0)
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{
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rcu_periph_clock_enable(RCU_AF);
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gpio_pin_remap_config(i2c->i2c_remap, ENABLE);
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}
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gpio_init(scl_port, GPIO_MODE_AF_OD, GPIO_OSPEED_10MHZ, scl_pin);
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gpio_init(sda_port, GPIO_MODE_AF_OD, GPIO_OSPEED_10MHZ, sda_pin);
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/* configure alternate1 function */
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if (pin_af != 0 || pin_af != 0)
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{
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rcu_periph_clock_enable(RCU_AF);
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gpio_afio_port_config(pin_af, ENABLE);
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gpio_afio_port_config(pin_af, ENABLE);
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}
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i2c_deinit(i2c->i2c_periph);
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#else
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gpio_af_set(scl_port, pin_af, scl_pin);
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gpio_mode_set(scl_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, scl_pin);
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#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E)
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gpio_output_options_set(scl_port, GPIO_OTYPE_OD, GPIO_OSPEED_60MHZ, scl_pin);
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/* configure I2C_SDA as alternate function push-pull */
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gpio_af_set(sda_port, pin_af, sda_pin);
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gpio_mode_set(sda_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, sda_pin);
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gpio_output_options_set(sda_port, GPIO_OTYPE_OD, GPIO_OSPEED_60MHZ, sda_pin);
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#else
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gpio_output_options_set(scl_port, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, scl_pin);
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/* configure I2C_SDA as alternate function push-pull */
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gpio_af_set(sda_port, pin_af, sda_pin);
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gpio_mode_set(sda_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, sda_pin);
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gpio_output_options_set(sda_port, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, sda_pin);
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#endif
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#endif
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}
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/**
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* @brief read data.
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* @param i2c_periph
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* @param *p_buffer
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* @param data_byte
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* @retval None
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*/
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static uint8_t gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint8_t *p_buffer, rt_uint16_t data_byte)
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{
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if (data_byte == 0)
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return 1;
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/* while there is data to be read */
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while (data_byte)
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{
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#if defined(SOC_SERIES_GD32F5xx) || defined(SOC_SERIES_GD32F4xx) || defined(SOC_SERIES_GD32E51x)
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if (IS_I2C_LEGACY(i2c_periph))
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{
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if (3 == data_byte)
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{
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/* wait until BTC bit is set */
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while (!i2c_flag_get(i2c_periph, I2C_FLAG_BTC))
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;
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/* disable acknowledge */
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i2c_ack_config(i2c_periph, I2C_ACK_DISABLE);
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}
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if (2 == data_byte)
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{
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/* wait until BTC bit is set */
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while (!i2c_flag_get(i2c_periph, I2C_FLAG_BTC))
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;
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/* send a stop condition to I2C bus */
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i2c_stop_on_bus(i2c_periph);
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||
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}
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/* wait until RBNE bit is set */
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if (i2c_flag_get(i2c_periph, I2C_FLAG_RBNE))
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{
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/* read a byte from the EEPROM */
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*p_buffer = i2c_data_receive(i2c_periph);
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||
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/* point to the next location where the byte read will be saved */
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||
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p_buffer++;
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||
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/* decrement the read bytes counter */
|
||
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data_byte--;
|
||
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}
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||
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}
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||
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else
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||
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#endif
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|
|
{
|
||
|
|
/* wait until the RBNE bit is set */
|
||
|
|
while (!i2c_flag_get_gd(i2c_periph, I2C_FLAG_RBNE_GD))
|
||
|
|
;
|
||
|
|
|
||
|
|
/* read a byte */
|
||
|
|
*p_buffer = i2c_data_receive_gd(i2c_periph);
|
||
|
|
/* point to the next location where the byte read will be saved */
|
||
|
|
p_buffer++;
|
||
|
|
/* decrement the read bytes counter */
|
||
|
|
data_byte--;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief write data.
|
||
|
|
* @param i2c_periph
|
||
|
|
* @param *p_buffer
|
||
|
|
* @param data_byte
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
static uint8_t gd32_i2c_write(rt_uint32_t i2c_periph, uint8_t *p_buffer, uint16_t data_byte)
|
||
|
|
{
|
||
|
|
if (data_byte == 0)
|
||
|
|
return 1;
|
||
|
|
|
||
|
|
while (data_byte)
|
||
|
|
{
|
||
|
|
#if defined(SOC_SERIES_GD32F5xx) || defined(SOC_SERIES_GD32F4xx) || defined(SOC_SERIES_GD32E51x)
|
||
|
|
if (IS_I2C_LEGACY(i2c_periph))
|
||
|
|
{
|
||
|
|
/* data transmission */
|
||
|
|
i2c_data_transmit(i2c_periph, *p_buffer);
|
||
|
|
/* point to the next byte to be written */
|
||
|
|
p_buffer++;
|
||
|
|
/* decrement the write bytes counter */
|
||
|
|
data_byte--;
|
||
|
|
/* wait until the TI bit is set */
|
||
|
|
while (!i2c_flag_get(i2c_periph, I2C_FLAG_BTC))
|
||
|
|
;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
#endif
|
||
|
|
{
|
||
|
|
#if defined(SOC_SERIES_GD32F5xx) || defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) || defined(SOC_SERIES_GD32L23x) || defined(SOC_SERIES_GD32E51x)
|
||
|
|
/* wait until the transmit data buffer is empty */
|
||
|
|
I2C_STAT_GD(i2c_periph) |= I2C_STAT_TBE_GD;
|
||
|
|
while (!i2c_flag_get_gd(i2c_periph, I2C_FLAG_TBE))
|
||
|
|
;
|
||
|
|
|
||
|
|
while (data_byte)
|
||
|
|
{
|
||
|
|
/* wait until the TI bit is set */
|
||
|
|
while (!i2c_flag_get_gd(i2c_periph, I2C_FLAG_TI_GD))
|
||
|
|
;
|
||
|
|
/* data transmission */
|
||
|
|
i2c_data_transmit(i2c_periph, *p_buffer);
|
||
|
|
/* point to the next byte to be written */
|
||
|
|
p_buffer++;
|
||
|
|
/* decrement the write bytes counter */
|
||
|
|
data_byte--;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (data_byte != 0)
|
||
|
|
{
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_ssize_t gd32_i2c_master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
|
||
|
|
{
|
||
|
|
static struct rt_i2c_msg *msg;
|
||
|
|
|
||
|
|
rt_uint32_t i, w_total_byte = 0, r_total_byte = 0;
|
||
|
|
rt_err_t ret = RT_ERROR;
|
||
|
|
|
||
|
|
RT_ASSERT(bus != RT_NULL);
|
||
|
|
|
||
|
|
struct gd32_i2c_bus *gd32_i2c = (struct gd32_i2c_bus *)bus->priv;
|
||
|
|
|
||
|
|
for (i = 0; i < num; i++)
|
||
|
|
{
|
||
|
|
msg = &msgs[i];
|
||
|
|
|
||
|
|
if (msg->flags & RT_I2C_RD)
|
||
|
|
{
|
||
|
|
r_total_byte += msg->len;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
w_total_byte += msg->len;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i < num; i++)
|
||
|
|
{
|
||
|
|
msg = &msgs[i];
|
||
|
|
if (!(msg->flags & RT_I2C_NO_START))
|
||
|
|
{
|
||
|
|
#if defined(SOC_SERIES_GD32F5xx) || defined(SOC_SERIES_GD32F4xx) || defined(SOC_SERIES_GD32E51x)
|
||
|
|
if (IS_I2C_LEGACY(gd32_i2c->i2c_periph))
|
||
|
|
{
|
||
|
|
if (msg->flags & RT_I2C_RD)
|
||
|
|
{
|
||
|
|
if (i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_I2CBSY))
|
||
|
|
{
|
||
|
|
i2c_stop_on_bus(gd32_i2c->i2c_periph);
|
||
|
|
}
|
||
|
|
/* enable acknowledge */
|
||
|
|
i2c_ack_config(gd32_i2c->i2c_periph, I2C_ACK_ENABLE);
|
||
|
|
/* i2c master sends start signal only when the bus is idle */
|
||
|
|
while (i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_I2CBSY))
|
||
|
|
;
|
||
|
|
/* send the start signal */
|
||
|
|
i2c_start_on_bus(gd32_i2c->i2c_periph);
|
||
|
|
/* i2c master sends START signal successfully */
|
||
|
|
while (!i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_SBSEND))
|
||
|
|
;
|
||
|
|
|
||
|
|
i2c_master_addressing(gd32_i2c->i2c_periph, msg->addr, I2C_RECEIVER);
|
||
|
|
|
||
|
|
while (!i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_ADDSEND))
|
||
|
|
;
|
||
|
|
/* address flag set means i2c slave sends ACK */
|
||
|
|
i2c_flag_clear(gd32_i2c->i2c_periph, I2C_FLAG_ADDSEND);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* configure slave address */
|
||
|
|
while (i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_I2CBSY))
|
||
|
|
;
|
||
|
|
//i2c_transfer_byte_number_config(gd32_i2c->i2c_periph, w_total_byte);
|
||
|
|
/* send a start condition to I2C bus */
|
||
|
|
i2c_start_on_bus(gd32_i2c->i2c_periph);
|
||
|
|
while (!i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_SBSEND))
|
||
|
|
;
|
||
|
|
|
||
|
|
i2c_master_addressing(gd32_i2c->i2c_periph, msg->addr, I2C_TRANSMITTER);
|
||
|
|
while (!i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_ADDSEND))
|
||
|
|
;
|
||
|
|
|
||
|
|
i2c_flag_clear(gd32_i2c->i2c_periph, I2C_FLAG_ADDSEND);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
#endif
|
||
|
|
{
|
||
|
|
#if defined(SOC_SERIES_GD32F5xx) || defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) || defined(SOC_SERIES_GD32L23x) || defined(SOC_SERIES_GD32E51x)
|
||
|
|
if (msg->flags & RT_I2C_ADDR_10BIT)
|
||
|
|
{
|
||
|
|
/* enable 10-bit addressing mode in master mode */
|
||
|
|
i2c_address10_enable_gd(gd32_i2c->i2c_periph);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* disable 10-bit addressing mode in master mode */
|
||
|
|
i2c_address10_disable_gd(gd32_i2c->i2c_periph);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (msg->flags & RT_I2C_RD)
|
||
|
|
{
|
||
|
|
/* configure slave address */
|
||
|
|
i2c_master_addressing_gd(gd32_i2c->i2c_periph, msg->addr, I2C_MASTER_RECEIVE_GD);
|
||
|
|
|
||
|
|
i2c_transfer_byte_number_config_gd(gd32_i2c->i2c_periph, r_total_byte);
|
||
|
|
/* send a start condition to I2C bus */
|
||
|
|
i2c_start_on_bus_gd(gd32_i2c->i2c_periph);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* configure slave address */
|
||
|
|
i2c_master_addressing_gd(gd32_i2c->i2c_periph, msg->addr, I2C_MASTER_TRANSMIT_GD);
|
||
|
|
while (i2c_flag_get_gd(gd32_i2c->i2c_periph, I2C_FLAG_I2CBSY_GD))
|
||
|
|
;
|
||
|
|
i2c_transfer_byte_number_config_gd(gd32_i2c->i2c_periph, w_total_byte);
|
||
|
|
/* send a start condition to I2C bus */
|
||
|
|
i2c_start_on_bus_gd(gd32_i2c->i2c_periph);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (msg->flags & RT_I2C_RD)
|
||
|
|
{
|
||
|
|
if (gd32_i2c_read(gd32_i2c->i2c_periph, msg->buf, msg->len) != 0)
|
||
|
|
{
|
||
|
|
LOG_E("i2c bus read failed,i2c bus stop!");
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if (gd32_i2c_write(gd32_i2c->i2c_periph, msg->buf, msg->len) != 0)
|
||
|
|
{
|
||
|
|
LOG_E("i2c bus write failed,i2c bus stop!");
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#if defined(SOC_SERIES_GD32F5xx) || defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) || defined(SOC_SERIES_GD32L23x) || defined(SOC_SERIES_GD32E51x)
|
||
|
|
if (!IS_I2C_LEGACY(gd32_i2c->i2c_periph))
|
||
|
|
{
|
||
|
|
if (r_total_byte != 0)
|
||
|
|
{
|
||
|
|
while (!i2c_flag_get_gd(gd32_i2c->i2c_periph, I2C_FLAG_TC_GD))
|
||
|
|
;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
ret = i;
|
||
|
|
|
||
|
|
out:
|
||
|
|
#if defined(SOC_SERIES_GD32F5xx) || defined(SOC_SERIES_GD32F4xx) || defined(SOC_SERIES_GD32E51x)
|
||
|
|
if (IS_I2C_LEGACY(gd32_i2c->i2c_periph))
|
||
|
|
{
|
||
|
|
if (!(msg->flags & RT_I2C_NO_STOP))
|
||
|
|
{
|
||
|
|
if (msg->flags & RT_I2C_RD)
|
||
|
|
{
|
||
|
|
while ((I2C_CTL0(gd32_i2c->i2c_periph) & I2C_CTL0_STOP))
|
||
|
|
;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* send a stop condition to I2C bus */
|
||
|
|
i2c_stop_on_bus(gd32_i2c->i2c_periph);
|
||
|
|
/* wait until stop condition generate */
|
||
|
|
while ((I2C_CTL0(gd32_i2c->i2c_periph) & I2C_CTL0_STOP))
|
||
|
|
;
|
||
|
|
/* clear the STPDET bit */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
#endif
|
||
|
|
{
|
||
|
|
#if defined(SOC_SERIES_GD32F5xx) || defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) || defined(SOC_SERIES_GD32L23x) || defined(SOC_SERIES_GD32E51x)
|
||
|
|
if (!(msg->flags & RT_I2C_NO_STOP))
|
||
|
|
{
|
||
|
|
while (!i2c_flag_get_gd(gd32_i2c->i2c_periph, I2C_FLAG_TC_GD))
|
||
|
|
;
|
||
|
|
/* send a stop condition to I2C bus */
|
||
|
|
i2c_stop_on_bus_gd(gd32_i2c->i2c_periph);
|
||
|
|
/* wait until stop condition generate */
|
||
|
|
while (!i2c_flag_get_gd(gd32_i2c->i2c_periph, I2C_FLAG_STPDET_GD))
|
||
|
|
;
|
||
|
|
/* clear the STPDET bit */
|
||
|
|
i2c_flag_clear_gd(gd32_i2c->i2c_periph, I2C_FLAG_STPDET_GD);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_i2c_bus_device_ops i2c_ops = {
|
||
|
|
.master_xfer = gd32_i2c_master_xfer,
|
||
|
|
.slave_xfer = RT_NULL,
|
||
|
|
.i2c_bus_control = RT_NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief I2C initialization function
|
||
|
|
* @param None
|
||
|
|
* @retval RT_EOK indicates successful initialization.
|
||
|
|
*/
|
||
|
|
int rt_hw_i2c_init(void)
|
||
|
|
{
|
||
|
|
rt_size_t obj_num = sizeof(gd_i2c_config) / sizeof(gd_i2c_config[0]);
|
||
|
|
|
||
|
|
for (int i = 0; i < obj_num; i++)
|
||
|
|
{
|
||
|
|
gd32_i2c_gpio_init(&gd_i2c_config[i]);
|
||
|
|
|
||
|
|
/* configure I2C timing. I2C speed clock=400kHz*/
|
||
|
|
#if defined(SOC_SERIES_GD32F5xx) || defined(SOC_SERIES_GD32F4xx) || defined(SOC_SERIES_GD32E51x)
|
||
|
|
if (IS_I2C_LEGACY(gd_i2c_config[i].i2c_periph))
|
||
|
|
{
|
||
|
|
i2c_clock_config(gd_i2c_config[i].i2c_periph, 100000, I2C_DTCY_2);
|
||
|
|
i2c_mode_addr_config(gd_i2c_config[i].i2c_periph, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, 0xa0);
|
||
|
|
i2c_enable(gd_i2c_config[i].i2c_periph);
|
||
|
|
i2c_ack_config(gd_i2c_config[i].i2c_periph, I2C_ACK_ENABLE);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
#endif
|
||
|
|
{
|
||
|
|
#if defined(SOC_SERIES_GD32F5xx) || defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E) || defined(SOC_SERIES_GD32L23x) || defined(SOC_SERIES_GD32E51x)
|
||
|
|
i2c_timing_config_gd(gd_i2c_config[i].i2c_periph, 0x1, 0x7, 0);
|
||
|
|
i2c_master_clock_config_gd(gd_i2c_config[i].i2c_periph, 0x2D, 0x87);
|
||
|
|
|
||
|
|
/* enable I2C1 */
|
||
|
|
i2c_enable_gd(gd_i2c_config[i].i2c_periph);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
gd_i2c_config[i].i2c_bus->ops = &i2c_ops;
|
||
|
|
gd_i2c_config[i].i2c_bus->priv = (void *)&gd_i2c_config[i];
|
||
|
|
|
||
|
|
rt_i2c_bus_device_register(gd_i2c_config[i].i2c_bus, gd_i2c_config[i].device_name);
|
||
|
|
}
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
INIT_BOARD_EXPORT(rt_hw_i2c_init);
|
||
|
|
|
||
|
|
#endif /* RT_USING_I2C */
|
||
|
|
|