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297 lines
8.5 KiB
297 lines
8.5 KiB
5 months ago
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/*
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* Copyright (c) 2006-2025, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-06-05 zengjianwei first version
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* 2025-06-23 Yucai Liu Support for non-complementary PWM output with advanced timers
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* 2025-10-11 kurisaw compatible with RT-Studio
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*/
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#include "drv_pwm.h"
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#include "pwm_config.h"
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#ifdef RT_USING_PWM
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#define DBG_TAG "drv.pwm"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#define MAX_PERIOD 65535
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#define MIN_PERIOD 3
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#define MIN_PULSE 2
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static struct gd32_pwm gd32_pwm_obj[] = {
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#ifdef BSP_USING_PWM0
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PWM0_CONFIG,
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#endif
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#ifdef BSP_USING_PWM1
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PWM1_CONFIG,
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#endif
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#ifdef BSP_USING_PWM2
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PWM2_CONFIG,
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#endif
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#ifdef BSP_USING_PWM3
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PWM3_CONFIG,
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#endif
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#ifdef BSP_USING_PWM4
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PWM4_CONFIG,
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#endif
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#ifdef BSP_USING_PWM5
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PWM5_CONFIG,
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#endif
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#ifdef BSP_USING_PWM6
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PWM6_CONFIG,
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#endif
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#ifdef BSP_USING_PWM7
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PWM7_CONFIG,
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#endif
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};
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typedef struct
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{
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rt_uint32_t timer_periph;
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rt_bool_t initialized;
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} TIMER_INIT_STATUS;
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static TIMER_INIT_STATUS timer_init_status[] = {
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{ TIMER0, RT_FALSE },
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{ TIMER1, RT_FALSE },
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{ TIMER2, RT_FALSE },
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{ TIMER3, RT_FALSE },
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{ TIMER4, RT_FALSE },
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{ TIMER5, RT_FALSE },
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{ TIMER6, RT_FALSE },
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{ TIMER7, RT_FALSE },
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};
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static void gd32_pwm_init(struct gd32_pwm *gd32_pwm)
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{
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rt_uint32_t pwm_port, pwm_pin;
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rcu_periph_enum pwm_periph;
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rt_uint32_t pin_af;
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if (get_pin_config(gd32_pwm->pin_name, &pwm_port, &pwm_pin, &pwm_periph) == -RT_ERROR)
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{
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return;
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}
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pin_alternate_config(gd32_pwm->alternate, &pin_af);
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/* enable timer clock */
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rcu_periph_clock_enable(gd32_pwm->timer_clk);
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rcu_periph_clock_enable(pwm_periph);
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/* GPIO pin configuration */
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gpio_af_set(pwm_port, pin_af, pwm_pin);
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gpio_mode_set(pwm_port, GPIO_MODE_AF, GPIO_PUPD_NONE, pwm_pin);
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#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E)
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gpio_output_options_set(pwm_port, GPIO_OTYPE_PP, GPIO_OSPEED_60MHZ, pwm_pin);
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#else
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gpio_output_options_set(pwm_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, pwm_pin);
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#endif
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}
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static rt_err_t drv_pwm_enable(struct gd32_pwm *pwm_dev, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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if (!enable)
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{
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timer_channel_output_state_config(pwm_dev->timer_periph, configuration->channel, TIMER_CCX_DISABLE);
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}
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else
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{
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if (configuration->complementary == RT_TRUE)
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{
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timer_channel_output_state_config(pwm_dev->timer_periph, configuration->channel - 1, TIMER_CCXN_ENABLE);
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}
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else
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{
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timer_channel_output_state_config(pwm_dev->timer_periph, configuration->channel, TIMER_CCX_ENABLE);
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}
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}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_get(struct gd32_pwm *pwm_dev, struct rt_pwm_configuration *configuration)
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{
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rt_uint64_t tim_clock;
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rt_uint16_t psc;
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rt_uint32_t chxcv;
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tim_clock = rcu_clock_freq_get(CK_SYS);
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psc = timer_prescaler_read(pwm_dev->timer_periph);
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if (psc == TIMER_CKDIV_DIV2)
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{
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tim_clock = tim_clock / 2;
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}
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else if (psc == TIMER_CKDIV_DIV4)
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{
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tim_clock = tim_clock / 4;
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}
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chxcv = timer_channel_capture_value_register_read(pwm_dev->timer_periph, configuration->channel);
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/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
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tim_clock /= 1000000UL;
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configuration->period = (TIMER_CAR(pwm_dev->timer_periph) + 1) * (psc + 1) * 1000UL / tim_clock;
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configuration->pulse = (chxcv + 1) * (psc + 1) * 1000UL / tim_clock;
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set(struct gd32_pwm *pwm_dev, struct rt_pwm_configuration *configuration)
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{
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rt_uint32_t period, pulse;
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rt_uint64_t tim_clock, psc;
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tim_clock = rcu_clock_freq_get(CK_SYS);
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/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
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tim_clock /= 1000000UL;
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period = (unsigned long long)configuration->period * tim_clock / 1000ULL;
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psc = period / MAX_PERIOD + 1;
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period = period / psc;
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timer_prescaler_config(pwm_dev->timer_periph, psc - 1, TIMER_PSC_RELOAD_NOW);
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if (period < MIN_PERIOD)
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{
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period = MIN_PERIOD;
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}
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timer_autoreload_value_config(pwm_dev->timer_periph, period - 1);
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pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL;
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if (pulse < MIN_PULSE)
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{
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pulse = MIN_PULSE;
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}
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else if (pulse > period)
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{
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pulse = period;
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}
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timer_channel_output_pulse_value_config(pwm_dev->timer_periph, configuration->channel, pulse);
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timer_counter_value_config(pwm_dev->timer_periph, 0);
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/* Update frequency value */
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timer_event_software_generate(pwm_dev->timer_periph, TIMER_EVENT_SRC_UPG);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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struct gd32_pwm *pwm_dev = (struct gd32_pwm *)device;
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return drv_pwm_enable(pwm_dev, configuration, RT_TRUE);
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case PWM_CMD_DISABLE:
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return drv_pwm_enable(pwm_dev, configuration, RT_FALSE);
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case PWM_CMD_SET:
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return drv_pwm_set(pwm_dev, configuration);
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case PWM_CMD_GET:
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return drv_pwm_get(pwm_dev, configuration);
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default:
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return -RT_EINVAL;
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}
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}
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static struct rt_pwm_ops drv_ops = {
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.control = drv_pwm_control
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};
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static void timer_initialize(uint32_t timer_periph)
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{
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timer_oc_parameter_struct timer_ocintpara;
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timer_parameter_struct timer_initpara;
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/* Check if timer is already initialized */
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for (int i = 0; i < sizeof(timer_init_status) / sizeof(timer_init_status[0]); i++)
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{
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if (timer_init_status[i].timer_periph == timer_periph && !timer_init_status[i].initialized)
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{
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/* TIMER configuration */
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timer_initpara.prescaler = 119;
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timer_initpara.alignedmode = TIMER_COUNTER_EDGE;
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timer_initpara.counterdirection = TIMER_COUNTER_UP;
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timer_initpara.period = 15999;
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timer_initpara.clockdivision = TIMER_CKDIV_DIV1;
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timer_initpara.repetitioncounter = 0;
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timer_init(timer_periph, &timer_initpara);
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/* CHX configuration in PWM mode */
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timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
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timer_ocintpara.outputnstate = TIMER_CCXN_DISABLE;
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timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
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timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH;
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timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW;
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timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
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timer_channel_output_config(gd32_pwm_obj[i].timer_periph, gd32_pwm_obj[i].channel, &timer_ocintpara);
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timer_init_status[i].initialized = RT_TRUE;
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/* Configure channel output */
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timer_channel_output_pulse_value_config(gd32_pwm_obj[i].timer_periph,
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gd32_pwm_obj[i].channel, 7999);
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timer_channel_output_mode_config(gd32_pwm_obj[i].timer_periph,
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gd32_pwm_obj[i].channel, TIMER_OC_MODE_PWM0);
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timer_channel_output_shadow_config(gd32_pwm_obj[i].timer_periph,
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gd32_pwm_obj[i].channel, TIMER_OC_SHADOW_DISABLE);
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/* Enable timer */
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timer_primary_output_config(timer_periph, ENABLE);
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/* auto-reload preload enable */
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timer_auto_reload_shadow_enable(gd32_pwm_obj[i].timer_periph);
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timer_enable(timer_periph);
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break;
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}
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}
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}
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static int drv_pwm_init(void)
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{
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int i, result = RT_EOK;
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for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); i++)
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{
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/* Initialize PWM hardware */
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gd32_pwm_init(&gd32_pwm_obj[i]);
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/* Initialize timer if not already initialized */
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timer_initialize(gd32_pwm_obj[i].timer_periph);
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/* Register PWM device */
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if (rt_device_pwm_register(&gd32_pwm_obj[i].pwm_device, gd32_pwm_obj[i].name,
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&drv_ops, RT_NULL) == RT_EOK)
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{
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LOG_D("%s register success", gd32_pwm_obj[i].name);
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}
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else
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{
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LOG_E("%s register failed", gd32_pwm_obj[i].name);
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result = -RT_ERROR;
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}
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}
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return result;
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}
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INIT_DEVICE_EXPORT(drv_pwm_init);
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#endif /* RT_USING_PWM */
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