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60 lines
1.5 KiB
60 lines
1.5 KiB
5 months ago
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2025-11-10 kurisaw ENET configuration
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*/
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#ifndef __ENET_CONFIG_H__
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#define __ENET_CONFIG_H__
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#include "drv_enet.h"
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#if defined(RT_USING_SAL) && defined(RT_USING_NETDEV) && defined(RT_USING_LWIP)
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ENET pin configuration table for RMII interface */
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const struct enet_pin_config enet0_pins[] =
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{
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/* ETH_RMII_REF_CLK */ {"PA1", "AF11"},
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/* ETH_MDIO */ {"PA2", "AF11"},
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/* ETH_RMII_CRS_DV */ {"PA7", "AF11"},
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/* ETH_RMII_TX_EN */ {"PG11", "AF11"},
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/* ETH_RMII_TXD0 */ {"PB12", "AF11"},
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/* ETH_RMII_TXD1 */ {"PG12", "AF11"},
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/* ETH_MDC */ {"PC1", "AF11"},
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/* ETH_RMII_RXD0 */ {"PC4", "AF11"},
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/* ETH_RMII_RXD1 */ {"PC5", "AF11"},
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};
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/* Clock output pin for PHY */
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const struct enet_pin_config enet_clock_pin = {
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"PA8", "AF0" /* Clock output for PHY */
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};
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/* ENET configuration */
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const struct enet_config enet0_cfg = {
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.pins = enet0_pins,
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.pin_count = sizeof(enet0_pins) / sizeof(enet0_pins[0]),
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.enet_periph = ENET0,
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.enet_clk = RCU_ENET0,
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.enet_tx_clk = RCU_ENET0TX,
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.enet_rx_clk = RCU_ENET0RX,
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.phy_interface = SYSCFG_ENET_PHY_RMII,
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.speed = GPIO_OSPEED_100_220MHZ,
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.otype = GPIO_OTYPE_PP,
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.pupd = GPIO_PUPD_NONE,
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* RT_USING_SAL && RT_USING_NETDEV && RT_USING_LWIP */
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#endif /* __ENET_CONFIG_H__ */
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