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406 lines
32 KiB
406 lines
32 KiB
5 months ago
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/*!
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\file gd32h75e.h
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\brief general definitions for GD32H75e
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\version 2025-01-24, V1.1.0, firmware for GD32H75E
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*/
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/*
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* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
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* Copyright (c) 2025, GigaDevice Semiconductor Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
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#ifndef GD32H75E_H
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#define GD32H75E_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !defined (GD32H75E)
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#error "Please select the target GD32H75E device used in your application (in gd32h75e.h file)"
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#endif /* undefine GD32H75E tip */
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/* define value of high speed crystal oscillator (HXTAL) in Hz */
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#if !defined (HXTAL_VALUE)
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#define HXTAL_VALUE ((uint32_t)25000000)
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#endif /* high speed crystal oscillator value */
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/* define startup timeout value of high speed crystal oscillator (HXTAL) */
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#if !defined (HXTAL_STARTUP_TIMEOUT)
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#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF)
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#endif /* high speed crystal oscillator startup timeout */
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/* define value of internal 64MHz RC oscillator (IRC64M) in Hz */
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#if !defined (IRC64M_VALUE)
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#define IRC64M_VALUE ((uint32_t)64000000)
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#endif /* internal 64MHz RC oscillator value */
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/* define startup timeout value of internal 64MHz RC oscillator (IRC64M) */
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#if !defined (IRC64M_STARTUP_TIMEOUT)
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#define IRC64M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* internal 64MHz RC oscillator startup timeout */
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/* define value of Low Power Internal 4Mhz RC oscillator (LPIRC4M) in Hz */
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#if !defined (LPIRC4M_VALUE)
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#define LPIRC4M_VALUE ((uint32_t)4000000)
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#endif /* Low Power Internal 4Mhz RC oscillator value */
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/* define startup timeout value of internal Low Power Internal 4Mhz RC oscillator (LPIRC4M) */
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#if !defined (LPIRC4M_STARTUP_TIMEOUT)
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#define LPIRC4M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* Low Power Internal 4Mhz RC oscillator startup timeout */
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/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
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#if !defined (IRC48M_VALUE)
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#define IRC48M_VALUE ((uint32_t)48000000)
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#endif /* internal 48MHz RC oscillator value */
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/* define startup timeout value of internal 48MHz RC oscillator (IRC48M) */
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#if !defined (IRC48M_STARTUP_TIMEOUT)
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#define IRC48M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* internal 48MHz RC oscillator startup timeout */
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/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
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#if !defined (IRC32K_VALUE)
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#define IRC32K_VALUE ((uint32_t)32000)
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#endif /* internal 32KHz RC oscillator value */
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/* define startup timeout value of internal 32KHz RC oscillator (IRC32K) */
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#if !defined (IRC32K_STARTUP_TIMEOUT)
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#define IRC32K_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* internal 32KHz RC oscillator startup timeout */
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/* define value of low speed crystal oscillator (LXTAL)in Hz */
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#if !defined (LXTAL_VALUE)
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#define LXTAL_VALUE ((uint32_t)32768)
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#endif /* low speed crystal oscillator value */
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/* define startup timeout value of low speed crystal oscillator (LXTAL) */
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#if !defined (LXTAL_STARTUP_TIMEOUT)
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#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x0FFFFFFF)
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#endif /* low speed crystal oscillator startup timeout */
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/* GD32H75E firmware library version number V1.1.0 */
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#define __GD32H75E_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __GD32H75E_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
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#define __GD32H75E_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __GD32H75E_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __GD32H75E_STDPERIPH_VERSION ((__GD32H75E_STDPERIPH_VERSION_MAIN << 24)\
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|(__GD32H75E_STDPERIPH_VERSION_SUB1 << 16)\
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|(__GD32H75E_STDPERIPH_VERSION_SUB2 << 8)\
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|(__GD32H75E_STDPERIPH_VERSION_RC))
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/* configuration of the Cortex-M7 processor and core peripherals */
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#define __CM7_REV 0x0102U /*!< Cortex-M7 revision r1p2 */
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#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
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#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1 /*!< FPU present */
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#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
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#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
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/* define interrupt number */
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typedef enum IRQn {
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/* Cortex-M7 processor exceptions numbers */
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NonMaskableInt_IRQn = -14, /*!< non mask-able interrupt */
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HardFault_IRQn = -13, /*!< hard-fault interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 memory management interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M7 bus fault interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M7 usage fault interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M7 sv call interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 debug monitor interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M7 pend sv interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M7 system tick interrupt */
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/* interruput numbers */
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WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
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VAVD_LVD_VOVD_IRQn = 1, /*!< AVD_LVD_OVD_IRQn through EXTI line detect interrupt */
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TAMPER_STAMP_LXTAL_IRQn = 2, /*!< RTC tamper and timestamp interrupt/LXTAL clock stuck interrupt */
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RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt */
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FMC_IRQn = 4, /*!< FMC interrupt */
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RCU_IRQn = 5, /*!< RCU interrupt */
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EXTI0_IRQn = 6, /*!< EXTI line 0 */
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EXTI1_IRQn = 7, /*!< EXTI line 1 */
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EXTI2_IRQn = 8, /*!< EXTI line 2 */
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EXTI3_IRQn = 9, /*!< EXTI line 3 */
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EXTI4_IRQn = 10, /*!< EXTI line 4 */
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DMA0_Channel0_IRQn = 11, /*!< DMA0 channel 0 interrupt */
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DMA0_Channel1_IRQn = 12, /*!< DMA0 channel 1 interrupt */
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DMA0_Channel2_IRQn = 13, /*!< DMA0 channel 2 interrupt */
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DMA0_Channel3_IRQn = 14, /*!< DMA0 channel 3 interrupt */
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DMA0_Channel4_IRQn = 15, /*!< DMA0 channel 4 interrupt */
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DMA0_Channel5_IRQn = 16, /*!< DMA0 channel 5 interrupt */
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DMA0_Channel6_IRQn = 17, /*!< DMA0 channel 6 interrupt */
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ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 */
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EXTI5_9_IRQn = 23, /*!< EXTI line 5 to 9 */
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TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupt */
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TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupt */
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TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger/commutation interrupt */
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TIMER0_Channel_IRQn = 27, /*!< TIMER0 capture/compare interrupt */
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TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
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TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
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I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
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I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
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I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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SPI0_IRQn = 35, /*!< SPI0 interrupt */
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SPI1_IRQn = 36, /*!< SPI1 interrupt */
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USART0_IRQn = 37, /*!< USART0 global and wakeup interrupt */
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USART1_IRQn = 38, /*!< USART1 global and wakeup interrupt */
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USART2_IRQn = 39, /*!< USART2 global and wakeup interrupt */
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EXTI10_15_IRQn = 40, /*!< EXTI line 10 to 15 */
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RTC_Alarm_IRQn = 41, /*!< RTC Alarm interrupt */
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TIMER7_BRK_IRQn = 43, /*!< TIMER7 Break global interrupt */
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TIMER7_UP_IRQn = 44, /*!< TIMER7 Update global interrupt */
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TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 Trigger and Commutation global interrupt */
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TIMER7_Channel_IRQn = 46, /*!< TIMER7 Capture Compare interrupt */
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DMA0_Channel7_IRQn = 47, /*!< DMA0 channel 7 interrupt */
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EXMC_IRQn = 48, /*!< EXMC interrupt */
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SDIO0_IRQn = 49, /*!< SDMMC0 interrupt */
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TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
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SPI2_IRQn = 51, /*!< SPI2 interrupt */
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UART3_IRQn = 52, /*!< UART3 interrupt */
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UART4_IRQn = 53, /*!< UART4 interrupt */
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TIMER5_DAC_UDR_IRQn = 54, /*!< TIMER5 global interrupt and DAC1/DAC0 underrun */
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TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
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DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
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DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
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DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
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DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
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DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
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ENET0_IRQn = 61, /*!< ENET 0 interrupt */
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ENET0_WKUP_IRQn = 62, /*!< ENET 0 wakeup through EXTI line interrupt */
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DMA1_Channel5_IRQn = 68, /*!< DMA1 channel 5 interrupt */
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DMA1_Channel6_IRQn = 69, /*!< DMA1 channel 6 interrupt */
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DMA1_Channel7_IRQn = 70, /*!< DMA1 channel 7 interrupt */
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USART5_IRQn = 71, /*!< UART5 global and wakeup interrupt */
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I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
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I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
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USBHS0_EP1_OUT_IRQn = 74, /*!< USBHS0 endpoint 1 out interrupt */
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USBHS0_EP1_IN_IRQn = 75, /*!< USBHS0 endpoint 1 in interrupt */
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USBHS0_WKUP_IRQn = 76, /*!< USBHS0 wakeup through EXTI line interrupt */
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USBHS0_IRQn = 77, /*!< USBHS0 interrupt */
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DCI_IRQn = 78, /*!< DCI interrupt */
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CAU_IRQn = 79, /*!< CAU interrupt */
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HAU_TRNG_IRQn = 80, /*!< HAU and TRNG interrupt */
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FPU_IRQn = 81, /*!< FPU interrupt */
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UART6_IRQn = 82, /*!< UART6 interrupt */
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UART7_IRQn = 83, /*!< UART7 interrupt */
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SPI3_IRQn = 84, /*!< SPI3 interrupt */
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SPI4_IRQn = 85, /*!< SPI4 interrupt */
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SPI5_IRQn = 86, /*!< SPI5 interrupt */
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SAI0_IRQn = 87, /*!< SAI0 interrupt */
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TLI_IRQn = 88, /*!< TLI interrupt */
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TLI_ER_IRQn = 89, /*!< TLI error interrupt */
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IPA_IRQn = 90, /*!< IPA interrupt */
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SAI1_IRQn = 91, /*!< SAI1 interrupt */
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OSPI0_IRQn = 92, /*!< OSPI0 global interrupt */
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I2C3_EV_IRQn = 95, /*!< I2C3 event interrupt */
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I2C3_ER_IRQn = 96, /*!< I2C3 error interrupt */
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RSPDIF_IRQn = 97, /*!< RSPDIF global interrupt */
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DMAMUX_OVR_IRQn = 102, /*!< DMAMUX overrun interrupt */
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HPDF_INT0_IRQn = 110, /*!< HPDF filiter 0 interrupt */
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HPDF_INT1_IRQn = 111, /*!< HPDF filiter 1 interrupt */
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HPDF_INT2_IRQn = 112, /*!< HPDF filiter 2 interrupt */
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HPDF_INT3_IRQn = 113, /*!< HPDF filiter 3 interrupt */
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SAI2_IRQn = 114, /*!< SAI2 interrupt */
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TIMER14_IRQn = 116, /*!< TIMER14 interrupt */
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TIMER15_IRQn = 117, /*!< TIMER15 interrupt */
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TIMER16_IRQn = 118, /*!< TIMER16 interrupt */
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MDIO_IRQn = 120, /*!< MDIO interrupt */
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MDMA_IRQn = 122, /*!< MDMA interrupt */
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SDIO1_IRQn = 124, /*!< SDIO1 interrupt */
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HWSEM_IRQn = 125, /*!< HWSEM interrupt */
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ADC2_IRQn = 127, /*!< ADC2 interrupt */
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CMP0_1_IRQn = 137, /*!< CMP0 and CMP1 interrupt */
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CTC_IRQn = 144, /*!< CTC interrupt */
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RAMECCMU_IRQn = 145, /*!< RAMECCMU interrupt */
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OSPI1_IRQn = 150, /*!< OSPI1 interrupt */
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RTDEC0_IRQn = 151, /*!< RTDEC0 interrupt */
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RTDEC1_IRQn = 152, /*!< RTDEC1 interrupt */
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FAC_IRQn = 153, /*!< FAC interrupt */
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TMU_IRQn = 154, /*!< TMU interrupt */
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TIMER22_IRQn = 161, /*!< TIMER22 interrupt */
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TIMER23_IRQn = 162, /*!< TIMER23 interrupt */
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TIMER40_IRQn = 165, /*!< TIMER40 interrupt */
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TIMER41_IRQn = 166, /*!< TIMER41 interrupt */
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TIMER42_IRQn = 167, /*!< TIMER42 interrupt */
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TIMER43_IRQn = 168, /*!< TIMER43 interrupt */
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TIMER44_IRQn = 169, /*!< TIMER44 interrupt */
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TIMER50_IRQn = 170, /*!< TIMER50 interrupt */
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TIMER51_IRQn = 171, /*!< TIMER51 interrupt */
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USBHS1_EP1_OUT_IRQn = 172, /*!< USBHS1 endpoint 1 out interrupt */
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USBHS1_EP1_IN_IRQn = 173, /*!< USBHS1 endpoint 1 in interrupt */
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USBHS1_WKUP_IRQn = 174, /*!< USBHS1 wakeup through EXTI line interrupt */
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USBHS1_IRQn = 175, /*!< USBHS1 interrupt */
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ENET1_IRQn = 176, /*!< ENET1 interrupt */
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ENET1_WKUP_IRQn = 177, /*!< ENET1 wakeup through EXTI line interrupt */
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CAN0_WKUP_IRQn = 179, /*!< CAN 0 wakeup through EXTI line interrupt */
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CAN0_Message_IRQn = 180, /*!< CAN 0 message buffer interrupt */
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CAN0_Busoff_IRQn = 181, /*!< CAN 0 bus off / bus off done interrupt */
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CAN0_Error_IRQn = 182, /*!< CAN 0 error interrupt */
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CAN0_FastError_IRQn = 183, /*!< CAN 0 error in fast transmission interrupt */
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CAN0_TEC_IRQn = 184, /*!< CAN 0 transmit warning interrupt */
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CAN0_REC_IRQn = 185, /*!< CAN 0 receive warning interrupt */
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CAN1_WKUP_IRQn = 186, /*!< CAN 1 wakeup through EXTI line interrupt */
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CAN1_Message_IRQn = 187, /*!< CAN 1 message buffer interrupt */
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CAN1_Busoff_IRQn = 188, /*!< CAN 1 bus off / bus off done interrupt */
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CAN1_Error_IRQn = 189, /*!< CAN 1 error interrupt */
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CAN1_FastError_IRQn = 190, /*!< CAN 1 error in fast transmission interrupt */
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CAN1_TEC_IRQn = 191, /*!< CAN 1 transmit warning interrupt */
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CAN1_REC_IRQn = 192, /*!< CAN 1 receive warning interrupt */
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CAN2_WKUP_IRQn = 193, /*!< CAN 2 wakeup through EXTI line interrupt */
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CAN2_Message_IRQn = 194, /*!< CAN 2 message buffer interrupt */
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CAN2_Busoff_IRQn = 195, /*!< CAN 2 bus off / bus off done interrupt */
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CAN2_Error_IRQn = 196, /*!< CAN 2 error interrupt */
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CAN2_FastError_IRQn = 197, /*!< CAN 2 error in fast transmission interrupt */
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CAN2_TEC_IRQn = 198, /*!< CAN 2 transmit warning interrupt */
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CAN2_REC_IRQn = 199, /*!< CAN 2 receive warning interrupt */
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EFUSE_IRQn = 200, /*!< EFUSE interrupt */
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I2C0_WKUP_IRQn = 201, /*!< I2C 0 wakeup through EXTI line interrupt */
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I2C1_WKUP_IRQn = 202, /*!< I2C 1 wakeup through EXTI line interrupt */
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I2C2_WKUP_IRQn = 203, /*!< I2C 2 wakeup through EXTI line interrupt */
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|
I2C3_WKUP_IRQn = 204, /*!< I2C 3 wakeup through EXTI line interrupt */
|
||
|
|
LPDTS_IRQn = 205, /*!< LPDTS interrupt */
|
||
|
|
LPDTS_WKUP_IRQn = 206, /*!< LPDTS wakeup through EXTI line interrupt */
|
||
|
|
TIMER0_DEC_IRQn = 207, /*!< TIMER0 DEC interrupt */
|
||
|
|
TIMER7_DEC_IRQn = 208, /*!< TIMER7 DEC interrupt */
|
||
|
|
TIMER1_DEC_IRQn = 209, /*!< TIMER1 DEC interrupt */
|
||
|
|
TIMER2_DEC_IRQn = 210, /*!< TIMER2 DEC interrupt */
|
||
|
|
TIMER3_DEC_IRQn = 211, /*!< TIMER3 DEC interrupt */
|
||
|
|
TIMER4_DEC_IRQn = 212, /*!< TIMER4 DEC interrupt */
|
||
|
|
TIMER22_DEC_IRQn = 213, /*!< TIMER22 DEC interrupt */
|
||
|
|
TIMER23_DEC_IRQn = 214, /*!< TIMER23 DEC interrupt */
|
||
|
|
} IRQn_Type;
|
||
|
|
|
||
|
|
/* includes */
|
||
|
|
#include "core_cm7.h"
|
||
|
|
#include "system_gd32h75e.h"
|
||
|
|
#include <stdint.h>
|
||
|
|
#ifdef FW_DEBUG_ERR_REPORT
|
||
|
|
#include "gd32h75e_err_report.h"
|
||
|
|
#endif /* FW_DEBUG_ERR_REPORT */
|
||
|
|
|
||
|
|
/* enum definitions */
|
||
|
|
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||
|
|
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||
|
|
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||
|
|
|
||
|
|
/* bit operations */
|
||
|
|
#define REG64(addr) (*(volatile uint64_t *)(uint32_t)(addr))
|
||
|
|
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||
|
|
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||
|
|
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||
|
|
#define BIT(x) ((uint32_t)((uint32_t)0x01U << (x)))
|
||
|
|
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||
|
|
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||
|
|
|
||
|
|
/* main flash and SRAM memory map */
|
||
|
|
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||
|
|
#define SRAM_BASE ((uint32_t)0x24000000U) /*!< SRAM base address */
|
||
|
|
/* SRAM and peripheral base bit-band region */
|
||
|
|
#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */
|
||
|
|
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */
|
||
|
|
/* peripheral memory map */
|
||
|
|
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||
|
|
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||
|
|
#define APB3_BUS_BASE ((uint32_t)0x50000000U) /*!< apb3 base address */
|
||
|
|
#define APB4_BUS_BASE ((uint32_t)0x58000000U) /*!< apb4 base address */
|
||
|
|
#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
|
||
|
|
#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */
|
||
|
|
#define AHB3_BUS_BASE ((uint32_t)0x51000000U) /*!< ahb3 base address */
|
||
|
|
#define AHB4_BUS_BASE ((uint32_t)0x58020000U) /*!< ahb4 base address */
|
||
|
|
/* advanced peripheral bus 1 memory map */
|
||
|
|
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||
|
|
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||
|
|
#define RSPDIF_BASE (APB1_BUS_BASE + 0x00004000U) /*!< RSPDIF base address */
|
||
|
|
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||
|
|
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||
|
|
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
||
|
|
#define CTC_BASE (APB1_BUS_BASE + 0x00008400U) /*!< CTC base address */
|
||
|
|
#define MDIO_BASE (APB1_BUS_BASE + 0x00009400U) /*!< MDIO base address */
|
||
|
|
/* advanced peripheral bus 2 memory map */
|
||
|
|
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
||
|
|
#define SAI_BASE (APB2_BUS_BASE + 0x00005800U) /*!< SAI base address */
|
||
|
|
#define HPDF_BASE (APB2_BUS_BASE + 0x00007000U) /*!< HPDF base address */
|
||
|
|
#define TRIGSEL_BASE (APB2_BUS_BASE + 0x00008400U) /*!< TRIGSEL base address */
|
||
|
|
#define EDOUT_BASE (APB2_BUS_BASE + 0x00008800U) /*!< EDOUT base address */
|
||
|
|
#define CAN_BASE (APB2_BUS_BASE + 0x0000A000U) /*!< CAN base address */
|
||
|
|
/* advanced peripheral bus 3 memory map */
|
||
|
|
#define TLI_BASE (APB3_BUS_BASE + 0x00001000U) /*!< TLI base address */
|
||
|
|
#define WWDGT_BASE (APB3_BUS_BASE + 0x00003000U) /*!< WWDGT base address */
|
||
|
|
/* advanced peripheral bus 4 memory map */
|
||
|
|
#define EXTI_BASE (APB4_BUS_BASE + 0x00000000U) /*!< EXTI base address */
|
||
|
|
#define SYSCFG_BASE (APB4_BUS_BASE + 0x00000400U) /*!< SYSCFG base address */
|
||
|
|
#define CMP_BASE (APB4_BUS_BASE + 0x00003800U) /*!< CMP base address */
|
||
|
|
#define VREF_BASE (APB4_BUS_BASE + 0x00003C00U) /*!< VREF base address */
|
||
|
|
#define RTC_BASE (APB4_BUS_BASE + 0x00004000U) /*!< CMP base address */
|
||
|
|
#define FWDGT_BASE (APB4_BUS_BASE + 0x00004800U) /*!< FWDGT base address */
|
||
|
|
#define PMU_BASE (APB4_BUS_BASE + 0x00005800U) /*!< PMU base address */
|
||
|
|
#define LPDTS_BASE (APB4_BUS_BASE + 0x00006800U) /*!< LPDTS base address */
|
||
|
|
/* advanced high performance bus 1 memory map */
|
||
|
|
#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
|
||
|
|
#define DMAMUX_BASE (AHB1_BUS_BASE + 0x00000800U) /*!< DMAMUX base address */
|
||
|
|
#define EFUSE_BASE (AHB1_BUS_BASE + 0x00002800U) /*!< EFUSE base address */
|
||
|
|
#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */
|
||
|
|
#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */
|
||
|
|
/* advanced high performance bus 2 memory map */
|
||
|
|
#define DCI_BASE (AHB2_BUS_BASE + 0x00020000U) /*!< DCI base address */
|
||
|
|
#define CAU_BASE (AHB2_BUS_BASE + 0x00021000U) /*!< CAU base address */
|
||
|
|
#define HAU_BASE (AHB2_BUS_BASE + 0x00021400U) /*!< HAU base address */
|
||
|
|
#define TRNG_BASE (AHB2_BUS_BASE + 0x00021800U) /*!< TRNG base address */
|
||
|
|
#define SDIO_BASE (AHB2_BUS_BASE + 0x00022400U) /*!< SDIO base address */
|
||
|
|
#define CPDM_BASE (AHB2_BUS_BASE + 0x00022800U) /*!< CPDM base address */
|
||
|
|
#define RAMECCMU_BASE (AHB2_BUS_BASE + 0x00023000U) /*!< RAMECCMU base address */
|
||
|
|
#define TMU_BASE (AHB2_BUS_BASE + 0x00024400U) /*!< TMU base address */
|
||
|
|
#define FAC_BASE (AHB2_BUS_BASE + 0x00024800U) /*!< FAC base address */
|
||
|
|
/* advanced high performance bus 3 memory map */
|
||
|
|
#define AXIM_BASE (AHB3_BUS_BASE + 0x00000000U) /*!< AXIM base address */
|
||
|
|
#define MDMA_BASE (AHB3_BUS_BASE + 0x01000000U) /*!< MDMA base address */
|
||
|
|
#define IPA_BASE (AHB3_BUS_BASE + 0x01001000U) /*!< IPA base address */
|
||
|
|
#define FMC_BASE (AHB3_BUS_BASE + 0x01002000U) /*!< FMC base address */
|
||
|
|
#define FLEXRAMC_BASE (AHB3_BUS_BASE + 0x01003000U) /*!< FLEXRAMC base address */
|
||
|
|
#define EXMC_BASE (AHB3_BUS_BASE + 0x01004000U) /*!< EXMC base address */
|
||
|
|
#define OSPI_BASE (AHB3_BUS_BASE + 0x01005000U) /*!< OSPI base address */
|
||
|
|
#define OSPM_BASE (AHB3_BUS_BASE + 0x0100B400U) /*!< OSPM base address */
|
||
|
|
#define RTDEC_BASE (AHB3_BUS_BASE + 0x0100B800U) /*!< RTDEC base address */
|
||
|
|
/* advanced high performance bus 4 memory map */
|
||
|
|
#define GPIO_BASE (AHB4_BUS_BASE + 0x00000000U) /*!< GPIO base address */
|
||
|
|
#define RCU_BASE (AHB4_BUS_BASE + 0x00004400U) /*!< RCU base address */
|
||
|
|
#define CRC_BASE (AHB4_BUS_BASE + 0x00004C00U) /*!< CRC base address */
|
||
|
|
#define HWSEM_BASE (AHB4_BUS_BASE + 0x00006400U) /*!< HWSEM base address */
|
||
|
|
/* option byte and debug memory map */
|
||
|
|
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
|
||
|
|
#define DBG_BASE ((uint32_t)0xE00E1000U) /*!< DBG base address */
|
||
|
|
|
||
|
|
/* define marco USE_STDPERIPH_DRIVER */
|
||
|
|
#if !defined USE_STDPERIPH_DRIVER
|
||
|
|
#define USE_STDPERIPH_DRIVER
|
||
|
|
#endif
|
||
|
|
#ifdef USE_STDPERIPH_DRIVER
|
||
|
|
#include "gd32h75e_libopt.h"
|
||
|
|
#endif /* USE_STDPERIPH_DRIVER */
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* GD32H75E_H */
|