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195 lines
14 KiB
195 lines
14 KiB
5 months ago
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/*!
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\file gd32h75e_dbg.h
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\brief definitions for the DBG
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\version 2025-08-07, V1.2.0, firmware for GD32H75E
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H75E_DBG_H
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#define GD32H75E_DBG_H
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#include "gd32h75e.h"
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/* DBG definitions */
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#define DBG DBG_BASE /*!< DBG base address */
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/* registers definitions */
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#define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */
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#define DBG_CTL0 REG32(DBG + 0x00000004U) /*!< DBG control register 0 */
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#define DBG_CTL1 REG32(DBG + 0x00000034U) /*!< DBG control register 1 */
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#define DBG_CTL2 REG32(DBG + 0x0000003CU) /*!< DBG control register 2 */
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#define DBG_CTL3 REG32(DBG + 0x0000004CU) /*!< DBG control register 3 */
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#define DBG_CTL4 REG32(DBG + 0x00000054U) /*!< DBG control register 4 */
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/* bits definitions */
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/* DBG_ID */
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#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
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/* DBG_CTL0 */
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#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
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#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
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#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
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#define DBG_CTL0_TRACE_MODE BITS(18,19) /*!< trace pin mode selection */
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#define DBG_CTL0_TRACECLKEN BIT(20) /*!< enable trace pin assignment */
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/* DBG_CTL1 */
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#define DBG_CTL1_WWDGT_HOLD BIT(6) /*!< debug WWDGT kept when core is halted */
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/* DBG_CTL2 */
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#define DBG_CTL2_TIMER1_HOLD BIT(0) /*!< debug TIMER1 kept when core is halted */
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#define DBG_CTL2_TIMER2_HOLD BIT(1) /*!< debug TIMER2 kept when core is halted */
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#define DBG_CTL2_TIMER3_HOLD BIT(2) /*!< debug TIMER3 kept when core is halted */
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#define DBG_CTL2_TIMER4_HOLD BIT(3) /*!< debug TIMER4 kept when core is halted */
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#define DBG_CTL2_TIMER5_HOLD BIT(4) /*!< debug TIMER5 kept when core is halted */
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#define DBG_CTL2_TIMER6_HOLD BIT(5) /*!< debug TIMER6 kept when core is halted */
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#define DBG_CTL2_TIMER22_HOLD BIT(6) /*!< debug TIMER22 kept when core is halted */
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#define DBG_CTL2_TIMER23_HOLD BIT(7) /*!< debug TIMER23 kept when core is halted */
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#define DBG_CTL2_TIMER50_HOLD BIT(10) /*!< debug TIMER50 kept when core is halted */
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#define DBG_CTL2_TIMER51_HOLD BIT(11) /*!< debug TIMER51 kept when core is halted */
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#define DBG_CTL2_I2C0_HOLD BIT(21) /*!< debug I2C0 kept when core is halted */
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#define DBG_CTL2_I2C1_HOLD BIT(22) /*!< debug I2C1 kept when core is halted */
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#define DBG_CTL2_I2C2_HOLD BIT(23) /*!< debug I2C2 kept when core is halted */
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#define DBG_CTL2_I2C3_HOLD BIT(24) /*!< debug I2C3 kept when core is halted */
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/* DBG_CTL3 */
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#define DBG_CTL3_TIMER0_HOLD BIT(0) /*!< debug TIMER0 kept when core is halted */
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#define DBG_CTL3_TIMER7_HOLD BIT(1) /*!< debug TIMER7 kept when core is halted */
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#define DBG_CTL3_CAN0_HOLD BIT(2) /*!< debug CAN0 kept when core is halted */
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#define DBG_CTL3_CAN1_HOLD BIT(3) /*!< debug CAN1 kept when core is halted */
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#define DBG_CTL3_CAN2_HOLD BIT(4) /*!< debug CAN2 kept when core is halted */
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#define DBG_CTL3_TIMER14_HOLD BIT(16) /*!< debug TIMER14 kept when core is halted */
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#define DBG_CTL3_TIMER15_HOLD BIT(17) /*!< debug TIMER15 kept when core is halted */
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#define DBG_CTL3_TIMER16_HOLD BIT(18) /*!< debug TIMER16 kept when core is halted */
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#define DBG_CTL3_TIMER40_HOLD BIT(19) /*!< debug TIMER40 kept when core is halted */
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#define DBG_CTL3_TIMER41_HOLD BIT(20) /*!< debug TIMER41 kept when core is halted */
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#define DBG_CTL3_TIMER42_HOLD BIT(21) /*!< debug TIMER42 kept when core is halted */
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#define DBG_CTL3_TIMER43_HOLD BIT(22) /*!< debug TIMER43 kept when core is halted */
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#define DBG_CTL3_TIMER44_HOLD BIT(23) /*!< debug TIMER44 kept when core is halted */
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/* DBG_CTL4 */
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#define DBG_CTL4_RTC_HOLD BIT(16) /*!< debug RTC kept when core is halted */
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#define DBG_CTL4_FWDGT_HOLD BIT(18) /*!< debug FWDGT kept when core is halted */
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/* constants definitions */
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#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
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#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
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#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
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/* define the peripheral debug hold bit position and its register index offset */
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#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
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#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
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#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
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/* register index */
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typedef enum
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{
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DBG_IDX_CTL1 = 0x34U, /*!< DBG control register 1 offset */
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DBG_IDX_CTL2 = 0x3CU, /*!< DBG control register 2 offset */
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DBG_IDX_CTL3 = 0x4CU, /*!< DBG control register 3 offset */
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DBG_IDX_CTL4 = 0x54U /*!< DBG control register 4 offset */
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}dbg_reg_idx;
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/* peripherals hold bit */
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typedef enum
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{
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DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< debug WWDGT kept when core is halted */
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DBG_I2C3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 24U), /*!< debug I2C3 kept when core is halted */
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DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 23U), /*!< debug I2C2 kept when core is halted */
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DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 22U), /*!< debug I2C1 kept when core is halted */
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DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 21U), /*!< debug I2C0 kept when core is halted */
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DBG_TIMER51_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 11U), /*!< debug TIMER51 kept when core is halted */
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DBG_TIMER50_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 10U), /*!< debug TIMER50 kept when core is halted */
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DBG_TIMER23_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 7U), /*!< debug TIMER23 kept when core is halted */
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DBG_TIMER22_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 6U), /*!< debug TIMER22 kept when core is halted */
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DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 5U), /*!< debug TIMER6 kept when core is halted */
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DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 4U), /*!< debug TIMER5 kept when core is halted */
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DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 3U), /*!< debug TIMER4 kept when core is halted */
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DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 2U), /*!< debug TIMER3 kept when core is halted */
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DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< debug TIMER2 kept when core is halted */
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DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< debug TIMER1 kept when core is halted */
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DBG_TIMER44_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 23U), /*!< debug TIMER44 kept when core is halted */
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DBG_TIMER43_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 22U), /*!< debug TIMER43 kept when core is halted */
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DBG_TIMER42_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 21U), /*!< debug TIMER42 kept when core is halted */
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DBG_TIMER41_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 20U), /*!< debug TIMER41 kept when core is halted */
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DBG_TIMER40_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 19U), /*!< debug TIMER40 kept when core is halted */
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DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 18U), /*!< debug TIMER16 kept when core is halted */
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DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 17U), /*!< debug TIMER15 kept when core is halted */
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DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 16U), /*!< debug TIMER14 kept when core is halted */
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DBG_CAN2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 4U), /*!< debug CAN2 kept when core is halted */
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DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 3U), /*!< debug CAN1 kept when core is halted */
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DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 2U), /*!< debug CAN0 kept when core is halted */
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DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 1U), /*!< debug TIMER7 kept when core is halted */
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DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 0U), /*!< debug TIMER0 kept when core is halted */
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DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL4, 18U), /*!< debug FWDGT kept when core is halted */
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DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL4, 16U) /*!< debug RTC kept when core is halted */
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}dbg_periph_enum;
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#define CTL0_TRACE_MODE(regval) (BITS(18,19) & ((uint32_t)(regval) << 18U))
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#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */
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#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
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#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
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#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
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/* parameter check definitions */
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#ifdef FW_DEBUG_ERR_REPORT
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/* check DBG LOW power parameter */
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#define NOT_DBG_LOW_POWER_PARAMETER(parameter) (((parameter) != DBG_LOW_POWER_SLEEP) && ((parameter) != DBG_LOW_POWER_DEEPSLEEP) && \
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((parameter) != DBG_LOW_POWER_STANDBY))
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#define NOT_DBG_TRACE_MODE_PARAMETER(trace_mode) (((trace_mode) != TRACE_MODE_ASYNC) && ((trace_mode) != TRACE_MODE_SYNC_DATASIZE_1) && \
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((trace_mode) != TRACE_MODE_SYNC_DATASIZE_2) && ((trace_mode) != TRACE_MODE_SYNC_DATASIZE_4))
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#endif /* FW_DEBUG_ERR_REPORT */
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/* function declarations */
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/* deinitialize the DBG */
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void dbg_deinit(void);
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/* read DBG_ID code register */
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uint32_t dbg_id_get(void);
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/*enable low power behavior when the mcu is in debug mode*/
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void dbg_low_power_enable(uint32_t dbg_low_power);
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/*disable low power behavior when the mcu is in debug mode*/
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void dbg_low_power_disable(uint32_t dbg_low_power);
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/*enable trace pin assignment*/
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void dbg_trace_pin_enable(void);
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/*disable trace pin assignment*/
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void dbg_trace_pin_disable(void);
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/* set trace pin mode */
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void dbg_trace_pin_mode_set(uint32_t trace_mode);
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/* enable peripheral behavior when the MCU is in debug mode */
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void dbg_periph_enable(dbg_periph_enum dbg_periph);
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/* disable peripheral behavior when the MCU is in debug mode */
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void dbg_periph_disable(dbg_periph_enum dbg_periph);
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#endif /* GD32H75E_DBG_H */
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