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148 lines
9.6 KiB
148 lines
9.6 KiB
5 months ago
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/*!
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\file gd32h75e_ospim.h
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\brief definitions for the OSPIM
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\version 2025-08-07, V1.2.0, firmware for GD32H75E
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H75E_OSPIM_H
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#define GD32H75E_OSPIM_H
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#include "gd32h75e.h"
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/* OSPIM definitions */
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#define OSPIM OSPM_BASE
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#define OSPIM_PCFG0 REG32(OSPIM + 0x00000004U) /*!< OSPI I/O manager port configuration register 0 */
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#define OSPIM_PCFG1 REG32(OSPIM + 0x00000008U) /*!< OSPI I/O manager port configuration register 1 */
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/* OSPIM_PCFG */
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#define OSPIM_PCFG_SCKEN BIT(0) /*!< enable for sck of port 0 */
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#define OSPIM_PCFG_SRCPCK BIT(1) /*!< source selection for sck of port n */
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#define OSPIM_PCFG_NCSEN BIT(8) /*!< enable for csn of port 0 */
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#define OSPIM_PCFG_SRCPCS BIT(9) /*!< source selection for csn of port n */
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#define OSPIM_PCFG_POLEN BIT(16) /*!< enable for IO[3:0] of port 0 */
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#define OSPIM_PCFG_SRCPLIO BITS(17,18) /*!< source selection for IO[3:0] of port 0 */
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#define OSPIM_PCFG_POHEN BIT(24) /*!< enable for IO[7:4] of port 0 */
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#define OSPIM_PCFG_SRCPHIO BITS(25,26) /*!< source selection for IO[7:4] of port 0 */
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/* constants definitions */
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/* ospi io manager configuration struct definitions */
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/* ospim register address */
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#define OSPIM_PCFG(regval) REG32(OSPIM + 0x4U * ((regval) + 1U)) /*!< the address of OSPI manager port configuration register */
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/* ospim register address */
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#define OSPIM_PORT0 0x00U /*!< OSPI manager port 0 */
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#define OSPIM_PORT1 0x01U /*!< OSPI manager port 1 */
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/* SCK of port */
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#define OSPIM_PORT_SCK_DISABLE 0x00000000U /*!< disable SCK of port */
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#define OSPIM_PORT_SCK_ENABLE OSPIM_PCFG_SCKEN /*!< disable SCK of port */
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/* source selection for SCK of port */
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#define OSPIM_SCK_SOURCE_OSPI0_SCK 0x00000000U /*!< the source of SCK is OSPI0_SCK */
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#define OSPIM_SCK_SOURCE_OSPI1_SCK OSPIM_PCFG_SRCPCK /*!< the source of SCK is OSPI1_SCK */
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/* CSN of port */
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#define OSPIM_PORT_CSN_DISABLE 0x00000000U /*!< disable CSN of port */
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#define OSPIM_PORT_CSN_ENABLE OSPIM_PCFG_NCSEN /*!< enable CSN of port */
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/* source selection for CSN of port */
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#define OSPIM_CSN_SOURCE_OSPI0_CSN 0x00000000U /*!< the source of CSN is OSPI0_CSN */
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#define OSPIM_CSN_SOURCE_OSPI1_CSN OSPIM_PCFG_SRCPCS /*!< the source of CSN is OSPI1_CSN */
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/* IO[3:0] of port */
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#define OSPIM_IO_LOW_DISABLE 0x00000000U /*!< disable IO[3:0] of port */
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#define OSPIM_IO_LOW_ENABLE OSPIM_PCFG_POLEN /*!< enable IO[3:0] of port */
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/* source selection for IO[3:0] of port 0 */
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#define OSPIM_SRCPLIO(regval) (BITS(17,18) & ((uint32_t)(regval) << 17U))
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#define OSPIM_SRCPLIO_OSPI0_IO_LOW OSPIM_SRCPLIO(0) /*!< select OSPI0_IO[3:0] in non-multiplexed mode, and select multiplexed IO[3:0] in multiplex mode */
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#define OSPIM_SRCPLIO_OSPI0_IO_HIGH OSPIM_SRCPLIO(1) /*!< select OSPI0_IO[7:4] in non-multiplexed mode, and select multiplexed IO[7:4] in multiplex mode */
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#define OSPIM_SRCPLIO_OSPI1_IO_LOW OSPIM_SRCPLIO(2) /*!< select OSPI1_IO[3:0], only valied in non-multiplexed mode */
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#define OSPIM_SRCPLIO_OSPI1_IO_HIGH OSPIM_SRCPLIO(3) /*!< select OSPI1_IO[7:4], only valied in non-multiplexed mode */
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/* IO[7:4] of port */
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#define OSPIM_IO_HIGH_DISABLE 0x00000000U /*!< disable IO[7:4] of port */
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#define OSPIM_IO_HIGH_ENABLE OSPIM_PCFG_POHEN /*!< enable IO[7:4] of port */
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/* source selection for IO[7:4] of port n */
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#define OSPIM_SRCPHIO(regval) (BITS(25,26) & ((uint32_t)(regval) << 25U))
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#define OSPIM_SRCPHIO_OSPI0_IO_LOW OSPIM_SRCPHIO(0) /*!< select OSPI0_IO[3:0] in non-multiplexed mode, and select multiplexed IO[3:0] in multiplex mode */
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#define OSPIM_SRCPHIO_OSPI0_IO_HIGH OSPIM_SRCPHIO(1) /*!< select OSPI0_IO[7:4] in non-multiplexed mode, and select multiplexed IO[7:4] in multiplex mode */
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#define OSPIM_SRCPHIO_OSPI1_IO_LOW OSPIM_SRCPHIO(2) /*!< select OSPI1_IO[3:0], only valied in non-multiplexed mode */
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#define OSPIM_SRCPHIO_OSPI1_IO_HIGH OSPIM_SRCPHIO(3) /*!< select OSPI1_IO[7:4], only valied in non-multiplexed mode */
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/* parameter check definitions */
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#ifdef FW_DEBUG_ERR_REPORT
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/* check OSPIM port */
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#define NOT_OSPIM_PORT(port) (((port) != OSPIM_PORT0) && ((port) != OSPIM_PORT1))
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/* check OSPIM port sck configuration */
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#define NOT_OSPIM_PORT_SCK(sckconfg) (((sckconfg) != OSPIM_PORT_SCK_DISABLE) && ((sckconfg) != OSPIM_PORT_SCK_ENABLE))
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/* check OSPIM port sck source */
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#define NOT_OSPIM_PORT_SCK_SOURCE(sck_source) (((sck_source) != OSPIM_SCK_SOURCE_OSPI0_SCK) && ((sck_source) != OSPIM_SCK_SOURCE_OSPI1_SCK))
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/* check OSPIM port CSN configuration */
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#define NOT_OSPIM_PORT_CSN(csnconfig) (((csnconfig) != OSPIM_PORT_CSN_DISABLE) && ((csnconfig) != OSPIM_PORT_CSN_ENABLE))
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/* check OSPIM port CSN source */
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#define NOT_OSPIM_PORT_CSN_SOURCE(csn_source) (((csn_source) != OSPIM_CSN_SOURCE_OSPI0_CSN) && ((csn_source) != OSPIM_CSN_SOURCE_OSPI1_CSN))
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/* check OSPIM IO[3:0] configuration */
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#define NOT_OSPIM_IO_LOW(ioconfig) (((ioconfig) != OSPIM_IO_LOW_DISABLE) && ((ioconfig) != OSPIM_IO_LOW_ENABLE))
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/* check the source of OSPIM IO[3:0] */
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#define NOT_OSPIM_SRC_LOW(io_source) (((io_source) != OSPIM_SRCPLIO_OSPI0_IO_LOW) && ((io_source) != OSPIM_SRCPLIO_OSPI0_IO_HIGH) && ((io_source) != OSPIM_SRCPLIO_OSPI1_IO_LOW) && ((io_source) != OSPIM_SRCPLIO_OSPI1_IO_HIGH))
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/* check OSPIM IO[7:4] configuration */
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#define NOT_OSPIM_IO_HIGH(ioconfig) (((ioconfig) != OSPIM_IO_HIGH_DISABLE) && ((ioconfig) != OSPIM_IO_HIGH_ENABLE))
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/* check the source of OSPIM IO[7:4] */
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#define NOT_OSPIM_SRC_HIGH(io_source) (((io_source) != OSPIM_SRCPHIO_OSPI0_IO_LOW) && ((io_source) != OSPIM_SRCPHIO_OSPI0_IO_HIGH) && ((io_source) != OSPIM_SRCPHIO_OSPI1_IO_LOW) && ((io_source) != OSPIM_SRCPHIO_OSPI1_IO_HIGH))
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#endif /* FW_DEBUG_ERR_REPORT */
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/* function declarations */
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/* reset the OSPIM peripheral */
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void ospim_deinit(void);
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/* ospim port configuration functions */
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/* configurate SCK for port */
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void ospim_port_sck_config(uint8_t port, uint32_t sckconfg);
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/* select source of SCK for port */
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void ospim_port_sck_source_select(uint8_t port, uint32_t sck_source);
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/* configurate CSN for port */
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void ospim_port_csn_config(uint8_t port, uint32_t csnconfig);
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/* select source of CSN for port */
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void ospim_port_csn_source_select(uint8_t port, uint32_t csn_source);
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/* configurate IO[3:0] for port */
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void ospim_port_io3_0_config(uint8_t port, uint32_t ioconfig);
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/* select source of IO[3:0] for port */
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void ospim_port_io3_0_source_select(uint8_t port, uint32_t io_source);
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/* configurate IO[7:4] for port */
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void ospim_port_io7_4_config(uint8_t port, uint32_t ioconfig);
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/* select source of IO[7:4] for port */
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void ospim_port_io7_4_source_select(uint8_t port, uint32_t io_source);
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#endif /* GD32H75E_OSPIM_H */
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