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204 lines
17 KiB
204 lines
17 KiB
5 months ago
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/*!
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\file gd32h75e_rameccmu.h
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\brief definitions for the RAMECCMU
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\version 2025-08-07, V1.2.0, firmware for GD32H75E
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H75E_RAMECCMU_H
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#define GD32H75E_RAMECCMU_H
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#include "gd32h75e.h"
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/* RAMECCMU definitions */
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#define RAMECCMU0 (RAMECCMU_BASE + 0x09FE6000U) /*!< RAMECCMU for Region 0 */
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#define RAMECCMU1 RAMECCMU_BASE /*!< RAMECCMU for Region 1 */
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/* registers definitions */
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#define RAMECCMU_INT(rameccmux) REG32((rameccmux) + 0x00000000U) /*!< RAMECCMU global interruput register */
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#define RAMECCMU_M0CTL(rameccmux) REG32((rameccmux) + 0x00000020U) /*!< RAMECCMU monitor 0 control register */
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#define RAMECCMU_M0STAT(rameccmux) REG32((rameccmux) + 0x00000024U) /*!< RAMECCMU monitor 0 status register */
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#define RAMECCMU_M0FADDR(rameccmux) REG32((rameccmux) + 0x00000028U) /*!< RAMECCMU monitor 0 ECC failing address register */
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#define RAMECCMU_M0FDL(rameccmux) REG32((rameccmux) + 0x0000002CU) /*!< RAMECCMU monitor 0 ECC failing data low register */
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#define RAMECCMU_M0FDH(rameccmux) REG32((rameccmux) + 0x00000030U) /*!< RAMECCMU monitor 0 ECC failing data high register */
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#define RAMECCMU_M0FECODE(rameccmux) REG32((rameccmux) + 0x00000034U) /*!< RAMECCMU monitor 0 failing ECC error code register */
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#define RAMECCMU_M1CTL(rameccmux) REG32((rameccmux) + 0x00000040U) /*!< RAMECCMU monitor 1 control register */
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#define RAMECCMU_M1STAT(rameccmux) REG32((rameccmux) + 0x00000044U) /*!< RAMECCMU monitor 1 status register */
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#define RAMECCMU_M1FADDR(rameccmux) REG32((rameccmux) + 0x00000048U) /*!< RAMECCMU monitor 1 ECC failing address register */
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#define RAMECCMU_M1FDL(rameccmux) REG32((rameccmux) + 0x0000004CU) /*!< RAMECCMU monitor 1 ECC failing data low register */
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#define RAMECCMU_M1FDH(rameccmux) REG32((rameccmux) + 0x00000050U) /*!< RAMECCMU monitor 1 ECC failing data high register */
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#define RAMECCMU_M1FECODE(rameccmux) REG32((rameccmux) + 0x00000054U) /*!< RAMECCMU monitor 1 failing ECC error code register */
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#define RAMECCMU_M2CTL(rameccmux) REG32((rameccmux) + 0x00000060U) /*!< RAMECCMU monitor 2 control register */
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#define RAMECCMU_M2STAT(rameccmux) REG32((rameccmux) + 0x00000064U) /*!< RAMECCMU monitor 2 status register */
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#define RAMECCMU_M2FADDR(rameccmux) REG32((rameccmux) + 0x00000068U) /*!< RAMECCMU monitor 2 ECC failing address register */
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#define RAMECCMU_M2FDL(rameccmux) REG32((rameccmux) + 0x0000006CU) /*!< RAMECCMU monitor 2 ECC failing data low register */
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#define RAMECCMU_M2FDH(rameccmux) REG32((rameccmux) + 0x00000070U) /*!< RAMECCMU monitor 2 ECC failing data high register */
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#define RAMECCMU_M2FECODE(rameccmux) REG32((rameccmux) + 0x00000074U) /*!< RAMECCMU monitor 2 failing ECC error code register */
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#define RAMECCMU_M3CTL(rameccmux) REG32((rameccmux) + 0x00000080U) /*!< RAMECCMU monitor 3 control register */
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#define RAMECCMU_M3STAT(rameccmux) REG32((rameccmux) + 0x00000084U) /*!< RAMECCMU monitor 3 status register */
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#define RAMECCMU_M3FADDR(rameccmux) REG32((rameccmux) + 0x00000088U) /*!< RAMECCMU monitor 3 ECC failing address register */
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#define RAMECCMU_M3FDL(rameccmux) REG32((rameccmux) + 0x0000008CU) /*!< RAMECCMU monitor 3 ECC failing data low register */
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#define RAMECCMU_M3FDH(rameccmux) REG32((rameccmux) + 0x00000090U) /*!< RAMECCMU monitor 3 ECC failing data high register */
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#define RAMECCMU_M3FECODE(rameccmux) REG32((rameccmux) + 0x00000094U) /*!< RAMECCMU monitor 3 failing ECC error code register */
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#define RAMECCMU_M4CTL(rameccmux) REG32((rameccmux) + 0x000000A0U) /*!< RAMECCMU monitor 4 control register */
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#define RAMECCMU_M4STAT(rameccmux) REG32((rameccmux) + 0x000000A4U) /*!< RAMECCMU monitor 4 status register */
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#define RAMECCMU_M4FADDR(rameccmux) REG32((rameccmux) + 0x000000A8U) /*!< RAMECCMU monitor 4 ECC failing address register */
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#define RAMECCMU_M4FDL(rameccmux) REG32((rameccmux) + 0x000000ACU) /*!< RAMECCMU monitor 4 ECC failing data low register */
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#define RAMECCMU_M4FDH(rameccmux) REG32((rameccmux) + 0x000000B0U) /*!< RAMECCMU monitor 4 ECC failing data high register */
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#define RAMECCMU_M4FECODE(rameccmux) REG32((rameccmux) + 0x000000B4U) /*!< RAMECCMU monitor 4 failing ECC error code register */
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/* bits definitions */
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/* RAMECCMU_INT */
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#define RAMECCMU_INT_GEIE BIT(0) /*!< global ECC interrupt enable */
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#define RAMECCMU_INT_GESERRIE BIT(1) /*!< global ECC single error interrupt enable */
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#define RAMECCMU_INT_GEDERRIE BIT(2) /*!< global ECC double error interrupt enable */
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#define RAMECCMU_INT_GEDERRBWIE BIT(3) /*!< global ECC double error on byte write interrupt enable */
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/* RAMECCMU_MxCTL */
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#define RAMECCMU_MXCTL_ECCSERRIE BIT(2) /*!< ECC single error interrupt enable */
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#define RAMECCMU_MXCTL_ECCDERRIE BIT(3) /*!< ECC double error interrupt enable */
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#define RAMECCMU_MXCTL_ECCDERRBWIE BIT(4) /*!< ECC double error on byte write interrupt enable */
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#define RAMECCMU_MXCTL_ECCERRLATEN BIT(5) /*!< ECC error latching enable */
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/* RAMECCMU_MxSTAT */
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#define RAMECCMU_MXSTAT_ECCSERRDCF BIT(0) /*!< ECC single error detected and corrected flag */
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#define RAMECCMU_MXSTAT_ECCDERRDF BIT(1) /*!< ECC double error detected flag */
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#define RAMECCMU_MXSTAT_ECCDERRBWDF BIT(2) /*!< ECC double error on byte write detected flag */
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/* RAMECCMU_MxFADDR */
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#define RAMECCMU_MXFADDR_ECCFADDR BITS(0,31) /*!< ECC error failing address */
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/* RAMECCMU_MxFDL */
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#define RAMECCMU_MXFDL_ECCFDL BITS(0,31) /*!< ECC failing data low bits */
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/* RAMECCMU_MxFDH */
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#define RAMECCMU_MXFDH_ECCFDH BITS(0,31) /*!< ECC failing data high bits */
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/* RAMECCMU_MxFECODE */
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#define RAMECCMU_MXFECODE_ECCFECODE BITS(0,31) /*!< ECC failing error code */
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/* constants definitions */
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/* RAMECCMU monitor select */
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typedef enum
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{
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RAMECCMU0_MONITOR0 = 0x00U, /*!< RAMECCMU0 monitor 0 */
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RAMECCMU0_MONITOR1 = 0x01U, /*!< RAMECCMU0 monitor 1 */
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RAMECCMU0_MONITOR2 = 0x02U, /*!< RAMECCMU0 monitor 2 */
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RAMECCMU0_MONITOR3 = 0x03U, /*!< RAMECCMU0 monitor 3 */
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RAMECCMU0_MONITOR4 = 0x04U, /*!< RAMECCMU0 monitor 4 */
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RAMECCMU1_MONITOR0 = 0x10U, /*!< RAMECCMU1 monitor 0 */
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RAMECCMU1_MONITOR1 = 0x11U, /*!< RAMECCMU1 monitor 1 */
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RAMECCMU1_MONITOR2 = 0x12U /*!< RAMECCMU1 monitor 2 */
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} rameccmu_monitor_enum;
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/* RAMECCMUx monitor register address */
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#define RAMECCMU_MXCTL(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x20U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor control register */
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#define RAMECCMU_MXSTAT(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x24U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor status register */
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#define RAMECCMU_MXFADDR(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x28U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing address register */
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#define RAMECCMU_MXFDL(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x2CU + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing data low register */
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#define RAMECCMU_MXFDH(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x30U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing data high register */
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#define RAMECCMU_MXFECODE(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x34U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor failing ECC error code register */
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#define RAMECCMU_INT_ECC_GLOBAL_ERROR BIT(0) /*!< ECC global error interrupt */
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#define RAMECCMU_INT_ECC_SINGLE_ERROR BIT(1) /*!< ECC single error interrupt */
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#define RAMECCMU_INT_ECC_DOUBLE_ERROR BIT(2) /*!< ECC double error interrupt */
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#define RAMECCMU_INT_ECC_DOUBLE_ERROR_BYTE_WRITE BIT(3) /*!< ECC double error on byte write interrupt */
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#define RAMECCMU_INT_ECC_ERROR_LATCHING BIT(4) /*!< ECC error latching */
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#define RAMECCMU_FLAG_ECC_SINGLE_ERROR RAMECCMU_MXSTAT_ECCSERRDCF /*!< ECC single error detected and corrected flag */
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#define RAMECCMU_FLAG_ECC_DOUBLE_ERROR RAMECCMU_MXSTAT_ECCDERRDF /*!< ECC double error detected flag */
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#define RAMECCMU_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE RAMECCMU_MXSTAT_ECCDERRBWDF /*!< ECC double error on byte write detected flag */
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#define RAMECCMU_INT_FLAG_ECC_SINGLE_ERROR RAMECCMU_MXSTAT_ECCSERRDCF /*!< ECC single error detected and corrected flag */
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#define RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR RAMECCMU_MXSTAT_ECCDERRDF /*!< ECC double error detected flag */
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#define RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE RAMECCMU_MXSTAT_ECCDERRBWDF /*!< ECC double error on byte write detected flag */
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/* parameter check definitions */
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#ifdef FW_DEBUG_ERR_REPORT
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#define NOT_RAMECCMU_PERIPH(xxx) (((xxx) != RAMECCMU0) && ((xxx) != RAMECCMU1))
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#define NOT_RAMECCMU_MONITOR(xxx) (((xxx) != RAMECCMU0_MONITOR0) && ((xxx) != RAMECCMU0_MONITOR1) && \
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((xxx) != RAMECCMU0_MONITOR2) && ((xxx) != RAMECCMU0_MONITOR3) && \
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((xxx) != RAMECCMU0_MONITOR4) && ((xxx) != RAMECCMU1_MONITOR0) && \
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((xxx) != RAMECCMU1_MONITOR1) && ((xxx) != RAMECCMU1_MONITOR2))
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#define NOT_RAMECCMU_INT_ERROR(xxx) (((xxx) != RAMECCMU_INT_ECC_GLOBAL_ERROR) && ((xxx) != RAMECCMU_INT_ECC_SINGLE_ERROR) && \
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((xxx) != RAMECCMU_INT_ECC_DOUBLE_ERROR) && ((xxx) != RAMECCMU_INT_ECC_DOUBLE_ERROR_BYTE_WRITE))
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#define NOT_RAMECCMU_MONITOR_INT_ERROR(xxx) (((xxx) != RAMECCMU_INT_ECC_SINGLE_ERROR) && ((xxx) != RAMECCMU_INT_ECC_DOUBLE_ERROR) && \
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((xxx) != RAMECCMU_INT_ECC_DOUBLE_ERROR_BYTE_WRITE) && ((xxx) != RAMECCMU_INT_ECC_ERROR_LATCHING))
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#define NOT_RAMECCMU_FLAG_ECC_ERROR(xxx) (((xxx) != RAMECCMU_FLAG_ECC_SINGLE_ERROR) && ((xxx) != RAMECCMU_FLAG_ECC_DOUBLE_ERROR) && \
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((xxx) != RAMECCMU_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE))
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#define NOT_RAMECCMU_INT_FLAG_ECC_ERROR(xxx) (((xxx) != RAMECCMU_INT_FLAG_ECC_SINGLE_ERROR) && ((xxx) != RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR) && \
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((xxx) != RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE))
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#endif /* FW_DEBUG_ERR_REPORT */
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/* function declarations */
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/* deinit RAMECCMU unit */
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void rameccmu_deinit(uint32_t rameccmu_periph);
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/* RAMECCMU monitor ECC functions */
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/* get RAMECCMU monitor ECC failing address */
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uint32_t rameccmu_monitor_failing_address_get(rameccmu_monitor_enum rameccmu_monitor);
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/* get RAMECCMU monitor ECC failing data low 32 bits */
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uint32_t rameccmu_monitor_failing_data_low_bits_get(rameccmu_monitor_enum rameccmu_monitor);
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/* get RAMECCMU monitor ECC failing data high 32 bits */
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uint32_t rameccmu_monitor_failing_data_high_bits_get(rameccmu_monitor_enum rameccmu_monitor);
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/* get RAMECCMU monitor failing ECC error code */
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uint32_t rameccmu_monitor_failing_ecc_error_code_get(rameccmu_monitor_enum rameccmu_monitor);
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/* interrupt & flag functions */
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/* enable RAMECCMU global ECC interruput */
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void rameccmu_global_interrupt_enable(uint32_t rameccmu_periph, uint32_t interrupt);
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/* disable RAMECCMU global ECC interruput */
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void rameccmu_global_interrupt_disable(uint32_t rameccmu_periph, uint32_t interrupt);
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/* enable RAMECCMU monitor ECC error interruput */
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void rameccmu_monitor_interrupt_enable(rameccmu_monitor_enum rameccmu_monitor, uint32_t monitor_interrupt);
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/* disable RAMECCMU monitor ECC error interruput */
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void rameccmu_monitor_interrupt_disable(rameccmu_monitor_enum rameccmu_monitor, uint32_t monitor_interrupt);
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/* get RAMECCMU monitor ECC error flag */
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FlagStatus rameccmu_monitor_flag_get(rameccmu_monitor_enum rameccmu_monitor, uint32_t flag);
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/* clear RAMECCMU monitor ECC error flag */
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void rameccmu_monitor_flag_clear(rameccmu_monitor_enum rameccmu_monitor, uint32_t flag);
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/* get RAMECCMU monitor ECC interrupt error flag */
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FlagStatus rameccmu_monitor_interrupt_flag_get(rameccmu_monitor_enum rameccmu_monitor, uint32_t int_flag);
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/* clear RAMECCMU monitor interrupt ECC error flag */
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void rameccmu_monitor_interrupt_flag_clear(rameccmu_monitor_enum rameccmu_monitor, uint32_t int_flag);
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#endif /* GD32H75E_RAMECCMU_H */
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