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198 lines
12 KiB
198 lines
12 KiB
5 months ago
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/*!
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\file gd32h75e_tmu.h
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\brief definitions for the TMU
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\version 2025-08-07, V1.2.0, firmware for GD32H75E
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H75E_TMU_H
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#define GD32H75E_TMU_H
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#include "gd32h75e.h"
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/* TMU definitions */
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#define TMU TMU_BASE
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/* registers definitions */
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#define TMU_CS REG32(TMU + 0x00000000U) /*!< TMU control and status register */
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#define TMU_IDATA REG32(TMU + 0x00000004U) /*!< TMU input data register */
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#define TMU_ODATA REG32(TMU + 0x00000008U) /*!< TMU output data register */
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/* bits definitions */
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/* TMU_CS */
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#define TMU_CS_MODE BITS(0,3) /*!< TMU operation mode selection */
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#define TMU_CS_ITRTNUM BITS(4,7) /*!< number of iterations selection */
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#define TMU_CS_FACTOR BITS(8,10) /*!< scaling factor */
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#define TMU_CS_RIE BIT(16) /*!< read TMU_ODATA interrupt enable */
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#define TMU_CS_RDEN BIT(17) /*!< read TMU_ODATA DMA request enable */
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#define TMU_CS_WDEN BIT(18) /*!< write TMU_IDATA DMA request enable */
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#define TMU_CS_ONUM BIT(19) /*!< times the TMU_ODATA needs to be read */
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#define TMU_CS_INUM BIT(20) /*!< times the TMU_IDATA needs to be write */
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#define TMU_CS_OWIDTH BIT(21) /*!< width of output data */
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#define TMU_CS_IWIDTH BIT(22) /*!< width of input data */
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#define TMU_CS_ENDF BIT(31) /*!< end of TMU operation flag */
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/* TMU_IDATA */
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#define TMU_IDATA_IDATA BITS(0,31) /*!< the input data of TMU operation */
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/* TMU_ODATA */
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#define TMU_ODATA_ODATA BITS(0,31) /*!< the output data of TMU operation */
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/* constants definitions */
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/* TMU init parameter struct definitions */
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typedef struct
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{
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uint32_t mode; /*!< mode of TMU operation */
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uint32_t iterations_number; /*!< number of iterations selection */
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uint32_t scale; /*!< scaling factor */
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uint32_t dma_read; /*!< DMA request to read TMU_ODATA */
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uint32_t dma_write; /*!< DMA request to write TMU_IDATA */
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uint32_t read_times; /*!< times the TMU_ODATA needs to be read */
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uint32_t write_times; /*!< times the TMU_IDATA needs to be write */
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uint32_t output_width; /*!< width of output data */
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uint32_t input_width; /*!< width of input data */
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}tmu_parameter_struct;
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/* TMU mode definitions */
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#define TMU_MODE(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
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#define TMU_MODE_COS TMU_MODE(0) /*!< mode0: m*cos(��) */
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#define TMU_MODE_SIN TMU_MODE(1) /*!< mode1: m*sin(��) */
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#define TMU_MODE_ATAN2 TMU_MODE(2) /*!< mode2: atan2(y,x) */
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#define TMU_MODE_MODULUS TMU_MODE(3) /*!< mode3: sqrt(x^2+y^2) */
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#define TMU_MODE_ATAN TMU_MODE(4) /*!< mode4: atan(x) */
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#define TMU_MODE_COSH TMU_MODE(5) /*!< mode5: cosh(x) */
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#define TMU_MODE_SINH TMU_MODE(6) /*!< mode6: sinh(x) */
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#define TMU_MODE_ATANH TMU_MODE(7) /*!< mode7: atanh(x) */
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#define TMU_MODE_LN TMU_MODE(8) /*!< mode8: ln(x) */
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#define TMU_MODE_SQRT TMU_MODE(9) /*!< mode9: sqrt(x) */
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/* TMU number of iterations definitions */
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#define ITERATIONS(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
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#define TMU_ITERATION_STEPS_4 ITERATIONS(1) /*!< 4 iteration steps */
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#define TMU_ITERATION_STEPS_8 ITERATIONS(2) /*!< 8 iteration steps */
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#define TMU_ITERATION_STEPS_12 ITERATIONS(3) /*!< 12 iteration steps */
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#define TMU_ITERATION_STEPS_16 ITERATIONS(4) /*!< 16 iteration steps */
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#define TMU_ITERATION_STEPS_20 ITERATIONS(5) /*!< 20 iteration steps */
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#define TMU_ITERATION_STEPS_24 ITERATIONS(6) /*!< 24 iteration steps */
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/* TMU scaling factor definitions */
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#define SCALE(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
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#define TMU_SCALING_FACTOR_1 SCALE(0) /*!< scaling factor = 1 */
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#define TMU_SCALING_FACTOR_2 SCALE(1) /*!< scaling factor = 2 */
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#define TMU_SCALING_FACTOR_4 SCALE(2) /*!< scaling factor = 4 */
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#define TMU_SCALING_FACTOR_8 SCALE(3) /*!< scaling factor = 8 */
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#define TMU_SCALING_FACTOR_16 SCALE(4) /*!< scaling factor = 16 */
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#define TMU_SCALING_FACTOR_32 SCALE(5) /*!< scaling factor = 32 */
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#define TMU_SCALING_FACTOR_64 SCALE(6) /*!< scaling factor = 64 */
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#define TMU_SCALING_FACTOR_128 SCALE(7) /*!< scaling factor = 128 */
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/* TMU DMA read enable definitions */
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#define TMU_READ_DMA_DISABLE ((uint32_t)0x00000000U) /*!< disable DMA request to read TMU_ODATA */
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#define TMU_READ_DMA_ENABLE TMU_CS_RDEN /*!< enable DMA request to read TMU_ODATA */
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/* TMU DMA write enable definitions */
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#define TMU_WRITE_DMA_DISABLE ((uint32_t)0x00000000U) /*!< disable DMA request to write TMU_IDATA */
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#define TMU_WRITE_DMA_ENABLE TMU_CS_WDEN /*!< enable DMA request to write TMU_IDATA */
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/* TMU_ODATA read times definitions */
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#define TMU_READ_TIMES_1 ((uint32_t)0x00000000U) /*!< one 32-bit read operation */
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#define TMU_READ_TIMES_2 TMU_CS_ONUM /*!< two 32-bit read operation */
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/* TMU_IDATA write times definitions */
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#define TMU_WRITE_TIMES_1 ((uint32_t)0x00000000U) /*!< one 32-bit write operation */
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#define TMU_WRITE_TIMES_2 TMU_CS_INUM /*!< two 32-bit write operation */
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/* TMU output data width definitions */
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#define TMU_OUTPUT_WIDTH_32 ((uint32_t)0x00000000U) /*!< TMU_ODATA contains the output data in q1.31 format */
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#define TMU_OUTPUT_WIDTH_16 TMU_CS_OWIDTH /*!< TMU_ODATA contains the output data in q1.15 format */
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/* TMU input data width definitions */
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#define TMU_INPUT_WIDTH_32 ((uint32_t)0x00000000U) /*!< TMU_IDATA contains the input data in q1.31 format */
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#define TMU_INPUT_WIDTH_16 TMU_CS_IWIDTH /*!< TMU_IDATA contains the input data in q1.15 format */
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/* parameter check definitions */
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#ifdef FW_DEBUG_ERR_REPORT
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/* check init parameter struct */
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#define NOT_TMU_MODE(mode) (((mode) != (TMU_MODE_COS)) && ((mode) != (TMU_MODE_SIN))&& ((mode) != (TMU_MODE_ATAN2)) && \
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((mode) != (TMU_MODE_MODULUS)) && ((mode) != (TMU_MODE_ATAN))&& ((mode) != (TMU_MODE_COSH)) && \
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((mode) != (TMU_MODE_SINH)) && ((mode) != (TMU_MODE_ATANH))&& ((mode) != (TMU_MODE_LN)) && \
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((mode) != (TMU_MODE_SQRT)))
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#define NOT_TMU_ITERATIONS_NUM(num) (((num) != (TMU_ITERATION_STEPS_4)) && ((num) != (TMU_ITERATION_STEPS_8))&& ((num) != (TMU_ITERATION_STEPS_12)) && \
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((num) != (TMU_ITERATION_STEPS_16)) && ((num) != (TMU_ITERATION_STEPS_20))&& ((num) != (TMU_ITERATION_STEPS_24)))
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#define NOT_TMU_SCALE_FACTOR(scale) (((scale) != (TMU_SCALING_FACTOR_1)) && ((scale) != (TMU_SCALING_FACTOR_2))&& ((scale) != (TMU_SCALING_FACTOR_4)) && \
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((scale) != (TMU_SCALING_FACTOR_8)) && ((scale) != (TMU_SCALING_FACTOR_16))&& ((scale) != (TMU_SCALING_FACTOR_32)) && \
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((scale) != (TMU_SCALING_FACTOR_64)) && ((scale) != (TMU_SCALING_FACTOR_128)))
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#define NOT_TMU_DMA_READ(dma_read) (((dma_read) != (TMU_READ_DMA_DISABLE)) && ((dma_read) != (TMU_READ_DMA_ENABLE)))
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#define NOT_TMU_DMA_WRITE(dma_write) (((dma_write) != (TMU_WRITE_DMA_DISABLE)) && ((dma_write) != (TMU_WRITE_DMA_ENABLE)))
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#define NOT_TMU_READ_TIMES(read_times) (((read_times) != (TMU_READ_TIMES_1)) && ((read_times) != (TMU_READ_TIMES_2)))
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#define NOT_TMU_WRITE_TIMES(write_times) (((write_times) != (TMU_WRITE_TIMES_1)) && ((write_times) != (TMU_WRITE_TIMES_2)))
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#define NOT_TMU_OUTPUT_WIDTH(output_width) (((output_width) != (TMU_OUTPUT_WIDTH_32)) && ((output_width) != (TMU_OUTPUT_WIDTH_16)))
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#define NOT_TMU_INPUT_WIDTH(input_width) (((input_width) != (TMU_INPUT_WIDTH_32)) && ((input_width) != (TMU_INPUT_WIDTH_16)))
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#endif /* FW_DEBUG_ERR_REPORT */
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/* function declarations */
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/* initialization functions */
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/* reset the TMU registers */
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void tmu_deinit(void);
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/* initialize the parameters of TMU struct with the default values */
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void tmu_struct_para_init(tmu_parameter_struct* init_struct);
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/* initialize TMU */
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void tmu_init(tmu_parameter_struct* init_struct);
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/* interrupt and dma configuration */
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/* enable TMU read interrupt */
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void tmu_read_interrupt_enable(void);
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/* disable TMU read interrupt */
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void tmu_read_interrupt_disable(void);
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/* enable TMU DMA read request */
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void tmu_dma_read_enable(void);
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/* disable TMU DMA read request */
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void tmu_dma_read_disable(void);
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/* enable TMU DMA write request */
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void tmu_dma_write_enable(void);
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/* disable TMU DMA write request */
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void tmu_dma_write_disable(void);
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/* TMU data write and read */
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/* write one data in q1.31 format */
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void tmu_one_q31_write(uint32_t data);
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/* write two data in q1.31 format */
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void tmu_two_q31_write(uint32_t data1, uint32_t data2);
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/* write two data in q1.15 format */
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void tmu_two_q15_write(uint16_t data1, uint16_t data2);
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/* read one data in q1.31 format */
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void tmu_one_q31_read(uint32_t* p);
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/* read two data in q1.31 format */
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void tmu_two_q31_read(uint32_t* p1, uint32_t* p2);
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/* read two data in q1.15 format */
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void tmu_two_q15_read(uint16_t* p1, uint16_t* p2);
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#endif /* GD32H75E_TMU_H */
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