sc/828eco
1
0 Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

创建

Browse Source
This commit is contained in:
sc committed 2026-02-14 19:03:02 +08:00
commit da43152a7e
3380 files changed
+1128754
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

828ECO/drivers/include/config/adc_config.h
+438
View File
@@ -0,0 +1,438 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-10-15 LZerro compatible with RT-Studio
* 2025-10-22 kurisaw optimize multi-channel GPIO configuration
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#include <rtthread.h>
#include <board.h>
#ifdef __cplusplus
extern "C"
{
#endif
#include "drv_adc.h"
#ifdef RT_USING_ADC
#define MAX_EXTERN_ADC_CHANNEL 20
#endif
#ifdef BSP_USING_ADC0
#ifdef BSP_ADC0_CH0_PIN
#define ADC0_CH0_PIN BSP_ADC0_CH0_PIN
#else
#define ADC0_CH0_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH1_PIN
#define ADC0_CH1_PIN BSP_ADC0_CH1_PIN
#else
#define ADC0_CH1_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH2_PIN
#define ADC0_CH2_PIN BSP_ADC0_CH2_PIN
#else
#define ADC0_CH2_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH3_PIN
#define ADC0_CH3_PIN BSP_ADC0_CH3_PIN
#else
#define ADC0_CH3_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH4_PIN
#define ADC0_CH4_PIN BSP_ADC0_CH4_PIN
#else
#define ADC0_CH4_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH5_PIN
#define ADC0_CH5_PIN BSP_ADC0_CH5_PIN
#else
#define ADC0_CH5_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH6_PIN
#define ADC0_CH6_PIN BSP_ADC0_CH6_PIN
#else
#define ADC0_CH6_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH7_PIN
#define ADC0_CH7_PIN BSP_ADC0_CH7_PIN
#else
#define ADC0_CH7_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH8_PIN
#define ADC0_CH8_PIN BSP_ADC0_CH8_PIN
#else
#define ADC0_CH8_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH9_PIN
#define ADC0_CH9_PIN BSP_ADC0_CH9_PIN
#else
#define ADC0_CH9_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH10_PIN
#define ADC0_CH10_PIN BSP_ADC0_CH10_PIN
#else
#define ADC0_CH10_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH11_PIN
#define ADC0_CH11_PIN BSP_ADC0_CH11_PIN
#else
#define ADC0_CH11_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH12_PIN
#define ADC0_CH12_PIN BSP_ADC0_CH12_PIN
#else
#define ADC0_CH12_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH13_PIN
#define ADC0_CH13_PIN BSP_ADC0_CH13_PIN
#else
#define ADC0_CH13_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH14_PIN
#define ADC0_CH14_PIN BSP_ADC0_CH14_PIN
#else
#define ADC0_CH14_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH15_PIN
#define ADC0_CH15_PIN BSP_ADC0_CH15_PIN
#else
#define ADC0_CH15_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH16_PIN
#define ADC0_CH16_PIN BSP_ADC0_CH16_PIN
#else
#define ADC0_CH16_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH17_PIN
#define ADC0_CH17_PIN BSP_ADC0_CH17_PIN
#else
#define ADC0_CH17_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH18_PIN
#define ADC0_CH18_PIN BSP_ADC0_CH18_PIN
#else
#define ADC0_CH18_PIN RT_NULL
#endif
#ifdef BSP_ADC0_CH19_PIN
#define ADC0_CH19_PIN BSP_ADC0_CH19_PIN
#else
#define ADC0_CH19_PIN RT_NULL
#endif
#ifndef ADC0_CONFIG
#define ADC0_CONFIG \
{ \
ADC0, \
RCU_ADC0, \
{ \
ADC0_CH0_PIN, \
ADC0_CH1_PIN, \
ADC0_CH2_PIN, \
ADC0_CH3_PIN, \
ADC0_CH4_PIN, \
ADC0_CH5_PIN, \
ADC0_CH6_PIN, \
ADC0_CH7_PIN, \
ADC0_CH8_PIN, \
ADC0_CH9_PIN, \
ADC0_CH10_PIN, \
ADC0_CH11_PIN, \
ADC0_CH12_PIN, \
ADC0_CH13_PIN, \
ADC0_CH14_PIN, \
ADC0_CH15_PIN, \
ADC0_CH16_PIN, \
ADC0_CH17_PIN, \
ADC0_CH18_PIN, \
ADC0_CH19_PIN, \
}, \
&adc0, \
"adc0", \
}
#endif /* ADC0_CONFIG */
#endif /* BSP_USING_ADC0 */
#ifdef BSP_USING_ADC1
#ifdef BSP_ADC1_CH0_PIN
#define ADC1_CH0_PIN BSP_ADC1_CH0_PIN
#else
#define ADC1_CH0_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH1_PIN
#define ADC1_CH1_PIN BSP_ADC1_CH1_PIN
#else
#define ADC1_CH1_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH2_PIN
#define ADC1_CH2_PIN BSP_ADC1_CH2_PIN
#else
#define ADC1_CH2_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH3_PIN
#define ADC1_CH3_PIN BSP_ADC1_CH3_PIN
#else
#define ADC1_CH3_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH4_PIN
#define ADC1_CH4_PIN BSP_ADC1_CH4_PIN
#else
#define ADC1_CH4_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH5_PIN
#define ADC1_CH5_PIN BSP_ADC1_CH5_PIN
#else
#define ADC1_CH5_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH6_PIN
#define ADC1_CH6_PIN BSP_ADC1_CH6_PIN
#else
#define ADC1_CH6_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH7_PIN
#define ADC1_CH7_PIN BSP_ADC1_CH7_PIN
#else
#define ADC1_CH7_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH8_PIN
#define ADC1_CH8_PIN BSP_ADC1_CH8_PIN
#else
#define ADC1_CH8_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH9_PIN
#define ADC1_CH9_PIN BSP_ADC1_CH9_PIN
#else
#define ADC1_CH9_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH10_PIN
#define ADC1_CH10_PIN BSP_ADC1_CH10_PIN
#else
#define ADC1_CH10_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH11_PIN
#define ADC1_CH11_PIN BSP_ADC1_CH11_PIN
#else
#define ADC1_CH11_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH12_PIN
#define ADC1_CH12_PIN BSP_ADC1_CH12_PIN
#else
#define ADC1_CH12_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH13_PIN
#define ADC1_CH13_PIN BSP_ADC1_CH13_PIN
#else
#define ADC1_CH13_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH14_PIN
#define ADC1_CH14_PIN BSP_ADC1_CH14_PIN
#else
#define ADC1_CH14_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH15_PIN
#define ADC1_CH15_PIN BSP_ADC1_CH15_PIN
#else
#define ADC1_CH15_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH16_PIN
#define ADC1_CH16_PIN BSP_ADC1_CH16_PIN
#else
#define ADC1_CH16_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH17_PIN
#define ADC1_CH17_PIN BSP_ADC1_CH17_PIN
#else
#define ADC1_CH17_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH18_PIN
#define ADC1_CH18_PIN BSP_ADC1_CH18_PIN
#else
#define ADC1_CH18_PIN RT_NULL
#endif
#ifdef BSP_ADC1_CH19_PIN
#define ADC1_CH19_PIN BSP_ADC1_CH19_PIN
#else
#define ADC1_CH19_PIN RT_NULL
#endif
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
ADC1, \
RCU_ADC1, \
{ \
ADC1_CH0_PIN, \
ADC1_CH1_PIN, \
ADC1_CH2_PIN, \
ADC1_CH3_PIN, \
ADC1_CH4_PIN, \
ADC1_CH5_PIN, \
ADC1_CH6_PIN, \
ADC1_CH7_PIN, \
ADC1_CH8_PIN, \
ADC1_CH9_PIN, \
ADC1_CH10_PIN, \
ADC1_CH11_PIN, \
ADC1_CH12_PIN, \
ADC1_CH13_PIN, \
ADC1_CH14_PIN, \
ADC1_CH15_PIN, \
ADC1_CH16_PIN, \
ADC1_CH17_PIN, \
ADC1_CH18_PIN, \
ADC1_CH19_PIN, \
}, \
&adc1, \
"adc1", \
}
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
#ifdef BSP_USING_ADC2
#ifdef BSP_ADC2_CH0_PIN
#define ADC2_CH0_PIN BSP_ADC2_CH0_PIN
#else
#define ADC2_CH0_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH1_PIN
#define ADC2_CH1_PIN BSP_ADC2_CH1_PIN
#else
#define ADC2_CH1_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH2_PIN
#define ADC2_CH2_PIN BSP_ADC2_CH2_PIN
#else
#define ADC2_CH2_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH3_PIN
#define ADC2_CH3_PIN BSP_ADC2_CH3_PIN
#else
#define ADC2_CH3_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH4_PIN
#define ADC2_CH4_PIN BSP_ADC2_CH4_PIN
#else
#define ADC2_CH4_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH5_PIN
#define ADC2_CH5_PIN BSP_ADC2_CH5_PIN
#else
#define ADC2_CH5_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH6_PIN
#define ADC2_CH6_PIN BSP_ADC2_CH6_PIN
#else
#define ADC2_CH6_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH7_PIN
#define ADC2_CH7_PIN BSP_ADC2_CH7_PIN
#else
#define ADC2_CH7_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH8_PIN
#define ADC2_CH8_PIN BSP_ADC2_CH8_PIN
#else
#define ADC2_CH8_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH9_PIN
#define ADC2_CH9_PIN BSP_ADC2_CH9_PIN
#else
#define ADC2_CH9_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH10_PIN
#define ADC2_CH10_PIN BSP_ADC2_CH10_PIN
#else
#define ADC2_CH10_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH11_PIN
#define ADC2_CH11_PIN BSP_ADC2_CH11_PIN
#else
#define ADC2_CH11_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH12_PIN
#define ADC2_CH12_PIN BSP_ADC2_CH12_PIN
#else
#define ADC2_CH12_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH13_PIN
#define ADC2_CH13_PIN BSP_ADC2_CH13_PIN
#else
#define ADC2_CH13_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH14_PIN
#define ADC2_CH14_PIN BSP_ADC2_CH14_PIN
#else
#define ADC2_CH14_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH15_PIN
#define ADC2_CH15_PIN BSP_ADC2_CH15_PIN
#else
#define ADC2_CH15_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH16_PIN
#define ADC2_CH16_PIN BSP_ADC2_CH16_PIN
#else
#define ADC2_CH16_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH17_PIN
#define ADC2_CH17_PIN BSP_ADC2_CH17_PIN
#else
#define ADC2_CH17_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH18_PIN
#define ADC2_CH18_PIN BSP_ADC2_CH18_PIN
#else
#define ADC2_CH18_PIN RT_NULL
#endif
#ifdef BSP_ADC2_CH19_PIN
#define ADC2_CH19_PIN BSP_ADC2_CH19_PIN
#else
#define ADC2_CH19_PIN RT_NULL
#endif
#ifndef ADC2_CONFIG
#define ADC2_CONFIG \
{ \
ADC2, \
RCU_ADC2, \
{ \
ADC2_CH0_PIN, \
ADC2_CH1_PIN, \
ADC2_CH2_PIN, \
ADC2_CH3_PIN, \
ADC2_CH4_PIN, \
ADC2_CH5_PIN, \
ADC2_CH6_PIN, \
ADC2_CH7_PIN, \
ADC2_CH8_PIN, \
ADC2_CH9_PIN, \
ADC2_CH10_PIN, \
ADC2_CH11_PIN, \
ADC2_CH12_PIN, \
ADC2_CH13_PIN, \
ADC2_CH14_PIN, \
ADC2_CH15_PIN, \
ADC2_CH16_PIN, \
ADC2_CH17_PIN, \
ADC2_CH18_PIN, \
ADC2_CH19_PIN, \
}, \
&adc2, \
"adc2", \
}
#endif /* ADC2_CONFIG */
#endif /* BSP_USING_ADC2 */
#ifdef __cplusplus
}
#endif
#endif // __ADC_CONFIG_H__
828ECO/drivers/include/config/can_config.h
+83
View File
@@ -0,0 +1,83 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-10-22 WangShun compatible with RT-Studio
*/
#ifndef __CAN_CONFIG_H__
#define __CAN_CONFIG_H__
#include <rtthread.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_CAN0)
#ifndef BSP_CAN0_RX_PIN
#define BSP_CAN0_RX_PIN "PD0"
#define BSP_CAN0_TX_PIN "PD1"
#define BSP_CAN0_AFIO "AF9"
#endif /* BSP_CAN0_RX_PIN */
#ifndef CAN0_CONFIG
#define CAN0_CONFIG \
{ \
.name = "can0", \
.can_periph = CAN0, \
.tx_pin_name = BSP_CAN0_TX_PIN, \
.rx_pin_name = BSP_CAN0_RX_PIN, \
.alternate = BSP_CAN0_AFIO, \
.device = &dev_can0, \
}
#endif /* CAN0_CONFIG */
#endif /* BSP_USING_CAN0 */
#if defined(BSP_USING_CAN1)
#ifndef BSP_CAN1_RX_PIN
#define BSP_CAN1_RX_PIN "PB5"
#define BSP_CAN1_TX_PIN "PB6"
#define BSP_CAN1_AFIO "AF9"
#endif /* BSP_CAN0_RX_PIN */
#ifndef CAN1_CONFIG
#define CAN1_CONFIG \
{ \
.name = "can1", \
.can_periph = CAN1, \
.tx_pin_name = BSP_CAN1_TX_PIN, \
.rx_pin_name = BSP_CAN1_RX_PIN, \
.alternate = BSP_CAN1_AFIO, \
.device = &dev_can1, \
}
#endif /* CAN1_CONFIG */
#endif /* BSP_USING_CAN1 */
#if defined(BSP_USING_CAN2)
#ifndef BSP_CAN2_RX_PIN
#define BSP_CAN2_RX_PIN "PD12"
#define BSP_CAN2_TX_PIN "PD13"
#define BSP_CAN2_AFIO "AF5"
#endif /* BSP_CAN2_RX_PIN */
#ifndef CAN2_CONFIG
#define CAN2_CONFIG \
{ \
.name = "can2", \
.can_periph = CAN2, \
.tx_pin_name = BSP_CAN2_TX_PIN, \
.rx_pin_name = BSP_CAN2_RX_PIN, \
.alternate = BSP_CAN2_AFIO, \
.device = &dev_can2, \
}
#endif /* CAN2_CONFIG */
#endif /* BSP_USING_CAN2 */
#ifdef __cplusplus
}
#endif
#endif /* __CAN_CONFIG_H__ */
828ECO/drivers/include/config/dac_config.h
+51
View File
@@ -0,0 +1,51 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-10-11 kurisaw first version
*/
#ifndef __DAC_CONFIG_H__
#define __DAC_CONFIG_H__
#include <rtthread.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_DAC0
#ifndef DAC0_CONFIG
#define DAC0_CONFIG \
{ \
.dac_periph = DAC0, \
.name = "dac0", \
.pin_name = BSP_DAC0_PIN, \
.channel = BSP_DAC0_CHANNEL, \
}
#endif /* DAC0_CONFIG */
#endif /* BSP_USING_DAC0 */
#ifdef BSP_USING_DAC1
#ifndef DAC1_CONFIG
#define DAC1_CONFIG \
{ \
.dac_periph = DAC0, \
.name = "dac1", \
.pin_name = BSP_DAC1_PIN, \
.channel = BSP_DAC1_CHANNEL, \
}
#endif /* DAC1_CONFIG */
#endif /* BSP_USING_DAC1 */
#ifdef __cplusplus
}
#endif
#endif /*__DAC_CONFIG_H__ */
828ECO/drivers/include/config/enet_config.h
+59
View File
@@ -0,0 +1,59 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-10 kurisaw ENET configuration
*/
#ifndef __ENET_CONFIG_H__
#define __ENET_CONFIG_H__
#include "drv_enet.h"
#if defined(RT_USING_SAL) && defined(RT_USING_NETDEV) && defined(RT_USING_LWIP)
#ifdef __cplusplus
extern "C" {
#endif
/* ENET pin configuration table for RMII interface */
const struct enet_pin_config enet0_pins[] =
{
/* ETH_RMII_REF_CLK */ {"PA1", "AF11"},
/* ETH_MDIO */ {"PA2", "AF11"},
/* ETH_RMII_CRS_DV */ {"PA7", "AF11"},
/* ETH_RMII_TX_EN */ {"PG11", "AF11"},
/* ETH_RMII_TXD0 */ {"PB12", "AF11"},
/* ETH_RMII_TXD1 */ {"PG12", "AF11"},
/* ETH_MDC */ {"PC1", "AF11"},
/* ETH_RMII_RXD0 */ {"PC4", "AF11"},
/* ETH_RMII_RXD1 */ {"PC5", "AF11"},
};
/* Clock output pin for PHY */
const struct enet_pin_config enet_clock_pin = {
"PA8", "AF0" /* Clock output for PHY */
};
/* ENET configuration */
const struct enet_config enet0_cfg = {
.pins = enet0_pins,
.pin_count = sizeof(enet0_pins) / sizeof(enet0_pins[0]),
.enet_periph = ENET0,
.enet_clk = RCU_ENET0,
.enet_tx_clk = RCU_ENET0TX,
.enet_rx_clk = RCU_ENET0RX,
.phy_interface = SYSCFG_ENET_PHY_RMII,
.speed = GPIO_OSPEED_100_220MHZ,
.otype = GPIO_OTYPE_PP,
.pupd = GPIO_PUPD_NONE,
};
#ifdef __cplusplus
}
#endif
#endif /* RT_USING_SAL && RT_USING_NETDEV && RT_USING_LWIP */
#endif /* __ENET_CONFIG_H__ */
828ECO/drivers/include/config/hwtimer_config.h
+195
View File
@@ -0,0 +1,195 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-10-22 kurisaw initial commit
*/
#ifndef __HWTIMER_CONFIG_H__
#define __HWTIMER_CONFIG_H__
#include <rtthread.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#include "drv_hwtimer.h"
#ifdef BSP_USING_HWTIMER0
#ifndef HWTIMER0_CONFIG
#define HWTIMER0_CONFIG \
{ \
"timer0", \
{ \
TIMER0, \
TIMER0_UP_IRQn, \
RCU_TIMER0, \
}, \
{ 0 }, \
{ \
10000000, /* max frequency */ \
1000, /* min frequency */ \
0xFFFF, /* 16-bit counter */ \
HWTIMER_CNTMODE_UP, /* count up mode */ \
}, \
}
#endif /* HWTIMER0_CONFIG */
#endif /* BSP_USING_HWTIMER0 */
#ifdef BSP_USING_HWTIMER1
#ifndef HWTIMER1_CONFIG
#define HWTIMER1_CONFIG \
{ \
"timer1", \
{ \
TIMER1, \
TIMER1_IRQn, \
RCU_TIMER1, \
}, \
{ 0 }, \
{ \
10000000, \
1000, \
0xFFFFFFFF, /* 32-bit counter */ \
HWTIMER_CNTMODE_UP, \
}, \
}
#endif /* HWTIMER1_CONFIG */
#endif /* BSP_USING_HWTIMER1 */
#ifdef BSP_USING_HWTIMER2
#ifndef HWTIMER2_CONFIG
#define HWTIMER2_CONFIG \
{ \
"timer2", \
{ \
TIMER2, \
TIMER2_IRQn, \
RCU_TIMER2, \
}, \
{ 0 }, \
{ \
10000000, \
1000, \
0xFFFF, /* 16-bit counter */ \
HWTIMER_CNTMODE_UP, \
}, \
}
#endif /* HWTIMER2_CONFIG */
#endif /* BSP_USING_HWTIMER2 */
#ifdef BSP_USING_HWTIMER3
#ifndef HWTIMER3_CONFIG
#define HWTIMER3_CONFIG \
{ \
"timer3", \
{ \
TIMER3, \
TIMER3_IRQn, \
RCU_TIMER3, \
}, \
{ 0 }, \
{ \
10000000, \
1000, \
0xFFFF, /* 16-bit counter */ \
HWTIMER_CNTMODE_UP, \
}, \
}
#endif /* HWTIMER3_CONFIG */
#endif /* BSP_USING_HWTIMER3 */
#ifdef BSP_USING_HWTIMER4
#ifndef HWTIMER4_CONFIG
#define HWTIMER4_CONFIG \
{ \
"timer4", \
{ \
TIMER4, \
TIMER4_IRQn, \
RCU_TIMER4, \
}, \
{ 0 }, \
{ \
10000000, \
1000, \
0xFFFFFFFF, /* 32-bit counter */ \
HWTIMER_CNTMODE_UP, \
}, \
}
#endif /* HWTIMER4_CONFIG */
#endif /* BSP_USING_HWTIMER4 */
#ifdef BSP_USING_HWTIMER5
#ifndef HWTIMER5_CONFIG
#define HWTIMER5_CONFIG \
{ \
"timer5", \
{ \
TIMER5, \
TIMER5_IRQn, \
RCU_TIMER5, \
}, \
{ 0 }, \
{ \
10000000, \
1000, \
0xFFFFFFFF, /* 32-bit counter */ \
HWTIMER_CNTMODE_UP, \
}, \
}
#endif /* HWTIMER5_CONFIG */
#endif /* BSP_USING_HWTIMER5 */
#ifdef BSP_USING_HWTIMER6
#ifndef HWTIMER6_CONFIG
#define HWTIMER6_CONFIG \
{ \
"timer6", \
{ \
TIMER6, \
TIMER6_IRQn, \
RCU_TIMER6, \
}, \
{ 0 }, \
{ \
10000000, \
1000, \
0xFFFFFFFF, /* 32-bit counter */ \
HWTIMER_CNTMODE_UP, \
}, \
}
#endif /* HWTIMER6_CONFIG */
#endif /* BSP_USING_HWTIMER6 */
#ifdef BSP_USING_HWTIMER7
#ifndef HWTIMER7_CONFIG
#define HWTIMER7_CONFIG \
{ \
"timer7", \
{ \
TIMER7, \
TIMER7_UP_IRQn, \
RCU_TIMER7, \
}, \
{ 0 }, \
{ \
10000000, \
1000, \
0xFFFF, /* 16-bit counter */ \
HWTIMER_CNTMODE_UP, \
}, \
}
#endif /* HWTIMER7_CONFIG */
#endif /* BSP_USING_HWTIMER7 */
#ifdef __cplusplus
}
#endif
#endif /* __HWTIMER_CONFIG_H__ */
828ECO/drivers/include/config/i2c_config.h
+146
View File
@@ -0,0 +1,146 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-10-10 WangShun compatible with RT-Studio
*/
#ifndef __I2C_CONFIG_H__
#define __I2C_CONFIG_H__
#include <rtthread.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_I2C0
#ifndef BSP_I2C0_SCL_PIN
#define BSP_I2C0_SCL_PIN "PB6"
#define BSP_I2C0_SDA_PIN "PB7"
#define BSP_I2C0_AFIO "AF4"
#endif /* BSP_I2C0_SCL_PIN */
#ifndef I2C0_CONFIG
#define I2C0_CONFIG \
{ \
.i2c_periph = I2C0, \
.per_clk = RCU_I2C0, \
.scl_pin_name = BSP_I2C0_SCL_PIN, \
.sda_pin_name = BSP_I2C0_SDA_PIN, \
.alternate = BSP_I2C0_AFIO, \
.i2c_bus = &i2c0, \
.device_name = "i2c0", \
}
#endif /* I2C0_CONFIG */
#endif /* BSP_USING_I2C0 */
#ifdef BSP_USING_I2C1
#ifndef BSP_I2C1_SCL_PIN
#define BSP_I2C1_SCL_PIN "PH4"
#define BSP_I2C1_SDA_PIN "PB11"
#define BSP_I2C1_AFIO "AF4"
#endif /* BSP_I2C1_SCL_PIN */
#ifndef I2C1_CONFIG
#define I2C1_CONFIG \
{ \
.i2c_periph = I2C1, \
.per_clk = RCU_I2C1, \
.scl_pin_name = BSP_I2C1_SCL_PIN, \
.sda_pin_name = BSP_I2C1_SDA_PIN, \
.alternate = BSP_I2C1_AFIO, \
.i2c_bus = &i2c1, \
.device_name = "i2c1", \
}
#endif /* I2C1_CONFIG */
#endif /* BSP_USING_I2C1 */
#ifdef BSP_USING_I2C2
#ifndef BSP_I2C2_SCL_PIN
#define BSP_I2C2_SCL_PIN "PA8"
#define BSP_I2C2_SDA_PIN "PC9"
#define BSP_I2C2_AFIO "AF4"
#endif /* BSP_I2C2_SCL_PIN */
#ifndef I2C2_CONFIG
#define I2C2_CONFIG \
{ \
.i2c_periph = I2C2, \
.per_clk = RCU_I2C2, \
.scl_pin_name = BSP_I2C2_SCL_PIN, \
.sda_pin_name = BSP_I2C2_SDA_PIN, \
.alternate = BSP_I2C2_AFIO, \
.i2c_bus = &i2c2, \
.device_name = "i2c2", \
}
#endif /* I2C2_CONFIG */
#endif /* BSP_USING_I2C2 */
#ifdef BSP_USING_I2C3
#ifndef BSP_I2C3_SCL_PIN
#define BSP_I2C3_SCL_PIN "PD12"
#define BSP_I2C3_SDA_PIN "PD13"
#define BSP_I2C3_AFIO "AF4"
#endif /* BSP_I2C3_SCL_PIN */
#ifndef I2C3_CONFIG
#define I2C3_CONFIG \
{ \
.i2c_periph = I2C3, \
.per_clk = RCU_I2C3, \
.scl_pin_name = BSP_I2C3_SCL_PIN, \
.sda_pin_name = BSP_I2C3_SDA_PIN, \
.alternate = BSP_I2C3_AFIO, \
.i2c_bus = &i2c3, \
.device_name = "i2c3", \
}
#endif /* I2C3_CONFIG */
#endif /* BSP_USING_I2C3 */
#ifdef BSP_USING_I2C4
#ifndef BSP_I2C4_SCL_PIN
#define BSP_I2C4_SCL_PIN "PG7"
#define BSP_I2C4_SDA_PIN "PG8"
#define BSP_I2C4_AFIO "AF6"
#endif /* BSP_I2C4_SCL_PIN */
#ifndef I2C4_CONFIG
#define I2C4_CONFIG \
{ \
.i2c_periph = I2C4, \
.per_clk = RCU_I2C4, \
.scl_pin_name = BSP_I2C4_SCL_PIN, \
.sda_pin_name = BSP_I2C4_SDA_PIN, \
.alternate = BSP_I2C4_AFIO, \
.i2c_bus = &i2c4, \
.device_name = "i2c4", \
}
#endif /* I2C4_CONFIG */
#endif /* BSP_USING_I2C4 */
#ifdef BSP_USING_I2C5
#ifndef BSP_I2C5_SCL_PIN
#define BSP_I2C5_SCL_PIN "PF11"
#define BSP_I2C5_SDA_PIN "PF12"
#define BSP_I2C5_AFIO "AF4"
#endif /* BSP_I2C5_SCL_PIN */
#ifndef I2C5_CONFIG
#define I2C5_CONFIG \
{ \
.i2c_periph = I2C5, \
.per_clk = RCU_I2C5, \
.scl_pin_name = BSP_I2C5_SCL_PIN, \
.sda_pin_name = BSP_I2C5_SDA_PIN, \
.alternate = BSP_I2C5_AFIO, \
.i2c_bus = &i2c5, \
.device_name = "i2c5", \
}
#endif /* I2C5_CONFIG */
#endif /* BSP_USING_I2C5 */
#ifdef __cplusplus
}
#endif
#endif /*__I2C_CONFIG_H__ */
828ECO/drivers/include/config/pwm_config.h
+145
View File
@@ -0,0 +1,145 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-10-11 kurisaw compatible with RT-Studio
*/
#ifndef __PWM_CONFIG_H__
#define __PWM_CONFIG_H__
#include <rtthread.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PWM0
#ifndef PWM0_CONFIG
#define PWM0_CONFIG \
{ \
.timer_periph = TIMER0, \
.name = "pwm0", \
.timer_clk = RCU_TIMER0, \
.pin_name = BSP_PWM0_PIN, \
.channel = BSP_PWM0_CHANNEL, \
.alternate = BSP_PWM0_AFIO, \
}
#endif /* PWM0_CONFIG */
#endif /* BSP_USING_PWM0 */
#ifdef BSP_USING_PWM1
#ifndef PWM1_CONFIG
#define PWM1_CONFIG \
{ \
.timer_periph = TIMER1, \
.name = "pwm1", \
.timer_clk = RCU_TIMER1, \
.pin_name = BSP_PWM1_PIN, \
.channel = BSP_PWM1_CHANNEL, \
.alternate = BSP_PWM1_AFIO, \
}
#endif /* PWM1_CONFIG */
#endif /* BSP_USING_PWM1 */
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
{ \
.timer_periph = TIMER2, \
.name = "pwm2", \
.timer_clk = RCU_TIMER2, \
.pin_name = BSP_PWM2_PIN, \
.channel = BSP_PWM2_CHANNEL, \
.alternate = BSP_PWM2_AFIO, \
}
#endif /* PWM2_CONFIG */
#endif /* BSP_USING_PWM2 */
#ifdef BSP_USING_PWM3
#ifndef PWM3_CONFIG
#define PWM3_CONFIG \
{ \
.timer_periph = TIMER3, \
.name = "pwm3", \
.timer_clk = RCU_TIMER3, \
.pin_name = BSP_PWM3_PIN, \
.channel = BSP_PWM3_CHANNEL, \
.alternate = BSP_PWM3_AFIO, \
}
#endif /* PWM3_CONFIG */
#endif /* BSP_USING_PWM3 */
#ifdef BSP_USING_PWM4
#ifndef PWM4_CONFIG
#define PWM4_CONFIG \
{ \
.timer_periph = TIMER4, \
.name = "pwm4", \
.timer_clk = RCU_TIMER4, \
.pin_name = BSP_PWM4_PIN, \
.channel = BSP_PWM4_CHANNEL, \
.alternate = BSP_PWM4_AFIO, \
}
#endif /* PWM4_CONFIG */
#endif /* BSP_USING_PWM4 */
#ifdef BSP_USING_PWM5
#ifndef PWM5_CONFIG
#define PWM5_CONFIG \
{ \
.timer_periph = TIMER5, \
.name = "pwm5", \
.timer_clk = RCU_TIMER5, \
.pin_name = BSP_PWM5_PIN, \
.channel = BSP_PWM5_CHANNEL, \
.alternate = BSP_PWM5_AFIO, \
}
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_PWM5 */
#ifdef BSP_USING_PWM6
#ifndef PWM6_CONFIG
#define PWM6_CONFIG \
{ \
.timer_periph = TIMER6, \
.name = "pwm6", \
.timer_clk = RCU_TIMER6, \
.pin_name = BSP_PWM6_PIN, \
.channel = BSP_PWM6_CHANNEL, \
.alternate = BSP_PWM6_AFIO, \
}
#endif /* PWM6_CONFIG */
#endif /* BSP_USING_PWM6 */
#ifdef BSP_USING_PWM7
#ifndef PWM7_CONFIG
#define PWM7_CONFIG \
{ \
.timer_periph = TIMER7, \
.name = "pwm7", \
.timer_clk = RCU_TIMER7, \
.pin_name = BSP_PWM7_PIN, \
.channel = BSP_PWM7_CHANNEL, \
.alternate = BSP_PWM7_AFIO, \
}
#endif /* PWM7_CONFIG */
#endif /* BSP_USING_PWM7 */
#ifdef __cplusplus
}
#endif
#endif /*__PWM_CONFIG_H__ */
828ECO/drivers/include/config/spi_config.h
+178
View File
@@ -0,0 +1,178 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift first version
* 2019-01-03 zylx modify DMA support
* 2025-10-10 WangShun compatible with RT-Studio
*/
#ifndef __SPI_CONFIG_H__
#define __SPI_CONFIG_H__
#include <rtthread.h>
#include <board.h>
#ifdef RT_SPI_USING_DMA
#define IF_SPI_DMA(x) x
#else
#define IF_SPI_DMA(x)
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI0
#ifndef BSP_SPI0_SCK_PIN
#define BSP_SPI0_SCK_PIN "PA5"
#define BSP_SPI0_MISO_PIN "PA6"
#define BSP_SPI0_MOSI_PIN "PA7"
#define BSP_SPI0_AFIO "AF5"
#endif /* BSP_SPI0_SCK_PIN */
#ifndef SPI0_BUS_CONFIG
#define SPI0_BUS_CONFIG \
{ \
.spi_periph = SPI0, \
.bus_name = "spi0", \
.spi_clk = RCU_SPI0, \
.spi_bus = &spi_bus0, \
.sck_pin_name = BSP_SPI0_SCK_PIN, \
.miso_pin_name = BSP_SPI0_MISO_PIN, \
.mosi_pin_name = BSP_SPI0_MOSI_PIN, \
.alternate = BSP_SPI0_AFIO, \
IF_SPI_DMA(.spi_dma = &spi_dma[0]) \
}
#endif /* SPI0_BUS_CONFIG */
#endif /* BSP_USING_SPI0 */
#ifdef BSP_USING_SPI1
#ifndef BSP_SPI1_SCK_PIN
#define BSP_SPI1_SCK_PIN "PB13"
#define BSP_SPI1_MISO_PIN "PB14"
#define BSP_SPI1_MOSI_PIN "PB15"
#define BSP_SPI1_AFIO "AF5"
#endif /* BSP_SPI1_SCK_PIN */
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.spi_periph = SPI1, \
.bus_name = "spi1", \
.spi_clk = RCU_SPI1, \
.spi_bus = &spi_bus1, \
.sck_pin_name = BSP_SPI1_SCK_PIN, \
.miso_pin_name = BSP_SPI1_MISO_PIN, \
.mosi_pin_name = BSP_SPI1_MOSI_PIN, \
.alternate = BSP_SPI1_AFIO, \
IF_SPI_DMA(.spi_dma = &spi_dma[1]) \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_USING_SPI2
#ifndef BSP_SPI2_SCK_PIN
#define BSP_SPI2_SCK_PIN "PB3"
#define BSP_SPI2_MISO_PIN "PB4"
#define BSP_SPI2_MOSI_PIN "PB5"
#define BSP_SPI2_AFIO "AF6"
#endif /* BSP_SPI1_SCK_PIN */
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.spi_periph = SPI2, \
.bus_name = "spi2", \
.spi_clk = RCU_SPI2, \
.spi_bus = &spi_bus2, \
.sck_pin_name = BSP_SPI2_SCK_PIN, \
.miso_pin_name = BSP_SPI2_MISO_PIN, \
.mosi_pin_name = BSP_SPI2_MOSI_PIN, \
.alternate = BSP_SPI2_AFIO, \
IF_SPI_DMA(.spi_dma = &spi_dma[2]) \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_USING_SPI3
#ifndef BSP_SPI3_SCK_PIN
#define BSP_SPI3_SCK_PIN "PE12"
#define BSP_SPI3_MISO_PIN "PE13"
#define BSP_SPI3_MOSI_PIN "PE14"
#define BSP_SPI3_AFIO "AF5"
#endif /* BSP_SPI3_SCK_PIN */
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.spi_periph = SPI3, \
.bus_name = "spi3", \
.spi_clk = RCU_SPI3, \
.spi_bus = &spi_bus3, \
.sck_pin_name = BSP_SPI3_SCK_PIN, \
.miso_pin_name = BSP_SPI3_MISO_PIN, \
.mosi_pin_name = BSP_SPI3_MOSI_PIN, \
.alternate = BSP_SPI3_AFIO, \
IF_SPI_DMA(.spi_dma = &spi_dma[3]) \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_USING_SPI4
#ifndef BSP_SPI4_SCK_PIN
#define BSP_SPI4_SCK_PIN "PF7"
#define BSP_SPI4_MISO_PIN "PF8"
#define BSP_SPI4_MOSI_PIN "PF9"
#define BSP_SPI4_AFIO "AF5"
#endif /* BSP_SPI4_SCK_PIN */
#ifndef SPI4_BUS_CONFIG
#define SPI4_BUS_CONFIG \
{ \
.spi_periph = SPI4, \
.bus_name = "spi4", \
.spi_clk = RCU_SPI4, \
.spi_bus = &spi_bus4, \
.sck_pin_name = BSP_SPI4_SCK_PIN, \
.miso_pin_name = BSP_SPI4_MISO_PIN, \
.mosi_pin_name = BSP_SPI4_MOSI_PIN, \
.alternate = BSP_SPI4_AFIO, \
IF_SPI_DMA(.spi_dma = &spi_dma[4]) \
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_USING_SPI5
#ifndef BSP_SPI5_SCK_PIN
#define BSP_SPI5_SCK_PIN "PG13"
#define BSP_SPI5_MISO_PIN "PG12"
#define BSP_SPI5_MOSI_PIN "PG14"
#define BSP_SPI5_AFIO "AF5"
#endif /* BSP_SPI5_SCK_PIN */
#ifndef SPI5_BUS_CONFIG
#define SPI5_BUS_CONFIG \
{ \
.spi_periph = SPI5, \
.bus_name = "spi5", \
.spi_clk = RCU_SPI5, \
.spi_bus = &spi_bus5, \
.sck_pin_name = BSP_SPI5_SCK_PIN, \
.miso_pin_name = BSP_SPI5_MISO_PIN, \
.mosi_pin_name = BSP_SPI5_MOSI_PIN, \
.alternate = BSP_SPI5_AFIO, \
IF_SPI_DMA(.spi_dma = &spi_dma[5]) \
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */
828ECO/drivers/include/config/uart_config.h
+204
View File
@@ -0,0 +1,204 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-30 SummerGift first version
* 2019-01-03 zylx modify dma support
* 2025-10-09 WangShun compatible with RT-Studio
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef BSP_UART0_AFIO
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E
#define BSP_UART0_AFIO "AF4"
#elif defined SOC_SERIES_GD32E23x
#define BSP_UART0_AFIO "AF1"
#endif
#endif
#ifndef BSP_UART1_AFIO
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32H75E
#define BSP_UART1_AFIO "AF7"
#elif defined SOC_SERIES_GD32E23x
#define BSP_UART1_AFIO "AF1"
#endif
#endif
#ifndef BSP_UART2_AFIO
#define BSP_UART2_AFIO "AF7"
#endif
#ifndef BSP_UART3_AFIO
#define BSP_UART3_AFIO "AF8"
#endif
#ifndef BSP_UART4_AFIO
#define BSP_UART4_AFIO "AF8"
#endif
#ifndef BSP_UART5_AFIO
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
#define BSP_UART5_AFIO "AF8"
#elif defined (SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E)
#define BSP_UART5_AFIO "AF7"
#endif
#endif
#ifndef BSP_UART6_AFIO
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
#define BSP_UART6_AFIO "AF8"
#elif defined (SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E)
#define BSP_UART6_AFIO "AF7"
#endif
#endif
#ifndef BSP_UART7_AFIO
#define BSP_UART7_AFIO "AF8"
#endif
#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
{ \
.uart_periph = USART0, \
.irqn = USART0_IRQn, \
.per_clk = RCU_USART0, \
.tx_pin_name = BSP_UART0_TX_PIN, \
.rx_pin_name = BSP_UART0_RX_PIN, \
.alternate = BSP_UART0_AFIO, \
.serial = &serial0, \
.device_name = "uart0", \
}
#endif /* UART0_CONFIG */
#endif /* BSP_USING_UART0 */
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.uart_periph = USART1, \
.irqn = USART1_IRQn, \
.per_clk = RCU_USART1, \
.tx_pin_name = BSP_UART1_TX_PIN, \
.rx_pin_name = BSP_UART1_RX_PIN, \
.alternate = BSP_UART1_AFIO, \
.serial = &serial1, \
.device_name = "uart1", \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.uart_periph = USART2, \
.irqn = USART2_IRQn, \
.per_clk = RCU_USART2, \
.tx_pin_name = BSP_UART2_TX_PIN, \
.rx_pin_name = BSP_UART2_RX_PIN, \
.alternate = BSP_UART2_AFIO, \
.serial = &serial2, \
.device_name = "uart2", \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.uart_periph = UART3, \
.irqn = UART3_IRQn, \
.per_clk = RCU_UART3, \
.tx_pin_name = BSP_UART3_TX_PIN, \
.rx_pin_name = BSP_UART3_RX_PIN, \
.alternate = BSP_UART3_AFIO, \
.serial = &serial3, \
.device_name = "uart3", \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.uart_periph = UART4, \
.irqn = UART4_IRQn, \
.per_clk = RCU_UART4, \
.tx_pin_name = BSP_UART4_TX_PIN, \
.rx_pin_name = BSP_UART4_RX_PIN, \
.alternate = BSP_UART4_AFIO, \
.serial = &serial4, \
.device_name = "uart4", \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.uart_periph = USART5, \
.irqn = USART5_IRQn, \
.per_clk = RCU_USART5, \
.tx_pin_name = BSP_UART5_TX_PIN, \
.rx_pin_name = BSP_UART5_RX_PIN, \
.alternate = BSP_UART5_AFIO, \
.serial = &serial5, \
.device_name = "uart5", \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.uart_periph = UART6, \
.irqn = UART6_IRQn, \
.per_clk = RCU_UART6, \
.tx_pin_name = BSP_UART6_TX_PIN, \
.rx_pin_name = BSP_UART6_RX_PIN, \
.alternate = BSP_UART6_AFIO, \
.serial = &serial6, \
.device_name = "uart6", \
}
#endif /* UART6_CONFIG */
#endif /* BSP_USING_UART6 */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.uart_periph = UART7, \
.irqn = UART7_IRQn, \
.per_clk = RCU_UART7, \
.tx_pin_name = BSP_UART7_TX_PIN, \
.rx_pin_name = BSP_UART7_RX_PIN, \
.alternate = BSP_UART7_AFIO, \
.serial = &serial7, \
.device_name = "uart7", \
}
#endif /* UART7_CONFIG */
#endif /* BSP_USING_UART7 */
#ifdef __cplusplus
}
#endif
#endif /* __UART_CONFIG_H__ */
828ECO/drivers/include/drv_adc.h
+40
View File
@@ -0,0 +1,40 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-05-03 BruceOu first implementation
* 2025-10-22 kurisaw optimize multi-channel GPIO configuration
*/
#ifndef __DRV_ADC_H__
#define __DRV_ADC_H__
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
#include "drv_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MAX_EXTERN_ADC_CHANNEL 20
/* gd32 adc driver class */
struct gd32_adc
{
uint32_t adc_periph;
rcu_periph_enum adc_clk;
const char *adc_pins[MAX_EXTERN_ADC_CHANNEL];
struct rt_adc_device *adc;
char *device_name;
};
#ifdef __cplusplus
}
#endif
#endif /* __DRV_ADC_H__ */
828ECO/drivers/include/drv_can.h
+109
View File
@@ -0,0 +1,109 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef __DRV_CAN_H__
#define __DRV_CAN_H__
#include <rtdevice.h>
#include <rtthread.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef RT_USING_CAN
/* Aliases for __IRQn */
#if defined(BSP_USING_CAN0) || defined(BSP_USING_CAN1) || defined(BSP_USING_CAN2)
/* BSP_USING_CAN0 */
#define CAN0_TX_IRQn CAN0_Message_IRQn
#define CAN0_RX_IRQn CAN0_Message_IRQn
#define CAN0_ERROR_IRQn CAN0_Error_IRQn
/* BSP_USING_CAN1 */
#define CAN1_TX_IRQn CAN1_Message_IRQn
#define CAN1_RX_IRQn CAN1_Message_IRQn
#define CAN1_ERROR_IRQn CAN1_Error_IRQn
/* BSP_USING_CAN2 */
#define CAN2_TX_IRQn CAN2_Message_IRQn
#define CAN2_RX_IRQn CAN2_Message_IRQn
#define CAN2_ERROR_IRQn CAN2_Error_IRQn
#endif
struct gd32_baud_rate_tab
{
uint32_t baud_rate;
uint8_t resync_jump_width;
uint8_t prop_time_segment;
uint8_t time_segment_1;
uint8_t time_segment_2;
uint32_t prescaler;
};
#ifdef RT_CAN_USING_CANFD
typedef struct
{
rt_uint32_t baud;
rt_uint8_t sjw;
rt_uint8_t prop;
rt_uint8_t seg1;
rt_uint8_t seg2;
rt_uint16_t prescaler;
} gd32_fd_data_baud_t;
enum CANFD_BAUD
{
CANFD_5MBaud = 5000UL * 1000, /* 5 MBit/sec */
CANFD_4MBaud = 4000UL * 1000, /* 4 MBit/sec */
CANFD_3MBaud = 3000UL * 1000, /* 3 MBit/sec */
CANFD_2MBaud = 2000UL * 1000, /* 2 MBit/sec */
CANFD_1MBaud = 1000UL * 1000, /* 1 MBit/sec */
CANFD_800kBaud = 1000UL * 800, /* 800 kBit/sec */
CANFD_500kBaud = 1000UL * 500, /* 500 kBit/sec */
CANFD_250kBaud = 1000UL * 250, /* 250 kBit/sec */
CANFD_125kBaud = 1000UL * 125, /* 125 kBit/sec */
CANFD_100kBaud = 1000UL * 100, /* 100 kBit/sec */
CANFD_50kBaud = 1000UL * 50, /* 50 kBit/sec */
CANFD_20kBaud = 1000UL * 20, /* 20 kBit/sec */
CANFD_10kBaud = 1000UL * 10 /* 10 kBit/sec */
};
#endif
/* gd32 can device */
typedef struct
{
char *name;
const char *tx_pin_name; /* can pin name */
const char *rx_pin_name; /* rx pin name */
const char *alternate;
uint32_t can_periph;
can_parameter_struct can_init;
can_fifo_parameter_struct can_fifo;
can_operation_modes_enum mode;
can_mailbox_descriptor_struct tx_message[16];
can_mailbox_descriptor_struct rx_message[16];
rt_uint8_t rx_message_valid[16];
void (*filter_cb)(uint32_t can_periph);
#ifdef RT_CAN_USING_CANFD
can_fd_parameter_struct can_fd_init;
rt_uint8_t fd_enabled;
rt_uint8_t fd_rx_buf[16][64];
#endif
struct rt_can_device *device; /* can device */
} gd32_can_struct;
void can_gpio_config(void);
int rt_hw_can_init(void);
#endif /* RT_USING_CAN */
#ifdef __cplusplus
}
#endif
#endif /* __DRV_CAN_H__ */
828ECO/drivers/include/drv_common.h
+40
View File
@@ -0,0 +1,40 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-09-0 WangShun first implementation
*/
#ifndef __DRV_COMMON_H__
#define __DRV_COMMON_H__
#include "drv_usart.h"
#include "drv_gpio.h"
#include <board.h>
#define GD32_FLASH_START_ADRESS ROM_START
#define GD32_FLASH_SIZE ROM_SIZE
#define GD32_FLASH_END_ADDRESS ROM_END
#define GD32_SRAM_SIZE RAM_SIZE
#define GD32_SRAM_START RAM_START
#define GD32_SRAM_END RAM_END
#ifdef __ARMCC_VERSION
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#endif
#define HEAP_END GD32_SRAM_END
#endif /* __DRV_COMMON_H__ */
828ECO/drivers/include/drv_config.h
+21
View File
@@ -0,0 +1,21 @@
/*
* drv_config.h for GD32 platform
*/
#ifndef __DRV_CONFIG_H__
#define __DRV_CONFIG_H__
#include <board.h>
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Include peripheral configuration headers under drivers/include/config */
#include "config/uart_config.h"
#ifdef __cplusplus
}
#endif
#endif /* __DRV_CONFIG_H__ */
828ECO/drivers/include/drv_dac.h
+41
View File
@@ -0,0 +1,41 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-10-11 kurisaw first version
*/
#ifndef __DRV_DAC_H__
#define __DRV_DAC_H__
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(RT_USING_DAC)
/* gd32 dac driver class */
struct gd32_dac
{
struct rt_dac_device dac_device;
uint32_t dac_periph;
char *name;
const char *pin_name;
rt_int16_t channel;
};
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DRV_DAC_H__ */
828ECO/drivers/include/drv_dma.h
+58
View File
@@ -0,0 +1,58 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-03-19 Evlers first implementation
*/
#ifndef _DRV_DMA_H_
#define _DRV_DMA_H_
#if defined SOC_SERIES_GD32E23x
#define DRV_DMA_CONFIG(chx) \
(struct dma_config)
{ \
.periph = DMA, \
.rcu = RCU_DMA, \
.channel = DMA_CH##chx, \
.irq = ((chx) == 0 ? DMA_Channel0_IRQn : \
(chx) == 1 ? DMA_Channel1_2_IRQn : \
(chx) == 2 ? DMA_Channel1_2_IRQn : \
(chx) == 3 ? DMA_Channel3_4_IRQn : \
(chx) == 4 ? DMA_Channel3_4_IRQn : (IRQn_Type)0) \
}
struct dma_config
{
uint32_t periph;
rcu_periph_enum rcu;
dma_channel_enum channel;
IRQn_Type irq;
};
#else
#define DRV_DMA_CONFIG(dmax, chx, subx) { \
.periph = DMA##dmax, \
.channel = DMA_CH##chx, \
.rcu = RCU_DMA##dmax, \
.subperiph = DMA_SUBPERI##subx, \
.irq = DMA##dmax##_Channel##chx##_IRQn, \
}
struct dma_config
{
uint32_t periph;
rcu_periph_enum rcu;
dma_channel_enum channel;
dma_subperipheral_enum subperiph;
IRQn_Type irq;
};
#endif
#endif /* _DRV_DMA_H_ */
828ECO/drivers/include/drv_enet.h
+98
View File
@@ -0,0 +1,98 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-10 kurisaw the first version
*/
#ifndef __DRV_ENET_H__
#define __DRV_ENET_H__
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#if defined(RT_USING_SAL) && defined(RT_USING_NETDEV) && defined(RT_USING_LWIP)
#ifdef __cplusplus
extern "C" {
#endif
#include "gd32h7xx.h"
#include "synopsys_emac.h"
#define EMAC_RXBUFNB 5
#define EMAC_TXBUFNB 5
#define EMAC_PHY_AUTO 0
#define EMAC_PHY_10MBIT 1
#define EMAC_PHY_100MBIT 2
#define MAX_ADDR_LEN 6
/* ENET pin configuration structure */
struct enet_pin_config
{
const char *pin_name; /* Pin name in format "PxY" */
const char *alternate; /* Alternate function in format "AFx" */
};
/* ENET configuration structure */
struct enet_config
{
const struct enet_pin_config *pins;
uint32_t pin_count;
uint32_t enet_periph;
rcu_periph_enum enet_clk;
rcu_periph_enum enet_tx_clk;
rcu_periph_enum enet_rx_clk;
uint32_t phy_interface;
uint32_t speed; /* GPIO speed - common for all pins */
uint8_t otype; /* Output type - common for all pins */
uint8_t pupd; /* Pull-up/pull-down - common for all pins */
};
struct gd32_emac
{
/* inherit from Ethernet device */
struct eth_device parent;
__ALIGNED(4)
rt_uint8_t phy_mode;
/* interface address info. */
__ALIGNED(4)
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
const struct enet_pin_config *pins;
uint32_t pin_count;
struct rt_synopsys_eth *ETHERNET_MAC;
IRQn_Type ETHER_MAC_IRQ;
EMAC_DMADESCTypeDef *DMATxDescToSet;
EMAC_DMADESCTypeDef *DMARxDescToGet;
#pragma pack(4)
EMAC_DMADESCTypeDef DMARxDscrTab[EMAC_RXBUFNB];
#pragma pack(4)
EMAC_DMADESCTypeDef DMATxDscrTab[EMAC_TXBUFNB];
#pragma pack(4)
rt_uint8_t Rx_Buff[EMAC_RXBUFNB][EMAC_MAX_PACKET_SIZE];
#pragma pack(4)
rt_uint8_t Tx_Buff[EMAC_TXBUFNB][EMAC_MAX_PACKET_SIZE];
struct rt_semaphore tx_buf_free;
};
/* Function declarations */
rt_err_t gd32_enet_gpio_init(struct gd32_emac *emac);
const struct enet_config *gd32_get_enet_config(void);
#ifdef __cplusplus
}
#endif
#endif /* RT_USING_SAL && RT_USING_NETDEV && RT_USING_LWIP */
#endif /* __DRV_ENET_H__ */
828ECO/drivers/include/drv_gpio.h
+93
View File
@@ -0,0 +1,93 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-20 BruceOu the first version
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined SOC_SERIES_GD32F10x
#include "gd32f10x_gpio.h"
#elif defined SOC_SERIES_GD32F20x
#include "gd32f20x_gpio.h"
#elif defined SOC_SERIES_GD32F30x
#include "gd32f30x_gpio.h"
#elif defined SOC_SERIES_GD32F4xx
#include "gd32f4xx_gpio.h"
#elif defined SOC_SERIES_GD32H7xx
#include "gd32h7xx_gpio.h"
#elif defined SOC_SERIES_GD32H75e
#include "gd32h75e_gpio.h"
#elif defined SOC_SERIES_GD32E50x
#include "gd32e50x_gpio.h"
#elif defined SOC_SERIES_GD32F5xx
#include "gd32f5xx_gpio.h"
#elif defined SOC_SERIES_GD32E23x
#include "gd32e23x_gpio.h"
#endif
#define __GD32_PORT(port) GPIO##port
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32H7xx
#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \
GPIO##port, GPIO_PIN_##pin, \
EXTI_SOURCE_GPIO##port, \
EXTI_SOURCE_PIN##pin, \
EXTI_##pin}
#else
#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \
GPIO##port, GPIO_PIN_##pin, \
GPIO_PORT_SOURCE_GPIO##port, \
GPIO_PIN_SOURCE_##pin}
#endif
#define GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0}
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) + PIN)
#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
#define PIN_GDPORT(pin) (GPIO_BASE + (0x400u * PIN_PORT(pin)))
#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
struct pin_index
{
rt_int16_t index;
rcu_periph_enum clk;
rt_uint32_t gpio_periph;
rt_uint32_t pin;
rt_uint8_t port_src;
rt_uint8_t pin_src;
rt_uint32_t exit_line;
};
struct pin_irq_map
{
rt_uint16_t pinbit;
IRQn_Type irqno;
};
int get_pin_config(const char *pin_name, uint32_t *port, uint32_t *pin, rcu_periph_enum *clk);
int pin_alternate_config(const char *alternate, uint32_t *af);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_GPIO_H__ */
828ECO/drivers/include/drv_hwtimer.h
+72
View File
@@ -0,0 +1,72 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-10-22 kurisaw first version
*/
#ifndef __DRV_HWTIMER_H__
#define __DRV_HWTIMER_H__
#include <rthw.h>
#include <rtdevice.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef RT_USING_HWTIMER
typedef struct
{
uint32_t reg_base;
IRQn_Type irqn;
rcu_periph_enum rcu;
} gd32_hwtimer_data;
typedef struct
{
char dev_name[RT_NAME_MAX];
const gd32_hwtimer_data hw_data;
rt_hwtimer_t hwtimer_dev;
const struct rt_hwtimer_info hwtimer_info;
} gd32_hwtimer_device;
enum timer_index
{
#ifdef BSP_USING_HWTIMER0
TIM0_INDEX,
#endif
#ifdef BSP_USING_HWTIMER1
TIM1_INDEX,
#endif
#ifdef BSP_USING_HWTIMER2
TIM2_INDEX,
#endif
#ifdef BSP_USING_HWTIMER3
TIM3_INDEX,
#endif
#ifdef BSP_USING_HWTIMER4
TIM4_INDEX,
#endif
#ifdef BSP_USING_HWTIMER5
TIM5_INDEX,
#endif
#ifdef BSP_USING_HWTIMER6
TIM6_INDEX,
#endif
#ifdef BSP_USING_HWTIMER7
TIM7_INDEX,
#endif
};
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DRV_HWTIMER_H__ */
828ECO/drivers/include/drv_i2c.h
+43
View File
@@ -0,0 +1,43 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-12-20 BruceOu the first version
* 2025-10-10 WangShun compatible with RT-Studio
*/
#ifndef __DRV_I2C__
#define __DRV_I2C__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
/* GD32 i2c driver */
struct gd32_i2c_bus
{
uint32_t i2c_periph;
rcu_periph_enum per_clk;
const char *scl_pin_name; /* scl pin name */
const char *sda_pin_name; /* sda pin name */
const char *alternate; /* afio name */
struct rt_i2c_bus_device *i2c_bus;
char *device_name;
};
#ifdef __cplusplus
}
#endif
#endif /* __DRV_I2C__ */
828ECO/drivers/include/drv_lcd.h
+66
View File
@@ -0,0 +1,66 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef __DRV_LCD_H__
#define __DRV_LCD_H__
#include <board.h>
#if defined(SOC_SERIES_GD32H7xx)
#include "gd32h7xx_tli.h"
#include "gd32h7xx_ipa.h"
#endif
#define HORIZONTAL_SYNCHRONOUS_PULSE 41
#define HORIZONTAL_BACK_PORCH 2
#define ACTIVE_WIDTH 480
#define HORIZONTAL_FRONT_PORCH 2
#define VERTICAL_SYNCHRONOUS_PULSE 10
#define VERTICAL_BACK_PORCH 2
#define ACTIVE_HEIGHT 272
#define VERTICAL_FRONT_PORCH 2
#define LCD_WIGHT ACTIVE_WIDTH
#define LCD_HIGHT ACTIVE_HEIGHT
#define PIXEL_FORMAT LAYER_PPF_RGB565
#define PRE_PIXEL_BYTES 2
typedef struct _RGB_DATA
{
uint8_t Alpha;
uint8_t R;
uint8_t G;
uint8_t B;
} RGB;
extern RGB color_write;
extern RGB color_black;
extern RGB color_red;
extern RGB color_blue;
extern RGB color_green;
extern RGB color_yellow;
extern RGB color_cyan;
extern RGB color_magenta;
extern RGB color_orange;
extern RGB color_purple;
extern RGB color_gray;
extern RGB color_lightgray;
extern RGB color_darkgray;
extern RGB color_brown;
extern RGB color_pink;
extern RGB color_gold;
extern RGB color_silver;
void lcd_draw_picture(uint32_t picture_addr, uint32_t picture_width, uint32_t picture_height, uint32_t picture_x, uint32_t picture_y);
void lcd_draw_point(uint32_t point_x, uint32_t point_y, RGB *color);
uint32_t to_RGB565(RGB *color);
#endif // __DRV_LCD_H__
828ECO/drivers/include/drv_legacy.h
+32
View File
@@ -0,0 +1,32 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-09-12 RTT the first version
*/
#ifndef DRIVERS_DRV_LEGACY_H_
#define DRIVERS_DRV_LEGACY_H_
#include <sys/types.h>
#include "rtdef.h"
#if RTTHREAD_VERSION <= 40101
#if defined(RT_USING_LIBC) && !defined(RT_USING_NANO)
typedef size_t rt_size_t; /**< Type for size number */
typedef ssize_t rt_ssize_t; /**< Used for a count of bytes or an error indication */
#else
typedef rt_base_t rt_ssize_t; /**< Used for a count of bytes or an error indication */
#endif /* defined(RT_USING_LIBC) && !defined(RT_USING_NANO) */
#else
#define RT_SECTION rt_section
#define RT_WEAK rt_weak
#define RT_USED rt_used
#ifndef ALIGN
#define ALIGN rt_align
#endif
#endif /* RTTHREAD_VERSION <= RT_VERSION_CHECK(4, 1, 1) */
#endif /* DRIVERS_DRV_LEGACY_H_ */
828ECO/drivers/include/drv_log.h
+28
View File
@@ -0,0 +1,28 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-15 SummerGift first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
828ECO/drivers/include/drv_pwm.h
+45
View File
@@ -0,0 +1,45 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-10-11 kurisaw compatible with RT-Studio
*/
#ifndef __DRV_PWM_H__
#define __DRV_PWM_H__
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(RT_USING_PWM)
/* gd32 pwm driver class */
struct gd32_pwm
{
struct rt_device_pwm pwm_device;
uint32_t timer_periph;
char *name;
rcu_periph_enum timer_clk;
const char *pin_name;
rt_int16_t channel;
const char *alternate;
};
rt_err_t rt_hw_pwm_init(void);
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DRV_PWM_H__ */
828ECO/drivers/include/drv_sdio.h
+297
View File
@@ -0,0 +1,297 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef __SDCARD_H_
#define __SDCARD_H_
#include <board.h>
#if defined(SOC_SERIES_GD32F10x)
#include "gd32f10x_sdio.h"
#include "gd32f10x_dma.h"
#elif defined(SOC_SERIES_GD32F20x)
#include "gd32f20x_sdio.h"
#include "gd32f20x_dma.h"
#elif defined(SOC_SERIES_GD32F30x)
#include "gd32f30x_sdio.h"
#include "gd32f30x_dma.h"
#elif defined(SOC_SERIES_GD32F4xx)
#include "gd32f4xx_sdio.h"
#include "gd32f4xx_dma.h"
#elif defined(SOC_SERIES_GD32H7xx)
#include "gd32h7xx_sdio.h"
#include "gd32h7xx_dma.h"
#endif
// #define USE_18V_SWITCH /* use SD Transceiver 1.8V mode */
#define SDIO_PERI_CLOCK RCU_SDIO0
#define SDIO_GPIO_CLK RCU_GPIOC
#define SDIO_GPIO_CMD RCU_GPIOD
#define SDIO_GPIO_D0 RCU_GPIOB
#define SDIO_GPIO_D1 RCU_GPIOC
#define SDIO_GPIO_D2 RCU_GPIOC
#define SDIO_GPIO_D3 RCU_GPIOC
#define SDIO_CLK_PORT GPIOC
#define SDIO_CLK_PIN GPIO_PIN_12
#define SDIO_CMD_PORT GPIOD
#define SDIO_CMD_PIN GPIO_PIN_2
#define SDIO_D0_PORT GPIOB
#define SDIO_D0_PIN GPIO_PIN_13
#define SDIO_D1_PORT GPIOC
#define SDIO_D1_PIN GPIO_PIN_9
#define SDIO_D2_PORT GPIOC
#define SDIO_D2_PIN GPIO_PIN_10
#define SDIO_D3_PORT GPIOC
#define SDIO_D3_PIN GPIO_PIN_11
/* SD memory card bus commands index */
#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /* CMD0, GO_IDLE_STATE */
#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /* CMD2, ALL_SEND_CID */
#define SD_CMD_SEND_RELATIVE_ADDR ((uint8_t)3) /* CMD3, SEND_RELATIVE_ADDR */
#define SD_CMD_SET_DSR ((uint8_t)4) /* CMD4, SET_DSR */
#define SD_CMD_SWITCH_FUNC ((uint8_t)6) /* CMD6, SWITCH_FUNC */
#define SD_CMD_SELECT_DESELECT_CARD ((uint8_t)7) /* CMD7, SELECT_DESELECT_CARD */
#define SD_CMD_SEND_IF_COND ((uint8_t)8) /* CMD8, SEND_IF_COND */
#define SD_CMD_SEND_CSD ((uint8_t)9) /* CMD9, SEND_CSD */
#define SD_CMD_SEND_CID ((uint8_t)10) /* CMD10, SEND_CID */
#define SD_CMD_VOLATAGE_SWITCH ((uint8_t)11) /* CMD11, SD_CMD_VOLATAGE_SWITCH */
#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /* CMD12, STOP_TRANSMISSION */
#define SD_CMD_SEND_STATUS ((uint8_t)13) /* CMD13, SEND_STATUS */
#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /* CMD15, GO_INACTIVE_STATE */
#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /* CMD16, SET_BLOCKLEN */
#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /* CMD17, READ_SINGLE_BLOCK */
#define SD_CMD_READ_MULTIPLE_BLOCK ((uint8_t)18) /* CMD18, READ_MULTIPLE_BLOCK */
#define SD_SEND_TUNING_PATTERN ((uint8_t)19) /* CMD19, SEND_TUNING_PATTERN */
#define SD_CMD_WRITE_BLOCK ((uint8_t)24) /* CMD24, WRITE_BLOCK */
#define SD_CMD_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /* CMD25, WRITE_MULTIPLE_BLOCK */
#define SD_CMD_PROG_CSD ((uint8_t)27) /* CMD27, PROG_CSD */
#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /* CMD28, SET_WRITE_PROT */
#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /* CMD29, CLR_WRITE_PROT */
#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /* CMD30, SEND_WRITE_PROT */
#define SD_CMD_ERASE_WR_BLK_START ((uint8_t)32) /* CMD32, ERASE_WR_BLK_START */
#define SD_CMD_ERASE_WR_BLK_END ((uint8_t)33) /* CMD33, ERASE_WR_BLK_END */
#define SD_CMD_ERASE ((uint8_t)38) /* CMD38, ERASE */
#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /* CMD42, LOCK_UNLOCK */
#define SD_CMD_APP_CMD ((uint8_t)55) /* CMD55, APP_CMD */
#define SD_CMD_GEN_CMD ((uint8_t)56) /* CMD56, GEN_CMD */
/* SD memory card application specific commands index */
#define SD_APPCMD_SET_BUS_WIDTH ((uint8_t)6) /* ACMD6, SET_BUS_WIDTH */
#define SD_APPCMD_SD_STATUS ((uint8_t)13) /* ACMD13, SD_STATUS */
#define SD_APPCMD_SEND_NUM_WR_BLOCKS ((uint8_t)22) /* ACMD22, SEND_NUM_WR_BLOCKS */
#define SD_APPCMD_SET_WR_BLK_ERASE_COUNT ((uint8_t)23) /* ACMD23, SET_WR_BLK_ERASE_COUNT */
#define SD_APPCMD_SD_SEND_OP_COND ((uint8_t)41) /* ACMD41, SD_SEND_OP_COND */
#define SD_APPCMD_SET_CLR_CARD_DETECT ((uint8_t)42) /* ACMD42, SET_CLR_CARD_DETECT */
#define SD_APPCMD_SEND_SCR ((uint8_t)51) /* ACMD51, SEND_SCR */
/* card command class */
#define SD_CCC_SWITCH BIT(10) /* class 10 */
#define SD_CCC_IO_MODE BIT(9) /* class 9 */
#define SD_CCC_APPLICATION_SPECIFIC BIT(8) /* class 8 */
#define SD_CCC_LOCK_CARD BIT(7) /* class 7 */
#define SD_CCC_WRITE_PROTECTION BIT(6) /* class 6 */
#define SD_CCC_ERASE BIT(5) /* class 5 */
#define SD_CCC_BLOCK_WRITE BIT(4) /* class 4 */
#define SD_CCC_BLOCK_READ BIT(2) /* class 2 */
#define SD_CCC_BASIC BIT(0) /* class 0 */
/* SD card data transmission mode */
#define SD_DMA_MODE ((uint32_t)0x00000000) /* DMA mode */
#define SD_POLLING_MODE ((uint32_t)0x00000001) /* polling mode */
/* lock unlock status */
#define SD_LOCK ((uint8_t)0x05) /* lock the SD card */
#define SD_UNLOCK ((uint8_t)0x02) /* unlock the SD card */
#define SD_SDSC ((uint32_t)0x00000000U) /*!< SD Standard Capacity <2G*/
#define SD_SDHC_SDXC ((uint32_t)0x00000001U) /*!< SD High Capacity <32G, SD Extended Capacity <2T */
#define SD_SPEED_DEFAULT ((uint32_t)0x00000000U) /*!< maintain current speed , clock frequency max value 25M*/
#define SD_SPEED_HIGH ((uint32_t)0x00000001U) /*!< switch high speed, clock frequency max value 50M */
#define SD_SPEED_SDR25 ((uint32_t)0x80FFFF01U) /*!< switch UHS-I SDR25 speed, clock frequency max value 50M */
#define SD_SPEED_SDR50 ((uint32_t)0x80FF1F02U) /*!< switch UHS-I SDR50 speed, clock frequency max value 104M */
#define SD_SPEED_SDR104 ((uint32_t)0x80FF1F03U) /*!< switch UHS-I SDR104 speed, clock frequency max value 208M */
#define SD_SPEED_DDR50 ((uint32_t)0x80FF1F04U) /*!< switch UHS-I DDR speed , clock frequency max value 50M */
/* supported memory cards types */
typedef enum
{
SDIO_STD_CAPACITY_SD_CARD_V1_1 = 0, /* standard capacity SD card version 1.1 */
SDIO_STD_CAPACITY_SD_CARD_V2_0, /* standard capacity SD card version 2.0 */
SDIO_STD_CAPACITY_SD_CARD_V3_0, /* standard capacity SD card version 3.0 */
SDIO_HIGH_CAPACITY_SD_CARD, /* high capacity SD card */
SDIO_SECURE_DIGITAL_IO_CARD, /* secure digital IO card */
SDIO_SECURE_DIGITAL_IO_COMBO_CARD, /* secure digital IO combo card */
SDIO_MULTIMEDIA_CARD, /* multimedia card */
SDIO_HIGH_CAPACITY_MULTIMEDIA_CARD, /* high capacity multimedia card */
SDIO_HIGH_SPEED_MULTIMEDIA_CARD /* high speed multimedia card */
} sdio_card_type_enum;
/* card identification (CID) register */
typedef struct
{
__IO uint8_t mid; /* manufacturer ID */
__IO uint16_t oid; /* OEM/application ID */
__IO uint32_t pnm0; /* product name */
__IO uint8_t pnm1; /* product name */
__IO uint8_t prv; /* product revision */
__IO uint32_t psn; /* product serial number */
__IO uint16_t mdt; /* manufacturing date */
__IO uint8_t cid_crc; /* CID CRC7 checksum */
} sd_cid_struct;
/* CSD register (CSD version 1.0 and 2.0) */
typedef struct
{
__IO uint8_t csd_struct; /* CSD struct */
__IO uint8_t taac; /* data read access-time */
__IO uint8_t nsac; /* data read access-time in CLK cycles */
__IO uint8_t tran_speed; /* max. data transfer rate */
__IO uint16_t ccc; /* card command classes */
__IO uint8_t read_bl_len; /* max. read data block length */
__IO uint8_t read_bl_partial; /* partial blocks for read allowed */
__IO uint8_t write_blk_misalign; /* write block misalignment */
__IO uint8_t read_blk_misalign; /* read block misalignment */
__IO uint8_t dsp_imp; /* DSR implemented */
__IO uint32_t c_size; /* device size, 12 bits in CSD version 1.0, 22 bits in CSD version 2.0 */
__IO uint8_t vdd_r_curr_min; /* max. read current @VDD min, CSD version 1.0 */
__IO uint8_t vdd_r_curr_max; /* max. read current @VDD max, CSD version 1.0 */
__IO uint8_t vdd_w_curr_min; /* max. write current @VDD min, CSD version 1.0 */
__IO uint8_t vdd_w_curr_max; /* max. write current @VDD max, CSD version 1.0 */
__IO uint8_t c_size_mult; /* device size multiplier, CSD version 1.0 */
__IO uint8_t erase_blk_en; /* erase single block enable */
__IO uint8_t sector_size; /* erase sector size */
__IO uint8_t wp_grp_size; /* write protect group size */
__IO uint8_t wp_grp_enable; /* write protect group enable */
__IO uint8_t r2w_factor; /* write speed factor */
__IO uint8_t write_bl_len; /* max. write data block length */
__IO uint8_t write_bl_partial; /* partial blocks for write allowed */
__IO uint8_t file_format_grp; /* file format group */
__IO uint8_t copy_flag; /* copy flag (OTP) */
__IO uint8_t perm_write_protect; /* permanent write protection */
__IO uint8_t tmp_write_protect; /* temporary write protection */
__IO uint8_t file_format; /* file format */
__IO uint8_t csd_crc; /* CSD CRC checksum */
} sd_csd_struct;
/* information of card */
typedef struct
{
sd_cid_struct card_cid; /* CID register */
sd_csd_struct card_csd; /* CSD register */
sdio_card_type_enum card_type; /* card tpye */
uint32_t card_capacity; /* card capacity */
uint32_t card_blocksize; /* card block size */
uint16_t card_rca; /* card relative card address */
} sd_card_info_struct;
/* SD error flags */
typedef enum
{
SD_OUT_OF_RANGE = 0, /* command's argument was out of range */
SD_ADDRESS_ERROR, /* misaligned address which did not match the block length */
SD_BLOCK_LEN_ERROR, /* transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
SD_ERASE_SEQ_ERROR, /* an error in the sequence of erase command occurs */
SD_ERASE_PARAM, /* an invalid selection of write-blocks for erase occurred */
SD_WP_VIOLATION, /* attempt to program a write protect block or permanent write protected card */
SD_LOCK_UNLOCK_FAILED, /* sequence or password error has been detected in lock/unlock card command */
SD_COM_CRC_ERROR, /* CRC check of the previous command failed */
SD_ILLEGAL_COMMAND, /* command not legal for the card state */
SD_CARD_ECC_FAILED, /* card internal ECC was applied but failed to correct the data */
SD_CC_ERROR, /* internal card controller error */
SD_GENERAL_UNKNOWN_ERROR, /* general or unknown error occurred during the operation */
SD_CSD_OVERWRITE, /* read only section of the CSD does not match the card content or an attempt to reverse the copy or permanent WP bits was made */
SD_WP_ERASE_SKIP, /* only partial address space was erased or the temporary or permanent write protected card was erased */
SD_CARD_ECC_DISABLED, /* command has been executed without using internal ECC */
SD_ERASE_RESET, /* erase sequence was cleared before executing because an out of erase sequence command was received */
SD_AKE_SEQ_ERROR, /* error in the sequence of the authentication process */
SD_CMD_CRC_ERROR, /* command response received (CRC check failed) */
SD_DATA_CRC_ERROR, /* data block sent/received (CRC check failed) */
SD_CMD_RESP_TIMEOUT, /* command response timeout */
SD_DATA_TIMEOUT, /* data timeout */
SD_TX_UNDERRUN_ERROR, /* transmit FIFO underrun error occurs */
SD_RX_OVERRUN_ERROR, /* received FIFO overrun error occurs */
SD_START_BIT_ERROR, /* start bit error in the bus */
SD_VOLTRANGE_INVALID, /* the voltage range is invalid */
SD_PARAMETER_INVALID, /* the parameter is invalid */
SD_OPERATION_IMPROPER, /* the operation is improper */
SD_FUNCTION_UNSUPPORTED, /* the function is unsupported */
SD_ERROR, /* an error occurred */
SD_DMA_ERROR, /* an error when idma transfer */
SD_OK /* no error occurred */
} sd_error_enum;
typedef enum
{
SD_NO_TRANSFER = 0, /* no data transfer is acting */
SD_TRANSFER_IN_PROGRESS /* data transfer is in progress */
} sd_transfer_state_enum;
/* function declarations */
/* initialize the SD card and make it in standby state */
sd_error_enum sd_init(uint32_t SDIO);
/* initialize the card and get CID and CSD of the card */
sd_error_enum sd_card_init(uint32_t SDIO);
/* configure the clock and the work voltage, and get the card type */
sd_error_enum sd_power_on(uint32_t SDIO);
/* close the power of SDIO */
sd_error_enum sd_power_off(uint32_t SDIO);
/* configure the bus mode */
sd_error_enum sd_bus_mode_config(uint32_t SDIO, uint32_t busmode, uint32_t speed);
/* configure the mode of transmission */
sd_error_enum sd_transfer_mode_config(uint32_t txmode);
/* read a block data into a buffer from the specified address of a card */
sd_error_enum sd_block_read(uint32_t SDIO, uint32_t *preadbuffer, uint32_t readaddr, uint16_t blocksize);
/* read multiple blocks data into a buffer from the specified address of a card */
sd_error_enum sd_multiblocks_read(uint32_t SDIO, uint32_t *preadbuffer, uint32_t readaddr, uint16_t blocksize, uint32_t blocksnumber);
/* write a block data to the specified address of a card */
sd_error_enum sd_block_write(uint32_t SDIO, uint32_t *pwritebuffer, uint32_t writeaddr, uint16_t blocksize);
/* write multiple blocks data to the specified address of a card */
sd_error_enum sd_multiblocks_write(uint32_t SDIO, uint32_t *pwritebuffer, uint32_t writeaddr, uint16_t blocksize, uint32_t blocksnumber);
/* erase a continuous area of a card */
sd_error_enum sd_erase(uint32_t SDIO, uint32_t startaddr, uint32_t endaddr);
/* process all the interrupts which the corresponding flags are set */
sd_error_enum sd_interrupts_process(uint32_t SDIO);
/* select or deselect a card */
sd_error_enum sd_card_select_deselect(uint32_t SDIO, uint16_t cardrca);
/* get the card status whose response format R1 contains a 32-bit field */
sd_error_enum sd_cardstatus_get(uint32_t SDIO, uint32_t *pcardstatus);
/* get the SD status, the size of the SD status is one data block of 512 bit */
sd_error_enum sd_sdstatus_get(uint32_t SDIO, uint32_t *psdstatus);
/* stop an ongoing data transfer */
sd_error_enum sd_transfer_stop(uint32_t SDIO);
/* lock or unlock a card */
sd_error_enum sd_lock_unlock(uint32_t SDIO, uint8_t lockstate);
/* get the data transfer state */
sd_transfer_state_enum sd_transfer_state_get(uint32_t SDIO);
/* get SD card capacity(KB) */
uint32_t sd_card_capacity_get(uint32_t SDIO);
/* get the detailed information of the SD card based on received CID and CSD */
sd_error_enum sd_card_information_get(uint32_t SDIO, sd_card_info_struct *pcardinfo);
/* switch 1.8V power level of SD card */
sd_error_enum sd_card_voltage_switch(uint32_t SDIO);
#ifdef USE_18V_SWITCH
/* configure CPDM */
void cpdm_config(void);
/* perform sampling point tuning using tuning command */
sd_error_enum sd_tuning(uint32_t SDIO);
#endif /* USE_18V_SWITCH */
#endif /* __SDCARD_H_ */
828ECO/drivers/include/drv_spi.h
+81
View File
@@ -0,0 +1,81 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-12-20 BruceOu first implementation
* 2025-10-10 WangShun compatible with RT-Studio
*/
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#define RT_SPI_USING_DMA
#if !defined(SOC_SERIES_GD32H7xx) && !defined(SOC_SERIES_GD32H75E)
#undef RT_SPI_USING_DMA
#endif
struct gd32_spi_cs
{
uint32_t GPIOx;
uint32_t GPIO_Pin;
};
#ifdef RT_SPI_USING_DMA
typedef struct
{
/* dma peripheral */
uint32_t dma_periph;
/* dma txchannel */
dma_channel_enum txdma_ch;
/* dma rxchannel */
dma_channel_enum rxdma_ch;
/* tx dma request */
uint32_t dma_mux_req_tx;
/* rx dma request */
uint32_t dma_mux_req_rx;
/* dma flag */
uint32_t rx_flag;
/* setting receive len */
rt_size_t setting_recv_len;
} gd32_spi_dma;
#endif
/* gd32 spi dirver class */
struct gd32_spi
{
uint32_t spi_periph;
char *bus_name;
rcu_periph_enum spi_clk;
struct rt_spi_bus *spi_bus;
const char *sck_pin_name; /* sck pin name */
const char *miso_pin_name; /* miso pin name */
const char *mosi_pin_name; /* mosi pin name */
const char *alternate; /* afio mode */
#ifdef RT_SPI_USING_DMA
gd32_spi_dma *spi_dma;
#endif
};
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_SPI_H__ */
828ECO/drivers/include/drv_usart.h
+82
View File
@@ -0,0 +1,82 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-20 BruceOu first implementation
* 2025-10-09 WangShun compatible with RT-Studio
*/
#ifndef __DRV_USART_H__
#define __DRV_USART_H__
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(SOC_SERIES_GD32H7xx) || !defined(SOC_SERIES_GD32H75E)
#undef RT_SERIAL_USING_DMA
#endif
#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n))
#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n))
#ifdef RT_SERIAL_USING_DMA
typedef struct
{
/* dma peripheral */
uint32_t dma_periph;
/* dma channel */
dma_channel_enum dma_ch;
#if defined(SOC_SERIES_GD32H7xx) || defined(SOC_SERIES_GD32H75E)
/* rx dma request */
uint32_t dma_mux_req_rx;
#endif
/* dma flag */
uint32_t rx_flag;
/* dma irq channel */
uint8_t rx_irq_ch;
/* setting receive len */
rt_size_t setting_recv_len;
/* last receive index */
rt_size_t last_recv_index;
} gd32_uart_dma;
#endif
/* GD32 uart driver */
struct gd32_uart
{
uint32_t uart_periph; /* Instance */
IRQn_Type irqn; /* irqn */
rcu_periph_enum per_clk; /* uart_clk */
const char *tx_pin_name; /* tx pin name */
const char *rx_pin_name; /* rx pin name */
const char *alternate; /* rx pin name */
#ifdef RT_SERIAL_USING_DMA
gd32_uart_dma *uart_dma;
#ifdef RT_SERIAL_USING_TX_DMA
gd32_uart_dma *uart_tx_dma;
#endif
#endif
struct rt_serial_device * serial; /* serial device */
char *device_name;
};
int rt_hw_usart_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_USART_H__ */
828ECO/drivers/include/synopsys_emac.h
+1285
View File
File diff suppressed because it is too large. Load diff
828ECO/drivers/include/usb/drv_otghs_dev.h
+29
View File
@@ -0,0 +1,29 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef __DRV_OTGFS_DEV_H__
#define __DRV_OTGFS_DEV_H__
#include <rtthread.h>
#include "drv_usb_dev.h"
void usbd_reset_callback(void);
void usbd_setup_stage_callback(struct urequest *setup_packet);
void usbd_data_in_stage_callback(uint8_t epnum, uint16_t data_count);
void usbd_data_out_stage_callback(uint8_t epnum, uint16_t data_count);
void usbd_set_connection_state(uint8_t state);
int gd_usbd_register(void);
#endif
828ECO/drivers/include/usb/drv_otghs_host.h
+34
View File
@@ -0,0 +1,34 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef __DRV_OTGFS_HOST_H__
#define __DRV_OTGFS_HOST_H__
#include <rtthread.h>
#include "drv_usb_host.h"
#include "drv_usbh_transc.h"
#include "drv_usbh_pipe.h"
#define OTG_FS_PORT 1
#if defined(BSP_USING_USB) && defined(RT_USING_USB_HOST)
void usbh_connect_callback(usb_core_driver *hhcd);
void usbh_disconnect_callback(usb_core_driver *hhcd);
void usbh_hc_notifyurbchange_callback(usb_core_driver *hhcd, uint8_t chnum, usb_urb_state urb_state);
int gd_usbh_register(void);
#endif /* BSP_USING_USB && RT_USING_USB_HOST */
#endif
828ECO/drivers/include/usb/drv_usb_core.h
+369
View File
@@ -0,0 +1,369 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USB_CORE_H
#define DRV_USB_CORE_H
#include "drv_usb_regs.h"
#define USB_FS_EP0_MAX_LEN 64U /*!< maximum packet size of endpoint 0 */
#define HC_MAX_PACKET_COUNT 140U /*!< maximum packet count */
#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /*!< endpoint number */
#define EP_DIR(x) ((uint8_t)((x) >> 7)) /*!< endpoint direction */
typedef struct urequest usb_req;
enum _usb_eptype
{
USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */
USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */
USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */
USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */
USB_EPTYPE_MASK = 3U /*!< endpoint type mask */
};
typedef enum
{
USB_OTG_OK = 0U, /*!< USB OTG status OK */
USB_OTG_FAIL /*!< USB OTG status fail */
} usb_otg_status;
typedef enum
{
USB_OK = 0U, /*!< USB status OK */
USB_FAIL /*!< USB status fail */
} usb_status;
typedef enum
{
USB_USE_FIFO, /*!< USB use FIFO transfer mode */
USB_USE_DMA /*!< USB use DMA transfer mode */
} usb_transfer_mode;
typedef enum
{
LPM_L0 = 0U, /*!< on */
LPM_L1, /*!< LPM L1 sleep */
LPM_L2, /*!< suspend */
LPM_L3, /*!< off */
} usb_lpm_state;
enum usb_ctl_status
{
USB_CTL_IDLE = 0U, /*!< USB control transfer idle state */
USB_CTL_DATA_IN, /*!< USB control transfer data IN state */
USB_CTL_LAST_DATA_IN, /*!< USB control transfer last data IN state */
USB_CTL_DATA_OUT, /*!< USB control transfer data OUT state */
USB_CTL_LAST_DATA_OUT, /*!< USB control transfer last data OUT state */
USB_CTL_STATUS_IN, /*!< USB control transfer status IN state*/
USB_CTL_STATUS_OUT /*!< USB control transfer status OUT state */
};
typedef enum
{
LPM_L0_ACTIVE = 0U, /*!< on */
LPM_L1_ACTIVE, /*!< LPM L1 sleep */
} usb_lpm_type;
typedef struct
{
uint8_t core_enum; /*!< USB core type */
uint8_t core_speed; /*!< USB core speed */
uint8_t num_pipe; /*!< USB host channel numbers */
uint8_t num_ep; /*!< USB device endpoint numbers */
uint8_t transfer_mode; /*!< USB transfer mode */
uint8_t phy_itf; /*!< USB core PHY interface */
uint8_t sof_enable; /*!< USB SOF output */
uint8_t low_power; /*!< USB low power */
uint8_t lpm_enable; /*!< USB link power mode(LPM) */
uint8_t vbus_sensing_enable; /*!< USB VBUS sensing feature */
uint8_t use_dedicated_ep1; /*!< USB dedicated endpoint1 interrupt */
uint8_t use_external_vbus; /*!< enable or disable the use of the external VBUS */
uint32_t base_reg; /*!< base register address */
} usb_core_basic;
#ifdef USE_DEVICE_MODE
/* USB descriptor */
typedef struct _usb_desc
{
uint8_t *dev_desc; /*!< device descriptor */
uint8_t *config_desc; /*!< configuration descriptor */
uint8_t *bos_desc; /*!< BOS descriptor */
#ifdef USE_USB_HS
uint8_t *other_speed_config_desc; /*!< other speed configuration descriptor */
uint8_t *qualifier_desc; /*!< qualifier descriptor */
#endif
void * const *strings; /*!< string descriptor */
} usb_desc;
/* USB power management */
typedef struct _usb_pm
{
uint8_t power_mode; /*!< power mode */
uint8_t power_low; /*!< power low */
uint8_t dev_remote_wakeup; /*!< remote wakeup */
uint8_t remote_wakeup_on; /*!< remote wakeup on */
usb_lpm_state lpm_state; /*!< LPM state */
uint32_t BESL; /*!< BESL value */
} usb_pm;
/* USB control information */
typedef struct _usb_control
{
usb_req req; /*!< USB standard device request */
uint8_t ctl_state; /*!< USB control transfer state */
uint8_t ctl_zlp; /*!< zero length package */
} usb_control;
typedef struct
{
struct
{
uint8_t num : 4U; /*!< the endpoint number.it can be from 0 to 6 */
uint8_t pad : 3U; /*!< padding between number and direction */
uint8_t dir : 1U; /*!< the endpoint direction */
} ep_addr;
uint8_t ep_type; /*!< USB endpoint type */
uint8_t ep_stall; /*!< USB endpoint STALL status */
uint8_t frame_num; /*!< number of frame */
uint16_t max_len; /*!< maximum packet length */
/* transaction level variables */
uint8_t *xfer_buf; /*!< transmit buffer */
uint32_t xfer_len; /*!< transmit buffer length */
uint32_t xfer_count; /*!< transmit buffer count */
uint32_t remain_len; /*!< remain packet length */
uint32_t dma_addr; /*!< DMA address */
} usb_transc;
typedef struct _usb_core_driver usb_dev;
typedef struct _usb_class_core
{
uint8_t alter_set; /*!< alternative set */
uint8_t command; /*!< device class request command */
uint8_t (*init)(usb_dev *udev, uint8_t config_index); /*!< initialize handler */
uint8_t (*deinit)(usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */
uint8_t (*req_proc)(usb_dev *udev, usb_req *req); /*!< device request handler */
uint8_t (*set_intf)(usb_dev *udev, usb_req *req); /*!< device set interface callback */
uint8_t (*ctlx_in)(usb_dev *udev); /*!< device control IN callback */
uint8_t (*ctlx_out)(usb_dev *udev); /*!< device control OUT callback */
uint8_t (*data_in)(usb_dev *udev, uint8_t ep_num); /*!< device data IN handler */
uint8_t (*data_out)(usb_dev *udev, uint8_t ep_num); /*!< device data OUT handler */
uint8_t (*SOF)(usb_dev *udev); /*!< start of frame handler */
uint8_t (*incomplete_isoc_in)(usb_dev *udev); /*!< incomplete synchronization IN transfer handler */
uint8_t (*incomplete_isoc_out)(usb_dev *udev); /*!< incomplete synchronization OUT transfer handler */
} usb_class_core;
typedef struct _usb_perp_dev
{
uint8_t config; /*!< configuration */
uint8_t dev_addr; /*!< device address */
__IO uint8_t cur_status; /*!< current status */
__IO uint8_t backup_status; /*!< backup status */
usb_transc transc_in[USBHS_MAX_TX_FIFOS]; /*!< endpoint IN transaction */
usb_transc transc_out[USBHS_MAX_TX_FIFOS]; /*!< endpoint OUT transaction */
usb_pm pm; /*!< power management */
usb_control control; /*!< USB control information */
usb_desc *desc; /*!< USB descriptors pointer */
usb_class_core *class_core; /*!< class driver */
void *class_data[4]; /*!< class data pointer */
void *user_data; /*!< user data pointer */
void *pdata; /*!< reserved data pointer */
} usb_perp_dev;
#endif /* USE_DEVICE_MODE */
#ifdef USE_HOST_MODE
typedef enum _usb_pipe_status
{
PIPE_IDLE = 0U, /*!< host pipe IDLE status */
PIPE_XF, /*!< host pipe transfer completed status */
PIPE_HALTED, /*!< host pipe halted status */
PIPE_NAK, /*!< host pipe NAK status */
PIPE_NYET, /*!< host pipe NYET status */
PIPE_STALL, /*!< host pipe STALL status */
PIPE_TRACERR, /*!< host pipe transaction error status */
PIPE_BBERR, /*!< host pipe babble error status */
PIPE_REQOVR, /*!< host pipe frame overrun status */
PIPE_DTGERR, /*!< host pipe data toggle error status */
} usb_pipe_status;
typedef enum _usb_pipe_mode
{
PIPE_PERIOD = 0U, /*!< USB host pipe PERIOD mode */
PIPE_NON_PERIOD = 1U /*!< USB host pipe NOT PERIOD mode */
} usb_pipe_mode;
typedef enum _usb_urb_state
{
URB_IDLE = 0U, /*!< USB URB IDLE state */
URB_DONE, /*!< USB URB DONE state */
URB_NOTREADY, /*!< USB URB NOT READY state */
URB_ERROR, /*!< USB URB ERROR state */
URB_STALL, /*!< USB URB STALL state */
URB_PING /*!< USB URB PING state */
} usb_urb_state;
typedef struct _usb_pipe
{
uint8_t in_used; /*!< pipe used */
uint8_t dev_addr; /*!< USB device address */
uint32_t dev_speed; /*!< USB device speed */
struct
{
uint8_t num; /*!< endpoint numbers */
uint8_t dir; /*!< endpoint direction */
uint8_t type; /*!< endpoint transfer type */
uint16_t mps; /*!< endpoint max packet size */
} ep;
__IO uint8_t supp_ping; /*!< host pipe support PING */
__IO uint8_t do_ping; /*!< host pipe do PING */
__IO uint32_t DPID; /*!< data PID */
uint8_t *xfer_buf; /*!< USB transfer buffer */
uint32_t xfer_len; /*!< USB transfer length */
uint32_t xfer_count; /*!< USB transfer count */
uint8_t data_toggle_in; /*!< toggle DATA IN */
uint8_t data_toggle_out; /*!< toggle DATA OUT */
__IO uint32_t err_count; /*!< error count */
__IO usb_pipe_status pp_status; /*!< USB pipe status */
__IO usb_urb_state urb_state; /*!< USB URB state */
} usb_pipe;
typedef struct _usb_host_drv
{
__IO uint32_t connect_status; /*!< connect status */
__IO uint32_t port_enabled; /*!< USB port enable */
__IO uint32_t backup_xfercount[USBHS_MAX_TX_FIFOS]; /*!< USB backup transfer data count */
usb_pipe pipe[USBHS_MAX_TX_FIFOS]; /*!< USB host pipe handles */
void *data; /*!< user data pointer */
} usb_host_drv;
#endif /* USE_HOST_MODE */
typedef struct _usb_core_driver
{
usb_core_basic bp; /*!< USB basic parameters */
usb_core_regs regs; /*!< USB registers */
#ifdef USE_DEVICE_MODE
usb_perp_dev dev; /*!< USB peripheral device */
#endif /* USE_DEVICE_MODE */
#ifdef USE_HOST_MODE
usb_host_drv host; /*!< USB peripheral host */
#endif /* USE_HOST_MODE */
} usb_core_driver;
typedef enum
{
BCD_NONE = 0,
BCD_SDP,
BCD_DCP,
BCD_CDP,
BCD_PS2,
BCD_ERROR
} bcd_type;
/* static inline function definitions */
/*!
\brief get the global interrupts
\param[in] usb_regs: pointer to USB core registers
\param[out] none
\retval interrupt status
*/
__STATIC_INLINE uint32_t usb_coreintr_get(usb_core_regs *usb_regs)
{
uint32_t reg_data = usb_regs->gr->GINTEN;
reg_data &= usb_regs->gr->GINTF;
return reg_data;
}
/*!
\brief set USB RX FIFO size
\param[in] usb_regs: pointer to USB core registers
\param[in] size: assigned FIFO size
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_set_rxfifo(usb_core_regs *usb_regs, uint16_t size)
{
usb_regs->gr->GRFLEN = size;
}
/*!
\brief enable the global interrupts
\param[in] usb_regs: pointer to USB core registers
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_globalint_enable(usb_core_regs *usb_regs)
{
/* enable USB global interrupt */
usb_regs->gr->GAHBCS |= GAHBCS_GINTEN;
}
/*!
\brief disable the global interrupts
\param[in] usb_regs: pointer to USB core registers
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_globalint_disable(usb_core_regs *usb_regs)
{
/* disable USB global interrupt */
usb_regs->gr->GAHBCS &= ~GAHBCS_GINTEN;
}
/* function declarations */
/* configures USB parameters */
void usb_para_init(usb_core_driver *core, uint32_t usb_periph, uint32_t usb_speed);
/* configure core capabilities */
usb_status usb_basic_init(usb_core_basic *usb_basic, usb_core_regs *usb_regs);
/*initializes the USB controller registers and prepares the core device mode or host mode operation*/
usb_status usb_core_init(usb_core_basic usb_basic, usb_core_regs *usb_regs);
/* write a packet into the TX FIFO associated with the endpoint */
usb_status usb_txfifo_write(usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count);
/* read a packet from the RX FIFO associated with the endpoint */
void *usb_rxfifo_read(usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count);
/* flush a TX FIFO or all TX FIFOs */
usb_status usb_txfifo_flush(usb_core_regs *usb_regs, uint8_t fifo_num);
/* flush the entire RX FIFO */
usb_status usb_rxfifo_flush(usb_core_regs *usb_regs);
/* set endpoint or channel TX FIFO size */
void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size);
/* set USB current mode */
void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode);
void usb_clock_active(usb_core_driver *udev);
#endif /* DRV_USB_CORE_H */
828ECO/drivers/include/usb/drv_usb_dev.h
+195
View File
@@ -0,0 +1,195 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USB_DEV_H
#define DRV_USB_DEV_H
#include "drv_usb_core.h"
#if defined(BSP_USING_USB) && defined(RT_USING_USB_DEVICE)
#define EP_IN(x) ((uint8_t)(0x80U | (x))) /*!< device IN endpoint */
#define EP_OUT(x) ((uint8_t)(x)) /*!< device OUT endpoint */
#define EP_MAX_PACKET_SIZE_MASK 0x07FFU /*!< endpoint maximum packet size mask */
#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b))
/* static inline function definitions */
/*!
\brief configure the USB device to be disconnected
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_dev_disconnect(usb_core_driver *udev)
{
udev->regs.dr->DCTL |= DCTL_SD;
}
/*!
\brief configure the USB device to be connected
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_dev_connect(usb_core_driver *udev)
{
udev->regs.dr->DCTL &= ~DCTL_SD;
}
/*!
\brief set the USB device address
\param[in] udev: pointer to USB device
\param[in] dev_addr: device address for setting
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_devaddr_set(usb_core_driver *udev, uint8_t dev_addr)
{
udev->regs.dr->DCFG &= ~DCFG_DAR;
udev->regs.dr->DCFG |= (uint32_t)dev_addr << 4;
}
/*!
\brief read device all OUT endpoint interrupt register
\param[in] udev: pointer to USB device
\param[out] none
\retval interrupt status
*/
__STATIC_INLINE uint32_t usb_oepintnum_read(usb_core_driver *udev)
{
uint32_t value = udev->regs.dr->DAEPINT;
value &= udev->regs.dr->DAEPINTEN;
return (value & DAEPINT_OEPITB) >> 16;
}
/*!
\brief read device OUT endpoint interrupt flag register
\param[in] udev: pointer to USB device
\param[in] ep_num: endpoint number
\param[out] none
\retval interrupt status
*/
__STATIC_INLINE uint32_t usb_oepintr_read(usb_core_driver *udev, uint8_t ep_num)
{
uint32_t value = udev->regs.er_out[ep_num]->DOEPINTF;
value &= udev->regs.dr->DOEPINTEN;
return value;
}
/*!
\brief read device all IN endpoint interrupt register
\param[in] udev: pointer to USB device
\param[out] none
\retval interrupt status
*/
__STATIC_INLINE uint32_t usb_iepintnum_read(usb_core_driver *udev)
{
uint32_t value = udev->regs.dr->DAEPINT;
value &= udev->regs.dr->DAEPINTEN;
return value & DAEPINT_IEPITB;
}
/*!
\brief set remote wakeup signaling
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_rwkup_set(usb_core_driver *udev)
{
if (udev->dev.pm.dev_remote_wakeup)
{
/* enable remote wakeup signaling */
udev->regs.dr->DCTL |= DCTL_RWKUP;
}
}
/*!
\brief reset remote wakeup signaling
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_rwkup_reset(usb_core_driver *udev)
{
if (udev->dev.pm.dev_remote_wakeup)
{
/* disable remote wakeup signaling */
udev->regs.dr->DCTL &= ~DCTL_RWKUP;
}
}
/*!
\brief enable USB BCD function
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_bcd_enable(usb_core_driver *udev)
{
udev->regs.gr->GCCFG |= GCCFG_BCDEN;
}
/*!
\brief disable USB BCD function
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_bcd_disable(usb_core_driver *udev)
{
udev->regs.gr->GCCFG &= ~GCCFG_BCDEN;
}
/* function declarations */
/* initialize USB core registers for device mode */
usb_status usb_devcore_init(usb_core_driver *udev);
/* enable the USB device mode interrupts */
usb_status usb_devint_enable(usb_core_driver *udev);
/* active the USB endpoint 0 transaction */
usb_status usb_transc0_active(usb_core_driver *udev, usb_transc *transc);
/* active the USB transaction */
usb_status usb_ep_active(usb_core_driver *udev, uint8_t ep_addr, uint8_t ep_mps, uint8_t ep_attr);
/* deactivate the USB transaction */
usb_status usb_ep_deactivate(usb_core_driver *udev, uint8_t ep_addr);
/* configure USB transaction to start IN transfer */
usb_status usb_ep_inxfer(usb_core_driver *udev, uint8_t ep_addr, uint8_t *buf, uint16_t count);
/* configure USB transaction to start OUT transfer */
usb_status usb_ep_outxfer(usb_core_driver *udev, uint8_t ep_addr, uint8_t *buf, uint16_t count);
/* set the USB transaction STALL status */
usb_status usb_ep_stall(usb_core_driver *udev, uint8_t ep_addr);
/* clear the USB transaction STALL status */
usb_status usb_ep_clrstall(usb_core_driver *udev, uint8_t ep_addr);
/* read device IN endpoint interrupt flag register */
uint32_t usb_iepintr_read(usb_core_driver *udev, uint8_t ep_num);
/* configures OUT endpoint 0 to receive SETUP packets */
void usb_ctlep_startout(usb_core_driver *udev);
/* active remote wakeup signaling */
void usb_rwkup_active(usb_core_driver *udev);
/* active USB core clock */
void usb_clock_active(usb_core_driver *udev);
/* USB device suspend */
void usb_dev_suspend(usb_core_driver *udev);
/* stop the device and clean up FIFOs */
void usb_dev_stop(usb_core_driver *udev);
/* USB battery charging detect operation */
bcd_type usbd_bcd_detect(usb_core_driver *udev);
#endif /* BSP_USING_USB && RT_USING_USB_DEVICE */
#endif /* DRV_USB_DEV_H */
828ECO/drivers/include/usb/drv_usb_host.h
+93
View File
@@ -0,0 +1,93 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USB_HOST_H
#define DRV_USB_HOST_H
#include "drv_usb_core.h"
#if defined(BSP_USING_USB) && defined(RT_USING_USB_HOST)
typedef enum
{
USBH_OK = 0U,
USBH_BUSY,
USBH_FAIL,
USBH_NOT_SUPPORTED,
USBH_UNRECOVERED_ERROR,
USBH_SPEED_UNKNOWN_ERROR,
USBH_APPLY_DEINIT
} usbh_status;
/*!
\brief get USB even frame
\param[in] udev: pointer to USB device
\param[out] none
\retval USB even frame state
*/
__STATIC_INLINE uint8_t usb_frame_even(usb_core_driver *udev)
{
return (uint8_t) !(udev->regs.hr->HFINFR & 0x01U);
}
/*!
\brief read USB port
\param[in] udev: pointer to USB device
\param[out] none
\retval port status
*/
__STATIC_INLINE uint32_t usb_port_read(usb_core_driver *udev)
{
return *udev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC);
}
/*!
\brief get USB current speed
\param[in] udev: pointer to USB device
\param[out] none
\retval USB current speed
*/
__STATIC_INLINE uint32_t usb_curspeed_get(usb_core_driver *udev)
{
return *udev->regs.HPCS & HPCS_PS;
}
/*!
\brief get USB current frame
\param[in] udev: pointer to USB device
\param[out] none
\retval USB current frame
*/
__STATIC_INLINE uint32_t usb_curframe_get(usb_core_driver *udev)
{
return (udev->regs.hr->HFINFR & 0xFFFFU);
}
/* function declarations */
/* initializes USB core for host mode */
usb_status usb_host_init(usb_core_driver *udev);
/* control the VBUS to power */
void usb_portvbus_switch(usb_core_driver *udev, uint8_t state);
/* reset host port */
uint32_t usb_port_reset(usb_core_driver *udev);
/* initialize host pipe */
usb_status usb_pipe_init(usb_core_driver *udev, uint8_t pipe_num);
/* prepare host pipe for transferring packets */
usb_status usb_pipe_xfer(usb_core_driver *udev, uint8_t pipe_num);
/* halt host pipe */
usb_status usb_pipe_halt(usb_core_driver *udev, uint8_t pipe_num);
/* configure host pipe to do ping operation */
usb_status usb_pipe_ping(usb_core_driver *udev, uint8_t pipe_num);
/* stop the USB host and clean up FIFO */
void usb_host_stop(usb_core_driver *udev);
#endif /* BSP_USING_USB && RT_USING_USB_HOST */
#endif /* DRV_USB_HOST_H */
828ECO/drivers/include/usb/drv_usb_hw.h
+42
View File
@@ -0,0 +1,42 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USB_HW_H
#define DRV_USB_HW_H
#include "drv_usb_core.h"
/* function declarations */
/* configure USB clock */
void usb_rcu_config(void);
/* configure USB data line GPIO */
void usb_gpio_config(void);
/* configure USB interrupt */
void usb_intr_config(void);
/* initializes delay unit using Timer2 */
void usb_timer_init(void);
/* delay in microseconds */
void usb_udelay(const uint32_t usec);
/* delay in milliseconds */
void usb_mdelay(const uint32_t msec);
/* configure USB clock */
void pllusb_rcu_config(uint32_t usb_periph);
#ifdef USE_HOST_MODE
/* configure systick */
void systick_config(void);
/* configure USB VBus */
void usb_vbus_config(void);
/* drive USB VBus */
void usb_vbus_drive(uint8_t State);
#endif /* USE_HOST_MODE */
#endif /* DRV_USB_HW_H */
828ECO/drivers/include/usb/drv_usb_regs.h
+728
View File
@@ -0,0 +1,728 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USB_REGS_H
#define DRV_USB_REGS_H
#include "usb_conf.h"
#define USBHS0 USBHS_BASE
#define USBHS1 (USBHS_BASE + 0x00040000U)
#define USBHS0_REG_BASE USBHS0 /*!< base address of USBHS0 registers */
#define USBHS1_REG_BASE USBHS1 /*!< base address of USBHS1 registers */
/* register definition */
#define USBHS_MAX_TX_FIFOS 16U /*!< FIFO number */
typedef struct
{
__IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */
__IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */
__IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */
__IO uint32_t GUSBCS; /*!< USB global USB control and status register 00Ch */
__IO uint32_t GRSTCTL; /*!< USB global reset control register 010h */
__IO uint32_t GINTF; /*!< USB global interrupt flag register 014h */
__IO uint32_t GINTEN; /*!< USB global interrupt enable register 018h */
__IO uint32_t GRSTATR; /*!< USB receive status debug read register 01Ch */
__IO uint32_t GRSTATP; /*!< USB receive status and pop register 020h */
__IO uint32_t GRFLEN; /*!< USB global receive FIFO length register 024h */
__IO uint32_t DIEP0TFLEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length register 028h */
__IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status register 02Ch */
uint32_t Reserved30[2]; /*!< Reserved 030h */
__IO uint32_t GCCFG; /*!< USB global core configuration register 038h */
__IO uint32_t CID; /*!< USB core ID register 03Ch */
uint32_t Reserved40[5]; /*!< Reserved 040h-053h */
__IO uint32_t GLPMCFG; /*!< LPM configuration register 54h */
__IO uint32_t PWRD; /*!< power down register 58h */
uint32_t Reserved5C; /*!< Reserved 5Ch */
__IO uint32_t ADPCTL; /*!< ADP control and status register 60h */
uint32_t Reserved64[3]; /*!< Reserved 64h-6Fh */
__IO uint32_t PHYCTL; /*!< USBHS PHY control register 70h */
uint32_t Reserved74[35]; /*!< Reserved 74h-FFh */
__IO uint32_t HPTFLEN; /*!< USB host periodic transmit FIFO length register 100h */
__IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */
} usb_gr;
typedef struct
{
__IO uint32_t HCTL; /*!< USB host control register 400h */
__IO uint32_t HFT; /*!< USB host frame interval register 404h */
__IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */
uint32_t Reserved40C; /*!< Reserved 40Ch */
__IO uint32_t HPTFQSTAT; /*!< USB host periodic transmit FIFO/queue status register 410h */
__IO uint32_t HACHINT; /*!< USB host all channels interrupt register 414h */
__IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */
} usb_hr;
typedef struct
{
__IO uint32_t HCHCTL; /*!< USB host channel control register 500h */
__IO uint32_t HCHSTCTL; /*!< Reserved 504h */
__IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */
__IO uint32_t HCHINTEN; /*!< USB host channel interrupt enable register 50Ch */
__IO uint32_t HCHLEN; /*!< USB host channel transfer length register 510h */
__IO uint32_t HCHDMAADDR; /*!< USB host channel-x DMA address register 514h*/
uint32_t Reserved[2];
} usb_pr;
typedef struct
{
__IO uint32_t DCFG; /*!< USB device configuration register 800h */
__IO uint32_t DCTL; /*!< USB device control register 804h */
__IO uint32_t DSTAT; /*!< USB device status register 808h */
uint32_t Reserved0C; /*!< Reserved 80Ch */
__IO uint32_t DIEPINTEN; /*!< USB device IN endpoint common interrupt enable register 810h */
__IO uint32_t DOEPINTEN; /*!< USB device OUT endpoint common interrupt enable register 814h */
__IO uint32_t DAEPINT; /*!< USB device all endpoints interrupt register 818h */
__IO uint32_t DAEPINTEN; /*!< USB device all endpoints interrupt enable register 81Ch */
uint32_t Reserved20; /*!< Reserved 820h */
uint32_t Reserved24; /*!< Reserved 824h */
__IO uint32_t DVBUSDT; /*!< USB device VBUS discharge time register 828h */
__IO uint32_t DVBUSPT; /*!< USB device VBUS pulsing time register 82Ch */
uint32_t Reserved30; /*!< Reserved 830h */
__IO uint32_t DIEPFEINTEN; /*!< USB Device IN endpoint FIFO empty interrupt enable register 834h */
__IO uint32_t DEP1INT; /*!< USB device endpoint 1 interrupt register 838h */
__IO uint32_t DEP1INTEN; /*!< USB device endpoint 1 interrupt enable register 83Ch */
uint32_t Reserved40; /*!< Reserved 840h */
__IO uint32_t DIEP1INTEN; /*!< USB device IN endpoint-1 interrupt enable register 844h */
uint32_t Reserved48[15]; /*!< Reserved 848-880h */
__IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */
} usb_dr;
typedef struct
{
__IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */
__IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved 900h + (EpNum * 20h) + 0Ch */
__IO uint32_t DIEPLEN; /*!< USB device IN endpoint transfer length register 900h + (EpNum * 20h) + 10h */
__IO uint32_t DIEPDMAADDR; /*!< Device IN endpoint-x DMA address register 900h + (EpNum * 20h) + 14h */
__IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */
} usb_erin;
typedef struct
{
__IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */
__IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved B00h + (EpNum * 20h) + 0Ch */
__IO uint32_t DOEPLEN; /*!< USB device IN endpoint transfer length register B00h + (EpNum * 20h) + 10h */
__IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */
} usb_erout;
typedef struct _usb_regs
{
usb_gr *gr; /*!< USBHS global registers */
usb_dr *dr; /*!< device control and status registers */
usb_hr *hr; /*!< host control and status registers */
usb_erin *er_in[8]; /*!< USB device IN endpoint register */
usb_erout *er_out[8]; /*!< USB device OUT endpoint register */
usb_pr *pr[16]; /*!< USB Host channel-x control register */
__IO uint32_t *HPCS; /*!< USB host port control and status register */
__IO uint32_t *DFIFO[USBHS_MAX_TX_FIFOS];
__IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */
} usb_core_regs;
/* global OTG control and status register bits definitions */
#define GOTGCS_OV BIT(20) /*!< select OTG version */
#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */
#define GOTGCS_ASV BIT(18) /*!< A-session valid */
#define GOTGCS_DI BIT(17) /*!< debounce interval */
#define GOTGCS_IDPS BIT(16) /*!< id pin status */
#define GOTGCS_EHE BIT(12) /*!< embedded host enable */
#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */
#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */
#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */
#define GOTGCS_HNPS BIT(8) /*!< HNP successes */
#define GOTGCS_BVOV BIT(7) /*!< override value of B-peripheral session valid */
#define GOTGCS_BVOE BIT(6) /*!< override enable of B-peripheral session valid */
#define GOTGCS_AVOV BIT(5) /*!< override value of A-peripheral session valid */
#define GOTGCS_AVOE BIT(4) /*!< override enable of A-peripheral session valid */
#define GOTGCS_VOV BIT(3) /*!< override value of VBUS valid */
#define GOTGCS_VOE BIT(2) /*!< override enable of VBUS valid */
#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */
#define GOTGCS_SRPS BIT(0) /*!< SRP successes */
/* global OTG interrupt flag register bits definitions */
#define GOTGINTF_IDCHG BIT(20) /*!< ID input change */
#define GOTGINTF_DF BIT(19) /*!< debounce finish */
#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */
#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */
#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */
#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */
#define GOTGINTF_SESEND BIT(2) /*!< session end */
/* global AHB control and status register bits definitions */
#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */
#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */
#define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */
#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */
#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */
/* global USB control and status register bits definitions */
#define GUSBCS_FDM BIT(30) /*!< force device mode */
#define GUSBCS_FHM BIT(29) /*!< force host mode */
#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */
#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */
#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */
#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */
#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */
#define GUSBCS_EMBPHY_FS BIT(6) /*!< embedded FS PHY selected */
#define GUSBCS_EMBPHY_HS BIT(5) /*!< embedded HS PHY selected */
#define GUSBCS_HS_CUR_FE BIT(4) /*!< HS current software enable */
#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */
/* global reset control register bits definitions */
#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */
#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */
#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */
#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */
#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */
#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */
#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */
#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */
/* global interrupt flag register bits definitions */
#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */
#define GINTF_SESIF BIT(30) /*!< session interrupt flag */
#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */
#define GINTF_IDPSC BIT(28) /*!< id pin status change */
#define GINTF_LPMIF BIT(27) /*!< LPM interrupt flag */
#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */
#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */
#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */
#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */
#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */
#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */
#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */
#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */
#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */
#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */
#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */
#define GINTF_RST BIT(12) /*!< USB reset */
#define GINTF_SP BIT(11) /*!< USB suspend */
#define GINTF_ESP BIT(10) /*!< early suspend */
#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */
#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */
#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */
#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */
#define GINTF_SOF BIT(3) /*!< start of frame */
#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */
#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */
#define GINTF_COPM BIT(0) /*!< current operation mode */
/* global interrupt enable register bits definitions */
#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */
#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */
#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */
#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */
#define GINTEN_LPMIE BIT(27) /*!< LPM interrupt enable */
#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */
#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */
#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */
#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */
#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */
#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */
#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */
#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */
#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */
#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */
#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */
#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */
#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */
#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */
#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */
#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */
#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */
#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */
#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */
#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */
#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */
/* global receive status read and pop register bits definitions */
#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */
#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */
#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */
#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */
#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */
/* global receive FIFO length register bits definitions */
#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */
/* host non-periodic transmit FIFO length register bits definitions */
#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */
#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */
/* USB IN endpoint 0 transmit FIFO length register bits definitions */
#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */
#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */
/* host non-periodic transmit FIFO/queue status register bits definitions */
#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */
#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */
#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */
#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/
#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */
#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */
#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */
/* global core configuration register bits definitions */
#define GCCFG_VDEN BIT(21) /*!< enable of VBUS sensing comparator to detect VBUS valid */
#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */
#define GCCFG_PWRON BIT(16) /*!< power on */
#define GCCFG_SDMEN BIT(15) /*!< secondary detection mode enable */
#define GCCFG_PEMEN BIT(14) /*!< primary detection mode enable */
#define GCCFG_DCDEN BIT(13) /*!< data connect detection mode enable */
#define GCCFG_BCDEN BIT(12) /*!< battery charging detection enable */
#define GCCFG_PS2F BIT(3) /*!< PS2 detection status */
#define GCCFG_SDF BIT(2) /*!< secondary detection status */
#define GCCFG_PDF BIT(1) /*!< primary detection status */
#define GCCFG_DCDF BIT(0) /*!< battery connect detection status */
/* core ID register bits definitions */
#define CID_CID BITS(0, 31) /*!< core ID */
/* global core LPM configuration register bits definitions */
#define GLPMCFG_BESLEN BIT(28) /*!< LPM Errata selection enable */
#define GLPMCFG_LPMRCS BITS(25, 27) /*!< LPM retry count status */
#define GLPMCFG_LPMSND BIT(24) /*!< send LPM transaction */
#define GLPMCFG_LPMRC BITS(21, 23) /*!< LPM retry count */
#define GLPMCFG_LPMCHI BITS(17, 20) /*!< channel number index */
#define GLPMCFG_RSOK BIT(16) /*!< Resume can be sent after sleep state */
#define GLPMCFG_LPMSLPS BIT(15) /*!< sleep status */
#define GLPMCFG_LPMRSP BITS(13, 14) /*!< response of LPM */
#define GLPMCFG_DSEN BIT(12) /*!< deep sleep enable */
#define GLPMCFG_BESLTH BITS(8, 11) /*!< BESL threshold */
#define GLPMCFG_SSEN BIT(7) /*!< shallow sleep enable */
#define GLPMCFG_REW BIT(6) /*!< bRemoteWake value */
#define GLPMCFG_BESL BITS(2, 5) /*!< best effort service latency */
#define GLPMCFG_ACKLPM BIT(1) /*!< ACK in LPM transaction enable */
#define GLPMCFG_LPMEN BIT(0) /*!< LPM enable */
/* power down register bits definition */
#define PWRD_ADPF BIT(23) /*!< ADP event interrupt flag */
#define PWRD_ADPMEN BIT(0) /*!< ADP module enable */
/* ADP control and status register bits definition */
#define ADPCTL_RWR BITS(27, 28) /*!< read and write request */
#define ADPCTL_ADPTFM BIT(26) /*!< the mask of ADP timeout interrupt flag */
#define ADPCTL_ADPSNFM BIT(25) /*!< the mask of ADP sense interrupt flag */
#define ADPCTL_ADPPRFM BIT(24) /*!< the mask of ADP probe interrupt flag */
#define ADPCTL_ADPTF BIT(23) /*!< ADP timeout interrupt flag */
#define ADPCTL_ADPSNF BIT(22) /*!< ADP sense interrupt flag */
#define ADPCTL_ADPPRF BIT(21) /*!< ADP probe interrupt flag */
#define ADPCTL_ADPEN BIT(20) /*!< ADP enable */
#define ADPCTL_ADPRST BIT(19) /*!< ADP reset */
#define ADPCTL_SNEN BIT(18) /*!< ADP sense enable */
#define ADPCTL_PREN BIT(17) /*!< ADP probe enable */
#define ADPCTL_CHGT BITS(6, 16) /*!< the latest time that VBUS ramps from VADPSINK to VADPPRB */
#define ADPCTL_PERPR BITS(4, 5) /*!< period of probe */
#define ADPCTL_RESOPR BITS(2, 3) /*!< the resolution of CHGT value */
#define ADPCTL_DSCHGPR BITS(0, 1) /*!< Time of probe discharge */
/* USBHS PHY control register bits definitions */
#define PHYCTL_HS_CALEN BIT(31) /*!< HS PHY calibration enable */
#define PHYCTL_HS_CALR BITS(25, 30) /*!< HS PHY calibration value */
#define PHYCTL_HS_RCALR BITS(21, 24) /*!< HS PHY R calibration value */
#define PHYCTL_SQUECH BIT(16) /*!< HS PHY squech flag */
#define PHYCTL_HS_BIST_DONE BIT(15) /*!< HS PHY bist finished flag */
#define PHYCTL_HS_BIST_SUCCESS BIT(14) /*!< HS PHY bist success flag */
#define PHYCTL_HS_BIST_FAIL BIT(13) /*!< HS PHY bist fail flag */
#define PHYCTL_HS_BIST_PKT_SEL BITS(11, 12) /*!< HS PHY bist packet select */
#define PHYCTL_HS_BIST_SEED BITS(3, 10) /*!< HS PHY bist seed */
#define PHYCTL_HS_BIST_EN BIT(2) /*!< HS PHY bist enable */
#define PHYCTL_HS_BIST_RESET BIT(1) /*!< HS PHY bist logic reset */
#define PHYCTL_HS_BIST_START BIT(0) /*!< HS PHY bist start */
/* host periodic transmit FIFO length register bits definitions */
#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */
#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */
/* device IN endpoint transmit FIFO length register bits definitions */
#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */
#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */
/* host control register bits definitions */
#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */
/* host frame interval register bits definitions */
#define HFT_FRI BITS(0, 15) /*!< frame interval */
/* host frame information remaining register bits definitions */
#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */
#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */
/* host periodic transmit FIFO/queue status register bits definitions */
#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */
#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */
#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */
#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */
#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */
#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */
#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */
#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */
#define TFQSTAT_TXFS BITS(0, 15)
#define TFQSTAT_CNUM BITS(27, 30)
/* host all channels interrupt register bits definitions */
#define HACHINT_HACHINT BITS(0, 15) /*!< host all channel interrupts */
/* host all channels interrupt enable register bits definitions */
#define HACHINTEN_CINTEN BITS(0, 15) /*!< channel interrupt enable */
/* host port control and status register bits definitions */
#define HPCS_PS BITS(17, 18) /*!< port speed */
#define HPCS_PTEST BITS(13, 16) /*!< port test control */
#define HPCS_PP BIT(12) /*!< port power */
#define HPCS_PLST BITS(10, 11) /*!< port line status */
#define HPCS_PRST BIT(8) /*!< port reset */
#define HPCS_PSP BIT(7) /*!< port suspend */
#define HPCS_PREM BIT(6) /*!< port resume */
#define HPCS_PEDC BIT(3) /*!< port enable/disable change */
#define HPCS_PE BIT(2) /*!< port enable */
#define HPCS_PCD BIT(1) /*!< port connect detected */
#define HPCS_PCST BIT(0) /*!< port connect status */
/* host channel-x control register bits definitions */
#define HCHCTL_CEN BIT(31) /*!< channel enable */
#define HCHCTL_CDIS BIT(30) /*!< channel disable */
#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */
#define HCHCTL_DAR BITS(22, 28) /*!< device address */
#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */
#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */
#define HCHCTL_LSD BIT(17) /*!< low-speed device */
#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */
#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */
#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */
/* host channel-x split transaction register bits definitions */
#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */
#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */
#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */
#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */
#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */
/* host channel-x interrupt flag register bits definitions */
#define HCHINTF_DTER BIT(10) /*!< data toggle error */
#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */
#define HCHINTF_BBER BIT(8) /*!< babble error */
#define HCHINTF_USBER BIT(7) /*!< USB bus Error */
#define HCHINTF_NYET BIT(6) /*!< NYET */
#define HCHINTF_ACK BIT(5) /*!< ACK */
#define HCHINTF_NAK BIT(4) /*!< NAK */
#define HCHINTF_STALL BIT(3) /*!< STALL */
#define HCHINTF_DMAER BIT(2) /*!< DMA error */
#define HCHINTF_CH BIT(1) /*!< channel halted */
#define HCHINTF_TF BIT(0) /*!< transfer finished */
/* host channel-x interrupt enable register bits definitions */
#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */
#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */
#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */
#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */
#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */
#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */
#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */
#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */
#define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */
#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */
#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */
/* host channel-x transfer length register bits definitions */
#define HCHLEN_PING BIT(31) /*!< PING token request */
#define HCHLEN_DPID BITS(29, 30) /*!< data PID */
#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */
#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */
/* host channel-x DMA address register bits definitions */
#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
#define PORT_SPEED(x) (((uint32_t)(x) << 17U) & HPCS_PS) /*!< Port speed */
#define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */
#define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */
#define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */
#define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22U) & HCHCTL_DAR) /*!< device address */
#define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18U) & HCHCTL_EPTYPE) /*!< endpoint type */
#define PIPE_CTL_EPNUM(x) (((uint32_t)(x) << 11U) & HCHCTL_EPNUM) /*!< endpoint number */
#define PIPE_CTL_EPDIR(x) (((uint32_t)(x) << 15U) & HCHCTL_EPDIR) /*!< endpoint direction */
#define PIPE_CTL_EPMPL(x) (((uint32_t)(x) << 0U) & HCHCTL_MPL) /*!< maximum packet length */
#define PIPE_CTL_LSD(x) (((uint32_t)(x) << 17U) & HCHCTL_LSD) /*!< low-Speed device */
#define PIPE_XFER_PCNT(x) (((uint32_t)(x) << 19U) & HCHLEN_PCNT) /*!< packet count */
#define PIPE_XFER_DPID(x) (((uint32_t)(x) << 29U) & HCHLEN_DPID) /*!< data PID */
#define PIPE_DPID_DATA0 PIPE_XFER_DPID(0) /*!< DATA0 */
#define PIPE_DPID_DATA1 PIPE_XFER_DPID(2) /*!< DATA1 */
#define PIPE_DPID_DATA2 PIPE_XFER_DPID(1) /*!< DATA2 */
#define PIPE_DPID_SETUP PIPE_XFER_DPID(3) /*!< MDATA (non-control)/SETUP (control) */
extern const uint32_t PIPE_DPID[2];
/* device configuration registers bits definitions */
#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */
#define DCFG_DAR BITS(4, 10) /*!< device address */
#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */
#define DCFG_DS BITS(0, 1) /*!< device speed */
/* device control registers bits definitions */
#define DCTL_L1RJCT BIT(18) /*!< deep sleep reject */
#define DCTL_POIF BIT(11) /*!< power-on initialization finished */
#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */
#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */
#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */
#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */
#define DCTL_DTEST BITS(4, 6) /*!< device test control */
#define DCTL_GONS BIT(3) /*!< global OUT NAK status */
#define DCTL_GINS BIT(2) /*!< global IN NAK status */
#define DCTL_SD BIT(1) /*!< soft disconnect */
#define DCTL_RWKUP BIT(0) /*!< remote wakeup */
/* device status registers bits definitions */
#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */
#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */
#define DSTAT_SPST BIT(0) /*!< suspend status */
/* device IN endpoint common interrupt enable registers bits definitions */
#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */
#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */
#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */
#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */
#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */
#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */
#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */
/* device OUT endpoint common interrupt enable registers bits definitions */
#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */
#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */
#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */
#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */
#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */
#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */
/* device all endpoints interrupt registers bits definitions */
#define DAEPINT_OEPITB BITS(16, 23) /*!< device all OUT endpoint interrupt bits */
#define DAEPINT_IEPITB BITS(0, 7) /*!< device all IN endpoint interrupt bits */
/* device all endpoints interrupt enable registers bits definitions */
#define DAEPINTEN_OEPIE BITS(16, 23) /*!< OUT endpoint interrupt enable */
#define DAEPINTEN_IEPIE BITS(0, 7) /*!< IN endpoint interrupt enable */
/* device VBUS discharge time registers bits definitions */
#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */
/* device VBUS pulsing time registers bits definitions */
#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */
/* device IN endpoint FIFO empty interrupt enable register bits definitions */
#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */
/* device endpoint 0 control register bits definitions */
#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */
#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */
#define DEP0CTL_SNAK BIT(27) /*!< set NAK */
#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */
#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */
#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */
#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */
#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */
#define DEP0CTL_NAKS BIT(17) /*!< NAK status */
#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */
#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */
/* device endpoint x control register bits definitions */
#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */
#define DEPCTL_EPD BIT(30) /*!< endpoint disable */
#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */
#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */
#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */
#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */
#define DEPCTL_SNAK BIT(27) /*!< set NAK */
#define DEPCTL_CNAK BIT(26) /*!< clear NAK */
#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */
#define DEPCTL_STALL BIT(21) /*!< STALL handshake */
#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */
#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */
#define DEPCTL_NAKS BIT(17) /*!< NAK status */
#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */
#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */
#define DEPCTL_EPACT BIT(15) /*!< endpoint active */
#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */
/* device IN endpoint-x interrupt flag register bits definitions */
#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */
#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */
#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */
#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */
#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */
#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */
#define DIEPINTF_TF BIT(0) /*!< transfer finished */
/* device OUT endpoint-x interrupt flag register bits definitions */
#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */
#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */
#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */
#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */
#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */
#define DOEPINTF_TF BIT(0) /*!< transfer finished */
/* device IN endpoint 0 transfer length register bits definitions */
#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */
#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */
/* device OUT endpoint 0 transfer length register bits definitions */
#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */
#define DOEP0LEN_PCNT BIT(19) /*!< packet count */
#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */
/* device OUT endpoint-x transfer length register bits definitions */
#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */
#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */
#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */
#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */
#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */
/* device IN endpoint-x DMA address register bits definitions */
#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
/* device OUT endpoint-x DMA address register bits definitions */
#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
/* device IN endpoint-x transmit FIFO status register bits definitions */
#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */
/* USB power and clock registers bits definition */
#define PWRCLKCTL_DSLEEP BIT(7) /*!< PHY is in deep sleep status */
#define PWRCLKCTL_SSLEEP BIT(6) /*!< PHY is in shallow sleep status */
#define PWRCLKCTL_SCGEN BIT(5) /*!< When this bit is set, the internal clock gating is enabled */
#define PWRCLKCTL_SUSP BIT(4) /*!< PHY is in suspend status */
#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */
#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */
#define RSTAT_GOUT_NAK 1U /*!< global OUT NAK (triggers an interrupt) */
#define RSTAT_DATA_UPDT 2U /*!< OUT data packet received */
#define RSTAT_XFER_COMP 3U /*!< OUT transfer completed (triggers an interrupt) */
#define RSTAT_SETUP_COMP 4U /*!< SETUP transaction completed (triggers an interrupt) */
#define RSTAT_SETUP_UPDT 6U /*!< SETUP data packet received */
#define DSTAT_EM_HS_PHY_30MHZ_60MHZ 0U /*!< USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */
#define DSTAT_EM_FS_PHY_30MHZ_60MHZ 1U /*!< USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */
#define DSTAT_EM_LS_PHY_6MHZ 2U /*!< USB enumerate speed use low-speed PHY clock in 6MHz */
#define DSTAT_EM_FS_PHY_48MHZ 3U /*!< USB enumerate speed use full-speed PHY clock in 48MHz */
#define DPID_DATA0 0U /*!< device endpoint data PID is DATA0 */
#define DPID_DATA1 2U /*!< device endpoint data PID is DATA1 */
#define DPID_DATA2 1U /*!< device endpoint data PID is DATA2 */
#define DPID_MDATA 3U /*!< device endpoint data PID is MDATA */
#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA */
#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/
#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA */
#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA */
#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA */
#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA */
#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */
#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */
#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */
#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */
#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */
#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */
#define USB_SPEED_INP_HIGH DCFG_DEVSPEED(0U) /*!< device internal PHY high speed */
#define USB_SPEED_INP_FULL DCFG_DEVSPEED(1U) /*!< device internal PHY full speed */
#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */
#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */
#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */
#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */
#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */
#define DOEP0_TLEN(regval) (DOEP0LEN_TLEN & ((regval) << 0U)) /*!< Transfer length */
#define DOEP0_PCNT(regval) (DOEP0LEN_PCNT & ((regval) << 19U)) /*!< Packet count */
#define DOEP0_STPCNT(regval) (DOEP0LEN_STPCNT & ((regval) << 29U)) /*!< SETUP packet count */
#define GRXSTS_PKTSTS_IN 2U
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
#define DEVICE_MODE 0U /*!< device mode */
#define HOST_MODE 1U /*!< host mode */
#define OTG_MODE 2U /*!< OTG mode */
#define HCTL_30_60MHZ 0U /*!< USB clock 30-60MHZ */
#define HCTL_48MHZ 1U /*!< USB clock 48MHZ */
#define HCTL_6MHZ 2U /*!< USB clock 6MHZ */
#define USBHS_MAX_PACKET_SIZE 512U /*!< USBHS max packet size */
#define USBHS_MAX_CHANNEL_COUNT 16U /*!< USBHS host channel count */
#define USBHS_MAX_EP_COUNT 8U /*!< USBHS device endpoint count */
#define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */
#define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */
#define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */
typedef enum
{
USB_EMBEDDED_PHY_FS = 0U, /*!< USB embedded FS PHY */
USB_EMBEDDED_PHY_HS, /*!< USB embedded HS PHY */
USB_ULPI_PHY_EXTERNAL /*!< USB external ULPI PHY */
} usb_phy_enum;
enum usb_reg_offset
{
USB_REG_OFFSET_CORE = 0x0000U, /*!< global OTG control and status register */
USB_REG_OFFSET_DEV = 0x0800U, /*!< device mode control and status registers */
USB_REG_OFFSET_EP = 0x0020U, /*!< offset of each endpoint */
USB_REG_OFFSET_EP_IN = 0x0900U, /*!< device IN endpoint 0 control register */
USB_REG_OFFSET_EP_OUT = 0x0B00U, /*!< device OUT endpoint 0 control register */
USB_REG_OFFSET_HOST = 0x0400U, /*!< host control register */
USB_REG_OFFSET_CH = 0x0020U, /*!< offset of each channel */
USB_REG_OFFSET_PORT = 0x0440U, /*!< host port control and status register */
USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< host channel-x control registers */
USB_REG_OFFSET_PWRCLKCTL = 0x0E00U /*!< power and clock register */
};
enum USB_SPEED
{
USB_SPEED_UNKNOWN = 0, /*!< USB speed unknown */
USB_SPEED_LOW, /*!< USB speed low */
USB_SPEED_FULL, /*!< USB speed full */
USB_SPEED_HIGH /*!< USB speed high */
};
#define EP0_OUT ((uint8_t)0x00U) /*!< endpoint out 0 */
#define EP0_IN ((uint8_t)0x80U) /*!< endpoint in 0 */
#define EP1_OUT ((uint8_t)0x01U) /*!< endpoint out 1 */
#define EP1_IN ((uint8_t)0x81U) /*!< endpoint in 1 */
#define EP2_OUT ((uint8_t)0x02U) /*!< endpoint out 2 */
#define EP2_IN ((uint8_t)0x82U) /*!< endpoint in 2 */
#define EP3_OUT ((uint8_t)0x03U) /*!< endpoint out 3 */
#define EP3_IN ((uint8_t)0x83U) /*!< endpoint in 3 */
#define EP4_OUT ((uint8_t)0x04U) /*!< endpoint out 4 */
#define EP4_IN ((uint8_t)0x84U) /*!< endpoint in 4 */
#define EP5_OUT ((uint8_t)0x05U) /*!< endpoint out 5 */
#define EP5_IN ((uint8_t)0x85U) /*!< endpoint in 5 */
#define EP6_OUT ((uint8_t)0x06U) /*!< endpoint out 6 */
#define EP6_IN ((uint8_t)0x86U) /*!< endpoint in 6 */
#define EP7_OUT ((uint8_t)0x06U) /*!< endpoint out 7 */
#define EP7_IN ((uint8_t)0x86U) /*!< endpoint in 7 */
#endif /* DRV_USB_REGS_H */
828ECO/drivers/include/usb/drv_usbd_int.h
+28
View File
@@ -0,0 +1,28 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USBD_INT_H
#define DRV_USBD_INT_H
#include "drv_usb_core.h"
#include "drv_usb_dev.h"
/* function declarations */
#ifdef USB_DEDICATED_EP1_ENABLED
/* USB dedicated OUT endpoint 1 interrupt service routine handler */
uint32_t usbd_int_dedicated_ep1out(usb_core_driver *udev);
/* USB dedicated IN endpoint 1 interrupt service routine handler */
uint32_t usbd_int_dedicated_ep1in(usb_core_driver *udev);
#endif /* USB_DEDICATED_EP1_ENABLED */
/* USB device-mode interrupts global service routine handler */
void usbd_isr(usb_core_driver *udev);
#endif /* DRV_USBD_INT_H */
828ECO/drivers/include/usb/drv_usbh_int.h
+19
View File
@@ -0,0 +1,19 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USBH_INT_H
#define DRV_USBH_INT_H
#include "drv_usb_host.h"
/* handle global host interrupt */
uint32_t usbh_isr(usb_core_driver *udev);
#endif /* DRV_USBH_INT_H */
828ECO/drivers/include/usb/drv_usbh_pipe.h
+48
View File
@@ -0,0 +1,48 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef __DRV_USBH_PIPE_H
#define __DRV_USBH_PIPE_H
#include "drv_usb_host.h"
#define HC_MAX 8U
#define HC_OK 0x0000U
#define HC_USED 0x8000U
#define HC_ERROR 0xFFFFU
#define HC_USED_MASK 0x7FFFU
/* allocate a new pipe */
uint8_t usbh_pipe_allocate(usb_core_driver *pudev, uint8_t ep_addr);
/* delete all USB host pipe */
uint8_t usbh_pipe_delete(usb_core_driver *pudev);
/* free a pipe */
uint8_t usbh_pipe_free(usb_core_driver *pudev, uint8_t pp_num);
/* create a pipe */
uint8_t usbh_pipe_create(usb_core_driver *pudev,
uint8_t dev_addr,
uint8_t dev_speed,
uint8_t pp_num,
uint8_t ep_num,
uint8_t ep_type,
uint16_t ep_mpl);
/* modify a pipe */
uint8_t usbh_pipe_update(usb_core_driver *pudev,
uint8_t pp_num,
uint8_t dev_addr,
uint32_t dev_speed,
uint16_t ep_mpl);
#endif /* __DRV_USBH_PIPE_H */
828ECO/drivers/include/usb/drv_usbh_transc.h
+41
View File
@@ -0,0 +1,41 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef __DRV_USBH_TRANSC_H
#define __DRV_USBH_TRANSC_H
#include "drv_usb_host.h"
#if defined(BSP_USING_USB) && defined(RT_USING_USB_HOST)
/* send the setup packet to the USB device */
usbh_status usbh_ctlsetup_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num);
/* send a data packet to the USB device */
usbh_status usbh_data_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len);
/* receive a data packet from the USB device */
usbh_status usbh_data_recev(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len);
/* get USB URB state */
static inline usb_urb_state usbh_urbstate_get(usb_core_driver *pudev, uint8_t pp_num)
{
return pudev->host.pipe[pp_num].urb_state;
}
/* get USB transfer data count */
static inline uint32_t usbh_xfercount_get(usb_core_driver *pudev, uint8_t pp_num)
{
return pudev->host.backup_xfercount[pp_num];
}
#endif /* BSP_USING_USB && RT_USING_USB_HOST */
#endif /* __DRV_USBH_TRANSC_H */
828ECO/drivers/include/usb/usb_conf.h
+139
View File
@@ -0,0 +1,139 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef USB_CONF_H
#define USB_CONF_H
#include <board.h>
#if defined(BSP_USING_USB)
#if defined(SOC_SERIES_GD32H75E)
#include "gd32h75e.h"
#elif defined(SOC_SERIES_GD32H7xx)
#include "gd32h7xx.h"
#endif
/* USB Core and PHY interface configuration */
/* USB HS PHY CONFIGURATION */
/* on-chip full-speed USB PHY */
#ifdef USE_USB_FS
#define OC_FS_PHY
#endif
/* on-chip high-speed USB PHY */
#ifdef USE_USB_HS
#define OC_HS_PHY
#endif /* USE_USB_HS */
#if defined(RT_USING_USB_DEVICE)
#define USB_SOF_OUTPUT 0U
/* USB FIFO size config */
#define RX_FIFO_SIZE 512U
#define TX0_FIFO_SIZE 128U
#define TX1_FIFO_SIZE 384U
#define TX2_FIFO_SIZE 0U
#define TX3_FIFO_SIZE 0U
#define TX4_FIFO_SIZE 0U
#define TX5_FIFO_SIZE 0U
#define TX6_FIFO_SIZE 0U
#define TX7_FIFO_SIZE 0U
#elif defined(RT_USING_USB_HOST)
#define USBH_USE_RTOS
#define USB_SOF_OUTPUT 1U
/* USB FIFO size config */
#define USB_RX_FIFO_SIZE 512
#define USB_HTX_NPFIFO_SIZE 256
#define USB_HTX_PFIFO_SIZE 256
#endif
/* General USB Configuration */
#define USB_LOW_POWER 0U
/* if uncomment it, need jump to USB JP */
//#define VBUS_SENSING_ENABLED
//#define USB_INTERNAL_DMA_ENABLED
//#define USB_DEDICATED_EP1_ENABLED
/* End General USB Configuration */
#ifdef USE_ULPI_PHY
#define USB_EXTERNAL_ULPI_PHY_ENABLED
#else
#ifdef OC_FS_PHY
#define USB_EMBEDDED_FS_PHY_ENABLED
#elif defined(OC_HS_PHY)
#define USB_EMBEDDED_HS_PHY_ENABLED
#else
#error "PHY is not selected"
#endif /* OC_FS_PHY */
#endif /* USE_ULPI_PHY */
#if defined(RT_USING_USB_HOST)
#define USE_HOST_MODE
#elif defined(RT_USING_USB_DEVICE)
#define USE_DEVICE_MODE
#else
#warning "Please select the USB mode as USBD or USBH; otherwise, the USE_OTG_MODE will be enabled by default."
#define USE_OTG_MODE
#endif
#ifndef OC_FS_PHY
#ifndef OC_HS_PHY
#error "OC_FS_PHY or OC_HS_PHY should be defined!"
#endif
#endif /* OC_FS_PHY */
#ifndef RT_USING_USB_DEVICE
#ifndef RT_USING_USB_HOST
#error "RT_USING_USB_DEVICE or RT_USING_USB_HOST should be defined!"
#endif
#endif /* USE_DEVICE_MODE */
#ifndef USE_USB_HS
#ifndef USE_USB_FS
#error "USE_USB_HS or USE_USB_FS should be defined!"
#endif
#endif /* USE_USB_HS */
/* all variables and data structures during the transaction process should be 4-bytes aligned */
#if defined(__GNUC__) /* GNU Compiler */
#define __ALIGN_END __attribute__((aligned(4)))
#define __ALIGN_BEGIN
#else
#define __ALIGN_END
#if defined(__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined(__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#elif defined(__TASKING__)/* TASKING Compiler */
#define __ALIGN_BEGIN __align(4)
#endif /* __CC_ARM */
#endif /* __GNUC__ */
/* __packed keyword used to decrease the data type alignment to 1-byte */
#if defined(__GNUC__) /* GNU Compiler */
#ifndef __packed
#define __packed __unaligned
#endif
#elif defined(__TASKING__) /* TASKING Compiler */
#define __packed __unaligned
#endif /* __GNUC__ */
#endif /* BSP_USING_USB */
#endif /* USB_CONF_H */