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sc committed 2026-02-14 19:03:02 +08:00
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828ECO/drivers/include/usb/drv_otghs_dev.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef __DRV_OTGFS_DEV_H__
#define __DRV_OTGFS_DEV_H__
#include <rtthread.h>
#include "drv_usb_dev.h"
void usbd_reset_callback(void);
void usbd_setup_stage_callback(struct urequest *setup_packet);
void usbd_data_in_stage_callback(uint8_t epnum, uint16_t data_count);
void usbd_data_out_stage_callback(uint8_t epnum, uint16_t data_count);
void usbd_set_connection_state(uint8_t state);
int gd_usbd_register(void);
#endif
828ECO/drivers/include/usb/drv_otghs_host.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef __DRV_OTGFS_HOST_H__
#define __DRV_OTGFS_HOST_H__
#include <rtthread.h>
#include "drv_usb_host.h"
#include "drv_usbh_transc.h"
#include "drv_usbh_pipe.h"
#define OTG_FS_PORT 1
#if defined(BSP_USING_USB) && defined(RT_USING_USB_HOST)
void usbh_connect_callback(usb_core_driver *hhcd);
void usbh_disconnect_callback(usb_core_driver *hhcd);
void usbh_hc_notifyurbchange_callback(usb_core_driver *hhcd, uint8_t chnum, usb_urb_state urb_state);
int gd_usbh_register(void);
#endif /* BSP_USING_USB && RT_USING_USB_HOST */
#endif
828ECO/drivers/include/usb/drv_usb_core.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USB_CORE_H
#define DRV_USB_CORE_H
#include "drv_usb_regs.h"
#define USB_FS_EP0_MAX_LEN 64U /*!< maximum packet size of endpoint 0 */
#define HC_MAX_PACKET_COUNT 140U /*!< maximum packet count */
#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /*!< endpoint number */
#define EP_DIR(x) ((uint8_t)((x) >> 7)) /*!< endpoint direction */
typedef struct urequest usb_req;
enum _usb_eptype
{
USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */
USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */
USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */
USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */
USB_EPTYPE_MASK = 3U /*!< endpoint type mask */
};
typedef enum
{
USB_OTG_OK = 0U, /*!< USB OTG status OK */
USB_OTG_FAIL /*!< USB OTG status fail */
} usb_otg_status;
typedef enum
{
USB_OK = 0U, /*!< USB status OK */
USB_FAIL /*!< USB status fail */
} usb_status;
typedef enum
{
USB_USE_FIFO, /*!< USB use FIFO transfer mode */
USB_USE_DMA /*!< USB use DMA transfer mode */
} usb_transfer_mode;
typedef enum
{
LPM_L0 = 0U, /*!< on */
LPM_L1, /*!< LPM L1 sleep */
LPM_L2, /*!< suspend */
LPM_L3, /*!< off */
} usb_lpm_state;
enum usb_ctl_status
{
USB_CTL_IDLE = 0U, /*!< USB control transfer idle state */
USB_CTL_DATA_IN, /*!< USB control transfer data IN state */
USB_CTL_LAST_DATA_IN, /*!< USB control transfer last data IN state */
USB_CTL_DATA_OUT, /*!< USB control transfer data OUT state */
USB_CTL_LAST_DATA_OUT, /*!< USB control transfer last data OUT state */
USB_CTL_STATUS_IN, /*!< USB control transfer status IN state*/
USB_CTL_STATUS_OUT /*!< USB control transfer status OUT state */
};
typedef enum
{
LPM_L0_ACTIVE = 0U, /*!< on */
LPM_L1_ACTIVE, /*!< LPM L1 sleep */
} usb_lpm_type;
typedef struct
{
uint8_t core_enum; /*!< USB core type */
uint8_t core_speed; /*!< USB core speed */
uint8_t num_pipe; /*!< USB host channel numbers */
uint8_t num_ep; /*!< USB device endpoint numbers */
uint8_t transfer_mode; /*!< USB transfer mode */
uint8_t phy_itf; /*!< USB core PHY interface */
uint8_t sof_enable; /*!< USB SOF output */
uint8_t low_power; /*!< USB low power */
uint8_t lpm_enable; /*!< USB link power mode(LPM) */
uint8_t vbus_sensing_enable; /*!< USB VBUS sensing feature */
uint8_t use_dedicated_ep1; /*!< USB dedicated endpoint1 interrupt */
uint8_t use_external_vbus; /*!< enable or disable the use of the external VBUS */
uint32_t base_reg; /*!< base register address */
} usb_core_basic;
#ifdef USE_DEVICE_MODE
/* USB descriptor */
typedef struct _usb_desc
{
uint8_t *dev_desc; /*!< device descriptor */
uint8_t *config_desc; /*!< configuration descriptor */
uint8_t *bos_desc; /*!< BOS descriptor */
#ifdef USE_USB_HS
uint8_t *other_speed_config_desc; /*!< other speed configuration descriptor */
uint8_t *qualifier_desc; /*!< qualifier descriptor */
#endif
void * const *strings; /*!< string descriptor */
} usb_desc;
/* USB power management */
typedef struct _usb_pm
{
uint8_t power_mode; /*!< power mode */
uint8_t power_low; /*!< power low */
uint8_t dev_remote_wakeup; /*!< remote wakeup */
uint8_t remote_wakeup_on; /*!< remote wakeup on */
usb_lpm_state lpm_state; /*!< LPM state */
uint32_t BESL; /*!< BESL value */
} usb_pm;
/* USB control information */
typedef struct _usb_control
{
usb_req req; /*!< USB standard device request */
uint8_t ctl_state; /*!< USB control transfer state */
uint8_t ctl_zlp; /*!< zero length package */
} usb_control;
typedef struct
{
struct
{
uint8_t num : 4U; /*!< the endpoint number.it can be from 0 to 6 */
uint8_t pad : 3U; /*!< padding between number and direction */
uint8_t dir : 1U; /*!< the endpoint direction */
} ep_addr;
uint8_t ep_type; /*!< USB endpoint type */
uint8_t ep_stall; /*!< USB endpoint STALL status */
uint8_t frame_num; /*!< number of frame */
uint16_t max_len; /*!< maximum packet length */
/* transaction level variables */
uint8_t *xfer_buf; /*!< transmit buffer */
uint32_t xfer_len; /*!< transmit buffer length */
uint32_t xfer_count; /*!< transmit buffer count */
uint32_t remain_len; /*!< remain packet length */
uint32_t dma_addr; /*!< DMA address */
} usb_transc;
typedef struct _usb_core_driver usb_dev;
typedef struct _usb_class_core
{
uint8_t alter_set; /*!< alternative set */
uint8_t command; /*!< device class request command */
uint8_t (*init)(usb_dev *udev, uint8_t config_index); /*!< initialize handler */
uint8_t (*deinit)(usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */
uint8_t (*req_proc)(usb_dev *udev, usb_req *req); /*!< device request handler */
uint8_t (*set_intf)(usb_dev *udev, usb_req *req); /*!< device set interface callback */
uint8_t (*ctlx_in)(usb_dev *udev); /*!< device control IN callback */
uint8_t (*ctlx_out)(usb_dev *udev); /*!< device control OUT callback */
uint8_t (*data_in)(usb_dev *udev, uint8_t ep_num); /*!< device data IN handler */
uint8_t (*data_out)(usb_dev *udev, uint8_t ep_num); /*!< device data OUT handler */
uint8_t (*SOF)(usb_dev *udev); /*!< start of frame handler */
uint8_t (*incomplete_isoc_in)(usb_dev *udev); /*!< incomplete synchronization IN transfer handler */
uint8_t (*incomplete_isoc_out)(usb_dev *udev); /*!< incomplete synchronization OUT transfer handler */
} usb_class_core;
typedef struct _usb_perp_dev
{
uint8_t config; /*!< configuration */
uint8_t dev_addr; /*!< device address */
__IO uint8_t cur_status; /*!< current status */
__IO uint8_t backup_status; /*!< backup status */
usb_transc transc_in[USBHS_MAX_TX_FIFOS]; /*!< endpoint IN transaction */
usb_transc transc_out[USBHS_MAX_TX_FIFOS]; /*!< endpoint OUT transaction */
usb_pm pm; /*!< power management */
usb_control control; /*!< USB control information */
usb_desc *desc; /*!< USB descriptors pointer */
usb_class_core *class_core; /*!< class driver */
void *class_data[4]; /*!< class data pointer */
void *user_data; /*!< user data pointer */
void *pdata; /*!< reserved data pointer */
} usb_perp_dev;
#endif /* USE_DEVICE_MODE */
#ifdef USE_HOST_MODE
typedef enum _usb_pipe_status
{
PIPE_IDLE = 0U, /*!< host pipe IDLE status */
PIPE_XF, /*!< host pipe transfer completed status */
PIPE_HALTED, /*!< host pipe halted status */
PIPE_NAK, /*!< host pipe NAK status */
PIPE_NYET, /*!< host pipe NYET status */
PIPE_STALL, /*!< host pipe STALL status */
PIPE_TRACERR, /*!< host pipe transaction error status */
PIPE_BBERR, /*!< host pipe babble error status */
PIPE_REQOVR, /*!< host pipe frame overrun status */
PIPE_DTGERR, /*!< host pipe data toggle error status */
} usb_pipe_status;
typedef enum _usb_pipe_mode
{
PIPE_PERIOD = 0U, /*!< USB host pipe PERIOD mode */
PIPE_NON_PERIOD = 1U /*!< USB host pipe NOT PERIOD mode */
} usb_pipe_mode;
typedef enum _usb_urb_state
{
URB_IDLE = 0U, /*!< USB URB IDLE state */
URB_DONE, /*!< USB URB DONE state */
URB_NOTREADY, /*!< USB URB NOT READY state */
URB_ERROR, /*!< USB URB ERROR state */
URB_STALL, /*!< USB URB STALL state */
URB_PING /*!< USB URB PING state */
} usb_urb_state;
typedef struct _usb_pipe
{
uint8_t in_used; /*!< pipe used */
uint8_t dev_addr; /*!< USB device address */
uint32_t dev_speed; /*!< USB device speed */
struct
{
uint8_t num; /*!< endpoint numbers */
uint8_t dir; /*!< endpoint direction */
uint8_t type; /*!< endpoint transfer type */
uint16_t mps; /*!< endpoint max packet size */
} ep;
__IO uint8_t supp_ping; /*!< host pipe support PING */
__IO uint8_t do_ping; /*!< host pipe do PING */
__IO uint32_t DPID; /*!< data PID */
uint8_t *xfer_buf; /*!< USB transfer buffer */
uint32_t xfer_len; /*!< USB transfer length */
uint32_t xfer_count; /*!< USB transfer count */
uint8_t data_toggle_in; /*!< toggle DATA IN */
uint8_t data_toggle_out; /*!< toggle DATA OUT */
__IO uint32_t err_count; /*!< error count */
__IO usb_pipe_status pp_status; /*!< USB pipe status */
__IO usb_urb_state urb_state; /*!< USB URB state */
} usb_pipe;
typedef struct _usb_host_drv
{
__IO uint32_t connect_status; /*!< connect status */
__IO uint32_t port_enabled; /*!< USB port enable */
__IO uint32_t backup_xfercount[USBHS_MAX_TX_FIFOS]; /*!< USB backup transfer data count */
usb_pipe pipe[USBHS_MAX_TX_FIFOS]; /*!< USB host pipe handles */
void *data; /*!< user data pointer */
} usb_host_drv;
#endif /* USE_HOST_MODE */
typedef struct _usb_core_driver
{
usb_core_basic bp; /*!< USB basic parameters */
usb_core_regs regs; /*!< USB registers */
#ifdef USE_DEVICE_MODE
usb_perp_dev dev; /*!< USB peripheral device */
#endif /* USE_DEVICE_MODE */
#ifdef USE_HOST_MODE
usb_host_drv host; /*!< USB peripheral host */
#endif /* USE_HOST_MODE */
} usb_core_driver;
typedef enum
{
BCD_NONE = 0,
BCD_SDP,
BCD_DCP,
BCD_CDP,
BCD_PS2,
BCD_ERROR
} bcd_type;
/* static inline function definitions */
/*!
\brief get the global interrupts
\param[in] usb_regs: pointer to USB core registers
\param[out] none
\retval interrupt status
*/
__STATIC_INLINE uint32_t usb_coreintr_get(usb_core_regs *usb_regs)
{
uint32_t reg_data = usb_regs->gr->GINTEN;
reg_data &= usb_regs->gr->GINTF;
return reg_data;
}
/*!
\brief set USB RX FIFO size
\param[in] usb_regs: pointer to USB core registers
\param[in] size: assigned FIFO size
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_set_rxfifo(usb_core_regs *usb_regs, uint16_t size)
{
usb_regs->gr->GRFLEN = size;
}
/*!
\brief enable the global interrupts
\param[in] usb_regs: pointer to USB core registers
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_globalint_enable(usb_core_regs *usb_regs)
{
/* enable USB global interrupt */
usb_regs->gr->GAHBCS |= GAHBCS_GINTEN;
}
/*!
\brief disable the global interrupts
\param[in] usb_regs: pointer to USB core registers
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_globalint_disable(usb_core_regs *usb_regs)
{
/* disable USB global interrupt */
usb_regs->gr->GAHBCS &= ~GAHBCS_GINTEN;
}
/* function declarations */
/* configures USB parameters */
void usb_para_init(usb_core_driver *core, uint32_t usb_periph, uint32_t usb_speed);
/* configure core capabilities */
usb_status usb_basic_init(usb_core_basic *usb_basic, usb_core_regs *usb_regs);
/*initializes the USB controller registers and prepares the core device mode or host mode operation*/
usb_status usb_core_init(usb_core_basic usb_basic, usb_core_regs *usb_regs);
/* write a packet into the TX FIFO associated with the endpoint */
usb_status usb_txfifo_write(usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count);
/* read a packet from the RX FIFO associated with the endpoint */
void *usb_rxfifo_read(usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count);
/* flush a TX FIFO or all TX FIFOs */
usb_status usb_txfifo_flush(usb_core_regs *usb_regs, uint8_t fifo_num);
/* flush the entire RX FIFO */
usb_status usb_rxfifo_flush(usb_core_regs *usb_regs);
/* set endpoint or channel TX FIFO size */
void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size);
/* set USB current mode */
void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode);
void usb_clock_active(usb_core_driver *udev);
#endif /* DRV_USB_CORE_H */
828ECO/drivers/include/usb/drv_usb_dev.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USB_DEV_H
#define DRV_USB_DEV_H
#include "drv_usb_core.h"
#if defined(BSP_USING_USB) && defined(RT_USING_USB_DEVICE)
#define EP_IN(x) ((uint8_t)(0x80U | (x))) /*!< device IN endpoint */
#define EP_OUT(x) ((uint8_t)(x)) /*!< device OUT endpoint */
#define EP_MAX_PACKET_SIZE_MASK 0x07FFU /*!< endpoint maximum packet size mask */
#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b))
/* static inline function definitions */
/*!
\brief configure the USB device to be disconnected
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_dev_disconnect(usb_core_driver *udev)
{
udev->regs.dr->DCTL |= DCTL_SD;
}
/*!
\brief configure the USB device to be connected
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_dev_connect(usb_core_driver *udev)
{
udev->regs.dr->DCTL &= ~DCTL_SD;
}
/*!
\brief set the USB device address
\param[in] udev: pointer to USB device
\param[in] dev_addr: device address for setting
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_devaddr_set(usb_core_driver *udev, uint8_t dev_addr)
{
udev->regs.dr->DCFG &= ~DCFG_DAR;
udev->regs.dr->DCFG |= (uint32_t)dev_addr << 4;
}
/*!
\brief read device all OUT endpoint interrupt register
\param[in] udev: pointer to USB device
\param[out] none
\retval interrupt status
*/
__STATIC_INLINE uint32_t usb_oepintnum_read(usb_core_driver *udev)
{
uint32_t value = udev->regs.dr->DAEPINT;
value &= udev->regs.dr->DAEPINTEN;
return (value & DAEPINT_OEPITB) >> 16;
}
/*!
\brief read device OUT endpoint interrupt flag register
\param[in] udev: pointer to USB device
\param[in] ep_num: endpoint number
\param[out] none
\retval interrupt status
*/
__STATIC_INLINE uint32_t usb_oepintr_read(usb_core_driver *udev, uint8_t ep_num)
{
uint32_t value = udev->regs.er_out[ep_num]->DOEPINTF;
value &= udev->regs.dr->DOEPINTEN;
return value;
}
/*!
\brief read device all IN endpoint interrupt register
\param[in] udev: pointer to USB device
\param[out] none
\retval interrupt status
*/
__STATIC_INLINE uint32_t usb_iepintnum_read(usb_core_driver *udev)
{
uint32_t value = udev->regs.dr->DAEPINT;
value &= udev->regs.dr->DAEPINTEN;
return value & DAEPINT_IEPITB;
}
/*!
\brief set remote wakeup signaling
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_rwkup_set(usb_core_driver *udev)
{
if (udev->dev.pm.dev_remote_wakeup)
{
/* enable remote wakeup signaling */
udev->regs.dr->DCTL |= DCTL_RWKUP;
}
}
/*!
\brief reset remote wakeup signaling
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_rwkup_reset(usb_core_driver *udev)
{
if (udev->dev.pm.dev_remote_wakeup)
{
/* disable remote wakeup signaling */
udev->regs.dr->DCTL &= ~DCTL_RWKUP;
}
}
/*!
\brief enable USB BCD function
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_bcd_enable(usb_core_driver *udev)
{
udev->regs.gr->GCCFG |= GCCFG_BCDEN;
}
/*!
\brief disable USB BCD function
\param[in] udev: pointer to USB device
\param[out] none
\retval none
*/
__STATIC_INLINE void usb_bcd_disable(usb_core_driver *udev)
{
udev->regs.gr->GCCFG &= ~GCCFG_BCDEN;
}
/* function declarations */
/* initialize USB core registers for device mode */
usb_status usb_devcore_init(usb_core_driver *udev);
/* enable the USB device mode interrupts */
usb_status usb_devint_enable(usb_core_driver *udev);
/* active the USB endpoint 0 transaction */
usb_status usb_transc0_active(usb_core_driver *udev, usb_transc *transc);
/* active the USB transaction */
usb_status usb_ep_active(usb_core_driver *udev, uint8_t ep_addr, uint8_t ep_mps, uint8_t ep_attr);
/* deactivate the USB transaction */
usb_status usb_ep_deactivate(usb_core_driver *udev, uint8_t ep_addr);
/* configure USB transaction to start IN transfer */
usb_status usb_ep_inxfer(usb_core_driver *udev, uint8_t ep_addr, uint8_t *buf, uint16_t count);
/* configure USB transaction to start OUT transfer */
usb_status usb_ep_outxfer(usb_core_driver *udev, uint8_t ep_addr, uint8_t *buf, uint16_t count);
/* set the USB transaction STALL status */
usb_status usb_ep_stall(usb_core_driver *udev, uint8_t ep_addr);
/* clear the USB transaction STALL status */
usb_status usb_ep_clrstall(usb_core_driver *udev, uint8_t ep_addr);
/* read device IN endpoint interrupt flag register */
uint32_t usb_iepintr_read(usb_core_driver *udev, uint8_t ep_num);
/* configures OUT endpoint 0 to receive SETUP packets */
void usb_ctlep_startout(usb_core_driver *udev);
/* active remote wakeup signaling */
void usb_rwkup_active(usb_core_driver *udev);
/* active USB core clock */
void usb_clock_active(usb_core_driver *udev);
/* USB device suspend */
void usb_dev_suspend(usb_core_driver *udev);
/* stop the device and clean up FIFOs */
void usb_dev_stop(usb_core_driver *udev);
/* USB battery charging detect operation */
bcd_type usbd_bcd_detect(usb_core_driver *udev);
#endif /* BSP_USING_USB && RT_USING_USB_DEVICE */
#endif /* DRV_USB_DEV_H */
828ECO/drivers/include/usb/drv_usb_host.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USB_HOST_H
#define DRV_USB_HOST_H
#include "drv_usb_core.h"
#if defined(BSP_USING_USB) && defined(RT_USING_USB_HOST)
typedef enum
{
USBH_OK = 0U,
USBH_BUSY,
USBH_FAIL,
USBH_NOT_SUPPORTED,
USBH_UNRECOVERED_ERROR,
USBH_SPEED_UNKNOWN_ERROR,
USBH_APPLY_DEINIT
} usbh_status;
/*!
\brief get USB even frame
\param[in] udev: pointer to USB device
\param[out] none
\retval USB even frame state
*/
__STATIC_INLINE uint8_t usb_frame_even(usb_core_driver *udev)
{
return (uint8_t) !(udev->regs.hr->HFINFR & 0x01U);
}
/*!
\brief read USB port
\param[in] udev: pointer to USB device
\param[out] none
\retval port status
*/
__STATIC_INLINE uint32_t usb_port_read(usb_core_driver *udev)
{
return *udev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC);
}
/*!
\brief get USB current speed
\param[in] udev: pointer to USB device
\param[out] none
\retval USB current speed
*/
__STATIC_INLINE uint32_t usb_curspeed_get(usb_core_driver *udev)
{
return *udev->regs.HPCS & HPCS_PS;
}
/*!
\brief get USB current frame
\param[in] udev: pointer to USB device
\param[out] none
\retval USB current frame
*/
__STATIC_INLINE uint32_t usb_curframe_get(usb_core_driver *udev)
{
return (udev->regs.hr->HFINFR & 0xFFFFU);
}
/* function declarations */
/* initializes USB core for host mode */
usb_status usb_host_init(usb_core_driver *udev);
/* control the VBUS to power */
void usb_portvbus_switch(usb_core_driver *udev, uint8_t state);
/* reset host port */
uint32_t usb_port_reset(usb_core_driver *udev);
/* initialize host pipe */
usb_status usb_pipe_init(usb_core_driver *udev, uint8_t pipe_num);
/* prepare host pipe for transferring packets */
usb_status usb_pipe_xfer(usb_core_driver *udev, uint8_t pipe_num);
/* halt host pipe */
usb_status usb_pipe_halt(usb_core_driver *udev, uint8_t pipe_num);
/* configure host pipe to do ping operation */
usb_status usb_pipe_ping(usb_core_driver *udev, uint8_t pipe_num);
/* stop the USB host and clean up FIFO */
void usb_host_stop(usb_core_driver *udev);
#endif /* BSP_USING_USB && RT_USING_USB_HOST */
#endif /* DRV_USB_HOST_H */
828ECO/drivers/include/usb/drv_usb_hw.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USB_HW_H
#define DRV_USB_HW_H
#include "drv_usb_core.h"
/* function declarations */
/* configure USB clock */
void usb_rcu_config(void);
/* configure USB data line GPIO */
void usb_gpio_config(void);
/* configure USB interrupt */
void usb_intr_config(void);
/* initializes delay unit using Timer2 */
void usb_timer_init(void);
/* delay in microseconds */
void usb_udelay(const uint32_t usec);
/* delay in milliseconds */
void usb_mdelay(const uint32_t msec);
/* configure USB clock */
void pllusb_rcu_config(uint32_t usb_periph);
#ifdef USE_HOST_MODE
/* configure systick */
void systick_config(void);
/* configure USB VBus */
void usb_vbus_config(void);
/* drive USB VBus */
void usb_vbus_drive(uint8_t State);
#endif /* USE_HOST_MODE */
#endif /* DRV_USB_HW_H */
828ECO/drivers/include/usb/drv_usb_regs.h
+728
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@@ -0,0 +1,728 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USB_REGS_H
#define DRV_USB_REGS_H
#include "usb_conf.h"
#define USBHS0 USBHS_BASE
#define USBHS1 (USBHS_BASE + 0x00040000U)
#define USBHS0_REG_BASE USBHS0 /*!< base address of USBHS0 registers */
#define USBHS1_REG_BASE USBHS1 /*!< base address of USBHS1 registers */
/* register definition */
#define USBHS_MAX_TX_FIFOS 16U /*!< FIFO number */
typedef struct
{
__IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */
__IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */
__IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */
__IO uint32_t GUSBCS; /*!< USB global USB control and status register 00Ch */
__IO uint32_t GRSTCTL; /*!< USB global reset control register 010h */
__IO uint32_t GINTF; /*!< USB global interrupt flag register 014h */
__IO uint32_t GINTEN; /*!< USB global interrupt enable register 018h */
__IO uint32_t GRSTATR; /*!< USB receive status debug read register 01Ch */
__IO uint32_t GRSTATP; /*!< USB receive status and pop register 020h */
__IO uint32_t GRFLEN; /*!< USB global receive FIFO length register 024h */
__IO uint32_t DIEP0TFLEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length register 028h */
__IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status register 02Ch */
uint32_t Reserved30[2]; /*!< Reserved 030h */
__IO uint32_t GCCFG; /*!< USB global core configuration register 038h */
__IO uint32_t CID; /*!< USB core ID register 03Ch */
uint32_t Reserved40[5]; /*!< Reserved 040h-053h */
__IO uint32_t GLPMCFG; /*!< LPM configuration register 54h */
__IO uint32_t PWRD; /*!< power down register 58h */
uint32_t Reserved5C; /*!< Reserved 5Ch */
__IO uint32_t ADPCTL; /*!< ADP control and status register 60h */
uint32_t Reserved64[3]; /*!< Reserved 64h-6Fh */
__IO uint32_t PHYCTL; /*!< USBHS PHY control register 70h */
uint32_t Reserved74[35]; /*!< Reserved 74h-FFh */
__IO uint32_t HPTFLEN; /*!< USB host periodic transmit FIFO length register 100h */
__IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */
} usb_gr;
typedef struct
{
__IO uint32_t HCTL; /*!< USB host control register 400h */
__IO uint32_t HFT; /*!< USB host frame interval register 404h */
__IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */
uint32_t Reserved40C; /*!< Reserved 40Ch */
__IO uint32_t HPTFQSTAT; /*!< USB host periodic transmit FIFO/queue status register 410h */
__IO uint32_t HACHINT; /*!< USB host all channels interrupt register 414h */
__IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */
} usb_hr;
typedef struct
{
__IO uint32_t HCHCTL; /*!< USB host channel control register 500h */
__IO uint32_t HCHSTCTL; /*!< Reserved 504h */
__IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */
__IO uint32_t HCHINTEN; /*!< USB host channel interrupt enable register 50Ch */
__IO uint32_t HCHLEN; /*!< USB host channel transfer length register 510h */
__IO uint32_t HCHDMAADDR; /*!< USB host channel-x DMA address register 514h*/
uint32_t Reserved[2];
} usb_pr;
typedef struct
{
__IO uint32_t DCFG; /*!< USB device configuration register 800h */
__IO uint32_t DCTL; /*!< USB device control register 804h */
__IO uint32_t DSTAT; /*!< USB device status register 808h */
uint32_t Reserved0C; /*!< Reserved 80Ch */
__IO uint32_t DIEPINTEN; /*!< USB device IN endpoint common interrupt enable register 810h */
__IO uint32_t DOEPINTEN; /*!< USB device OUT endpoint common interrupt enable register 814h */
__IO uint32_t DAEPINT; /*!< USB device all endpoints interrupt register 818h */
__IO uint32_t DAEPINTEN; /*!< USB device all endpoints interrupt enable register 81Ch */
uint32_t Reserved20; /*!< Reserved 820h */
uint32_t Reserved24; /*!< Reserved 824h */
__IO uint32_t DVBUSDT; /*!< USB device VBUS discharge time register 828h */
__IO uint32_t DVBUSPT; /*!< USB device VBUS pulsing time register 82Ch */
uint32_t Reserved30; /*!< Reserved 830h */
__IO uint32_t DIEPFEINTEN; /*!< USB Device IN endpoint FIFO empty interrupt enable register 834h */
__IO uint32_t DEP1INT; /*!< USB device endpoint 1 interrupt register 838h */
__IO uint32_t DEP1INTEN; /*!< USB device endpoint 1 interrupt enable register 83Ch */
uint32_t Reserved40; /*!< Reserved 840h */
__IO uint32_t DIEP1INTEN; /*!< USB device IN endpoint-1 interrupt enable register 844h */
uint32_t Reserved48[15]; /*!< Reserved 848-880h */
__IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */
} usb_dr;
typedef struct
{
__IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */
__IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved 900h + (EpNum * 20h) + 0Ch */
__IO uint32_t DIEPLEN; /*!< USB device IN endpoint transfer length register 900h + (EpNum * 20h) + 10h */
__IO uint32_t DIEPDMAADDR; /*!< Device IN endpoint-x DMA address register 900h + (EpNum * 20h) + 14h */
__IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */
} usb_erin;
typedef struct
{
__IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */
__IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved B00h + (EpNum * 20h) + 0Ch */
__IO uint32_t DOEPLEN; /*!< USB device IN endpoint transfer length register B00h + (EpNum * 20h) + 10h */
__IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */
} usb_erout;
typedef struct _usb_regs
{
usb_gr *gr; /*!< USBHS global registers */
usb_dr *dr; /*!< device control and status registers */
usb_hr *hr; /*!< host control and status registers */
usb_erin *er_in[8]; /*!< USB device IN endpoint register */
usb_erout *er_out[8]; /*!< USB device OUT endpoint register */
usb_pr *pr[16]; /*!< USB Host channel-x control register */
__IO uint32_t *HPCS; /*!< USB host port control and status register */
__IO uint32_t *DFIFO[USBHS_MAX_TX_FIFOS];
__IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */
} usb_core_regs;
/* global OTG control and status register bits definitions */
#define GOTGCS_OV BIT(20) /*!< select OTG version */
#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */
#define GOTGCS_ASV BIT(18) /*!< A-session valid */
#define GOTGCS_DI BIT(17) /*!< debounce interval */
#define GOTGCS_IDPS BIT(16) /*!< id pin status */
#define GOTGCS_EHE BIT(12) /*!< embedded host enable */
#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */
#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */
#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */
#define GOTGCS_HNPS BIT(8) /*!< HNP successes */
#define GOTGCS_BVOV BIT(7) /*!< override value of B-peripheral session valid */
#define GOTGCS_BVOE BIT(6) /*!< override enable of B-peripheral session valid */
#define GOTGCS_AVOV BIT(5) /*!< override value of A-peripheral session valid */
#define GOTGCS_AVOE BIT(4) /*!< override enable of A-peripheral session valid */
#define GOTGCS_VOV BIT(3) /*!< override value of VBUS valid */
#define GOTGCS_VOE BIT(2) /*!< override enable of VBUS valid */
#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */
#define GOTGCS_SRPS BIT(0) /*!< SRP successes */
/* global OTG interrupt flag register bits definitions */
#define GOTGINTF_IDCHG BIT(20) /*!< ID input change */
#define GOTGINTF_DF BIT(19) /*!< debounce finish */
#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */
#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */
#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */
#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */
#define GOTGINTF_SESEND BIT(2) /*!< session end */
/* global AHB control and status register bits definitions */
#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */
#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */
#define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */
#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */
#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */
/* global USB control and status register bits definitions */
#define GUSBCS_FDM BIT(30) /*!< force device mode */
#define GUSBCS_FHM BIT(29) /*!< force host mode */
#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */
#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */
#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */
#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */
#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */
#define GUSBCS_EMBPHY_FS BIT(6) /*!< embedded FS PHY selected */
#define GUSBCS_EMBPHY_HS BIT(5) /*!< embedded HS PHY selected */
#define GUSBCS_HS_CUR_FE BIT(4) /*!< HS current software enable */
#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */
/* global reset control register bits definitions */
#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */
#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */
#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */
#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */
#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */
#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */
#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */
#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */
/* global interrupt flag register bits definitions */
#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */
#define GINTF_SESIF BIT(30) /*!< session interrupt flag */
#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */
#define GINTF_IDPSC BIT(28) /*!< id pin status change */
#define GINTF_LPMIF BIT(27) /*!< LPM interrupt flag */
#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */
#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */
#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */
#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */
#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */
#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */
#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */
#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */
#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */
#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */
#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */
#define GINTF_RST BIT(12) /*!< USB reset */
#define GINTF_SP BIT(11) /*!< USB suspend */
#define GINTF_ESP BIT(10) /*!< early suspend */
#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */
#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */
#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */
#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */
#define GINTF_SOF BIT(3) /*!< start of frame */
#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */
#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */
#define GINTF_COPM BIT(0) /*!< current operation mode */
/* global interrupt enable register bits definitions */
#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */
#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */
#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */
#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */
#define GINTEN_LPMIE BIT(27) /*!< LPM interrupt enable */
#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */
#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */
#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */
#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */
#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */
#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */
#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */
#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */
#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */
#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */
#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */
#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */
#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */
#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */
#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */
#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */
#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */
#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */
#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */
#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */
#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */
/* global receive status read and pop register bits definitions */
#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */
#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */
#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */
#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */
#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */
/* global receive FIFO length register bits definitions */
#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */
/* host non-periodic transmit FIFO length register bits definitions */
#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */
#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */
/* USB IN endpoint 0 transmit FIFO length register bits definitions */
#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */
#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */
/* host non-periodic transmit FIFO/queue status register bits definitions */
#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */
#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */
#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */
#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/
#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */
#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */
#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */
/* global core configuration register bits definitions */
#define GCCFG_VDEN BIT(21) /*!< enable of VBUS sensing comparator to detect VBUS valid */
#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */
#define GCCFG_PWRON BIT(16) /*!< power on */
#define GCCFG_SDMEN BIT(15) /*!< secondary detection mode enable */
#define GCCFG_PEMEN BIT(14) /*!< primary detection mode enable */
#define GCCFG_DCDEN BIT(13) /*!< data connect detection mode enable */
#define GCCFG_BCDEN BIT(12) /*!< battery charging detection enable */
#define GCCFG_PS2F BIT(3) /*!< PS2 detection status */
#define GCCFG_SDF BIT(2) /*!< secondary detection status */
#define GCCFG_PDF BIT(1) /*!< primary detection status */
#define GCCFG_DCDF BIT(0) /*!< battery connect detection status */
/* core ID register bits definitions */
#define CID_CID BITS(0, 31) /*!< core ID */
/* global core LPM configuration register bits definitions */
#define GLPMCFG_BESLEN BIT(28) /*!< LPM Errata selection enable */
#define GLPMCFG_LPMRCS BITS(25, 27) /*!< LPM retry count status */
#define GLPMCFG_LPMSND BIT(24) /*!< send LPM transaction */
#define GLPMCFG_LPMRC BITS(21, 23) /*!< LPM retry count */
#define GLPMCFG_LPMCHI BITS(17, 20) /*!< channel number index */
#define GLPMCFG_RSOK BIT(16) /*!< Resume can be sent after sleep state */
#define GLPMCFG_LPMSLPS BIT(15) /*!< sleep status */
#define GLPMCFG_LPMRSP BITS(13, 14) /*!< response of LPM */
#define GLPMCFG_DSEN BIT(12) /*!< deep sleep enable */
#define GLPMCFG_BESLTH BITS(8, 11) /*!< BESL threshold */
#define GLPMCFG_SSEN BIT(7) /*!< shallow sleep enable */
#define GLPMCFG_REW BIT(6) /*!< bRemoteWake value */
#define GLPMCFG_BESL BITS(2, 5) /*!< best effort service latency */
#define GLPMCFG_ACKLPM BIT(1) /*!< ACK in LPM transaction enable */
#define GLPMCFG_LPMEN BIT(0) /*!< LPM enable */
/* power down register bits definition */
#define PWRD_ADPF BIT(23) /*!< ADP event interrupt flag */
#define PWRD_ADPMEN BIT(0) /*!< ADP module enable */
/* ADP control and status register bits definition */
#define ADPCTL_RWR BITS(27, 28) /*!< read and write request */
#define ADPCTL_ADPTFM BIT(26) /*!< the mask of ADP timeout interrupt flag */
#define ADPCTL_ADPSNFM BIT(25) /*!< the mask of ADP sense interrupt flag */
#define ADPCTL_ADPPRFM BIT(24) /*!< the mask of ADP probe interrupt flag */
#define ADPCTL_ADPTF BIT(23) /*!< ADP timeout interrupt flag */
#define ADPCTL_ADPSNF BIT(22) /*!< ADP sense interrupt flag */
#define ADPCTL_ADPPRF BIT(21) /*!< ADP probe interrupt flag */
#define ADPCTL_ADPEN BIT(20) /*!< ADP enable */
#define ADPCTL_ADPRST BIT(19) /*!< ADP reset */
#define ADPCTL_SNEN BIT(18) /*!< ADP sense enable */
#define ADPCTL_PREN BIT(17) /*!< ADP probe enable */
#define ADPCTL_CHGT BITS(6, 16) /*!< the latest time that VBUS ramps from VADPSINK to VADPPRB */
#define ADPCTL_PERPR BITS(4, 5) /*!< period of probe */
#define ADPCTL_RESOPR BITS(2, 3) /*!< the resolution of CHGT value */
#define ADPCTL_DSCHGPR BITS(0, 1) /*!< Time of probe discharge */
/* USBHS PHY control register bits definitions */
#define PHYCTL_HS_CALEN BIT(31) /*!< HS PHY calibration enable */
#define PHYCTL_HS_CALR BITS(25, 30) /*!< HS PHY calibration value */
#define PHYCTL_HS_RCALR BITS(21, 24) /*!< HS PHY R calibration value */
#define PHYCTL_SQUECH BIT(16) /*!< HS PHY squech flag */
#define PHYCTL_HS_BIST_DONE BIT(15) /*!< HS PHY bist finished flag */
#define PHYCTL_HS_BIST_SUCCESS BIT(14) /*!< HS PHY bist success flag */
#define PHYCTL_HS_BIST_FAIL BIT(13) /*!< HS PHY bist fail flag */
#define PHYCTL_HS_BIST_PKT_SEL BITS(11, 12) /*!< HS PHY bist packet select */
#define PHYCTL_HS_BIST_SEED BITS(3, 10) /*!< HS PHY bist seed */
#define PHYCTL_HS_BIST_EN BIT(2) /*!< HS PHY bist enable */
#define PHYCTL_HS_BIST_RESET BIT(1) /*!< HS PHY bist logic reset */
#define PHYCTL_HS_BIST_START BIT(0) /*!< HS PHY bist start */
/* host periodic transmit FIFO length register bits definitions */
#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */
#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */
/* device IN endpoint transmit FIFO length register bits definitions */
#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */
#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */
/* host control register bits definitions */
#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */
/* host frame interval register bits definitions */
#define HFT_FRI BITS(0, 15) /*!< frame interval */
/* host frame information remaining register bits definitions */
#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */
#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */
/* host periodic transmit FIFO/queue status register bits definitions */
#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */
#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */
#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */
#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */
#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */
#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */
#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */
#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */
#define TFQSTAT_TXFS BITS(0, 15)
#define TFQSTAT_CNUM BITS(27, 30)
/* host all channels interrupt register bits definitions */
#define HACHINT_HACHINT BITS(0, 15) /*!< host all channel interrupts */
/* host all channels interrupt enable register bits definitions */
#define HACHINTEN_CINTEN BITS(0, 15) /*!< channel interrupt enable */
/* host port control and status register bits definitions */
#define HPCS_PS BITS(17, 18) /*!< port speed */
#define HPCS_PTEST BITS(13, 16) /*!< port test control */
#define HPCS_PP BIT(12) /*!< port power */
#define HPCS_PLST BITS(10, 11) /*!< port line status */
#define HPCS_PRST BIT(8) /*!< port reset */
#define HPCS_PSP BIT(7) /*!< port suspend */
#define HPCS_PREM BIT(6) /*!< port resume */
#define HPCS_PEDC BIT(3) /*!< port enable/disable change */
#define HPCS_PE BIT(2) /*!< port enable */
#define HPCS_PCD BIT(1) /*!< port connect detected */
#define HPCS_PCST BIT(0) /*!< port connect status */
/* host channel-x control register bits definitions */
#define HCHCTL_CEN BIT(31) /*!< channel enable */
#define HCHCTL_CDIS BIT(30) /*!< channel disable */
#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */
#define HCHCTL_DAR BITS(22, 28) /*!< device address */
#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */
#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */
#define HCHCTL_LSD BIT(17) /*!< low-speed device */
#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */
#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */
#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */
/* host channel-x split transaction register bits definitions */
#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */
#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */
#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */
#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */
#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */
/* host channel-x interrupt flag register bits definitions */
#define HCHINTF_DTER BIT(10) /*!< data toggle error */
#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */
#define HCHINTF_BBER BIT(8) /*!< babble error */
#define HCHINTF_USBER BIT(7) /*!< USB bus Error */
#define HCHINTF_NYET BIT(6) /*!< NYET */
#define HCHINTF_ACK BIT(5) /*!< ACK */
#define HCHINTF_NAK BIT(4) /*!< NAK */
#define HCHINTF_STALL BIT(3) /*!< STALL */
#define HCHINTF_DMAER BIT(2) /*!< DMA error */
#define HCHINTF_CH BIT(1) /*!< channel halted */
#define HCHINTF_TF BIT(0) /*!< transfer finished */
/* host channel-x interrupt enable register bits definitions */
#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */
#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */
#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */
#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */
#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */
#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */
#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */
#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */
#define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */
#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */
#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */
/* host channel-x transfer length register bits definitions */
#define HCHLEN_PING BIT(31) /*!< PING token request */
#define HCHLEN_DPID BITS(29, 30) /*!< data PID */
#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */
#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */
/* host channel-x DMA address register bits definitions */
#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
#define PORT_SPEED(x) (((uint32_t)(x) << 17U) & HPCS_PS) /*!< Port speed */
#define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */
#define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */
#define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */
#define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22U) & HCHCTL_DAR) /*!< device address */
#define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18U) & HCHCTL_EPTYPE) /*!< endpoint type */
#define PIPE_CTL_EPNUM(x) (((uint32_t)(x) << 11U) & HCHCTL_EPNUM) /*!< endpoint number */
#define PIPE_CTL_EPDIR(x) (((uint32_t)(x) << 15U) & HCHCTL_EPDIR) /*!< endpoint direction */
#define PIPE_CTL_EPMPL(x) (((uint32_t)(x) << 0U) & HCHCTL_MPL) /*!< maximum packet length */
#define PIPE_CTL_LSD(x) (((uint32_t)(x) << 17U) & HCHCTL_LSD) /*!< low-Speed device */
#define PIPE_XFER_PCNT(x) (((uint32_t)(x) << 19U) & HCHLEN_PCNT) /*!< packet count */
#define PIPE_XFER_DPID(x) (((uint32_t)(x) << 29U) & HCHLEN_DPID) /*!< data PID */
#define PIPE_DPID_DATA0 PIPE_XFER_DPID(0) /*!< DATA0 */
#define PIPE_DPID_DATA1 PIPE_XFER_DPID(2) /*!< DATA1 */
#define PIPE_DPID_DATA2 PIPE_XFER_DPID(1) /*!< DATA2 */
#define PIPE_DPID_SETUP PIPE_XFER_DPID(3) /*!< MDATA (non-control)/SETUP (control) */
extern const uint32_t PIPE_DPID[2];
/* device configuration registers bits definitions */
#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */
#define DCFG_DAR BITS(4, 10) /*!< device address */
#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */
#define DCFG_DS BITS(0, 1) /*!< device speed */
/* device control registers bits definitions */
#define DCTL_L1RJCT BIT(18) /*!< deep sleep reject */
#define DCTL_POIF BIT(11) /*!< power-on initialization finished */
#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */
#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */
#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */
#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */
#define DCTL_DTEST BITS(4, 6) /*!< device test control */
#define DCTL_GONS BIT(3) /*!< global OUT NAK status */
#define DCTL_GINS BIT(2) /*!< global IN NAK status */
#define DCTL_SD BIT(1) /*!< soft disconnect */
#define DCTL_RWKUP BIT(0) /*!< remote wakeup */
/* device status registers bits definitions */
#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */
#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */
#define DSTAT_SPST BIT(0) /*!< suspend status */
/* device IN endpoint common interrupt enable registers bits definitions */
#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */
#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */
#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */
#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */
#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */
#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */
#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */
/* device OUT endpoint common interrupt enable registers bits definitions */
#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */
#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */
#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */
#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */
#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */
#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */
/* device all endpoints interrupt registers bits definitions */
#define DAEPINT_OEPITB BITS(16, 23) /*!< device all OUT endpoint interrupt bits */
#define DAEPINT_IEPITB BITS(0, 7) /*!< device all IN endpoint interrupt bits */
/* device all endpoints interrupt enable registers bits definitions */
#define DAEPINTEN_OEPIE BITS(16, 23) /*!< OUT endpoint interrupt enable */
#define DAEPINTEN_IEPIE BITS(0, 7) /*!< IN endpoint interrupt enable */
/* device VBUS discharge time registers bits definitions */
#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */
/* device VBUS pulsing time registers bits definitions */
#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */
/* device IN endpoint FIFO empty interrupt enable register bits definitions */
#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */
/* device endpoint 0 control register bits definitions */
#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */
#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */
#define DEP0CTL_SNAK BIT(27) /*!< set NAK */
#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */
#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */
#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */
#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */
#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */
#define DEP0CTL_NAKS BIT(17) /*!< NAK status */
#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */
#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */
/* device endpoint x control register bits definitions */
#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */
#define DEPCTL_EPD BIT(30) /*!< endpoint disable */
#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */
#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */
#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */
#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */
#define DEPCTL_SNAK BIT(27) /*!< set NAK */
#define DEPCTL_CNAK BIT(26) /*!< clear NAK */
#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */
#define DEPCTL_STALL BIT(21) /*!< STALL handshake */
#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */
#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */
#define DEPCTL_NAKS BIT(17) /*!< NAK status */
#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */
#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */
#define DEPCTL_EPACT BIT(15) /*!< endpoint active */
#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */
/* device IN endpoint-x interrupt flag register bits definitions */
#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */
#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */
#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */
#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */
#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */
#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */
#define DIEPINTF_TF BIT(0) /*!< transfer finished */
/* device OUT endpoint-x interrupt flag register bits definitions */
#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */
#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */
#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */
#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */
#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */
#define DOEPINTF_TF BIT(0) /*!< transfer finished */
/* device IN endpoint 0 transfer length register bits definitions */
#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */
#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */
/* device OUT endpoint 0 transfer length register bits definitions */
#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */
#define DOEP0LEN_PCNT BIT(19) /*!< packet count */
#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */
/* device OUT endpoint-x transfer length register bits definitions */
#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */
#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */
#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */
#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */
#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */
/* device IN endpoint-x DMA address register bits definitions */
#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
/* device OUT endpoint-x DMA address register bits definitions */
#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
/* device IN endpoint-x transmit FIFO status register bits definitions */
#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */
/* USB power and clock registers bits definition */
#define PWRCLKCTL_DSLEEP BIT(7) /*!< PHY is in deep sleep status */
#define PWRCLKCTL_SSLEEP BIT(6) /*!< PHY is in shallow sleep status */
#define PWRCLKCTL_SCGEN BIT(5) /*!< When this bit is set, the internal clock gating is enabled */
#define PWRCLKCTL_SUSP BIT(4) /*!< PHY is in suspend status */
#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */
#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */
#define RSTAT_GOUT_NAK 1U /*!< global OUT NAK (triggers an interrupt) */
#define RSTAT_DATA_UPDT 2U /*!< OUT data packet received */
#define RSTAT_XFER_COMP 3U /*!< OUT transfer completed (triggers an interrupt) */
#define RSTAT_SETUP_COMP 4U /*!< SETUP transaction completed (triggers an interrupt) */
#define RSTAT_SETUP_UPDT 6U /*!< SETUP data packet received */
#define DSTAT_EM_HS_PHY_30MHZ_60MHZ 0U /*!< USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */
#define DSTAT_EM_FS_PHY_30MHZ_60MHZ 1U /*!< USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */
#define DSTAT_EM_LS_PHY_6MHZ 2U /*!< USB enumerate speed use low-speed PHY clock in 6MHz */
#define DSTAT_EM_FS_PHY_48MHZ 3U /*!< USB enumerate speed use full-speed PHY clock in 48MHz */
#define DPID_DATA0 0U /*!< device endpoint data PID is DATA0 */
#define DPID_DATA1 2U /*!< device endpoint data PID is DATA1 */
#define DPID_DATA2 1U /*!< device endpoint data PID is DATA2 */
#define DPID_MDATA 3U /*!< device endpoint data PID is MDATA */
#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA */
#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/
#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA */
#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA */
#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA */
#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA */
#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */
#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */
#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */
#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */
#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */
#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */
#define USB_SPEED_INP_HIGH DCFG_DEVSPEED(0U) /*!< device internal PHY high speed */
#define USB_SPEED_INP_FULL DCFG_DEVSPEED(1U) /*!< device internal PHY full speed */
#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */
#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */
#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */
#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */
#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */
#define DOEP0_TLEN(regval) (DOEP0LEN_TLEN & ((regval) << 0U)) /*!< Transfer length */
#define DOEP0_PCNT(regval) (DOEP0LEN_PCNT & ((regval) << 19U)) /*!< Packet count */
#define DOEP0_STPCNT(regval) (DOEP0LEN_STPCNT & ((regval) << 29U)) /*!< SETUP packet count */
#define GRXSTS_PKTSTS_IN 2U
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
#define DEVICE_MODE 0U /*!< device mode */
#define HOST_MODE 1U /*!< host mode */
#define OTG_MODE 2U /*!< OTG mode */
#define HCTL_30_60MHZ 0U /*!< USB clock 30-60MHZ */
#define HCTL_48MHZ 1U /*!< USB clock 48MHZ */
#define HCTL_6MHZ 2U /*!< USB clock 6MHZ */
#define USBHS_MAX_PACKET_SIZE 512U /*!< USBHS max packet size */
#define USBHS_MAX_CHANNEL_COUNT 16U /*!< USBHS host channel count */
#define USBHS_MAX_EP_COUNT 8U /*!< USBHS device endpoint count */
#define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */
#define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */
#define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */
typedef enum
{
USB_EMBEDDED_PHY_FS = 0U, /*!< USB embedded FS PHY */
USB_EMBEDDED_PHY_HS, /*!< USB embedded HS PHY */
USB_ULPI_PHY_EXTERNAL /*!< USB external ULPI PHY */
} usb_phy_enum;
enum usb_reg_offset
{
USB_REG_OFFSET_CORE = 0x0000U, /*!< global OTG control and status register */
USB_REG_OFFSET_DEV = 0x0800U, /*!< device mode control and status registers */
USB_REG_OFFSET_EP = 0x0020U, /*!< offset of each endpoint */
USB_REG_OFFSET_EP_IN = 0x0900U, /*!< device IN endpoint 0 control register */
USB_REG_OFFSET_EP_OUT = 0x0B00U, /*!< device OUT endpoint 0 control register */
USB_REG_OFFSET_HOST = 0x0400U, /*!< host control register */
USB_REG_OFFSET_CH = 0x0020U, /*!< offset of each channel */
USB_REG_OFFSET_PORT = 0x0440U, /*!< host port control and status register */
USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< host channel-x control registers */
USB_REG_OFFSET_PWRCLKCTL = 0x0E00U /*!< power and clock register */
};
enum USB_SPEED
{
USB_SPEED_UNKNOWN = 0, /*!< USB speed unknown */
USB_SPEED_LOW, /*!< USB speed low */
USB_SPEED_FULL, /*!< USB speed full */
USB_SPEED_HIGH /*!< USB speed high */
};
#define EP0_OUT ((uint8_t)0x00U) /*!< endpoint out 0 */
#define EP0_IN ((uint8_t)0x80U) /*!< endpoint in 0 */
#define EP1_OUT ((uint8_t)0x01U) /*!< endpoint out 1 */
#define EP1_IN ((uint8_t)0x81U) /*!< endpoint in 1 */
#define EP2_OUT ((uint8_t)0x02U) /*!< endpoint out 2 */
#define EP2_IN ((uint8_t)0x82U) /*!< endpoint in 2 */
#define EP3_OUT ((uint8_t)0x03U) /*!< endpoint out 3 */
#define EP3_IN ((uint8_t)0x83U) /*!< endpoint in 3 */
#define EP4_OUT ((uint8_t)0x04U) /*!< endpoint out 4 */
#define EP4_IN ((uint8_t)0x84U) /*!< endpoint in 4 */
#define EP5_OUT ((uint8_t)0x05U) /*!< endpoint out 5 */
#define EP5_IN ((uint8_t)0x85U) /*!< endpoint in 5 */
#define EP6_OUT ((uint8_t)0x06U) /*!< endpoint out 6 */
#define EP6_IN ((uint8_t)0x86U) /*!< endpoint in 6 */
#define EP7_OUT ((uint8_t)0x06U) /*!< endpoint out 7 */
#define EP7_IN ((uint8_t)0x86U) /*!< endpoint in 7 */
#endif /* DRV_USB_REGS_H */
828ECO/drivers/include/usb/drv_usbd_int.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USBD_INT_H
#define DRV_USBD_INT_H
#include "drv_usb_core.h"
#include "drv_usb_dev.h"
/* function declarations */
#ifdef USB_DEDICATED_EP1_ENABLED
/* USB dedicated OUT endpoint 1 interrupt service routine handler */
uint32_t usbd_int_dedicated_ep1out(usb_core_driver *udev);
/* USB dedicated IN endpoint 1 interrupt service routine handler */
uint32_t usbd_int_dedicated_ep1in(usb_core_driver *udev);
#endif /* USB_DEDICATED_EP1_ENABLED */
/* USB device-mode interrupts global service routine handler */
void usbd_isr(usb_core_driver *udev);
#endif /* DRV_USBD_INT_H */
828ECO/drivers/include/usb/drv_usbh_int.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef DRV_USBH_INT_H
#define DRV_USBH_INT_H
#include "drv_usb_host.h"
/* handle global host interrupt */
uint32_t usbh_isr(usb_core_driver *udev);
#endif /* DRV_USBH_INT_H */
828ECO/drivers/include/usb/drv_usbh_pipe.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef __DRV_USBH_PIPE_H
#define __DRV_USBH_PIPE_H
#include "drv_usb_host.h"
#define HC_MAX 8U
#define HC_OK 0x0000U
#define HC_USED 0x8000U
#define HC_ERROR 0xFFFFU
#define HC_USED_MASK 0x7FFFU
/* allocate a new pipe */
uint8_t usbh_pipe_allocate(usb_core_driver *pudev, uint8_t ep_addr);
/* delete all USB host pipe */
uint8_t usbh_pipe_delete(usb_core_driver *pudev);
/* free a pipe */
uint8_t usbh_pipe_free(usb_core_driver *pudev, uint8_t pp_num);
/* create a pipe */
uint8_t usbh_pipe_create(usb_core_driver *pudev,
uint8_t dev_addr,
uint8_t dev_speed,
uint8_t pp_num,
uint8_t ep_num,
uint8_t ep_type,
uint16_t ep_mpl);
/* modify a pipe */
uint8_t usbh_pipe_update(usb_core_driver *pudev,
uint8_t pp_num,
uint8_t dev_addr,
uint32_t dev_speed,
uint16_t ep_mpl);
#endif /* __DRV_USBH_PIPE_H */
828ECO/drivers/include/usb/drv_usbh_transc.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef __DRV_USBH_TRANSC_H
#define __DRV_USBH_TRANSC_H
#include "drv_usb_host.h"
#if defined(BSP_USING_USB) && defined(RT_USING_USB_HOST)
/* send the setup packet to the USB device */
usbh_status usbh_ctlsetup_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num);
/* send a data packet to the USB device */
usbh_status usbh_data_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len);
/* receive a data packet from the USB device */
usbh_status usbh_data_recev(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len);
/* get USB URB state */
static inline usb_urb_state usbh_urbstate_get(usb_core_driver *pudev, uint8_t pp_num)
{
return pudev->host.pipe[pp_num].urb_state;
}
/* get USB transfer data count */
static inline uint32_t usbh_xfercount_get(usb_core_driver *pudev, uint8_t pp_num)
{
return pudev->host.backup_xfercount[pp_num];
}
#endif /* BSP_USING_USB && RT_USING_USB_HOST */
#endif /* __DRV_USBH_TRANSC_H */
828ECO/drivers/include/usb/usb_conf.h
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-11-07 RealThread the first version
*/
#ifndef USB_CONF_H
#define USB_CONF_H
#include <board.h>
#if defined(BSP_USING_USB)
#if defined(SOC_SERIES_GD32H75E)
#include "gd32h75e.h"
#elif defined(SOC_SERIES_GD32H7xx)
#include "gd32h7xx.h"
#endif
/* USB Core and PHY interface configuration */
/* USB HS PHY CONFIGURATION */
/* on-chip full-speed USB PHY */
#ifdef USE_USB_FS
#define OC_FS_PHY
#endif
/* on-chip high-speed USB PHY */
#ifdef USE_USB_HS
#define OC_HS_PHY
#endif /* USE_USB_HS */
#if defined(RT_USING_USB_DEVICE)
#define USB_SOF_OUTPUT 0U
/* USB FIFO size config */
#define RX_FIFO_SIZE 512U
#define TX0_FIFO_SIZE 128U
#define TX1_FIFO_SIZE 384U
#define TX2_FIFO_SIZE 0U
#define TX3_FIFO_SIZE 0U
#define TX4_FIFO_SIZE 0U
#define TX5_FIFO_SIZE 0U
#define TX6_FIFO_SIZE 0U
#define TX7_FIFO_SIZE 0U
#elif defined(RT_USING_USB_HOST)
#define USBH_USE_RTOS
#define USB_SOF_OUTPUT 1U
/* USB FIFO size config */
#define USB_RX_FIFO_SIZE 512
#define USB_HTX_NPFIFO_SIZE 256
#define USB_HTX_PFIFO_SIZE 256
#endif
/* General USB Configuration */
#define USB_LOW_POWER 0U
/* if uncomment it, need jump to USB JP */
//#define VBUS_SENSING_ENABLED
//#define USB_INTERNAL_DMA_ENABLED
//#define USB_DEDICATED_EP1_ENABLED
/* End General USB Configuration */
#ifdef USE_ULPI_PHY
#define USB_EXTERNAL_ULPI_PHY_ENABLED
#else
#ifdef OC_FS_PHY
#define USB_EMBEDDED_FS_PHY_ENABLED
#elif defined(OC_HS_PHY)
#define USB_EMBEDDED_HS_PHY_ENABLED
#else
#error "PHY is not selected"
#endif /* OC_FS_PHY */
#endif /* USE_ULPI_PHY */
#if defined(RT_USING_USB_HOST)
#define USE_HOST_MODE
#elif defined(RT_USING_USB_DEVICE)
#define USE_DEVICE_MODE
#else
#warning "Please select the USB mode as USBD or USBH; otherwise, the USE_OTG_MODE will be enabled by default."
#define USE_OTG_MODE
#endif
#ifndef OC_FS_PHY
#ifndef OC_HS_PHY
#error "OC_FS_PHY or OC_HS_PHY should be defined!"
#endif
#endif /* OC_FS_PHY */
#ifndef RT_USING_USB_DEVICE
#ifndef RT_USING_USB_HOST
#error "RT_USING_USB_DEVICE or RT_USING_USB_HOST should be defined!"
#endif
#endif /* USE_DEVICE_MODE */
#ifndef USE_USB_HS
#ifndef USE_USB_FS
#error "USE_USB_HS or USE_USB_FS should be defined!"
#endif
#endif /* USE_USB_HS */
/* all variables and data structures during the transaction process should be 4-bytes aligned */
#if defined(__GNUC__) /* GNU Compiler */
#define __ALIGN_END __attribute__((aligned(4)))
#define __ALIGN_BEGIN
#else
#define __ALIGN_END
#if defined(__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined(__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#elif defined(__TASKING__)/* TASKING Compiler */
#define __ALIGN_BEGIN __align(4)
#endif /* __CC_ARM */
#endif /* __GNUC__ */
/* __packed keyword used to decrease the data type alignment to 1-byte */
#if defined(__GNUC__) /* GNU Compiler */
#ifndef __packed
#define __packed __unaligned
#endif
#elif defined(__TASKING__) /* TASKING Compiler */
#define __packed __unaligned
#endif /* __GNUC__ */
#endif /* BSP_USING_USB */
#endif /* USB_CONF_H */