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@@ -0,0 +1,750 @@
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.syntax unified
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.cpu cortex-m7
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.fpu softvfp
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.thumb
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.global Default_Handler
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/* necessary symbols defined in linker script to initialize data */
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.word _sidata
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.word _sdata
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.word _edata
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.word _sbss
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.word _ebss
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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/* reset Handler */
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Reset_Handler:
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movs r1, #0
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b DataInit
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CopyData:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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DataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyData
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ldr r2, =_sbss
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b Zerobss
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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Zerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call SystemInit function */
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bl SystemInit
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/* Call static constructors */
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bl __libc_init_array
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/*Call the main function */
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bl entry
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bx lr
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.size Reset_Handler, .-Reset_Handler
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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.section .vectors,"a",%progbits
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.global __gVectors
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__gVectors:
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.word _sp /* Top of Stack */
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.word Reset_Handler /* Reset Handler */
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.word NMI_Handler /* NMI Handler */
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.word HardFault_Handler /* Hard Fault Handler */
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.word MemManage_Handler /* MPU Fault Handler */
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.word BusFault_Handler /* Bus Fault Handler */
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.word UsageFault_Handler /* Usage Fault Handler */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word SVC_Handler /* SVCall Handler */
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.word DebugMon_Handler /* Debug Monitor Handler */
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.word 0 /* Reserved */
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.word PendSV_Handler /* PendSV Handler */
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.word SysTick_Handler /* SysTick Handler */
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/* External interrupts handler */
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.word WWDGT_IRQHandler /* Vector Number 16,Window Watchdog Timer */
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.word VAVD_LVD_VOVD_IRQHandler /* Vector Number 17,VAVD/LVD/VOVD through EXTI Line detect */
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.word TAMPER_STAMP_LXTAL_IRQHandler /* Vector Number 18,RTC Tamper and TimeStamp through EXTI Line detect, LXTAL clock security system interrupt */
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.word RTC_WKUP_IRQHandler /* Vector Number 19,RTC Wakeup from EXTI interrupt */
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.word FMC_IRQHandler /* Vector Number 20,FMC global interrupt */
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.word RCU_IRQHandler /* Vector Number 21,RCU global interrupt */
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.word EXTI0_IRQHandler /* Vector Number 22,EXTI Line 0 */
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.word EXTI1_IRQHandler /* Vector Number 23,EXTI Line 1 */
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.word EXTI2_IRQHandler /* Vector Number 24,EXTI Line 2 */
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.word EXTI3_IRQHandler /* Vector Number 25,EXTI Line 3 */
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.word EXTI4_IRQHandler /* Vector Number 26,EXTI Line 4 */
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.word DMA0_Channel0_IRQHandler /* Vector Number 27,DMA0 Channel 0 */
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.word DMA0_Channel1_IRQHandler /* Vector Number 28,DMA0 Channel 1 */
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.word DMA0_Channel2_IRQHandler /* Vector Number 29,DMA0 Channel 2 */
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.word DMA0_Channel3_IRQHandler /* Vector Number 30,DMA0 Channel 3 */
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.word DMA0_Channel4_IRQHandler /* Vector Number 31,DMA0 Channel 4 */
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.word DMA0_Channel5_IRQHandler /* Vector Number 32,DMA0 Channel 5 */
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.word DMA0_Channel6_IRQHandler /* Vector Number 33,DMA0 Channel 6 */
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.word ADC0_1_IRQHandler /* Vector Number 34,ADC0 and ADC1 interrupt */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word EXTI5_9_IRQHandler /* Vector Number 39,EXTI5 to EXTI9 */
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.word TIMER0_BRK_IRQHandler /* Vector Number 40,TIMER0 Break */
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.word TIMER0_UP_IRQHandler /* Vector Number 41,TIMER0 Update */
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.word TIMER0_TRG_CMT_IRQHandler /* Vector Number 42,TIMER0 Trigger and Commutation */
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.word TIMER0_Channel_IRQHandler /* Vector Number 43,TIMER0 Capture Compare */
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.word TIMER1_IRQHandler /* Vector Number 44,TIMER1 */
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.word TIMER2_IRQHandler /* Vector Number 45,TIMER2 */
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.word TIMER3_IRQHandler /* Vector Number 46,TIMER3 */
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.word I2C0_EV_IRQHandler /* Vector Number 47,I2C0 Event */
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.word I2C0_ER_IRQHandler /* Vector Number 48,I2C0 Error */
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.word I2C1_EV_IRQHandler /* Vector Number 49,I2C1 Event */
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.word I2C1_ER_IRQHandler /* Vector Number 50,I2C1 Error */
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.word SPI0_IRQHandler /* Vector Number 51,SPI0 */
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.word SPI1_IRQHandler /* Vector Number 52,SPI1 */
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.word USART0_IRQHandler /* Vector Number 53,USART0 global and wakeup */
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.word USART1_IRQHandler /* Vector Number 54,USART1 global and wakeup */
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.word USART2_IRQHandler /* Vector Number 55,USART2 global and wakeup */
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.word EXTI10_15_IRQHandler /* Vector Number 56,EXTI10 to EXTI15 */
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.word RTC_Alarm_IRQHandler /* Vector Number 57,RTC Alarm */
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.word 0 /* Reserved */
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.word TIMER7_BRK_IRQHandler /* Vector Number 59,TIMER7 Break */
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.word TIMER7_UP_IRQHandler /* Vector Number 60,TIMER7 Update */
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.word TIMER7_TRG_CMT_IRQHandler /* Vector Number 61,TIMER7 Trigger and Commutation */
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.word TIMER7_Channel_IRQHandler /* Vector Number 62,TIMER7 Channel Capture Compare */
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.word DMA0_Channel7_IRQHandler /* Vector Number 63,DMA0 Channel 7 */
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.word EXMC_IRQHandler /* Vector Number 64,EXMC */
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.word 0 /* Reserved */
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.word TIMER4_IRQHandler /* Vector Number 66,TIMER4 */
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.word SPI2_IRQHandler /* Vector Number 67,SPI2 */
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.word UART3_IRQHandler /* Vector Number 68,UART3 */
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.word UART4_IRQHandler /* Vector Number 69,UART4 */
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.word TIMER5_DAC_UDR_IRQHandler /* Vector Number 70,TIMER5 global interrupt and DAC1/DAC0 underrun error */
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.word TIMER6_IRQHandler /* Vector Number 71,TIMER6 */
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.word DMA1_Channel0_IRQHandler /* Vector Number 72,DMA1 Channel0 */
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.word DMA1_Channel1_IRQHandler /* Vector Number 73,DMA1 Channel1 */
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.word DMA1_Channel2_IRQHandler /* Vector Number 74,DMA1 Channel2 */
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.word DMA1_Channel3_IRQHandler /* Vector Number 75,DMA1 Channel3 */
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.word DMA1_Channel4_IRQHandler /* Vector Number 76,DMA1 Channel4 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word DMA1_Channel5_IRQHandler /* Vector Number 84,DMA1 Channel5 */
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.word DMA1_Channel6_IRQHandler /* Vector Number 85,DMA1 Channel6 */
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.word DMA1_Channel7_IRQHandler /* Vector Number 86,DMA1 Channel7 */
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.word USART5_IRQHandler /* Vector Number 87,USART5 global and wakeup */
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.word I2C2_EV_IRQHandler /* Vector Number 88,I2C2 Event */
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.word I2C2_ER_IRQHandler /* Vector Number 89,I2C2 Error */
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.word USBHS0_EP1_OUT_IRQHandler /* Vector Number 90,USBHS0 Endpoint 1 Out */
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.word USBHS0_EP1_IN_IRQHandler /* Vector Number 91,USBHS0 Endpoint 1 in */
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.word USBHS0_WKUP_IRQHandler /* Vector Number 92,USBHS0 Wakeup through EXTI Line */
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.word USBHS0_IRQHandler /* Vector Number 93,USBHS0 */
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.word 0 /* Vector Number 94,Reserved */
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.word 0 /* Vector Number 95,Reserved */
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.word TRNG_IRQHandler /* Vector Number 96,TRNG */
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.word FPU_IRQHandler /* Vector Number 97,FPU */
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.word UART6_IRQHandler /* Vector Number 98,UART6 */
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.word UART7_IRQHandler /* Vector Number 99,UART7 */
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.word SPI3_IRQHandler /* Vector Number 100,SPI3 */
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.word SPI4_IRQHandler /* Vector Number 101,SPI4 */
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.word SPI5_IRQHandler /* Vector Number 102,SPI5 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word OSPI0_IRQHandler /* Vector Number 108,OSPI0 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word I2C3_EV_IRQHandler /* Vector Number 111,I2C3 Event */
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.word I2C3_ER_IRQHandler /* Vector Number 112,I2C3 Error */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word DMAMUX_OVR_IRQHandler /* Vector Number 118,DMAMUX Overrun interrupt */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word HPDF_INT0_IRQHandler /* Vector Number 126,HPDF global interrupt 0 */
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.word HPDF_INT1_IRQHandler /* Vector Number 127,HPDF global interrupt 1 */
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.word HPDF_INT2_IRQHandler /* Vector Number 128,HPDF global interrupt 2 */
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.word HPDF_INT3_IRQHandler /* Vector Number 129,HPDF global interrupt 3 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word TIMER14_IRQHandler /* Vector Number 132,TIMER14 */
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.word TIMER15_IRQHandler /* Vector Number 133,TIMER15 */
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.word TIMER16_IRQHandler /* Vector Number 134,TIMER16 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word MDMA_IRQHandler /* Vector Number 138,MDMA */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word ADC2_IRQHandler /* Vector Number 143,ADC2 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word CMP0_1_IRQHandler /* Vector Number 153,CMP0 and CMP1 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word CTC_IRQHandler /* Vector Number 160,Clock Recovery System */
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.word RAMECCMU_IRQHandler /* Vector Number 161,RAMECCMU */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word OSPI1_IRQHandler /* Vector Number 166,OSPI1 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word FAC_IRQHandler /* Vector Number 169,FAC */
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.word TMU_IRQHandler /* Vector Number 170,TMU */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word TIMER22_IRQHandler /* Vector Number 177,TIMER22 */
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.word TIMER23_IRQHandler /* Vector Number 178,TIMER23 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word TIMER40_IRQHandler /* Vector Number 181,TIMER40 */
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.word TIMER41_IRQHandler /* Vector Number 182,TIMER41 */
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.word TIMER42_IRQHandler /* Vector Number 183,TIMER42 */
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.word TIMER43_IRQHandler /* Vector Number 184,TIMER43 */
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.word TIMER44_IRQHandler /* Vector Number 185,TIMER44 */
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.word TIMER50_IRQHandler /* Vector Number 186,TIMER50 */
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.word TIMER51_IRQHandler /* Vector Number 187,TIMER51 */
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.word USBHS1_EP1_OUT_IRQHandler /* Vector Number 188,USBHS1 endpoint 1 out */
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.word USBHS1_EP1_IN_IRQHandler /* Vector Number 189,USBHS1 endpoint 1 in */
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.word USBHS1_WKUP_IRQHandler /* Vector Number 190,USBHS1 wakeup */
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.word USBHS1_IRQHandler /* Vector Number 191,USBHS1 */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word CAN0_WKUP_IRQHandler /* Vector Number 195,CAN0 wakeup */
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.word CAN0_Message_IRQHandler /* Vector Number 196,CAN0 interrupt for message buffer */
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.word CAN0_Busoff_IRQHandler /* Vector Number 197,CAN0 interrupt for Bus off / Bus off done */
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.word CAN0_Error_IRQHandler /* Vector Number 198,CAN0 interrupt for Error */
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.word CAN0_FastError_IRQHandler /* Vector Number 199,CAN0 interrupt for Error in fast transmission */
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.word CAN0_TEC_IRQHandler /* Vector Number 200,CAN0 interrupt for Transmit warning */
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||||
.word CAN0_REC_IRQHandler /* Vector Number 201,CAN0 interrupt for Receive warning */
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.word CAN1_WKUP_IRQHandler /* Vector Number 202,CAN1 wakeup */
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.word CAN1_Message_IRQHandler /* Vector Number 203,CAN1 interrupt for message buffer */
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.word CAN1_Busoff_IRQHandler /* Vector Number 204,CAN1 interrupt for Bus off / Bus off done */
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||||
.word CAN1_Error_IRQHandler /* Vector Number 205,CAN1 interrupt for Error */
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||||
.word CAN1_FastError_IRQHandler /* Vector Number 206,CAN1 interrupt for Error in fast transmission */
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||||
.word CAN1_TEC_IRQHandler /* Vector Number 207,CAN1 interrupt for Transmit warning */
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||||
.word CAN1_REC_IRQHandler /* Vector Number 208,CAN1 interrupt for Receive warning */
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||||
.word CAN2_WKUP_IRQHandler /* Vector Number 209,CAN2 wakeup */
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||||
.word CAN2_Message_IRQHandler /* Vector Number 210,CAN2 interrupt for message buffer */
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||||
.word CAN2_Busoff_IRQHandler /* Vector Number 211,CAN2 interrupt for Bus off / Bus off done */
|
||||
.word CAN2_Error_IRQHandler /* Vector Number 212,CAN2 interrupt for Error */
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.word CAN2_FastError_IRQHandler /* Vector Number 213,CAN2 interrupt for Error in fast transmission */
|
||||
.word CAN2_TEC_IRQHandler /* Vector Number 214,CAN2 interrupt for Transmit warning */
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||||
.word CAN2_REC_IRQHandler /* Vector Number 215,CAN2 interrupt for Receive warning */
|
||||
.word EFUSE_IRQHandler /* Vector Number 216,EFUSE */
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||||
.word I2C0_WKUP_IRQHandler /* Vector Number 217,I2C0 wakeup */
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||||
.word I2C1_WKUP_IRQHandler /* Vector Number 218,I2C1 wakeup */
|
||||
.word I2C2_WKUP_IRQHandler /* Vector Number 219,I2C2 wakeup */
|
||||
.word I2C3_WKUP_IRQHandler /* Vector Number 220,I2C3 wakeup */
|
||||
.word LPDTS_IRQHandler /* Vector Number 221,LPDTS */
|
||||
.word LPDTS_WKUP_IRQHandler /* Vector Number 222,LPDTS wakeup */
|
||||
.word TIMER0_DEC_IRQHandler /* Vector Number 223,TIMER0 DEC */
|
||||
.word TIMER7_DEC_IRQHandler /* Vector Number 224,TIMER7 DEC */
|
||||
.word TIMER1_DEC_IRQHandler /* Vector Number 225,TIMER1 DEC */
|
||||
.word TIMER2_DEC_IRQHandler /* Vector Number 226,TIMER2 DEC */
|
||||
.word TIMER3_DEC_IRQHandler /* Vector Number 227,TIMER3 DEC */
|
||||
.word TIMER4_DEC_IRQHandler /* Vector Number 228,TIMER4 DEC */
|
||||
.word TIMER22_DEC_IRQHandler /* Vector Number 229,TIMER22 DEC */
|
||||
.word TIMER23_DEC_IRQHandler /* Vector Number 230,TIMER23 DEC */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
|
||||
.size __gVectors, . - __gVectors
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
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.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDGT_IRQHandler
|
||||
.thumb_set WWDGT_IRQHandler,Default_Handler
|
||||
|
||||
.weak VAVD_LVD_VOVD_IRQHandler
|
||||
.thumb_set VAVD_LVD_VOVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_STAMP_LXTAL_IRQHandler
|
||||
.thumb_set TAMPER_STAMP_LXTAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCU_IRQHandler
|
||||
.thumb_set RCU_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel0_IRQHandler
|
||||
.thumb_set DMA0_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel1_IRQHandler
|
||||
.thumb_set DMA0_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel2_IRQHandler
|
||||
.thumb_set DMA0_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel3_IRQHandler
|
||||
.thumb_set DMA0_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel4_IRQHandler
|
||||
.thumb_set DMA0_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel5_IRQHandler
|
||||
.thumb_set DMA0_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel6_IRQHandler
|
||||
.thumb_set DMA0_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC0_1_IRQHandler
|
||||
.thumb_set ADC0_1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_9_IRQHandler
|
||||
.thumb_set EXTI5_9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_BRK_IRQHandler
|
||||
.thumb_set TIMER0_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_UP_IRQHandler
|
||||
.thumb_set TIMER0_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_TRG_CMT_IRQHandler
|
||||
.thumb_set TIMER0_TRG_CMT_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_Channel_IRQHandler
|
||||
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER1_IRQHandler
|
||||
.thumb_set TIMER1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER2_IRQHandler
|
||||
.thumb_set TIMER2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER3_IRQHandler
|
||||
.thumb_set TIMER3_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_EV_IRQHandler
|
||||
.thumb_set I2C0_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_ER_IRQHandler
|
||||
.thumb_set I2C0_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI0_IRQHandler
|
||||
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART0_IRQHandler
|
||||
.thumb_set USART0_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_15_IRQHandler
|
||||
.thumb_set EXTI10_15_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_BRK_IRQHandler
|
||||
.thumb_set TIMER7_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_UP_IRQHandler
|
||||
.thumb_set TIMER7_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_TRG_CMT_IRQHandler
|
||||
.thumb_set TIMER7_TRG_CMT_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_Channel_IRQHandler
|
||||
.thumb_set TIMER7_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel7_IRQHandler
|
||||
.thumb_set DMA0_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXMC_IRQHandler
|
||||
.thumb_set EXMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER4_IRQHandler
|
||||
.thumb_set TIMER4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART3_IRQHandler
|
||||
.thumb_set UART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER5_DAC_UDR_IRQHandler
|
||||
.thumb_set TIMER5_DAC_UDR_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER6_IRQHandler
|
||||
.thumb_set TIMER6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel0_IRQHandler
|
||||
.thumb_set DMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART5_IRQHandler
|
||||
.thumb_set USART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS0_EP1_OUT_IRQHandler
|
||||
.thumb_set USBHS0_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS0_EP1_IN_IRQHandler
|
||||
.thumb_set USBHS0_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS0_WKUP_IRQHandler
|
||||
.thumb_set USBHS0_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS0_IRQHandler
|
||||
.thumb_set USBHS0_IRQHandler,Default_Handler
|
||||
|
||||
.weak TRNG_IRQHandler
|
||||
.thumb_set TRNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART6_IRQHandler
|
||||
.thumb_set UART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak OSPI0_IRQHandler
|
||||
.thumb_set OSPI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX_OVR_IRQHandler
|
||||
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDF_INT0_IRQHandler
|
||||
.thumb_set HPDF_INT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDF_INT1_IRQHandler
|
||||
.thumb_set HPDF_INT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDF_INT2_IRQHandler
|
||||
.thumb_set HPDF_INT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDF_INT3_IRQHandler
|
||||
.thumb_set HPDF_INT3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER14_IRQHandler
|
||||
.thumb_set TIMER14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER15_IRQHandler
|
||||
.thumb_set TIMER15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER16_IRQHandler
|
||||
.thumb_set TIMER16_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDMA_IRQHandler
|
||||
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC2_IRQHandler
|
||||
.thumb_set ADC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak CMP0_1_IRQHandler
|
||||
.thumb_set CMP0_1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CTC_IRQHandler
|
||||
.thumb_set CTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RAMECCMU_IRQHandler
|
||||
.thumb_set RAMECCMU_IRQHandler,Default_Handler
|
||||
|
||||
.weak OSPI1_IRQHandler
|
||||
.thumb_set OSPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FAC_IRQHandler
|
||||
.thumb_set FAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMU_IRQHandler
|
||||
.thumb_set TMU_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER22_IRQHandler
|
||||
.thumb_set TIMER22_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER23_IRQHandler
|
||||
.thumb_set TIMER23_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER40_IRQHandler
|
||||
.thumb_set TIMER40_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER41_IRQHandler
|
||||
.thumb_set TIMER41_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER42_IRQHandler
|
||||
.thumb_set TIMER42_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER43_IRQHandler
|
||||
.thumb_set TIMER43_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER44_IRQHandler
|
||||
.thumb_set TIMER44_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER50_IRQHandler
|
||||
.thumb_set TIMER50_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER51_IRQHandler
|
||||
.thumb_set TIMER51_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS1_EP1_OUT_IRQHandler
|
||||
.thumb_set USBHS1_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS1_EP1_IN_IRQHandler
|
||||
.thumb_set USBHS1_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS1_WKUP_IRQHandler
|
||||
.thumb_set USBHS1_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS1_IRQHandler
|
||||
.thumb_set USBHS1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_WKUP_IRQHandler
|
||||
.thumb_set CAN0_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_Message_IRQHandler
|
||||
.thumb_set CAN0_Message_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_Busoff_IRQHandler
|
||||
.thumb_set CAN0_Busoff_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_Error_IRQHandler
|
||||
.thumb_set CAN0_Error_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_FastError_IRQHandler
|
||||
.thumb_set CAN0_FastError_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_TEC_IRQHandler
|
||||
.thumb_set CAN0_TEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_REC_IRQHandler
|
||||
.thumb_set CAN0_REC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_WKUP_IRQHandler
|
||||
.thumb_set CAN1_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_Message_IRQHandler
|
||||
.thumb_set CAN1_Message_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_Busoff_IRQHandler
|
||||
.thumb_set CAN1_Busoff_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_Error_IRQHandler
|
||||
.thumb_set CAN1_Error_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_FastError_IRQHandler
|
||||
.thumb_set CAN1_FastError_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TEC_IRQHandler
|
||||
.thumb_set CAN1_TEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_REC_IRQHandler
|
||||
.thumb_set CAN1_REC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_WKUP_IRQHandler
|
||||
.thumb_set CAN2_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_Message_IRQHandler
|
||||
.thumb_set CAN2_Message_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_Busoff_IRQHandler
|
||||
.thumb_set CAN2_Busoff_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_Error_IRQHandler
|
||||
.thumb_set CAN2_Error_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_FastError_IRQHandler
|
||||
.thumb_set CAN2_FastError_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TEC_IRQHandler
|
||||
.thumb_set CAN2_TEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_REC_IRQHandler
|
||||
.thumb_set CAN2_REC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EFUSE_IRQHandler
|
||||
.thumb_set EFUSE_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_WKUP_IRQHandler
|
||||
.thumb_set I2C0_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_WKUP_IRQHandler
|
||||
.thumb_set I2C1_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_WKUP_IRQHandler
|
||||
.thumb_set I2C2_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_WKUP_IRQHandler
|
||||
.thumb_set I2C3_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPDTS_IRQHandler
|
||||
.thumb_set LPDTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPDTS_WKUP_IRQHandler
|
||||
.thumb_set LPDTS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_DEC_IRQHandler
|
||||
.thumb_set TIMER0_DEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_DEC_IRQHandler
|
||||
.thumb_set TIMER7_DEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER1_DEC_IRQHandler
|
||||
.thumb_set TIMER1_DEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER2_DEC_IRQHandler
|
||||
.thumb_set TIMER2_DEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER3_DEC_IRQHandler
|
||||
.thumb_set TIMER3_DEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER4_DEC_IRQHandler
|
||||
.thumb_set TIMER4_DEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER22_DEC_IRQHandler
|
||||
.thumb_set TIMER22_DEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER23_DEC_IRQHandler
|
||||
.thumb_set TIMER23_DEC_IRQHandler,Default_Handler
|
||||
@@ -0,0 +1,61 @@
|
||||
/*!
|
||||
\file gd32h75e_report_err.c
|
||||
\brief Reporting Error driver
|
||||
|
||||
\version 2025-01-24, V1.1.0, firmware for GD32H75E
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32h75e_err_report.h"
|
||||
|
||||
/* initialize the error report buffer and index */
|
||||
err_report_struct err_report_buffer[ERR_REPORT_BUFFER_SIZE];
|
||||
uint8_t err_report_buff_index = 0x00U;
|
||||
|
||||
/*!
|
||||
\brief reporting error in debug mode
|
||||
\param[in] moduleid: module ID where the error occurred
|
||||
\param[in] apiid: API ID associated with the error
|
||||
\param[in] errid: error ID indicating the specific error type
|
||||
\param[out] err_report_buffer: stores the id of the error type
|
||||
\retval none
|
||||
*/
|
||||
void fw_debug_report_err(uint16_t moduleid, uint16_t apiid, uint8_t errid)
|
||||
{
|
||||
err_report_struct *debug_report_err_buffer;
|
||||
|
||||
if(err_report_buff_index < ERR_REPORT_BUFFER_SIZE) {
|
||||
debug_report_err_buffer = &err_report_buffer[err_report_buff_index++];
|
||||
debug_report_err_buffer->moduleid = moduleid;
|
||||
debug_report_err_buffer->apiid = apiid;
|
||||
debug_report_err_buffer->errid = errid;
|
||||
} else {
|
||||
/* illegal parameters */
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,877 @@
|
||||
/*!
|
||||
\file system_gd32h75e.c
|
||||
\brief CMSIS Cortex-M7 Device Peripheral Access Layer Source File for
|
||||
gd32h75e Device Series
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#include "gd32h75e.h"
|
||||
|
||||
/* system frequency define */
|
||||
#define __IRC64M (IRC64M_VALUE) /* internal 64 MHz RC oscillator frequency */
|
||||
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
|
||||
#define __LPIRC4M (LPIRC4M_VALUE) /* low power internal 4 MHz RC oscillator frequency */
|
||||
#define __SYS_OSC_CLK (__IRC64M) /* main oscillator frequency */
|
||||
|
||||
#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */
|
||||
#define RCU_APB4EN_SYSCFG (uint32_t)0x01 /* enable SYSCFG clk */
|
||||
|
||||
/* select a system clock by uncommenting the following line */
|
||||
/* use IRC64M */
|
||||
//#define __SYSTEM_CLOCK_IRC64M (__IRC64M)
|
||||
//#define __SYSTEM_CLOCK_480M_PLL0_IRC64M (uint32_t)(480000000)
|
||||
//#define __SYSTEM_CLOCK_600M_PLL0_IRC64M (uint32_t)(600000000)
|
||||
|
||||
/* use LPIRC4M */
|
||||
//#define __SYSTEM_CLOCK_LPIRC4M (__LPIRC4M)
|
||||
|
||||
/* use HXTAL(CK_HXTAL = 25M) */
|
||||
//#define __SYSTEM_CLOCK_HXTAL (__HXTAL)
|
||||
//#define __SYSTEM_CLOCK_200M_PLL0_HXTAL (uint32_t)(200000000)
|
||||
//#define __SYSTEM_CLOCK_400M_PLL0_HXTAL (uint32_t)(400000000)
|
||||
//#define __SYSTEM_CLOCK_480M_PLL0_HXTAL (uint32_t)(480000000)
|
||||
#define __SYSTEM_CLOCK_600M_PLL0_HXTAL (uint32_t)(600000000)
|
||||
|
||||
/*
|
||||
Note: the power mode need to match the mcu selection and external power supply circuit.
|
||||
|
||||
according to the selected mcu and external power supply circuit to uncomment
|
||||
the following macro SEL_PMU_SMPS_MODE.
|
||||
*/
|
||||
//#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY
|
||||
//#define SEL_PMU_SMPS_MODE PMU_DIRECT_SMPS_SUPPLY
|
||||
//#define SEL_PMU_SMPS_MODE PMU_BYPASS
|
||||
|
||||
#define SEL_IRC64MDIV 0x00U
|
||||
#define SEL_HXTAL 0x01U
|
||||
#define SEL_LPIRC4M 0x02U
|
||||
#define SEL_PLL0P 0x03U
|
||||
|
||||
#define PLL0PSC_REG_OFFSET 0U
|
||||
#define PLL0N_REG_OFFSET 6U
|
||||
#define PLL0P_REG_OFFSET 16U
|
||||
#define PLL0Q_REG_OFFSET 0U
|
||||
#define PLL0R_REG_OFFSET 24U
|
||||
|
||||
/* set the system clock frequency and declare the system clock configuration function */
|
||||
#ifdef __SYSTEM_CLOCK_IRC64M
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC64M;
|
||||
static void system_clock_64m_irc64m(void);
|
||||
#elif defined (__SYSTEM_CLOCK_480M_PLL0_IRC64M)
|
||||
#define PLL0PSC 16U
|
||||
#define PLL0N (120U - 1U)
|
||||
#define PLL0P (1U - 1U)
|
||||
#define PLL0Q (2U - 1U)
|
||||
#define PLL0R (2U - 1U)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_480M_PLL0_IRC64M;
|
||||
static void system_clock_480m_irc64m(void);
|
||||
#elif defined (__SYSTEM_CLOCK_600M_PLL0_IRC64M)
|
||||
#define PLL0PSC 16U
|
||||
#define PLL0N (150U - 1U)
|
||||
#define PLL0P (1U - 1U)
|
||||
#define PLL0Q (2U - 1U)
|
||||
#define PLL0R (2U - 1U)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_600M_PLL0_IRC64M;
|
||||
static void system_clock_600m_irc64m(void);
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_LPIRC4M)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_LPIRC4M;
|
||||
static void system_clock_4m_lpirc4m(void);
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
|
||||
static void system_clock_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL0_HXTAL)
|
||||
#define PLL0PSC 5U
|
||||
#define PLL0N (40U - 1U)
|
||||
#define PLL0P (1U - 1U)
|
||||
#define PLL0Q (2U - 1U)
|
||||
#define PLL0R (2U - 1U)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL0_HXTAL;
|
||||
static void system_clock_200m_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_400M_PLL0_HXTAL)
|
||||
#define PLL0PSC 5U
|
||||
#define PLL0N (80U - 1U)
|
||||
#define PLL0P (1U - 1U)
|
||||
#define PLL0Q (2U - 1U)
|
||||
#define PLL0R (2U - 1U)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_400M_PLL0_HXTAL;
|
||||
static void system_clock_400m_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_480M_PLL0_HXTAL)
|
||||
#define PLL0PSC 5U
|
||||
#define PLL0N (96U - 1U)
|
||||
#define PLL0P (1U - 1U)
|
||||
#define PLL0Q (2U - 1U)
|
||||
#define PLL0R (2U - 1U)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_480M_PLL0_HXTAL;
|
||||
static void system_clock_480m_hxtal(void);
|
||||
#elif defined (__SYSTEM_CLOCK_600M_PLL0_HXTAL)
|
||||
#define PLL0PSC 5U
|
||||
#define PLL0N (120U - 1U)
|
||||
#define PLL0P (1U - 1U)
|
||||
#define PLL0Q (2U - 1U)
|
||||
#define PLL0R (2U - 1U)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_600M_PLL0_HXTAL;
|
||||
static void system_clock_600m_hxtal(void);
|
||||
#endif /* __SYSTEM_CLOCK_IRC64M */
|
||||
|
||||
/* configure the system clock */
|
||||
static void system_clock_config(void);
|
||||
|
||||
/*!
|
||||
\brief setup the microcontroller system, initialize the system
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings */
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1U)
|
||||
/* set CP10 and CP11 Full Access */
|
||||
SCB->CPACR |= (uint32_t)((0x03U << 10U * 2U) | (0x03U << 11U * 2U));
|
||||
#endif
|
||||
/* enable IRC64M */
|
||||
RCU_CTL |= RCU_CTL_IRC64MEN;
|
||||
while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
|
||||
}
|
||||
|
||||
/* no TCM wait state */
|
||||
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
|
||||
SYSCFG_SRAMCFG1 &= ~SYSCFG_SRAMCFG1_TCM_WAITSTATE;
|
||||
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
|
||||
/* reset RCU */
|
||||
/* reset HXTALEN, CKMEN, PLL0EN, PLL1EN, PLL2EN, PLLUSB0 and PLLUSB1 bits */
|
||||
RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLL0EN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_HXTALBPS);
|
||||
RCU_ADDCTL1 &= ~(RCU_ADDCTL1_PLLUSBHS0EN | RCU_ADDCTL1_PLLUSBHS1EN | RCU_ADDCTL1_LPIRC4MEN);
|
||||
/* reset CFG0, CFG1, CFG2, CFG3 registers */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_APB3PSC | RCU_CFG0_APB4PSC | RCU_CFG0_AHBPSC |
|
||||
RCU_CFG0_I2C0SEL | RCU_CFG0_SCS | RCU_CFG0_RTCDIV);
|
||||
RCU_CFG1 &= ~(RCU_CFG1_HPDFSEL | RCU_CFG1_TIMERSEL | RCU_CFG1_PERSEL |
|
||||
RCU_CFG1_USART0SEL | RCU_CFG1_USART1SEL | RCU_CFG1_USART2SEL | RCU_CFG1_USART5SEL | RCU_CFG1_PLL2RDIV);
|
||||
RCU_CFG2 &= ~(RCU_CFG2_HPDFASEL | RCU_CFG2_CKOUT0SEL | RCU_CFG2_CKOUT1SEL | RCU_CFG2_CKOUT0DIV | RCU_CFG2_CKOUT1DIV);
|
||||
RCU_CFG3 &= ~(RCU_CFG3_ADC01SEL | RCU_CFG3_ADC2SEL
|
||||
| RCU_CFG3_I2C3SEL | RCU_CFG3_I2C2SEL | RCU_CFG3_I2C1SEL);
|
||||
RCU_CFG4 &= ~(RCU_CFG4_EXMCSEL);
|
||||
RCU_CFG5 &= ~(RCU_CFG5_SPI0SEL | RCU_CFG5_SPI1SEL | RCU_CFG5_SPI2SEL |
|
||||
RCU_CFG5_SPI3SEL | RCU_CFG5_SPI4SEL | RCU_CFG5_SPI5SEL);
|
||||
/* disable all interrupts */
|
||||
RCU_INT = 0x14FF0000U;
|
||||
RCU_ADDINT = 0x00700000U;
|
||||
/* reset all PLL0 parameter */
|
||||
RCU_PLL0 = 0x01002020U;
|
||||
RCU_PLL1 = 0x01012020U;
|
||||
RCU_PLL2 = 0x01012020U;
|
||||
RCU_PLLALL = 0x00000000U;
|
||||
RCU_PLLADDCTL = 0x00010101U;
|
||||
RCU_PLLUSBCFG = 0x00000000U;
|
||||
RCU_PLL0FRA = 0x00000000U;
|
||||
RCU_PLL1FRA = 0x00000000U;
|
||||
RCU_PLL2FRA = 0x00000000U;
|
||||
|
||||
#if defined (SEL_PMU_SMPS_MODE)
|
||||
/* power supply config */
|
||||
pmu_smps_ldo_supply_config(SEL_PMU_SMPS_MODE);
|
||||
#endif
|
||||
|
||||
/* configure system clock */
|
||||
system_clock_config();
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
nvic_vector_table_set(NVIC_VECTTAB_RAM, VECT_TAB_OFFSET);
|
||||
#else
|
||||
nvic_vector_table_set(NVIC_VECTTAB_FLASH, VECT_TAB_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the system clock
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_config(void)
|
||||
{
|
||||
#ifdef __SYSTEM_CLOCK_IRC64M
|
||||
system_clock_64m_irc64m();
|
||||
#elif defined (__SYSTEM_CLOCK_480M_PLL0_IRC64M)
|
||||
system_clock_480m_irc64m();
|
||||
#elif defined (__SYSTEM_CLOCK_600M_PLL0_IRC64M)
|
||||
system_clock_600m_irc64m();
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_LPIRC4M)
|
||||
system_clock_4m_lpirc4m();
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_HXTAL)
|
||||
system_clock_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL0_HXTAL)
|
||||
system_clock_200m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_400M_PLL0_HXTAL)
|
||||
system_clock_400m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_480M_PLL0_HXTAL)
|
||||
system_clock_480m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_600M_PLL0_HXTAL)
|
||||
system_clock_600m_hxtal();
|
||||
#endif /* __SYSTEM_CLOCK_IRC64M */
|
||||
}
|
||||
|
||||
#ifdef __SYSTEM_CLOCK_IRC64M
|
||||
/*!
|
||||
\brief configure the system clock to 64M by IRC64M
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_64m_irc64m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC64M */
|
||||
RCU_CTL |= RCU_CTL_IRC64MEN;
|
||||
|
||||
/* wait until IRC64M is stable or the startup time is longer than IRC64M_STARTUP_TIMEOUT */
|
||||
do {
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC64MSTB);
|
||||
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* AHB = SYSCLK / 1 */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB4 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB4_CKAHB_DIV1;
|
||||
/* APB3 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB3_CKAHB_DIV1;
|
||||
/* APB2 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
|
||||
/* configure IRC64M div */
|
||||
RCU_ADDCTL1 &= ~(RCU_ADDCTL1_IRC64MDIV);
|
||||
RCU_ADDCTL1 |= RCU_IRC64M_DIV1;
|
||||
|
||||
/* select IRC64M as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_IRC64MDIV;
|
||||
|
||||
/* wait until IRC64M is selected as system clock */
|
||||
while(RCU_SCSS_IRC64MDIV != (RCU_CFG0 & RCU_CFG0_SCSS)) {
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_480M_PLL0_IRC64M)
|
||||
/*!
|
||||
\brief configure the system clock to 480M by PLL0 which selects IRC64M as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_480m_irc64m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC64M */
|
||||
RCU_CTL |= RCU_CTL_IRC64MEN;
|
||||
|
||||
/* wait until IRC64M is stable or the startup time is longer than IRC64M_STARTUP_TIMEOUT */
|
||||
do {
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC64MSTB);
|
||||
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* insert TCM wait state at 480MHz */
|
||||
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
|
||||
SYSCFG_SRAMCFG1 |= SYSCFG_SRAMCFG1_TCM_WAITSTATE;
|
||||
|
||||
/* IRC64M is already stable */
|
||||
/* AHB = SYSCLK / 2 */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2;
|
||||
/* APB4 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
|
||||
/* APB3 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
|
||||
/* APB2 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* PLL0 select IRC64MDIV, config IRC64MDIV as IRC64M, PLL0 input and output range */
|
||||
RCU_ADDCTL1 &= ~(RCU_ADDCTL1_IRC64MDIV);
|
||||
RCU_ADDCTL1 |= RCU_IRC64M_DIV1;
|
||||
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
|
||||
RCU_PLLALL |= (RCU_PLLSRC_IRC64MDIV | RCU_PLL0RNG_4M_8M);
|
||||
|
||||
/* PLL0P = IRC64MDIV / 16 * 120 / 1 = 480 MHz */
|
||||
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
|
||||
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
|
||||
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
|
||||
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
|
||||
|
||||
/* enable PLL0P, PLL0Q, PLL0R */
|
||||
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
|
||||
|
||||
/* enable PLL0 */
|
||||
RCU_CTL |= RCU_CTL_PLL0EN;
|
||||
|
||||
/* wait until PLL0 is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
|
||||
}
|
||||
|
||||
/* select PLL0 as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
|
||||
|
||||
/* wait until PLL0 is selected as system clock */
|
||||
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_600M_PLL0_IRC64M)
|
||||
/*!
|
||||
\brief configure the system clock to 600M by PLL0 which selects IRC64M as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_600m_irc64m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable IRC64M */
|
||||
RCU_CTL |= RCU_CTL_IRC64MEN;
|
||||
|
||||
/* wait until IRC64M is stable or the startup time is longer than IRC64M_STARTUP_TIMEOUT */
|
||||
do {
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_IRC64MSTB);
|
||||
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* insert TCM wait state at 600MHz */
|
||||
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
|
||||
SYSCFG_SRAMCFG1 |= SYSCFG_SRAMCFG1_TCM_WAITSTATE;
|
||||
|
||||
/* IRC64M is already stable */
|
||||
/* AHB = SYSCLK / 2 */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2;
|
||||
/* APB4 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
|
||||
/* APB3 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
|
||||
/* APB2 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* PLL0 select IRC64MDIV, config IRC64MDIV as IRC64M, PLL0 input and output range */
|
||||
RCU_ADDCTL1 &= ~(RCU_ADDCTL1_IRC64MDIV);
|
||||
RCU_ADDCTL1 |= RCU_IRC64M_DIV1;
|
||||
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
|
||||
RCU_PLLALL |= (RCU_PLLSRC_IRC64MDIV | RCU_PLL0RNG_4M_8M);
|
||||
|
||||
/* PLL0P = IRC64MDIV / 16 * 150 / 1 = 600 MHz */
|
||||
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
|
||||
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
|
||||
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
|
||||
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
|
||||
|
||||
/* enable PLL0P, PLL0Q, PLL0R */
|
||||
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
|
||||
|
||||
/* enable PLL0 */
|
||||
RCU_CTL |= RCU_CTL_PLL0EN;
|
||||
|
||||
/* wait until PLL0 is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
|
||||
}
|
||||
|
||||
/* select PLL0 as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
|
||||
|
||||
/* wait until PLL0 is selected as system clock */
|
||||
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_LPIRC4M)
|
||||
/*!
|
||||
\brief configure the system clock to LPIRC4M
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_4m_lpirc4m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable LPIRC4M */
|
||||
RCU_ADDCTL1 |= RCU_ADDCTL1_LPIRC4MEN;
|
||||
|
||||
/* wait until LPIRC4M is stable or the startup time is longer than LPIRC4M_STARTUP_TIMEOUT */
|
||||
do {
|
||||
timeout++;
|
||||
stab_flag = (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB);
|
||||
} while((0U == stab_flag) && (LPIRC4M_STARTUP_TIMEOUT != timeout));
|
||||
/* if fail */
|
||||
if(0U == (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB)) {
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* LPIRC4M is stable */
|
||||
/* AHB = SYSCLK / 1*/
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB4 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB4_CKAHB_DIV1;
|
||||
/* APB3 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB3_CKAHB_DIV1;
|
||||
/* APB2 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
|
||||
/* select LPIRC4M as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_LPIRC4M;
|
||||
|
||||
/* wait until LPIRC4M is selected as system clock */
|
||||
while(RCU_SCSS_LPIRC4M != (RCU_CFG0 & RCU_CFG0_SCSS)) {
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to HXTAL
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do {
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK / 1*/
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB4 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB4_CKAHB_DIV1;
|
||||
/* APB3 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB3_CKAHB_DIV1;
|
||||
/* APB2 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
|
||||
/* select HXTAL as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
|
||||
|
||||
/* wait until HXTAL is selected as system clock */
|
||||
while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS)) {
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_200M_PLL0_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 200M by PLL0 which selects HXTAL as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_200m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do {
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK / 1 */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB4 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
|
||||
/* APB3 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
|
||||
/* APB2 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* PLL0 select HXTAL, configure PLL0 input and output range */
|
||||
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
|
||||
RCU_PLLALL |= (RCU_PLLSRC_HXTAL | RCU_PLLALL_PLL0VCOSEL | RCU_PLL0RNG_4M_8M);
|
||||
|
||||
/* PLL0P = HXTAL / 5 * 40 = 200 MHz */
|
||||
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
|
||||
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
|
||||
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
|
||||
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
|
||||
|
||||
/* enable PLL0P, PLL0Q, PLL0R */
|
||||
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
|
||||
|
||||
/* enable PLL0 */
|
||||
RCU_CTL |= RCU_CTL_PLL0EN;
|
||||
|
||||
/* wait until PLL0 is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
|
||||
}
|
||||
|
||||
/* select PLL0 as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
|
||||
|
||||
/* wait until PLL0 is selected as system clock */
|
||||
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_400M_PLL0_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 400M by PLL0 which selects HXTAL as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_400m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do {
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* insert TCM wait state at 400MHz */
|
||||
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
|
||||
SYSCFG_SRAMCFG1 |= SYSCFG_SRAMCFG1_TCM_WAITSTATE;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK / 1 */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2;
|
||||
/* APB4 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
|
||||
/* APB3 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
|
||||
/* APB2 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* PLL0 select HXTAL, configure PLL0 input and output range */
|
||||
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
|
||||
RCU_PLLALL |= (RCU_PLLSRC_HXTAL | RCU_PLLALL_PLL0VCOSEL | RCU_PLL0RNG_4M_8M);
|
||||
|
||||
/* PLL0P = HXTAL / 5 * 80 = 400 MHz */
|
||||
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
|
||||
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
|
||||
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
|
||||
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
|
||||
|
||||
/* enable PLL0P, PLL0Q, PLL0R */
|
||||
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL |= RCU_CTL_PLL0EN;
|
||||
|
||||
/* wait until PLL0 is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
|
||||
}
|
||||
|
||||
/* select PLL0 as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
|
||||
|
||||
/* wait until PLL0 is selected as system clock */
|
||||
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_480M_PLL0_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 480M by PLL0 which selects HXTAL as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_480m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do {
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* insert TCM wait state at 480MHz */
|
||||
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
|
||||
SYSCFG_SRAMCFG1 |= SYSCFG_SRAMCFG1_TCM_WAITSTATE;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK / 2 */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2;
|
||||
/* APB4 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
|
||||
/* APB3 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
|
||||
/* APB2 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* PLL select HXTAL, configure PLL input and output range */
|
||||
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
|
||||
RCU_PLLALL |= (RCU_PLLSRC_HXTAL | RCU_PLL0RNG_4M_8M);
|
||||
|
||||
/* PLL0P = HXTAL / 5 * 96 = 480 MHz */
|
||||
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
|
||||
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
|
||||
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
|
||||
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
|
||||
|
||||
/* enable PLL0P, PLL0Q, PLL0R */
|
||||
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
|
||||
|
||||
/* enable PLL0 */
|
||||
RCU_CTL |= RCU_CTL_PLL0EN;
|
||||
|
||||
/* wait until PLL0 is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
|
||||
}
|
||||
|
||||
/* select PLL0 as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
|
||||
|
||||
/* wait until PLL0 is selected as system clock */
|
||||
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_600M_PLL0_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 600M by PLL0 which selects HXTAL as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_600m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do {
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* insert TCM wait state at 600MHz */
|
||||
RCU_APB4EN |= RCU_APB4EN_SYSCFG;
|
||||
SYSCFG_SRAMCFG1 |= SYSCFG_SRAMCFG1_TCM_WAITSTATE;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK / 2 */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2;
|
||||
/* APB4 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB4_CKAHB_DIV2;
|
||||
/* APB3 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB3_CKAHB_DIV2;
|
||||
/* APB2 = AHB / 1 */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB / 2 */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||||
|
||||
/* PLL select HXTAL, configure PLL input and output range */
|
||||
RCU_PLLALL &= ~(RCU_PLLALL_PLLSEL | RCU_PLLALL_PLL0VCOSEL | RCU_PLLALL_PLL0RNG);
|
||||
RCU_PLLALL |= (RCU_PLLSRC_HXTAL | RCU_PLL0RNG_4M_8M);
|
||||
|
||||
/* PLL0P = HXTAL / 5 * 120 = 600 MHz */
|
||||
RCU_PLL0 &= ~(RCU_PLL0_PLL0N | RCU_PLL0_PLL0PSC | RCU_PLL0_PLL0P | RCU_PLL0_PLL0R | RCU_PLL0_PLLSTBSRC);
|
||||
RCU_PLL0 |= ((PLL0N << PLL0N_REG_OFFSET) | (PLL0PSC << PLL0PSC_REG_OFFSET) | (PLL0P << PLL0P_REG_OFFSET) | (PLL0R << PLL0R_REG_OFFSET));
|
||||
RCU_PLLADDCTL &= ~(RCU_PLLADDCTL_PLL0Q);
|
||||
RCU_PLLADDCTL |= (PLL0Q << PLL0Q_REG_OFFSET);
|
||||
|
||||
/* enable PLL0P, PLL0Q, PLL0R */
|
||||
RCU_PLLADDCTL |= RCU_PLLADDCTL_PLL0PEN | RCU_PLLADDCTL_PLL0QEN | RCU_PLLADDCTL_PLL0REN;
|
||||
|
||||
/* enable PLL0 */
|
||||
RCU_CTL |= RCU_CTL_PLL0EN;
|
||||
|
||||
/* wait until PLL0 is stable */
|
||||
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
|
||||
}
|
||||
|
||||
/* select PLL0 as system clock */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
|
||||
|
||||
/* wait until PLL0 is selected as system clock */
|
||||
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __SYSTEM_CLOCK_IRC64M */
|
||||
|
||||
/*!
|
||||
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t sws = 0U;
|
||||
uint32_t irc64div = 0U;
|
||||
uint32_t pllpsc = 0U, plln = 0U, pllp = 0U, pllsel = 0U;
|
||||
|
||||
sws = GET_BITS(RCU_CFG0, 2, 3);
|
||||
switch(sws) {
|
||||
/* IRC64M is selected as CK_SYS */
|
||||
case SEL_IRC64MDIV:
|
||||
irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17));
|
||||
SystemCoreClock = IRC64M_VALUE / irc64div;
|
||||
break;
|
||||
/* HXTAL is selected as CK_SYS */
|
||||
case SEL_LPIRC4M:
|
||||
SystemCoreClock = LPIRC4M_VALUE;
|
||||
break;
|
||||
/* HXTAL is selected as CK_SYS */
|
||||
case SEL_HXTAL:
|
||||
SystemCoreClock = HXTAL_VALUE;
|
||||
break;
|
||||
/* PLL0P is selected as CK_SYS */
|
||||
case SEL_PLL0P:
|
||||
/* get the value of PLL0PSC[0,5], PLL0N[6,14], PLL0P[16,22] */
|
||||
pllpsc = GET_BITS(RCU_PLL0, 0, 5);
|
||||
plln = GET_BITS(RCU_PLL0, 6, 14) + 1U;
|
||||
pllp = GET_BITS(RCU_PLL0, 16, 22) + 1U;
|
||||
|
||||
/* PLL clock source selection, HXTAL or IRC64M_VALUE or LPIRC4M_VALUE */
|
||||
pllsel = GET_BITS(RCU_PLLALL, 16, 17);
|
||||
if(0U == pllsel) {
|
||||
irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17));
|
||||
SystemCoreClock = (IRC64M_VALUE / irc64div / pllpsc) * plln / pllp;
|
||||
} else if(1U == pllsel) {
|
||||
SystemCoreClock = (LPIRC4M_VALUE / pllpsc) * plln / pllp;
|
||||
} else {
|
||||
SystemCoreClock = (HXTAL_VALUE / pllpsc) * plln / pllp;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
/* should not be here */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __FIRMWARE_VERSION_DEFINE
|
||||
/*!
|
||||
\brief get firmware version
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval firmware version
|
||||
*/
|
||||
uint32_t gd32h75e_firmware_version_get(void)
|
||||
{
|
||||
return __GD32H75E_STDPERIPH_VERSION;
|
||||
}
|
||||
#endif /* __FIRMWARE_VERSION_DEFINE */
|
||||
Reference in new issue
Block a user