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828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_adc.h
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/*!
\file gd32h75e_adc.h
\brief definitions for the ADC
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_ADC_H
#define GD32H75E_ADC_H
#include "gd32h75e.h"
/* ADC definitions */
#define ADC0 ADC_BASE /*!< ADC0 base address */
#define ADC1 (ADC_BASE + 0x00000400U) /*!< ADC1 base address */
#define ADC2 (ADC_BASE + 0x00000800U) /*!< ADC2 base address */
/* registers definitions */
#define ADC_STAT(adcx) REG32((adcx) + 0x00000000U) /*!< ADC status register */
#define ADC_CTL0(adcx) REG32((adcx) + 0x00000004U) /*!< ADC control register 0 */
#define ADC_CTL1(adcx) REG32((adcx) + 0x00000008U) /*!< ADC control register 1 */
#define ADC_IOFF0(adcx) REG32((adcx) + 0x0000000CU) /*!< ADC inserted channel data offset register 0 */
#define ADC_IOFF1(adcx) REG32((adcx) + 0x00000010U) /*!< ADC inserted channel data offset register 1 */
#define ADC_IOFF2(adcx) REG32((adcx) + 0x00000014U) /*!< ADC inserted channel data offset register 2 */
#define ADC_IOFF3(adcx) REG32((adcx) + 0x00000018U) /*!< ADC inserted channel data offset register 3 */
#define ADC_WDHT0(adcx) REG32((adcx) + 0x0000001CU) /*!< ADC watchdog high threshold register 0 */
#define ADC_WDLT0(adcx) REG32((adcx) + 0x00000020U) /*!< ADC watchdog low threshold register 0 */
#define ADC_RSQ0(adcx) REG32((adcx) + 0x00000024U) /*!< ADC routine sequence register 0 */
#define ADC_RSQ1(adcx) REG32((adcx) + 0x00000028U) /*!< ADC routine sequence register 1 */
#define ADC_RSQ2(adcx) REG32((adcx) + 0x0000002CU) /*!< ADC routine sequence register 2 */
#define ADC_RSQ3(adcx) REG32((adcx) + 0x00000030U) /*!< ADC routine sequence register 3 */
#define ADC_RSQ4(adcx) REG32((adcx) + 0x00000034U) /*!< ADC routine sequence register 4 */
#define ADC_RSQ5(adcx) REG32((adcx) + 0x00000038U) /*!< ADC routine sequence register 5 */
#define ADC_RSQ6(adcx) REG32((adcx) + 0x0000003CU) /*!< ADC routine sequence register 6 */
#define ADC_RSQ7(adcx) REG32((adcx) + 0x00000040U) /*!< ADC routine sequence register 7 */
#define ADC_RSQ8(adcx) REG32((adcx) + 0x00000044U) /*!< ADC routine sequence register 8 */
#define ADC_ISQ0(adcx) REG32((adcx) + 0x00000048U) /*!< ADC inserted sequence register 0 */
#define ADC_ISQ1(adcx) REG32((adcx) + 0x0000004CU) /*!< ADC inserted sequence register 1 */
#define ADC_ISQ2(adcx) REG32((adcx) + 0x00000050U) /*!< ADC inserted sequence register 2 */
#define ADC_IDATA0(adcx) REG32((adcx) + 0x00000054U) /*!< ADC inserted data register 0 */
#define ADC_IDATA1(adcx) REG32((adcx) + 0x00000058U) /*!< ADC inserted data register 1 */
#define ADC_IDATA2(adcx) REG32((adcx) + 0x0000005CU) /*!< ADC inserted data register 2 */
#define ADC_IDATA3(adcx) REG32((adcx) + 0x00000060U) /*!< ADC inserted data register 3 */
#define ADC_RDATA(adcx) REG32((adcx) + 0x00000064U) /*!< ADC routine data register */
#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x00000080U) /*!< ADC oversampling control register */
#define ADC_WD1SR(adcx) REG32((adcx) + 0x000000A0U) /*!< ADC watchdog 1 channel selection register */
#define ADC_WD2SR(adcx) REG32((adcx) + 0x000000A4U) /*!< ADC watchdog 2 channel selection register */
#define ADC_WDHT1(adcx) REG32((adcx) + 0x000000A8U) /*!< ADC watchdog high threshold register 1 */
#define ADC_WDLT1(adcx) REG32((adcx) + 0x000000ACU) /*!< ADC watchdog low threshold register 1 */
#define ADC_WDHT2(adcx) REG32((adcx) + 0x000000B0U) /*!< ADC watchdog high threshold register 2 */
#define ADC_WDLT2(adcx) REG32((adcx) + 0x000000B4U) /*!< ADC watchdog low threshold register 2 */
#define ADC_DIFCTL(adcx) REG32((adcx) + 0x000000B8U) /*!< ADC differential mode control register */
#define ADC_SSTAT REG32((ADC0) + 0x00000300U) /*!< ADC summary status register */
#define ADC_SYNCCTL(adcx) REG32((adcx) + 0x00000304U) /*!< ADC sync control register */
#define ADC_SYNCDATA0 REG32((ADC0) + 0x00000308U) /*!< ADC sync routine data register 0 */
#define ADC_SYNCDATA1 REG32((ADC0) + 0x0000030CU) /*!< ADC sync routine data register 1 */
/* bits definitions */
/* ADC_STAT */
#define ADC_STAT_WDE0 BIT(0) /*!< analog watchdog 0 event flag */
#define ADC_STAT_EOC BIT(1) /*!< end of sequence conversion flag */
#define ADC_STAT_EOIC BIT(2) /*!< end of inserted sequence conversion flag */
#define ADC_STAT_STIC BIT(3) /*!< start flag of inserted sequence */
#define ADC_STAT_STRC BIT(4) /*!< start flag of routine sequence */
#define ADC_STAT_ROVF BIT(5) /*!< routine data register overflow */
#define ADC_STAT_WDE1 BIT(30) /*!< analog watchdog 1 event flag */
#define ADC_STAT_WDE2 BIT(31) /*!< analog watchdog 2 event flag */
/* ADC_CTL0 */
#define ADC_CTL0_WD0CHSEL BITS(0,4) /*!< analog watchdog channel select */
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
#define ADC_CTL0_WDE0IE BIT(6) /*!< interrupt enable for WDE0 */
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for EOIC */
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
#define ADC_CTL0_WD0SC BIT(9) /*!< when in scan mode, analog watchdog 0 is effective on a single channel */
#define ADC_CTL0_ICA BIT(10) /*!< inserted sequence convert automatically */
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on routine channels */
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
#define ADC_CTL0_DISNUM BITS(13,15) /*!< number of conversions in discontinuous mode */
#define ADC_CTL0_IWD0EN BIT(22) /*!< inserted channel analog watchdog 0 enable */
#define ADC_CTL0_RWD0EN BIT(23) /*!< routine channel analog watchdog 0 enable */
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */
#define ADC_CTL0_WDE1IE BIT(30) /*!< interrupt enable for WDE1 */
#define ADC_CTL0_WDE2IE BIT(31) /*!< interrupt enable for WDE2 */
/* ADC_CTL1 */
#define ADC_CTL1_ADCON BIT(0) /*!< ADC on */
#define ADC_CTL1_CTN BIT(1) /*!< continuous mode */
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
#define ADC_CTL1_CALNUM BITS(4,6) /*!< ADC calibration times */
#define ADC_CTL1_DMA BIT(8) /*!< DMA request enable */
#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */
#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
#define ADC_CTL1_HPDFCFG BIT(12) /*!< HPDF mode configuration */
#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger mode for inserted channels */
#define ADC_CTL1_SWICST BIT(22) /*!< software start on inserted channel */
#define ADC_CTL1_TSVEN1 BIT(23) /*!< temperature sensor channel enable */
#define ADC_CTL1_INREFEN BIT(24) /*!< vrefint channel enable */
#define ADC_CTL1_VBATEN BIT(25) /*!< vbat channel enable */
#define ADC_CTL1_CALMOD BIT(27) /*!< ADC calibration mode */
#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger mode for routine channels */
#define ADC_CTL1_SWRCST BIT(30) /*!< software start on routine channel. */
#define ADC_CTL1_TSVEN2 BIT(31) /*!< high-precision temperature sensor channel enable */
/* ADC_IOFFx x=0..3 */
#define ADC_IOFFX_IOFF BITS(0,23) /*!< data offset for inserted channel x */
/* ADC_WDHT0 */
#define ADC_WDHT0_WDHT0 BITS(0,23) /*!< high threshold for analog watchdog 0 */
/* ADC_WDLT0 */
#define ADC_WDLT0_WDLT0 BITS(0,23) /*!< low threshold for analog watchdog 0 */
/* ADC_RSQx x=0..8 */
#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion channel number in the routine sequence */
#define ADC_RSQX_RSMPN BITS(5,14) /*!< nth conversion sample time in the routine sequence */
#define ADC_RSQ0_RL BITS(20,23) /*!< routine sequence length */
/* ADC_ISQx x=0..2 */
#define ADC_ISQX_ISQN BITS(0,4) /*!< nth conversion channel number in the inserted sequence */
#define ADC_ISQX_ISMPN BITS(5,14) /*!< nth conversion sample time in the inserted sequence */
#define ADC_ISQ0_IL BITS(20,21) /*!< inserted sequence length */
/* ADC_IDATAx x=0..3 */
#define ADC_IDATAX_IDATAN BITS(0,31) /*!< Inserted number n conversion data */
/* ADC_RDATA */
#define ADC_RDATA_RDATA BITS(0,31) /*!< routine channel data */
/* ADC_OVSAMPCTL */
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
#define ADC_OVSAMPCTL_OVSR BITS(16,25) /*!< oversampling ratio */
/* ADC_WD1SR */
#define ADC_WD1SR_AWD1CS BITS(0,21) /*!< analog watchdog 1 channel selection */
/* ADC_WD2SR */
#define ADC_WD2SR_AWD2CS BITS(0,21) /*!< analog watchdog 2 channel selection */
/* ADC_WDHT1 */
#define ADC_WDHT1_WDHT1 BITS(0,23) /*!< high threshold for analog watchdog 1 */
/* ADC_WDHT1 */
#define ADC_WDLT1_WDLT1 BITS(0,23) /*!< low threshold for analog watchdog 1 */
/* ADC_WDHT2 */
#define ADC_WDHT2_WDHT2 BITS(0,23) /*!< high threshold for analog watchdog 2 */
/* ADC_WDHT2 */
#define ADC_WDLT2_WDLT2 BITS(0,23) /*!< low threshold for analog watchdog 2 */
/* ADC_DIFCTL */
#define ADC_DIFCTL_DIFCTL BITS(0,21) /*!< Differential mode for channel 0..21 */
/* ADC_SSTAT */
#define ADC_SSTAT_ADC0_WDE0 BIT(0) /*!< the bit is mirror image of the WDE0 bit of ADC0 */
#define ADC_SSTAT_ADC0_WDE1 BIT(1) /*!< the bit is mirror image of the WDE1 bit of ADC0 */
#define ADC_SSTAT_ADC0_WDE2 BIT(2) /*!< the bit is mirror image of the WDE2 bit of ADC0 */
#define ADC_SSTAT_ADC0_EOC BIT(3) /*!< the bit is mirror image of the EOC bit of ADC0 */
#define ADC_SSTAT_ADC0_EOIC BIT(4) /*!< the bit is mirror image of the EOIC bit of ADC0 */
#define ADC_SSTAT_ADC0_STIC BIT(5) /*!< the bit is mirror image of the STIC bit of ADC0 */
#define ADC_SSTAT_ADC0_STRC BIT(6) /*!< the bit is mirror image of the STRC bit of ADC0 */
#define ADC_SSTAT_ADC0_ROVF BIT(7) /*!< the bit is mirror image of the ROVF bit of ADC0 */
#define ADC_SSTAT_ADC1_WDE0 BIT(8) /*!< the bit is mirror image of the WDE0 bit of ADC1 */
#define ADC_SSTAT_ADC1_WDE1 BIT(9) /*!< the bit is mirror image of the WDE1 bit of ADC1 */
#define ADC_SSTAT_ADC1_WDE2 BIT(10) /*!< the bit is mirror image of the WDE2 bit of ADC1 */
#define ADC_SSTAT_ADC1_EOC BIT(11) /*!< the bit is mirror image of the EOC bit of ADC1 */
#define ADC_SSTAT_ADC1_EOIC BIT(12) /*!< the bit is mirror image of the EOIC bit of ADC1 */
#define ADC_SSTAT_ADC1_STIC BIT(13) /*!< the bit is mirror image of the STIC bit of ADC1 */
#define ADC_SSTAT_ADC1_STRC BIT(14) /*!< the bit is mirror image of the STRC bit of ADC1 */
#define ADC_SSTAT_ADC1_ROVF BIT(15) /*!< the bit is mirror image of the ROVF bit of ADC1 */
#define ADC_SSTAT_ADC2_WDE0 BIT(16) /*!< the bit is mirror image of the WDE0 bit of ADC2 */
#define ADC_SSTAT_ADC2_WDE1 BIT(17) /*!< the bit is mirror image of the WDE1 bit of ADC2 */
#define ADC_SSTAT_ADC2_WDE2 BIT(18) /*!< the bit is mirror image of the WDE2 bit of ADC2 */
#define ADC_SSTAT_ADC2_EOC BIT(19) /*!< the bit is mirror image of the EOC bit of ADC2 */
#define ADC_SSTAT_ADC2_EOIC BIT(20) /*!< the bit is mirror image of the EOIC bit of ADC2 */
#define ADC_SSTAT_ADC2_STIC BIT(21) /*!< the bit is mirror image of the STIC bit of ADC2 */
#define ADC_SSTAT_ADC2_STRC BIT(22) /*!< the bit is mirror image of the STRC bit of ADC2 */
#define ADC_SSTAT_ADC2_ROVF BIT(23) /*!< the bit is mirror image of the ROVF bit of ADC2 */
/* ADC_SYNCCTL */
#define ADC_SYNCCTL_SYNCM BITS(0,3) /*!< ADC sync mode */
#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC sync delay */
#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC sync DMA disable mode */
#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC sync DMA mode selection */
#define ADC_SYNCCTL_ADCSCK BITS(16,19) /*!< ADC sync clock mode */
#define ADC_SYNCCTL_ADCCK BITS(20,23) /*!< ADC clock prescaler */
/* ADC_SYNCDATA0 */
#define ADC_SYNCDATA0_SYNCDATA0 BITS(0,15) /*!< ADC0 routine data in ADC synchronization mode */
#define ADC_SYNCDATA0_SYNCDATA1 BITS(16,31) /*!< ADC1 routine data in ADC synchronization mode */
/* constants definitions */
/* ADC status flag */
#define ADC_FLAG_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event flag */
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion flag */
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion flag */
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted sequence */
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of routine sequence */
#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */
#define ADC_FLAG_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event flag */
#define ADC_FLAG_WDE2 ADC_STAT_WDE2 /*!< analog watchdog 2 event flag */
/* ADC interrupt */
#define ADC_INT_WDE0 ADC_CTL0_WDE0IE /*!< interrupt enable for WDE0 */
#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< interrupt enable for EOC */
#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< interrupt enable for EOIC */
#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< interrupt enable for ROVF */
#define ADC_INT_WDE1 ADC_CTL0_WDE1IE /*!< interrupt enable for WDE1 */
#define ADC_INT_WDE2 ADC_CTL0_WDE2IE /*!< interrupt enable for WDE2 */
/* ADC interrupt flag */
#define ADC_INT_FLAG_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event interrupt flag */
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion interrupt flag */
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion interrupt flag */
#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow interrupt flag */
#define ADC_INT_FLAG_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event interrupt flag */
#define ADC_INT_FLAG_WDE2 ADC_STAT_WDE2 /*!< analog watchdog 2 event interrupt flag */
/* number of conversions in discontinuous mode */
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to ADC_CTL0_DISNUM bit field */
/* ADC special function definitions */
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted sequence convert automatically */
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
/* ADC calibration mode */
#define ADC_CALIBRATION_OFFSET_MISMATCH ((uint32_t)0x00000000U) /*!< ADC calibration offset and mismatch mode */
#define ADC_CALIBRATION_OFFSET ADC_CTL1_CALMOD /*!< ADC calibration mode */
/* ADC calibration times */
#define CTL1_CALNUM(regval) (BITS(4,6) & ((uint32_t)(regval) << 4U)) /*!< write value to ADC_CTL1_CLBNUM bit field */
#define ADC_CALIBRATION_NUM1 CTL1_CALNUM(0) /*!< ADC calibration 1 time */
#define ADC_CALIBRATION_NUM2 CTL1_CALNUM(1) /*!< ADC calibration 2 times */
#define ADC_CALIBRATION_NUM4 CTL1_CALNUM(2) /*!< ADC calibration 4 times */
#define ADC_CALIBRATION_NUM8 CTL1_CALNUM(3) /*!< ADC calibration 8 times */
#define ADC_CALIBRATION_NUM16 CTL1_CALNUM(4) /*!< ADC calibration 16 times */
#define ADC_CALIBRATION_NUM32 CTL1_CALNUM(5) /*!< ADC calibration 32 times */
/* ADC data alignment */
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
/* end of conversion mode */
#define ADC_EOC_SET_SEQUENCE ((uint32_t)0x00000000U) /*!< only at the end of a sequence of routine conversions, the EOC bit is set */
#define ADC_EOC_SET_CONVERSION ADC_CTL1_EOCM /*!< at the end of each routine conversion, the EOC bit is set */
/* ADC internal channel definitions */
#define ADC_CHANNEL_INTERNAL_TEMPSENSOR ADC_CTL1_TSVEN1 /*!< temperature sensor channel */
#define ADC_CHANNEL_INTERNAL_VREFINT ADC_CTL1_INREFEN /*!< vrefint channel */
#define ADC_CHANNEL_INTERNAL_VBAT ADC_CTL1_VBATEN /*!< vbat channel */
#define ADC_CHANNEL_INTERNAL_HP_TEMPSENSOR ADC_CTL1_TSVEN2 /*!< high-precision temperature sensor channel */
/* ADC data offset for inserted channel x */
#define IOFFX_IOFF(regval) (BITS(0,23) & ((uint32_t)(regval) << 0U)) /*!< write value to ADC_IOFFX_IOFF bit field */
/* ADC high threshold for analog watchdog 0 */
#define WDHT0_WDHT0(regval) (BITS(0,23) & ((uint32_t)(regval) << 0U)) /*!< write value to ADC_WDHT0_WDHT0 bit field */
/* ADC low threshold for analog watchdog 0 */
#define WDLT0_WDLT0(regval) (BITS(0,23) & ((uint32_t)(regval) << 0U)) /*!< write value to ADC_WDLT0_WDLT0 bit field */
/* ADC high threshold for analog watchdog 1 */
#define WDHT1_WDHT1(regval) (BITS(0,23) & ((uint32_t)(regval) << 0U)) /*!< write value to ADC_WDHT1_WDHT1 bit field */
/* ADC low threshold for analog watchdog 1 */
#define WDLT1_WDLT1(regval) (BITS(0,23) & ((uint32_t)(regval) << 0U)) /*!< write value to ADC_WDLT1_WDLT1 bit field */
/* ADC high threshold for analog watchdog 2 */
#define WDHT2_WDHT2(regval) (BITS(0,23) & ((uint32_t)(regval) << 0U)) /*!< write value to ADC_WDHT2_WDHT2 bit field */
/* ADC low threshold for analog watchdog 2 */
#define WDLT2_WDLT2(regval) (BITS(0,23) & ((uint32_t)(regval) << 0U)) /*!< write value to ADC_WDLT2_WDLT2 bit field */
/* ADC sequence sample time */
#define SQX_SMP(regval) (BITS(5,14) & ((uint32_t)(regval) << 5U)) /*!< write value to RSQX_SMPn or ISQX_SMPn bit field */
/* ADC routine sequence length */
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20U)) /*!< write value to ADC_RSQ0_RL bit field */
/* ADC inserted sequence length */
#define ISQ0_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20U)) /*!< write value to ADC_ISQ0_IL bit field */
/* ADC resolution */
#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24U)) /*!< write value to ADC_CTL0_DRES bit field */
#define ADC_RESOLUTION_14B ((uint8_t)0x00U) /*!< 14-bit ADC resolution */
#define ADC_RESOLUTION_12B ((uint8_t)0x01U) /*!< 12-bit ADC resolution */
#define ADC_RESOLUTION_10B ((uint8_t)0x02U) /*!< 10-bit ADC resolution */
#define ADC_RESOLUTION_8B ((uint8_t)0x03U) /*!< 8-bit ADC resolution */
#define ADC_RESOLUTION_6B ((uint8_t)0x04U) /*!< 6-bit ADC resolution */
/* oversampling shift */
#define OVSCR_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5U)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */
#define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_3B OVSCR_OVSS(3) /*!< 3-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_4B OVSCR_OVSS(4) /*!< 4-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_5B OVSCR_OVSS(5) /*!< 5-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_6B OVSCR_OVSS(6) /*!< 6-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_7B OVSCR_OVSS(7) /*!< 7-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_9B OVSCR_OVSS(9) /*!< 9-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_10B OVSCR_OVSS(10) /*!< 10-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_11B OVSCR_OVSS(11) /*!< 11-bit oversampling shift */
/* oversampling ratio */
#define OVSCR_OVSR(regval) (BITS(16,25) & ((uint32_t)(regval) << 16U)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */
/* triggered oversampling */
#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */
#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */
/* configure the ADC clock */
#define SYNCCTL_ADCSCK(regval) (BITS(16,19) & ((uint32_t)(regval) << 16U)) /*!< write value to ADC_SYNCCTL_ADCSCK bit field */
#define SYNCCTL_ADCCK(regval) (BITS(20,23) & ((uint32_t)(regval) << 20U)) /*!< write value to ADC_SYNCCTL_ADCCK bit field */
#define ADC_CLK_SYNC_HCLK_DIV2 (SYNCCTL_ADCCK(0) | SYNCCTL_ADCSCK(8)) /*!< ADC sync clock mode HCLK div2 */
#define ADC_CLK_SYNC_HCLK_DIV4 (SYNCCTL_ADCCK(0) | SYNCCTL_ADCSCK(9)) /*!< ADC sync clock mode HCLK div4 */
#define ADC_CLK_SYNC_HCLK_DIV6 (SYNCCTL_ADCCK(0) | SYNCCTL_ADCSCK(10)) /*!< ADC sync clock mode HCLK div6 */
#define ADC_CLK_SYNC_HCLK_DIV8 (SYNCCTL_ADCCK(0) | SYNCCTL_ADCSCK(11)) /*!< ADC sync clock mode HCLK div8 */
#define ADC_CLK_SYNC_HCLK_DIV10 (SYNCCTL_ADCCK(0) | SYNCCTL_ADCSCK(12)) /*!< ADC sync clock mode HCLK div10 */
#define ADC_CLK_SYNC_HCLK_DIV12 (SYNCCTL_ADCCK(0) | SYNCCTL_ADCSCK(13)) /*!< ADC sync clock mode HCLK div12 */
#define ADC_CLK_SYNC_HCLK_DIV14 (SYNCCTL_ADCCK(0) | SYNCCTL_ADCSCK(14)) /*!< ADC sync clock mode HCLK div14 */
#define ADC_CLK_SYNC_HCLK_DIV16 (SYNCCTL_ADCCK(0) | SYNCCTL_ADCSCK(15)) /*!< ADC sync clock mode HCLK div16 */
#define ADC_CLK_ASYNC_DIV1 (SYNCCTL_ADCCK(0) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div1 */
#define ADC_CLK_ASYNC_DIV2 (SYNCCTL_ADCCK(1) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div2 */
#define ADC_CLK_ASYNC_DIV4 (SYNCCTL_ADCCK(2) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div4 */
#define ADC_CLK_ASYNC_DIV6 (SYNCCTL_ADCCK(3) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div6 */
#define ADC_CLK_ASYNC_DIV8 (SYNCCTL_ADCCK(4) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div8 */
#define ADC_CLK_ASYNC_DIV10 (SYNCCTL_ADCCK(5) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div10 */
#define ADC_CLK_ASYNC_DIV12 (SYNCCTL_ADCCK(6) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div12 */
#define ADC_CLK_ASYNC_DIV16 (SYNCCTL_ADCCK(7) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div16 */
#define ADC_CLK_ASYNC_DIV32 (SYNCCTL_ADCCK(8) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div32 */
#define ADC_CLK_ASYNC_DIV64 (SYNCCTL_ADCCK(9) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div64 */
#define ADC_CLK_ASYNC_DIV128 (SYNCCTL_ADCCK(10) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div128 */
#define ADC_CLK_ASYNC_DIV256 (SYNCCTL_ADCCK(11) | SYNCCTL_ADCSCK(0)) /*!< ADC async clock mode div256 */
/* ADC sync DMA mode selection */
#define SYNCCTL_SYNCDMA(regval) (BITS(14,15) & ((uint32_t)(regval) << 14U)) /*!< write value to ADC_SYNCCTL_SYNCDMA bit field */
#define ADC_SYNC_DMA_DISABLE SYNCCTL_SYNCDMA(0) /*!< ADC sync DMA disabled */
#define ADC_SYNC_DMA_MODE0 SYNCCTL_SYNCDMA(1) /*!< ADC sync DMA mode 0 */
#define ADC_SYNC_DMA_MODE1 SYNCCTL_SYNCDMA(2) /*!< ADC sync DMA mode 1 */
/* ADC sync delay */
#define SYNCCTL_SYNCDLY(regval) (BITS(8,11) & ((uint32_t)(regval) << 8U)) /*!< write value to ADC_SYNCCTL_SYNCDLY bit field */
#define ADC_SYNC_DELAY_5CYCLE SYNCCTL_SYNCDLY(0) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */
#define ADC_SYNC_DELAY_6CYCLE SYNCCTL_SYNCDLY(1) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */
#define ADC_SYNC_DELAY_7CYCLE SYNCCTL_SYNCDLY(2) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */
#define ADC_SYNC_DELAY_8CYCLE SYNCCTL_SYNCDLY(3) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */
#define ADC_SYNC_DELAY_9CYCLE SYNCCTL_SYNCDLY(4) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */
#define ADC_SYNC_DELAY_10CYCLE SYNCCTL_SYNCDLY(5) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */
#define ADC_SYNC_DELAY_11CYCLE SYNCCTL_SYNCDLY(6) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */
#define ADC_SYNC_DELAY_12CYCLE SYNCCTL_SYNCDLY(7) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */
#define ADC_SYNC_DELAY_13CYCLE SYNCCTL_SYNCDLY(8) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */
#define ADC_SYNC_DELAY_14CYCLE SYNCCTL_SYNCDLY(9) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */
#define ADC_SYNC_DELAY_15CYCLE SYNCCTL_SYNCDLY(10) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */
#define ADC_SYNC_DELAY_16CYCLE SYNCCTL_SYNCDLY(11) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */
#define ADC_SYNC_DELAY_17CYCLE SYNCCTL_SYNCDLY(12) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */
#define ADC_SYNC_DELAY_18CYCLE SYNCCTL_SYNCDLY(13) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */
#define ADC_SYNC_DELAY_19CYCLE SYNCCTL_SYNCDLY(14) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */
#define ADC_SYNC_DELAY_20CYCLE SYNCCTL_SYNCDLY(15) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */
/* ADC sync mode */
#define SYNCCTL_SYNCM(regval) (BITS(0,3) & ((uint32_t)(regval) << 0U)) /*!< write value to ADC_SYNCCTL_SYNCM bit field */
#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */
#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< combined routine parallel & inserted parallel mode */
#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< combined routine parallel & trigger rotation mode */
#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< inserted parallel mode */
#define ADC_DAUL_ROUTINE_PARALLEL SYNCCTL_SYNCM(6) /*!< routine parallel mode */
#define ADC_DAUL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< follow-up mode */
#define ADC_DAUL_INSERTED_TRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< trigger rotation mode */
/* external trigger mode for routine and inserted channel */
#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */
#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */
#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */
#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */
/* ADC channel definitions */
#define ADC_ROUTINE_CHANNEL ((uint8_t)0x01U) /*!< ADC routine sequence */
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted sequence */
#define ADC_ROUTINE_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both routine and inserted sequence */
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of routine & inserted channel */
/* ADC inserted channel definitions */
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */
/* ADC channel definitions */
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */
#define ADC_CHANNEL_19 ((uint8_t)0x13U) /*!< ADC channel 19 */
#define ADC_CHANNEL_20 ((uint8_t)0x14U) /*!< ADC channel 20 */
/* analog watchdog 1/2 channel selection for channel n(n=0..20) */
#define ADC_AWD1_2_SELECTION_CHANNEL_0 ((uint32_t)0x00000001U) /*!< ADC channel 0 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_1 ((uint32_t)0x00000002U) /*!< ADC channel 1 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_2 ((uint32_t)0x00000004U) /*!< ADC channel 2 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_3 ((uint32_t)0x00000008U) /*!< ADC channel 3 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_4 ((uint32_t)0x00000010U) /*!< ADC channel 4 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_5 ((uint32_t)0x00000020U) /*!< ADC channel 5 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_6 ((uint32_t)0x00000040U) /*!< ADC channel 6 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_7 ((uint32_t)0x00000080U) /*!< ADC channel 7 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_8 ((uint32_t)0x00000100U) /*!< ADC channel 8 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_9 ((uint32_t)0x00000200U) /*!< ADC channel 9 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_10 ((uint32_t)0x00000400U) /*!< ADC channel 10 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_11 ((uint32_t)0x00000800U) /*!< ADC channel 11 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_12 ((uint32_t)0x00001000U) /*!< ADC channel 12 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_13 ((uint32_t)0x00002000U) /*!< ADC channel 13 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_14 ((uint32_t)0x00004000U) /*!< ADC channel 14 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_15 ((uint32_t)0x00008000U) /*!< ADC channel 15 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_16 ((uint32_t)0x00010000U) /*!< ADC channel 16 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_17 ((uint32_t)0x00020000U) /*!< ADC channel 17 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_18 ((uint32_t)0x00040000U) /*!< ADC channel 18 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_19 ((uint32_t)0x00080000U) /*!< ADC channel 19 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_20 ((uint32_t)0x00100000U) /*!< ADC channel 20 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_ALL ((uint32_t)0x001FFFFFU) /*!< all ADC channels analog watchdog 1/2 selection */
/* Differential mode for channel n(n=0..21) */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_0 ((uint32_t)0x00000001U) /*!< ADC channel 0 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_1 ((uint32_t)0x00000002U) /*!< ADC channel 1 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_2 ((uint32_t)0x00000004U) /*!< ADC channel 2 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_3 ((uint32_t)0x00000008U) /*!< ADC channel 3 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_4 ((uint32_t)0x00000010U) /*!< ADC channel 4 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_5 ((uint32_t)0x00000020U) /*!< ADC channel 5 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_6 ((uint32_t)0x00000040U) /*!< ADC channel 6 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_7 ((uint32_t)0x00000080U) /*!< ADC channel 7 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_8 ((uint32_t)0x00000100U) /*!< ADC channel 8 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_9 ((uint32_t)0x00000200U) /*!< ADC channel 9 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_10 ((uint32_t)0x00000400U) /*!< ADC channel 10 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_11 ((uint32_t)0x00000800U) /*!< ADC channel 11 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_12 ((uint32_t)0x00001000U) /*!< ADC channel 12 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_13 ((uint32_t)0x00002000U) /*!< ADC channel 13 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_14 ((uint32_t)0x00004000U) /*!< ADC channel 14 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_15 ((uint32_t)0x00008000U) /*!< ADC channel 15 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_16 ((uint32_t)0x00010000U) /*!< ADC channel 16 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_17 ((uint32_t)0x00020000U) /*!< ADC channel 17 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_18 ((uint32_t)0x00040000U) /*!< ADC channel 18 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_19 ((uint32_t)0x00080000U) /*!< ADC channel 19 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_20 ((uint32_t)0x00100000U) /*!< ADC channel 20 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_21 ((uint32_t)0x00200000U) /*!< ADC channel 21 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_ALL ((uint32_t)0x003FFFFFU) /*!< all ADC channels differential mode */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check the adc periph */
#define NOT_ADC_PERIPH(adc_periph) (((adc_periph) != ADC0) && ((adc_periph) != ADC1) && \
((adc_periph) != ADC2))
/* check the adc prescaler ratio */
#define NOT_ADC_CLK_MODE(prescaler) (((prescaler) != ADC_CLK_SYNC_HCLK_DIV2) && ((prescaler) != ADC_CLK_SYNC_HCLK_DIV4) && \
((prescaler) != ADC_CLK_SYNC_HCLK_DIV6) && ((prescaler) != ADC_CLK_SYNC_HCLK_DIV8) && \
((prescaler) != ADC_CLK_SYNC_HCLK_DIV10) && ((prescaler) != ADC_CLK_SYNC_HCLK_DIV12) && \
((prescaler) != ADC_CLK_SYNC_HCLK_DIV14) && ((prescaler) != ADC_CLK_SYNC_HCLK_DIV16) && \
((prescaler) != ADC_CLK_ASYNC_DIV1) && ((prescaler) != ADC_CLK_ASYNC_DIV2) && \
((prescaler) != ADC_CLK_ASYNC_DIV4) && ((prescaler) != ADC_CLK_ASYNC_DIV6) && \
((prescaler) != ADC_CLK_ASYNC_DIV8) && ((prescaler) != ADC_CLK_ASYNC_DIV10) && \
((prescaler) != ADC_CLK_ASYNC_DIV12) && ((prescaler) != ADC_CLK_ASYNC_DIV16) && \
((prescaler) != ADC_CLK_ASYNC_DIV32) && ((prescaler) != ADC_CLK_ASYNC_DIV64) && \
((prescaler) != ADC_CLK_ASYNC_DIV128) && ((prescaler) != ADC_CLK_ASYNC_DIV256))
/* check adc special mode */
#define ADC_SPECIAL_FUNCTION_LOW ((uint32_t)0x00000002U)
#define ADC_SPECIAL_FUNCTION_HIGH ((uint32_t)0x00000502U)
#define NOT_ADC_SPECIAL_FUNCTION_VALUE(function) ((ADC_SPECIAL_FUNCTION_LOW > (function)) || (ADC_SPECIAL_FUNCTION_HIGH < (function)))
/* check ENABLE and DISABLE */
#define NOT_ADC_ENABLE_DISABLE(newvalue) (((newvalue) != ENABLE) && ((newvalue) != DISABLE))
/* check data alignment */
#define NOT_ADC_DATA_ALIGNMENT(data_alignment) (((data_alignment) != ADC_DATAALIGN_RIGHT) && ((data_alignment) != ADC_DATAALIGN_LEFT))
/* check adc calibration mode */
#define NOT_CALIBRATION_MODE(clb_mode) (((clb_mode) != ADC_CALIBRATION_OFFSET_MISMATCH) && ((clb_mode) != ADC_CALIBRATION_OFFSET))
/* check adc calibration number */
#define NOT_ADC_CALIBRATION_NUMBER(clb_num) (((clb_num) != ADC_CALIBRATION_NUM1) && ((clb_num) != ADC_CALIBRATION_NUM2) && \
((clb_num) != ADC_CALIBRATION_NUM4) && ((clb_num) != ADC_CALIBRATION_NUM8) && \
((clb_num) != ADC_CALIBRATION_NUM16) && ((clb_num) != ADC_CALIBRATION_NUM32))
/* check ADC resolution */
#define NOT_ADC_RESOLUTION(resolution) (((resolution) != ADC_RESOLUTION_14B) && ((resolution) != ADC_RESOLUTION_12B) && ((resolution) \
!= ADC_RESOLUTION_10B) && ((resolution) != ADC_RESOLUTION_8B) && ((resolution) != ADC_RESOLUTION_6B))
/* check ADC resolution */
#define NOT_ADC_CHANNEL_INTERNAL(internal_channel) (((internal_channel) != ADC_CHANNEL_INTERNAL_TEMPSENSOR) && ((internal_channel) != ADC_CHANNEL_INTERNAL_VREFINT) && \
((internal_channel) != ADC_CHANNEL_INTERNAL_VBAT) && ((internal_channel) != ADC_CHANNEL_INTERNAL_HP_TEMPSENSOR))
/* check ADC sequence */
#define NOT_ADC_SEQUENCE(adc_sequence) (((adc_sequence) != ADC_ROUTINE_CHANNEL) && ((adc_sequence) != ADC_INSERTED_CHANNEL))
/* check discontinuous mode length */
#define ADC_DISCONTINUOUS_MODE_LENGTH_LOW ((uint32_t)0x00000001U)
#define ADC_DISCONTINUOUS_MODE_LENGTH_HIGH ((uint32_t)0x00000008U)
#define NOT_ADC_DISCONTINUOUS_MODE_LENGTH(length) ((ADC_DISCONTINUOUS_MODE_LENGTH_LOW > (length)) || (ADC_DISCONTINUOUS_MODE_LENGTH_HIGH < (length)))
/* check ADC sequence */
#define NOT_ADC_SEQUENCE(adc_sequence) (((adc_sequence) != ADC_ROUTINE_CHANNEL) && ((adc_sequence) != ADC_INSERTED_CHANNEL))
/* check ADC sequence */
#define NOT_ADC_SEQUENCE_EXD(adc_sequence) (((adc_sequence) != ADC_ROUTINE_CHANNEL) && ((adc_sequence) != ADC_INSERTED_CHANNEL)&& ((adc_sequence) != ADC_CHANNEL_DISCON_DISABLE))
/* check ADC channel length */
#define ADC_CHANNEL_LENGTH_LOW ((uint32_t)0x00000001U)
#define ADC_CHANNEL_LENGTH_HIGH ((uint32_t)0x00000010U)
#define NOT_ADC_CHANNEL_LENGTH(length) ((ADC_CHANNEL_LENGTH_LOW > (length)) || (ADC_CHANNEL_LENGTH_HIGH < (length)))
/* check routine sequence rank */
#define ADC_ROUTINE_SEQUENCE_RANK_HIGH ((uint32_t)0x0000000FU)
#define NOT_ADC_ROUTINE_SEQUENCE_RANK_VALUE(rank) (ADC_ROUTINE_SEQUENCE_RANK_HIGH < (rank))
/* check ADC channel select */
#define NOT_ADC_CHANNEL(channel) (((channel) != ADC_CHANNEL_0) && ((channel) != ADC_CHANNEL_1) && \
((channel) != ADC_CHANNEL_2) && ((channel) != ADC_CHANNEL_3) && \
((channel) != ADC_CHANNEL_4) && ((channel) != ADC_CHANNEL_5) && \
((channel) != ADC_CHANNEL_6) && ((channel) != ADC_CHANNEL_7) && \
((channel) != ADC_CHANNEL_8) && ((channel) != ADC_CHANNEL_9) && \
((channel) != ADC_CHANNEL_10) && ((channel) != ADC_CHANNEL_11) && \
((channel) != ADC_CHANNEL_12) && ((channel) != ADC_CHANNEL_13) && \
((channel) != ADC_CHANNEL_14) && ((channel) != ADC_CHANNEL_15) && \
((channel) != ADC_CHANNEL_16) && ((channel) != ADC_CHANNEL_17) && \
((channel) != ADC_CHANNEL_18) && ((channel) != ADC_CHANNEL_19) && \
((channel) != ADC_CHANNEL_20))
/* check ADC sample_time */
#define ADC_ADC_SAMPLE_TIME_HIGH ((uint32_t)0x00000329U)
#define NOT_ADC_SAMPLE_TIME(sample_time) (ADC_ADC_SAMPLE_TIME_HIGH < (sample_time))
/* check inserted sequence rank */
#define ADC_INSERTED_SEQUENCE_RANK_HIGH ((uint32_t)0x00000003U)
#define NOT_ADC_INSERTED_SEQUENCE_RANK_VALUE(rank) (ADC_INSERTED_SEQUENCE_RANK_HIGH < (rank))
/* check inserted channel */
#define NOT_INSERTED_CHANNEL(inserted_channel) (((inserted_channel) != ADC_INSERTED_CHANNEL_0) && ((inserted_channel) != ADC_INSERTED_CHANNEL_1) && \
((inserted_channel) != ADC_INSERTED_CHANNEL_2) && ((inserted_channel) != ADC_INSERTED_CHANNEL_3))
/* check inserted offset value */
#define ADC_INSERTED_OFFSET_HIGH ((uint32_t)0x00FFFFFFU)
#define NOT_ADC_INSERTED_OFFSET_VALUE(offset) (ADC_INSERTED_OFFSET_HIGH < (offset))
/* check ADC trigger mode */
#define NOT_ADC_TRIGGER_MODE(trigger_mode) (((trigger_mode) != EXTERNAL_TRIGGER_DISABLE) && ((trigger_mode) != EXTERNAL_TRIGGER_RISING) && \
((trigger_mode) != EXTERNAL_TRIGGER_FALLING) && ((trigger_mode) != EXTERNAL_TRIGGER_RISING_FALLING))
/* end of conversion mode */
#define NOT_ADC_END_OF_CONVERSION_MODE(end_selection) (((end_selection) != ADC_EOC_SET_SEQUENCE) && ((end_selection) != ADC_EOC_SET_CONVERSION))
/* check ADC sequence */
#define NOT_ADC_SEQUENC_BOTH(adc_sequence) (((adc_sequence) != ADC_ROUTINE_CHANNEL) && ((adc_sequence) != ADC_INSERTED_CHANNEL) && \
((adc_sequence) != ADC_ROUTINE_INSERTED_CHANNEL))
/* check differential mode for ADC channel */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_LOW ((uint32_t)0x00000001U)
#define ADC_DIFFERENTIAL_MODE_CHANNEL_HIGH ((uint32_t)0x003FFFFFU)
#define NOT_ADC_DIFFERENTIAL_MODE_CHANNEL(length) ((ADC_DIFFERENTIAL_MODE_CHANNEL_LOW > (length)) || (ADC_DIFFERENTIAL_MODE_CHANNEL_HIGH < (length)))
/* check ADC analog watchdog 1/2 selection */
#define ADC_ANALOG_WATCHDOG_SEL_LOW ((uint32_t)0x00000001U)
#define ADC_ANALOG_WATCHDOG_SEL_HIGH ((uint32_t)0x001FFFFFU)
#define NOT_ADC_ANALOG_WATCHDOG_SEL(selection_channel) ((ADC_ANALOG_WATCHDOG_SEL_LOW > (selection_channel)) || (ADC_ANALOG_WATCHDOG_SEL_HIGH < (selection_channel)))
/* check analog watchdog threshold */
#define ADC_ANALOG_WATCHDOG_THRESHOLD_HIGH ((uint32_t)0x00FFFFFFU)
#define NOT_ADC_ANALOG_WATCHDOG_THRESHOLD(threshold) (ADC_ANALOG_WATCHDOG_THRESHOLD_HIGH < (threshold))
/* check ADC oversampling mode */
#define NOT_ADC_OVERSAMPLING_MODE(mode) (((mode) != ADC_OVERSAMPLING_ALL_CONVERT) && ((mode) != ADC_OVERSAMPLING_ONE_CONVERT))
/* check ADC oversampling shift */
#define NOT_ADC_OVERSAMPLING_SHIFT(shift) (((shift) != ADC_OVERSAMPLING_SHIFT_NONE) && ((shift) != ADC_OVERSAMPLING_SHIFT_1B) && \
((shift) != ADC_OVERSAMPLING_SHIFT_2B) && ((shift) != ADC_OVERSAMPLING_SHIFT_3B) && \
((shift) != ADC_OVERSAMPLING_SHIFT_4B) && ((shift) != ADC_OVERSAMPLING_SHIFT_5B) && \
((shift) != ADC_OVERSAMPLING_SHIFT_6B) && ((shift) != ADC_OVERSAMPLING_SHIFT_7B) && \
((shift) != ADC_OVERSAMPLING_SHIFT_8B) && ((shift) != ADC_OVERSAMPLING_SHIFT_9B) && \
((shift) != ADC_OVERSAMPLING_SHIFT_10B) && ((shift) != ADC_OVERSAMPLING_SHIFT_11B))
/* check ADC oversampling ratio */
#define ADC_OVERSAMPLING_RATIO_HIGH ((uint32_t)0x000003FFU)
#define NOT_ADC_OVERSAMPLING_RATIO(ratio) (ADC_OVERSAMPLING_RATIO_HIGH < (ratio))
/* check ADC falg */
#define NOT_ADC_FLAG(flag) (((flag) != ADC_FLAG_WDE0) && ((flag) != ADC_FLAG_EOC) && \
((flag) != ADC_FLAG_EOIC) && ((flag) != ADC_FLAG_STIC) && \
((flag) != ADC_FLAG_STRC) && ((flag) != ADC_FLAG_ROVF) && \
((flag) != ADC_FLAG_WDE1) && ((flag) != ADC_FLAG_WDE2))
/* check ADC interrupt */
#define NOT_ADC_INTERRUPT(interrupt) (((interrupt) != ADC_INT_WDE0) && ((interrupt) != ADC_INT_EOC) && \
((interrupt) != ADC_INT_EOIC) && ((interrupt) != ADC_INT_ROVF) && \
((interrupt) != ADC_INT_WDE1) && ((interrupt) != ADC_INT_WDE2))
/* check ADC interrupt flag */
#define NOT_ADC_INTERRUPT_FLAG(flag) (((int_flag) != ADC_INT_FLAG_WDE0) && ((int_flag) != ADC_INT_FLAG_EOC) && \
((int_flag) != ADC_INT_FLAG_EOIC) && ((int_flag) != ADC_INT_FLAG_ROVF) && \
((int_flag) != ADC_INT_FLAG_WDE1) && ((int_flag) != ADC_INT_FLAG_WDE2))
/* check the adc sync mode */
#define NOT_ADC_SYNC_mode(sync_mode) (((sync_mode) != ADC_SYNC_MODE_INDEPENDENT) && ((sync_mode) != ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL) && \
((sync_mode) != ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION) && ((sync_mode) != ADC_DAUL_INSERTED_PARALLEL) && \
((sync_mode) != ADC_DAUL_ROUTINE_PARALLEL) && ((sync_mode) != ADC_DAUL_ROUTINE_FOLLOW_UP) && \
((sync_mode) != ADC_DAUL_INSERTED_TRIGGER_ROTATION))
/* check the adc sync delay sample */
#define NOT_ADC_SYNC_DELAY_SAMPLE(sample_delay) (((sample_delay) != ADC_SYNC_DELAY_5CYCLE) && ((sample_delay) != ADC_SYNC_DELAY_6CYCLE) && \
((sample_delay) != ADC_SYNC_DELAY_7CYCLE) && ((sample_delay) != ADC_SYNC_DELAY_8CYCLE) && \
((sample_delay) != ADC_SYNC_DELAY_9CYCLE) && ((sample_delay) != ADC_SYNC_DELAY_10CYCLE) && \
((sample_delay) != ADC_SYNC_DELAY_11CYCLE) && ((sample_delay) != ADC_SYNC_DELAY_12CYCLE) && \
((sample_delay) != ADC_SYNC_DELAY_13CYCLE) && ((sample_delay) != ADC_SYNC_DELAY_14CYCLE) && \
((sample_delay) != ADC_SYNC_DELAY_15CYCLE) && ((sample_delay) != ADC_SYNC_DELAY_16CYCLE) && \
((sample_delay) != ADC_SYNC_DELAY_17CYCLE) && ((sample_delay) != ADC_SYNC_DELAY_18CYCLE) && \
((sample_delay) != ADC_SYNC_DELAY_19CYCLE) && ((sample_delay) != ADC_SYNC_DELAY_20CYCLE))
/* check the adc sync dma mode */
#define NOT_ADC_SYNC_DMA_mode(dma_mode) (((dma_mode) != ADC_SYNC_DMA_DISABLE) && ((dma_mode) != ADC_SYNC_DMA_MODE0) && \
((dma_mode) != ADC_SYNC_DMA_MODE1))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* initialization config */
/* reset ADC */
void adc_deinit(uint32_t adc_periph);
/* configure the ADC clock */
void adc_clock_config(uint32_t adc_periph, uint32_t prescaler);
/* enable or disable ADC special function */
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue);
/* configure ADC data alignment */
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment);
/* enable ADC interface */
void adc_enable(uint32_t adc_periph);
/* disable ADC interface */
void adc_disable(uint32_t adc_periph);
/* configure ADC calibration mode */
void adc_calibration_mode_config(uint32_t adc_periph, uint32_t clb_mode);
/* configure ADC calibration number */
void adc_calibration_number(uint32_t adc_periph, uint32_t clb_num);
/* ADC calibration and reset calibration */
void adc_calibration_enable(uint32_t adc_periph);
/* configure ADC resolution */
void adc_resolution_config(uint32_t adc_periph, uint32_t resolution);
/* enable or disable ADC internal channels */
void adc_internal_channel_config(uint32_t internal_channel, ControlStatus newvalue);
/* DMA config */
/* enable DMA request */
void adc_dma_mode_enable(uint32_t adc_periph);
/* disable DMA request */
void adc_dma_mode_disable(uint32_t adc_periph);
/* when DMA=1, the DMA engine issues a request at end of each routine conversion */
void adc_dma_request_after_last_enable(uint32_t adc_periph);
/* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */
void adc_dma_request_after_last_disable(uint32_t adc_periph);
/* enable hpdf mode */
void adc_hpdf_mode_enable(uint32_t adc_periph);
/* disable hpdf mode */
void adc_hpdf_mode_disable(uint32_t adc_periph);
/* routine sequence and inserted sequence config */
/* configure ADC discontinuous mode */
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t length);
/* configure the length of routine sequence or inserted sequence */
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t length);
/* configure ADC routine channel */
void adc_routine_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
/* configure ADC inserted channel */
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
/* configure ADC inserted channel offset */
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint32_t offset);
/* configure differential mode for channel */
void adc_channel_differential_mode_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue);
/* enable ADC external trigger */
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t trigger_mode);
/* enable ADC software trigger */
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_sequence);
/* configure end of conversion mode */
void adc_end_of_conversion_config(uint32_t adc_periph, uint32_t end_selection);
/* get channel data */
/* read ADC routine sequence data register */
uint32_t adc_routine_data_read(uint32_t adc_periph);
/* read ADC inserted sequence data register */
uint32_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel);
/* ADC analog watchdog functions */
/* configure ADC analog watchdog 0 single channel */
void adc_watchdog0_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
/* configure ADC analog watchdog 0 group channel */
void adc_watchdog0_group_channel_enable(uint32_t adc_periph, uint8_t adc_sequence);
/* disable ADC analog watchdog 0 */
void adc_watchdog0_disable(uint32_t adc_periph);
/* configure ADC analog watchdog 1 channel */
void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t selection_channel, ControlStatus newvalue);
/* configure ADC analog watchdog 2 channel */
void adc_watchdog2_channel_config(uint32_t adc_periph, uint32_t selection_channel, ControlStatus newvalue);
/* disable ADC analog watchdog 1 */
void adc_watchdog1_disable(uint32_t adc_periph);
/* disable ADC analog watchdog 2 */
void adc_watchdog2_disable(uint32_t adc_periph);
/* configure ADC analog watchdog 0 threshold */
void adc_watchdog0_threshold_config(uint32_t adc_periph, uint32_t low_threshold, uint32_t high_threshold);
/* configure ADC analog watchdog 1 threshold */
void adc_watchdog1_threshold_config(uint32_t adc_periph, uint32_t low_threshold, uint32_t high_threshold);
/* configure ADC analog watchdog 2 threshold */
void adc_watchdog2_threshold_config(uint32_t adc_periph, uint32_t low_threshold, uint32_t high_threshold);
/* ADC oversample functions */
/* configure ADC oversample mode */
void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint16_t ratio);
/* enable ADC oversample mode */
void adc_oversample_mode_enable(uint32_t adc_periph);
/* disable ADC oversample mode */
void adc_oversample_mode_disable(uint32_t adc_periph);
/* flag and interrupt functions */
/* get the ADC flag bits */
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t flag);
/* clear the ADC flag bits */
void adc_flag_clear(uint32_t adc_periph, uint32_t flag);
/* enable ADC interrupt */
void adc_interrupt_enable(uint32_t adc_periph, uint32_t interrupt);
/* disable ADC interrupt */
void adc_interrupt_disable(uint32_t adc_periph, uint32_t interrupt);
/* get the ADC interrupt bits */
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t int_flag);
/* clear the ADC flag */
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t int_flag);
/* ADC synchronization */
/* configure the ADC sync mode */
void adc_sync_mode_config(uint32_t sync_mode);
/* configure the delay between 2 sampling phases in ADC sync modes */
void adc_sync_delay_config(uint32_t sample_delay);
/* configure ADC sync DMA mode selection */
void adc_sync_dma_config(uint32_t dma_mode);
/* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */
void adc_sync_dma_request_after_last_enable(void);
/* configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected */
void adc_sync_dma_request_after_last_disable(void);
/* read ADC sync master adc routine data register 0 */
uint32_t adc_sync_master_adc_routine_data0_read(void);
/* read ADC sync slave adc routine data register 0 */
uint32_t adc_sync_slave_adc_routine_data0_read(void);
/* read ADC sync routine data register 1 */
uint32_t adc_sync_routine_data1_read(void);
#endif /* GD32H75E_ADC_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_axiim.h
+226
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@@ -0,0 +1,226 @@
/*!
\file gd32h75e_axiim.h
\brief definitions for AXIIM(AXI interconnect matrix)
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_AXIIM_H
#define GD32H75E_AXIIM_H
#include "gd32h75e.h"
/* AXI interconnect matrix definitions */
#define AXIIM_BASE ((uint32_t)0x51000000U) /*!< AXI interconnect matrix base address */
#define AXIIM AXIIM_BASE /*!< AXI interconnect matrix definition */
/* registers definitions */
#define AXI_PERIPH_ID4 REG32(AXIIM + 0x00001FD0U) /*!< AXI peripheral ID4 register */
#define AXI_PERIPH_ID0 REG32(AXIIM + 0x00001FE0U) /*!< AXI peripheral ID0 register */
#define AXI_PERIPH_ID1 REG32(AXIIM + 0x00001FE4U) /*!< AXI peripheral ID1 register */
#define AXI_PERIPH_ID2 REG32(AXIIM + 0x00001FE8U) /*!< AXI peripheral ID2 register */
#define AXI_PERIPH_ID3 REG32(AXIIM + 0x00001FECU) /*!< AXI peripheral ID3 register */
#define AXI_COMP_ID0 REG32(AXIIM + 0x00001FF0U) /*!< AXI componet ID0 register */
#define AXI_COMP_ID1 REG32(AXIIM + 0x00001FF4U) /*!< AXI componet ID1 register */
#define AXI_COMP_ID2 REG32(AXIIM + 0x00001FF8U) /*!< AXI componet ID2 register */
#define AXI_COMP_ID3 REG32(AXIIM + 0x00001FFCU) /*!< AXI componet ID3 register */
#define AXI_MPXBM_ISS_CTL(mportx) REG32(AXIIM + 0x00002008U + 0x00001000U * (mportx)) /*!< AXI master port x bus matrix issuing functionality control register */
#define AXI_MP0BM_ISS_CTL REG32(AXIIM + 0x00002008U) /*!< AXI master port 0 bus matrix issuing functionality control register */
#define AXI_MP1BM_ISS_CTL REG32(AXIIM + 0x00003008U) /*!< AXI master port 1 bus matrix issuing functionality control register */
#define AXI_MP2BM_ISS_CTL REG32(AXIIM + 0x00004008U) /*!< AXI master port 2 bus matrix issuing functionality control register */
#define AXI_MP3BM_ISS_CTL REG32(AXIIM + 0x00005008U) /*!< AXI master port 3 bus matrix issuing functionality control register */
#define AXI_MP4BM_ISS_CTL REG32(AXIIM + 0x00006008U) /*!< AXI master port 4 bus matrix issuing functionality control register */
#define AXI_MP5BM_ISS_CTL REG32(AXIIM + 0x00007008U) /*!< AXI master port 5 bus matrix issuing functionality control register */
#define AXI_MP6BM_ISS_CTL REG32(AXIIM + 0x00008008U) /*!< AXI master port 6 bus matrix issuing functionality control register */
#define AXI_MP7BM_ISS_CTL REG32(AXIIM + 0x00009008U) /*!< AXI master port 7 bus matrix issuing functionality control register */
#define AXI_MPXBM_CTL(mportx) REG32(AXIIM + 0x00002024U + 0x00001000U * (mportx)) /*!< AXI master port x bus matrix functionality control register */
#define AXI_MP0BM_CTL REG32(AXIIM + 0x00002024U) /*!< AXI master port 0 bus matrix functionality control register */
#define AXI_MP1BM_CTL REG32(AXIIM + 0x00003024U) /*!< AXI master port 1 bus matrix functionality control register */
#define AXI_MP6BM_CTL REG32(AXIIM + 0x00008024U) /*!< AXI master port 6 bus matrix functionality control register */
#define AXI_MP7BM_CTL REG32(AXIIM + 0x00009024U) /*!< AXI master port 7 bus matrix functionality control register */
#define AXI_MPX_LB_CTL(mportx) REG32(AXIIM + 0x0000202CU + 0x00001000U * (mportx)) /*!< AXI master port x long burst functionality control register */
#define AXI_MP0_LB_CTL REG32(AXIIM + 0x0000202CU) /*!< AXI master port 0 long burst functionality control register */
#define AXI_MP1_LB_CTL REG32(AXIIM + 0x0000302CU) /*!< AXI master port 1 long burst functionality control register */
#define AXI_MPX_ISS_CTL(mportx) REG32(AXIIM + 0x00002108U + 0x00001000U * (mportx)) /*!< AXI master port x issuing functionality control register */
#define AXI_MP0_ISS_CTL REG32(AXIIM + 0x00002108U) /*!< AXI master port 0 issuing functionality control register */
#define AXI_MP1_ISS_CTL REG32(AXIIM + 0x00003108U) /*!< AXI master port 1 issuing functionality control register */
#define AXI_MP6_ISS_CTL REG32(AXIIM + 0x00008108U) /*!< AXI master port 6 issuing functionality control register */
#define AXI_MP7_ISS_CTL REG32(AXIIM + 0x00009108U) /*!< AXI master port 7 issuing functionality control register */
#define AXI_SPX_CTL(sportx) REG32(AXIIM + 0x00042024U + 0x00001000U * (sportx)) /*!< AXI slave port x functionality control register */
#define AXI_SP0_CTL REG32(AXIIM + 0x00042024U) /*!< AXI slave port 0 functionality control register */
#define AXI_SP2_CTL REG32(AXIIM + 0x00044024U) /*!< AXI slave port 2 functionality control register */
#define AXI_SPX_AHBISS_CTL(sportx) REG32(AXIIM + 0x00042028U + 0x00001000U * (sportx)) /*!< AXI slave port x AHB issuing functionality control register */
#define AXI_SP0_AHBISS_CTL REG32(AXIIM + 0x00042028U) /*!< AXI slave port 0 AHB issuing functionality control register */
#define AXI_SP2_AHBISS_CTL REG32(AXIIM + 0x00044028U) /*!< AXI slave port 2 AHB issuing functionality control register */
/* AXI slave port x = 0 to 5 */
#define AXI_SPX_RDQOS_CTL(sportx) REG32(AXIIM + 0x00042100U + 0x00001000U * (sportx)) /*!< AXI slave port x read QOS control register */
#define AXI_SPX_WRQOS_CTL(sportx) REG32(AXIIM + 0x00042104U + 0x00001000U * (sportx)) /*!< AXI slave port x write QOS control register */
#define AXI_SPX_ISS_CTL(sportx) REG32(AXIIM + 0x00042108U + 0x00001000U * (sportx)) /*!< AXI slave port x issuing functionality control register */
#define AXI_PERIPH_ID4_JEP106CCODE BITS(0,3) /*!< JEP106 continuation code */
#define AXI_PERIPH_ID4_4KBCNT BITS(4,7) /*!< register file size */
#define AXI_PERIPH_ID0_PARTNUM BITS(0,7) /*!< part number bit[7:0] */
#define AXI_PERIPH_ID1_PARTNUM BITS(0,3) /*!< part number bit[11:8] */
#define AXI_PERIPH_ID1_JEP106ID BITS(4,7) /*!< JEP106 identity[3:0] */
#define AXI_PERIPH_ID2_JEP106ID BITS(0,2) /*!< JEP106 identity[6:4] */
#define AXI_PERIPH_ID2_JEP106CF BIT(3) /*!< JEP106 code flag */
#define AXI_PERIPH_ID2_PARTREV BITS(4,7) /*!< part revision */
#define AXI_PERIPH_ID3_CUSTMOD BITS(0,3) /*!< customer modification[3:0] */
#define AXI_PERIPH_ID3_CUSTREV BITS(4,7) /*!< customer version */
#define AXI_COMP_ID0_PREAMB BITS(0,7) /*!< preamble bits[7:0] */
#define AXI_COMP_ID1_PREAMB BITS(0,3) /*!< preamble bits[11:8] */
#define AXI_COMP_ID1_CLASS BITS(4,7) /*!< component class */
#define AXI_COMP_ID2_PREAMB BITS(0,7) /*!< preamble bits[19:12] */
#define AXI_COMP_ID3_PREAMB BITS(0,7) /*!< preamble bits[27:20] */
#define AXI_MPXBM_ISS_CTL_RD_ISSOV BIT(0) /*!< override target read issuing function */
#define AXI_MPXBM_ISS_CTL_WR_ISSOV BIT(1) /*!< override target write issuing function */
#define AXI_MPXBM_CTL_BPDIS BIT(0) /*!< beats packing function disable configure */
#define AXI_MPX_LB_CTL_LBEN BIT(0) /*!< control long burst function */
#define AXI_MPX_ISS_CTL_RD_ISSOV BIT(0) /*!< override AMIB read issuing function */
#define AXI_MPX_ISS_CTL_WR_ISSOV BIT(1) /*!< override AMIB write issuing function */
#define AXI_SPX_CTL_TRANSALT BIT(0) /*!< slave port transaction alteration configure bit */
#define AXI_SPX_AHBISS_CTL_WR_AHB_ISSOV BIT(0) /*!< converts AHB-Lite write transaction to single beat AXI transaction */
#define AXI_SPX_AHBISS_CTL_RD_AHB_ISSOV BIT(1) /*!< converts AHB-Lite read transaction to single beat AXI transaction */
#define AXI_SPX_RDQOS_CTL_RDQOS BITS(0,3) /*!< slave port read channel QoS configure bits */
#define AXI_SPX_WRQOS_CTL_WRQOS BITS(0,3) /*!< slave port write channel QoS configure bits */
#define AXI_SPX_ISS_CTL_RD_ISSOV BIT(0) /*!< slave port override ASIB read issuing control bit */
#define AXI_SPX_ISS_CTL_WR_ISSOV BIT(1) /*!< slave port override ASIB write issuing control bit */
/* AXI master port select */
typedef enum
{
MASTER_PORT0 = 0U, /*!< AXI master port 0 */
MASTER_PORT1, /*!< AXI master port 1 */
MASTER_PORT2, /*!< AXI master port 2 */
MASTER_PORT3, /*!< AXI master port 3 */
MASTER_PORT4, /*!< AXI master port 4 */
MASTER_PORT5, /*!< AXI master port 5 */
MASTER_PORT6, /*!< AXI master port 6 */
MASTER_PORT7 /*!< AXI master port 7 */
} master_port_enum;
/* AXI slave port select */
typedef enum
{
SLAVE_PORT0 = 0U, /*!< AXI slave port 0 */
SLAVE_PORT1, /*!< AXI slave port 1 */
SLAVE_PORT2, /*!< AXI slave port 2 */
SLAVE_PORT3, /*!< AXI slave port 3 */
SLAVE_PORT4, /*!< AXI slave port 4 */
SLAVE_PORT5 /*!< AXI slave port 5 */
} slave_port_enum;
/* AXI master port x bus mutrix read issuing capability is set to 1, mportx: MASTER_PORTx (x=0..7) */
#define __AXI_MPXBM_READ_ISSOV_ENABLE(mportx) {AXI_MPXBM_ISS_CTL(mportx) |= AXI_MPXBM_ISS_CTL_RD_ISSOV}
/* AXI master port x bus mutrix read issuing capability is normal, mportx: MASTER_PORTx (x=0..7) */
#define __AXI_MPXBM_READ_ISSOV_DISABLE(mportx) {AXI_MPXBM_ISS_CTL(mportx) &= ~AXI_MPXBM_ISS_CTL_RD_ISSOV}
/* AXI master port x bus mutrix write issuing capability is set to 1, mportx: MASTER_PORTx (x=0..7) */
#define __AXI_MPXBM_WRITE_ISSOV_ENABLE(mportx) {AXI_MPXBM_ISS_CTL(mportx) |= AXI_MPXBM_ISS_CTL_WR_ISSOV}
/* AXI master port x bus mutrix write issuing capability is normal, mportx: MASTER_PORTx (x=0..7) */
#define __AXI_MPXBM_WRITE_ISSOV_DISABLE(mportx) {AXI_MPXBM_ISS_CTL(mportx) &= ~AXI_MPXBM_ISS_CTL_WR_ISSOV}
/* enable AXI master port x beats packing function, mportx: MASTER_PORTx (x=0,1,6,7) */
#define __AXI_MPXBM_BEATS_PACKING_ENABLE(mportx) {AXI_MPXBM_CTL(mportx) &= ~AXI_MPXBM_CTL_BPDIS}
/* disable AXI master port x beats packing function, mportx: MASTER_PORTx (x=0,1,6,7) */
#define __AXI_MPXBM_BEATS_PACKING_DISABLE(mportx) {AXI_MPXBM_CTL(mportx) |= AXI_MPXBM_CTL_BPDIS}
/* enable AXI master port long burst function, mportx: MASTER_PORTx (x=0,1) */
#define __AXI_MPX_LONG_BURST_ENABLE(mportx) {AXI_MPX_LB_CTL(mportx) |= AXI_MPX_LB_CTL_LBEN}
/* disable AXI master port x long burst function, mportx: MASTER_PORTx (x=0,1) */
#define __AXI_MPX_LONG_BURST_DISABLE(mportx) {AXI_MPX_LB_CTL(mportx) &= ~AXI_MPX_LB_CTL_LBEN}
/* force AMIB read issuing capability to 1, mportx: MASTER_PORTx (x=0,1,2,7) */
#define __AXI_MPX_READ_ISSOV_ENABLE(mportx) {AXI_MPX_ISS_CTL(mportx) |= AXI_MPX_ISS_CTL_RD_ISSOV}
/* AMIB read issuing capability is normal, mportx: MASTER_PORTx (x=0,1,2,7) */
#define __AXI_MPX_READ_ISSOV_DISABLE(mportx) {AXI_MPX_ISS_CTL(mportx) &= ~AXI_MPX_ISS_CTL_RD_ISSOV}
/* force AMIB write issuing capability to 1, mportx: MASTER_PORTx (x=0,1,2,7) */
#define __AXI_MPX_WRITE_ISSOV_ENABLE(mportx) {AXI_MPX_ISS_CTL(mportx) |= AXI_MPX_ISS_CTL_WR_ISSOV}
/* AMIB write issuing capability is normal, mportx: MASTER_PORTx (x=0,1,2,7) */
#define __AXI_MPX_WRITE_ISSOV_DISABLE(mportx) {AXI_MPX_ISS_CTL(mportx) &= ~AXI_MPX_ISS_CTL_WR_ISSOV}
/* enable AXI slave port transaction alteration function, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_TRANSACTION_ALTER_ENABLE(sportx) {AXI_SPX_CTL(sportx) |= AXI_SPX_CTL_TRANSALT}
/* AXI slave port transaction alteration function in normal operation, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_TRANSACTION_ALTER_DISABLE(sportx) {AXI_SPX_CTL(sportx) &= ~AXI_SPX_CTL_TRANSALT}
/* enable convert AHB-Lite write transaction to single beat AXI transaction, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_CONVERT_AHB_WR_TO_SINGLE_BEAT_TRANS_ENABLE(sportx) {AXI_SPX_AHBISS_CTL(sportx) |= AXI_SPX_AHBISS_CTL_WR_AHB_ISSOV}
/* disable convert AHB-Lite write transaction to single beat AXI transaction, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_CONVERT_AHB_WR_TO_SINGLE_BEAT_TRANS_DISABLE(sportx) {AXI_SPX_AHBISS_CTL(sportx) &= ~AXI_SPX_AHBISS_CTL_WR_AHB_ISSOV}
/* enable convert AHB-Lite read transaction to single beat AXI transaction, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_CONVERT_AHB_RD_TO_SINGLE_BEAT_TRANS_ENABLE(sportx) {AXI_SPX_AHBISS_CTL(sportx) |= AXI_SPX_AHBISS_CTL_RD_AHB_ISSOV}
/* disable convert AHB-Lite read transaction to single beat AXI transaction, mportx: SLAVE_PORTx (x=0,2) */
#define __AXI_SPX_CONVERT_AHB_RD_TO_SINGLE_BEAT_TRANS_DISABLE(sportx) {AXI_SPX_AHBISS_CTL(sportx) &= ~AXI_SPX_AHBISS_CTL_RD_AHB_ISSOV}
/* configure slave port read channel QoS, sportx: SLAVE_PORTx (x=0..5), priority: 0x0~0xF */
#define __AXI_SPX_READ_QOS_SET(sportx, priority) {AXI_SPX_RDQOS_CTL(sportx) |= ( (priority) & AXI_SPX_RDQOS_CTL_RDQOS)}
/* configure slave port write channel QoS, sportx: SLAVE_PORTx (x=0..5), priority: 0x0~0xF */
#define __AXI_SPX_WRITE_QOS_SET(sportx, priority) {AXI_SPX_WRQOS_CTL(sportx) |= ( (priority) & AXI_SPX_WRQOS_CTL_WRQOS)}
/* force ASIB read issuing capability to 1, sportx: SLAVE_PORTx (x=0..5) */
#define __AXI_SPX_READ_ISSOV_ENABLE(sportx) {AXI_SPX_ISS_CTL(sportx) |= AXI_SPX_ISS_CTL_RD_ISSOV}
/* ASIB read issuing capability in normal operation, mportx: SLAVE_PORTx (x=0..5) */
#define __AXI_SPX_READ_ISSOV_DISABLE(sportx) {AXI_SPX_ISS_CTL(sportx) &= ~AXI_SPX_ISS_CTL_RD_ISSOV}
/* force ASIB write issuing capability to 1, sportx: SLAVE_PORTx (x=0..5) */
#define __AXI_SPX_WRITE_ISSOV_ENABLE(sportx) {AXI_SPX_ISS_CTL(sportx) |= AXI_SPX_ISS_CTL_WD_ISSOV}
/* ASIB write issuing capability in normal operation, mportx: SLAVE_PORTx (x=0..5) */
#define __AXI_SPX_WRITE_ISSOV_DISABLE(sportx) {AXI_SPX_ISS_CTL(sportx) &= ~AXI_SPX_ISS_CTL_WD_ISSOV}
#endif /* GD32H75E_AXIIM_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_can.h
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828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_cmp.h
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/*!
\file gd32h75e_cmp.h
\brief definitions for the CMP
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_CMP_H
#define GD32H75E_CMP_H
#include "gd32h75e.h"
/* CMP definitions */
#define CMP CMP_BASE /*!< CMP base address */
/* registers definitions */
#define CMP_STAT REG32((CMP) + 0x00000000U) /*!< CMP status register */
#define CMP_IFC REG32((CMP) + 0x00000004U) /*!< CMP interrupt flag clear register */
#define CMP_SR REG32((CMP) + 0x00000008U) /*!< CMP alternate select register */
#define CMP0_CS REG32((CMP) + 0x0000000CU) /*!< CMP0 control and status register */
#define CMP1_CS REG32((CMP) + 0x00000010U) /*!< CMP1 control and status register */
/* bits definitions */
/* CMP_STAT */
#define CMP_STAT_CMP0O BIT(0) /*!< CMP0 output */
#define CMP_STAT_CMP1O BIT(1) /*!< CMP1 output */
#define CMP_STAT_CMP0IF BIT(16) /*!< CMP0 interrupt flag */
#define CMP_STAT_CMP1IF BIT(17) /*!< CMP1 interrupt flag */
/* CMP_IFC */
#define CMP_IFC_CMP0IC BIT(16) /*!< CMP0 interrupt flag clear */
#define CMP_IFC_CMP1IC BIT(17) /*!< CMP1 interrupt flag clear */
/* CMP_SR */
#define CMP_SR_AFSE_PA6 BIT(0) /*!< PA6 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PA8 BIT(1) /*!< PA8 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PB12 BIT(2) /*!< PB12 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PE6 BIT(3) /*!< PE6 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PE15 BIT(4) /*!< PE15 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PG2 BIT(5) /*!< PG2 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PG3 BIT(6) /*!< PG3 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PG4 BIT(7) /*!< PG4 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PK0 BIT(8) /*!< PK0 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PK1 BIT(9) /*!< PK1 alternate function select for CMPx_OUT */
#define CMP_SR_AFSE_PK2 BIT(10) /*!< PK2 alternate function select for CMPx_OUT */
/* CMPx_CS */
#define CMP_CS_CMPXEN BIT(0) /*!< CMPx enable */
#define CMP_CS_CMPXBEN BIT(1) /*!< CMPx scaler bridge enable bit */
#define CMP_CS_CMPXSEN BIT(2) /*!< CMPx voltage scaler enable bit */
#define CMP_CS_CMPXPL BIT(3) /*!< CMPx output polarity */
#define CMP_CS_WNDEN BIT(4) /*!< CMP Window mode enable */
#define CMP_CS_CMPXINTEN BIT(6) /*!< CMPx interrupt enable */
#define CMP_CS_CMPXHST BITS(8,9) /*!< CMPx hysteresis */
#define CMP_CS_CMPXM BITS(12,13) /*!< CMPx mode */
#define CMP_CS_CMPXMISEL BITS(16,18) /*!< CMP_IM input selection */
#define CMP_CS_CMPXPSEL BIT(20) /*!< CMP_IP input selection */
#define CMP_CS_CMPXBLK BITS(24,27) /*!< CMPx output blanking source */
#define CMP_CS_CMPXLK BIT(31) /*!< CMPx lock */
/* constants definitions */
/* CMP units */
typedef enum{
CMP0, /*!< comparator 0 */
CMP1 /*!< comparator 1 */
}cmp_enum;
/* CMP operating mode */
#define CS_CMPXM(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U))
#define CMP_MODE_HIGHSPEED CS_CMPXM(0) /*!< CMP mode high speed */
#define CMP_MODE_MIDDLESPEED CS_CMPXM(1) /*!< CMP mode middle speed */
#define CMP_MODE_VERYLOWSPEED CS_CMPXM(3) /*!< CMP mode very low speed */
/* CMP hysteresis */
#define CS_CMPXHST(regval) (BITS(8,9) & ((uint32_t)(regval) << 8U))
#define CMP_HYSTERESIS_NO CS_CMPXHST(0) /*!< CMP output no hysteresis */
#define CMP_HYSTERESIS_LOW CS_CMPXHST(1) /*!< CMP output low hysteresis */
#define CMP_HYSTERESIS_MIDDLE CS_CMPXHST(2) /*!< CMP output middle hysteresis */
#define CMP_HYSTERESIS_HIGH CS_CMPXHST(3) /*!< CMP output high hysteresis */
/* CMP inverting input */
#define CS_CMPXMSEL(regval) (BITS(16,18) & ((uint32_t)(regval) << 16U))
#define CMP_INVERTING_INPUT_1_4VREFINT CS_CMPXMSEL(0) /*!< CMP inverting input 1/4 Vrefint */
#define CMP_INVERTING_INPUT_1_2VREFINT CS_CMPXMSEL(1) /*!< CMP inverting input 1/2 Vrefint */
#define CMP_INVERTING_INPUT_3_4VREFINT CS_CMPXMSEL(2) /*!< CMP inverting input 3/4 Vrefint */
#define CMP_INVERTING_INPUT_VREFINT CS_CMPXMSEL(3) /*!< CMP inverting input Vrefint */
#define CMP_INVERTING_INPUT_DAC0_OUT0 CS_CMPXMSEL(4) /*!< CMP inverting input DAC0_OUT0 */
#define CMP_INVERTING_INPUT_DAC0_OUT1 CS_CMPXMSEL(5) /*!< CMP inverting input DAC0_OUT1 */
#define CMP_INVERTING_INPUT_PB1_PE10 CS_CMPXMSEL(6) /*!< CMP inverting input PB1 for CMP0 or PE10 for CMP1 */
#define CMP_INVERTING_INPUT_PC4_PE7 CS_CMPXMSEL(7) /*!< CMP inverting input PC4 for CMP0 or PE7 for CMP1 */
/* CMP noninverting input*/
#define CS_CMPXPSEL(regval) (BIT(20) & ((uint32_t)(regval) << 20U))
#define CMP_NONINVERTING_INPUT_PB0_PE9 CS_CMPXPSEL(0) /*!< CMP noninverting input PB0 for CMP0 or PE9 for CMP1 */
#define CMP_NONINVERTING_INPUT_PB2_PE11 CS_CMPXPSEL(1) /*!< CMP noninverting input PB2 for CMP0 or PE11 for CMP1 */
/* CMP output polarity*/
#define CS_CMPXPL(regval) (BIT(3) & ((uint32_t)(regval) << 3U))
#define CMP_OUTPUT_POLARITY_NONINVERTED CS_CMPXPL(0) /*!< CMP output not inverted */
#define CMP_OUTPUT_POLARITY_INVERTED CS_CMPXPL(1) /*!< CMP output inverted */
/* CMP blanking suorce */
#define CS_CMPXBLK(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U))
#define CMP_BLANKING_NONE CS_CMPXBLK(0) /*!< CMP no blanking source */
#define CMP_BLANKING_TIMER0_OC0 CS_CMPXBLK(1) /*!< CMP TIMER0_CH0 output compare signal selected as blanking source */
#define CMP_BLANKING_TIMER1_OC2 CS_CMPXBLK(2) /*!< CMP TIMER1_CH2 output compare signal selected as blanking source */
#define CMP_BLANKING_TIMER2_OC2 CS_CMPXBLK(3) /*!< CMP TIMER2_CH2 output compare signal selected as blanking source */
#define CMP_BLANKING_TIMER2_OC3 CS_CMPXBLK(4) /*!< CMP TIMER2_CH3 output compare signal selected as blanking source */
#define CMP_BLANKING_TIMER7_OC0 CS_CMPXBLK(5) /*!< CMP TIMER7_CH0 output compare signal selected as blanking source */
#define CMP_BLANKING_TIMER14_OC0 CS_CMPXBLK(6) /*!< CMP TIMER14_CH0 output compare signal selected as blanking source */
/* comparator output level */
#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001U) /*!< comparator output high */
#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000U) /*!< comparator output low */
/* CMP alternate output ports */
#define CMP_AFSE_GPIO_PA6 CMP_SR_AFSE_PA6 /*!< CMP alternate GPIO PA6 */
#define CMP_AFSE_GPIO_PA8 CMP_SR_AFSE_PA8 /*!< CMP alternate GPIO PA8 */
#define CMP_AFSE_GPIO_PB12 CMP_SR_AFSE_PB12 /*!< CMP alternate GPIO PB12 */
#define CMP_AFSE_GPIO_PE6 CMP_SR_AFSE_PE6 /*!< CMP alternate GPIO PE6 */
#define CMP_AFSE_GPIO_PE15 CMP_SR_AFSE_PE15 /*!< CMP alternate GPIO PE15 */
#define CMP_AFSE_GPIO_PG2 CMP_SR_AFSE_PG2 /*!< CMP alternate GPIO PG2 */
#define CMP_AFSE_GPIO_PG3 CMP_SR_AFSE_PG3 /*!< CMP alternate GPIO PG3 */
#define CMP_AFSE_GPIO_PG4 CMP_SR_AFSE_PG4 /*!< CMP alternate GPIO PG4 */
#define CMP_AFSE_GPIO_PK0 CMP_SR_AFSE_PK0 /*!< CMP alternate GPIO PK0 */
#define CMP_AFSE_GPIO_PK1 CMP_SR_AFSE_PK1 /*!< CMP alternate GPIO PK1*/
#define CMP_AFSE_GPIO_PK2 CMP_SR_AFSE_PK2 /*!< CMP alternate GPIO PK2 */
/* CMP flag definitions */
#define CMP_FLAG_COMPARE CMP_STAT_CMP0IF /*!< CMP compare flag */
/* CMP interrupt definitions */
#define CMP_INT_COMPARE CMP_CS_CMPXINTEN /*!< CMP compare interrupt */
/* CMP interrupt flag */
#define CMP_INT_FLAG_COMPARE CMP_STAT_CMP0IF /*!< CMP interrupt flag */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check CMP operating mode */
#define NOT_CMP_OPERATING_MODE(operating_mode) (((operating_mode) != CMP_MODE_HIGHSPEED) && ((operating_mode) != CMP_MODE_MIDDLESPEED) && \
((operating_mode) != CMP_MODE_VERYLOWSPEED))
/* check CMP output hysteresis */
#define NOT_CMP_OUTPUT_HYSTERESIS(output_hysteresis) (((output_hysteresis) != CMP_HYSTERESIS_NO) && ((output_hysteresis) != CMP_HYSTERESIS_LOW) && \
((output_hysteresis) != CMP_HYSTERESIS_MIDDLE) && ((output_hysteresis) != CMP_HYSTERESIS_HIGH))
/* check CMP inverting input */
#define NOT_CMP_INVERTING_INPUT(inverting_input) (((inverting_input) != CMP_INVERTING_INPUT_1_4VREFINT) && ((inverting_input) != CMP_INVERTING_INPUT_1_2VREFINT) && \
((inverting_input) != CMP_INVERTING_INPUT_3_4VREFINT) && ((inverting_input) != CMP_INVERTING_INPUT_VREFINT) && \
((inverting_input) != CMP_INVERTING_INPUT_DAC0_OUT0) && ((inverting_input) != CMP_INVERTING_INPUT_DAC0_OUT1) && \
((inverting_input) != CMP_INVERTING_INPUT_PB1_PE10) && ((inverting_input) != CMP_INVERTING_INPUT_PC4_PE7))
/* check CMP noninverting input */
#define NOT_CMP_NONINVERTING_INPUT(noninverting_input) (((noninverting_input) != CMP_NONINVERTING_INPUT_PB0_PE9) && ((noninverting_input) != CMP_NONINVERTING_INPUT_PB2_PE11))
/* check CMP output polarity */
#define NOT_CMP_OUTPUT_POLARITY(output_polarity) (((output_polarity) != CMP_OUTPUT_POLARITY_NONINVERTED) && ((output_polarity) != CMP_OUTPUT_POLARITY_INVERTED))
/* check CMP output selection */
#define NOT_CMP_OUTPUT_SELECTION(output_selection) (((output_selection) != CMP_OUTPUT_NONE) && ((output_selection) != CMP_OUTPUT_TIMER0_BKIN) && \
((output_selection) != CMP_OUTPUT_TIMER0_IC0) && ((output_selection) != CMP_OUTPUT_TIMER0_OCPRECLR) && \
((output_selection) != CMP_OUTPUT_TIMER1_IC3) && ((output_selection) != CMP_OUTPUT_TIMER1_OCPRECLR) && \
((output_selection) != CMP_OUTPUT_TIMER2_IC0) && ((output_selection) != CMP_OUTPUT_TIMER2_OCPRECLR))
#define NOT_CMP_AFSE_GPIO_PIN(cmp_output_sel) (((cmp_output_sel) != CMP_AFSE_GPIO_PA6) && ((cmp_output_sel) != CMP_AFSE_GPIO_PA8) && \
((cmp_output_sel) != CMP_AFSE_GPIO_PB12) && ((cmp_output_sel) != CMP_AFSE_GPIO_PE6) && \
((cmp_output_sel) != CMP_AFSE_GPIO_PE15) && ((cmp_output_sel) != CMP_AFSE_GPIO_PG2) && \
((cmp_output_sel) != CMP_AFSE_GPIO_PG3) && ((cmp_output_sel) != CMP_AFSE_GPIO_PG4) && \
((cmp_output_sel) != CMP_AFSE_GPIO_PK0) && ((cmp_output_sel) != CMP_AFSE_GPIO_PK1) && \
((cmp_output_sel) != CMP_AFSE_GPIO_PK2))
/* check CMP blanking source selection */
#define NOT_CMP_BLK_SOURCE_SEL(blanking_source) (((blanking_source_selection) != CMP_BLANKING_NONE) && ((blanking_source_selection) != CMP_BLANKING_TIMER0_OC0) && \
((blanking_source_selection) != CMP_BLANKING_TIMER1_OC2) && ((blanking_source_selection) != CMP_BLANKING_TIMER2_OC2) && \
((blanking_source_selection) != CMP_BLANKING_TIMER2_OC3) && ((blanking_source_selection) != CMP_BLANKING_TIMER7_OC0) && \
((blanking_source_selection) != CMP_BLANKING_TIMER14_OC0))
/* check CMP falg */
#define NOT_CMP_FLAG(flag) ((flag) != CMP_FLAG_COMPARE)
/* check CMP interrupt */
#define NOT_CMP_INTERRUPT(interrupt) ((interrupt) != CMP_INT_COMPARE)
/* check CMP interrupt flag */
#define NOT_CMP_INTERRUPT_FLAG(flag) ((flag) != CMP_INT_FLAG_COMPARE)
#endif
/* function declarations */
/* initialization functions */
/* CMP deinit */
void cmp_deinit(cmp_enum cmp_periph);
/* CMP mode init */
void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis);
/* CMP noninverting input select */
void cmp_noninverting_input_select(cmp_enum cmp_periph, uint32_t noninverting_input);
/* CMP output init */
void cmp_output_init(cmp_enum cmp_periph, uint32_t output_polarity);
/* config comparator output port */
void cmp_output_mux_config(cmp_enum cmp_periph, uint32_t cmp_output_sel);
/* CMP output blanking function init */
void cmp_blanking_init(cmp_enum cmp_periph,uint32_t blanking_source_selection);
/* enable functions */
/* enable CMP */
void cmp_enable(cmp_enum cmp_periph);
/* disable CMP */
void cmp_disable(cmp_enum cmp_periph);
/* enable the window mode */
void cmp_window_enable(void);
/* disable the window mode */
void cmp_window_disable(void);
/* lock the CMP */
void cmp_lock_enable(cmp_enum cmp_periph);
/* enable the voltage scaler */
void cmp_voltage_scaler_enable(cmp_enum cmp_periph);
/* disable the voltage scaler */
void cmp_voltage_scaler_disable(cmp_enum cmp_periph);
/* enable the scaler bridge */
void cmp_scaler_bridge_enable(cmp_enum cmp_periph);
/* disable the scaler bridge */
void cmp_scaler_bridge_disable(cmp_enum cmp_periph);
/* get state related functions */
/* get output level */
uint32_t cmp_output_level_get(cmp_enum cmp_periph);
/* flag and interrupt functions */
/* get CMP flag */
FlagStatus cmp_flag_get(cmp_enum cmp_periph, uint32_t flag);
/* clear CMP flag */
void cmp_flag_clear(cmp_enum cmp_periph, uint32_t flag);
/* enable CMP interrupt */
void cmp_interrupt_enable(cmp_enum cmp_periph, uint32_t interrupt);
/* disable CMP interrupt */
void cmp_interrupt_disable(cmp_enum cmp_periph, uint32_t interrupt);
/* get CMP interrupt flag */
FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag);
/* clear CMP interrupt flag */
void cmp_interrupt_flag_clear(cmp_enum cmp_periph, uint32_t flag);
#endif /* GD32H75E_CMP_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_crc.h
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/*!
\file gd32h75e_crc.h
\brief definitions for the CRC
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_CRC_H
#define GD32H75E_CRC_H
#include "gd32h75e.h"
/* CRC definitions */
#define CRC CRC_BASE /*!< CRC bsae address */
/* registers definitions */
#define CRC_DATA REG32((CRC) + 0x00000000U) /*!< CRC data register */
#define CRC_FDATA REG32((CRC) + 0x00000004U) /*!< CRC free data register */
#define CRC_CTL REG32((CRC) + 0x00000008U) /*!< CRC control register */
#define CRC_IDATA REG32((CRC) + 0x00000010U) /*!< CRC initialization data register */
#define CRC_POLY REG32((CRC) + 0x00000014U) /*!< CRC polynomial register */
/* bits definitions */
/* CRC_DATA */
#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */
/* CRC_FDATA */
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
/* CRC_CTL */
#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */
#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */
#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */
#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */
/* CRC_INIT */
#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */
/* CRC_POLY */
#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */
/* constants definitions */
/* size of polynomial function */
#define CTL_PS(regval) (BITS(3, 4) & ((uint32_t)(regval) << 3))
#define CRC_CTL_PS_32 ((uint8_t)CTL_PS(0)) /*!< 32-bit polynomial for CRC calculation */
#define CRC_CTL_PS_16 ((uint8_t)CTL_PS(1)) /*!< 16-bit polynomial for CRC calculation */
#define CRC_CTL_PS_8 ((uint8_t)CTL_PS(2)) /*!< 8-bit polynomial for CRC calculation */
#define CRC_CTL_PS_7 ((uint8_t)CTL_PS(3)) /*!< 7-bit polynomial for CRC calculation */
/* input data reverse function */
#define CTL_REV_I(regval) (BITS(5, 6) & ((uint32_t)(regval) << 5))
#define CRC_INPUT_DATA_NOT ((uint8_t)CTL_REV_I(0)) /*!< input data not reverse */
#define CRC_INPUT_DATA_BYTE ((uint8_t)CTL_REV_I(1)) /*!< input data reversed by byte type */
#define CRC_INPUT_DATA_HALFWORD ((uint8_t)CTL_REV_I(2)) /*!< input data reversed by half-word type */
#define CRC_INPUT_DATA_WORD ((uint8_t)CTL_REV_I(3)) /*!< input data reversed by word type */
/* input data format */
#define INPUT_FORMAT_WORD 0U /*!< input data in word format */
#define INPUT_FORMAT_HALFWORD 1U /*!< input data in half-word format */
#define INPUT_FORMAT_BYTE 2U /*!< input data in byte format */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check CRC input data reverse */
#define NOT_CRC_INPUT_DATA_REV(reverse) (((reverse) != CRC_INPUT_DATA_NOT) && ((reverse) != CRC_INPUT_DATA_BYTE) && \
((reverse) != CRC_INPUT_DATA_HALFWORD)&& ((reverse) != CRC_INPUT_DATA_WORD))
/* check CRC POLYNOMIAL size */
#define NOT_CRC_POLY_SIZE(size) (((size) != CRC_CTL_PS_32) && ((size) != CRC_CTL_PS_16) && \
((size) != CRC_CTL_PS_8)&& ((size) != CRC_CTL_PS_7))
/* check CRC input data format */
#define NOT_CRC_INPUT_DATA_FORMAT(format) (((format) != INPUT_FORMAT_WORD) && ((format) != INPUT_FORMAT_HALFWORD) && \
((format) != INPUT_FORMAT_BYTE))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* deinit CRC calculation unit */
void crc_deinit(void);
/* write the initial value register */
void crc_init_data_register_write(uint32_t init_data);
/* read the data register */
uint32_t crc_data_register_read(void);
/* read the free data register */
uint8_t crc_free_data_register_read(void);
/* write the free data register */
void crc_free_data_register_write(uint8_t free_data);
/* disable the reverse operation of output data */
void crc_reverse_output_data_disable(void);
/* enable the reverse operation of output data */
void crc_reverse_output_data_enable(void);
/* configure the CRC input data function */
void crc_input_data_reverse_config(uint32_t data_reverse);
/* reset data register to the value of initialization data register */
void crc_data_register_reset(void);
/* configure the CRC size of polynomial function */
void crc_polynomial_size_set(uint32_t poly_size);
/* configure the CRC polynomial value function */
void crc_polynomial_set(uint32_t poly);
/* CRC calculate single data */
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format);
/* CRC calculate a data array */
uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format);
#endif /* GD32H75E_CRC_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_ctc.h
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/*!
\file gd32h75e_ctc.h
\brief definitions for the CTC
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_CTC_H
#define GD32H75E_CTC_H
#include "gd32h75e.h"
/* CTC definitions */
#define CTC CTC_BASE
/* registers definitions */
#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
/* bits definitions */
/* CTC_CTL0 */
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */
#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */
#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */
#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */
/* CTC_CTL1 */
#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
/* CTC_STAT */
#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */
#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */
#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */
#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */
#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */
#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */
#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */
#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */
#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */
/* CTC_INTC */
#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */
#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */
#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */
#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */
/* constants definitions */
/* hardware automatically trim mode definitions */
#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/
/* reference signal source polarity definitions */
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
/* reference signal source selection definitions */
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */
/* reference signal source prescaler definitions */
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */
#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */
#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */
#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */
#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */
#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */
#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */
#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
/* CTC interrupt enable definitions */
#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */
#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
/* CTC interrupt source definitions */
#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
/* CTC flag definitions */
#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */
#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */
#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */
#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check trim value */
#define NOT_CTC_TRIM_VALUE(value) (((value) > 0x3FU))
/* check hard mode */
#define NOT_CTC_HARD_MODE(hard_mode) (((hard_mode) != CTC_HARDWARE_TRIM_MODE_ENABLE) && ((hard_mode) != CTC_HARDWARE_TRIM_MODE_DISABLE))
/* check reference signal source polarity */
#define NOT_CTC_REFSOURCE_POLARITY(polarity) (((polarity) != CTC_REFSOURCE_POLARITY_FALLING) && ((polarity) != CTC_REFSOURCE_POLARITY_RISING))
/* check reference signal source */
#define NOT_CTC_REFSOURCE(refs) (((refs) != CTC_REFSOURCE_GPIO) && ((refs) != CTC_REFSOURCE_LXTAL))
/* check reference signal source prescaler */
#define NOT_CTC_REFSOURCE_PSC(prescaler) (((prescaler) != CTC_REFSOURCE_PSC_OFF) && ((prescaler) != CTC_REFSOURCE_PSC_DIV2) && \
((prescaler) != CTC_REFSOURCE_PSC_DIV4) && ((prescaler) != CTC_REFSOURCE_PSC_DIV8) && \
((prescaler) != CTC_REFSOURCE_PSC_DIV16) && ((prescaler) != CTC_REFSOURCE_PSC_DIV32) && \
((prescaler) != CTC_REFSOURCE_PSC_DIV64) && ((prescaler) != CTC_REFSOURCE_PSC_DIV128))
/* check CTC flag */
#define NOT_CTC_FLAG(flag) (((flag) != CTC_FLAG_CKOK) && ((flag) != CTC_FLAG_CKWARN) && ((flag) != CTC_FLAG_ERR) && ((flag) != CTC_FLAG_EREF) && \
((flag) != CTC_FLAG_CKERR) && ((flag) != CTC_FLAG_REFMISS) && ((flag) != CTC_FLAG_TRIMERR))
/* check CTC interrupt enable source */
#define NOT_CTC_INTERRUPT_SOURCE(interrupt) (((interrupt) != CTC_INT_CKOK) && ((interrupt) != CTC_INT_CKWARN) && \
((interrupt) != CTC_INT_ERR) && ((interrupt) != CTC_INT_EREF))
/* check CTC interrupt flag */
#define NOT_CTC_INT_FLAG(flag) (((flag) != CTC_INT_FLAG_CKOK) && ((flag) != CTC_INT_FLAG_CKWARN) && ((flag) != CTC_INT_FLAG_ERR) && ((flag) != CTC_INT_FLAG_EREF) && \
((flag) != CTC_INT_FLAG_CKERR) && ((flag) != CTC_INT_FLAG_REFMISS) && ((flag) != CTC_INT_FLAG_TRIMERR))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* reset ctc clock trim controller */
void ctc_deinit(void);
/* enable CTC trim counter */
void ctc_counter_enable(void);
/* disable CTC trim counter */
void ctc_counter_disable(void);
/* configure the IRC48M trim value */
void ctc_irc48m_trim_value_config(uint8_t trim_value);
/* generate software reference source sync pulse */
void ctc_software_refsource_pulse_generate(void);
/* configure hardware automatically trim mode */
void ctc_hardware_trim_mode_config(uint32_t hardmode);
/* configure reference signal source polarity */
void ctc_refsource_polarity_config(uint32_t polarity);
/* select reference signal source */
void ctc_refsource_signal_select(uint32_t refs);
/* configure reference signal source prescaler */
void ctc_refsource_prescaler_config(uint32_t prescaler);
/* configure clock trim base limit value */
void ctc_clock_limit_value_config(uint8_t limit_value);
/* configure CTC counter reload value */
void ctc_counter_reload_value_config(uint16_t reload_value);
/* read CTC counter capture value when reference sync pulse occurred */
uint16_t ctc_counter_capture_value_read(void);
/* read CTC trim counter direction when reference sync pulse occurred */
FlagStatus ctc_counter_direction_read(void);
/* read CTC counter reload value */
uint16_t ctc_counter_reload_value_read(void);
/* read the IRC48M trim value */
uint8_t ctc_irc48m_trim_value_read(void);
/* interrupt & flag functions */
/* get CTC flag */
FlagStatus ctc_flag_get(uint32_t flag);
/* clear CTC flag */
void ctc_flag_clear(uint32_t flag);
/* enable the CTC interrupt */
void ctc_interrupt_enable(uint32_t interrupt);
/* disable the CTC interrupt */
void ctc_interrupt_disable(uint32_t interrupt);
/* get CTC interrupt flag */
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
/* clear CTC interrupt flag */
void ctc_interrupt_flag_clear(uint32_t int_flag);
#endif /* GD32H75E_CTC_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_dac.h
+367
View File
@@ -0,0 +1,367 @@
/*!
\file gd32h75e_dac.h
\brief definitions for the DAC
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_DAC_H
#define GD32H75E_DAC_H
#include "gd32h75e.h"
/* DACx(x=0) definitions */
#define DAC0 (DAC_BASE)
/* registers definitions */
#define DAC_CTL0(dacx) REG32((dacx) + 0x00000000U) /*!< DACx control register 0 */
#define DAC_SWT(dacx) REG32((dacx) + 0x00000004U) /*!< DACx software trigger register */
#define DAC_OUT0_R12DH(dacx) REG32((dacx) + 0x00000008U) /*!< DACx_OUT0 12-bit right-aligned data holding register */
#define DAC_OUT0_L12DH(dacx) REG32((dacx) + 0x0000000CU) /*!< DACx_OUT0 12-bit left-aligned data holding register */
#define DAC_OUT0_R8DH(dacx) REG32((dacx) + 0x00000010U) /*!< DACx_OUT0 8-bit right-aligned data holding register */
#define DAC_OUT1_R12DH(dacx) REG32((dacx) + 0x00000014U) /*!< DACx_OUT1 12-bit right-aligned data holding register */
#define DAC_OUT1_L12DH(dacx) REG32((dacx) + 0x00000018U) /*!< DACx_OUT1 12-bit left-aligned data holding register */
#define DAC_OUT1_R8DH(dacx) REG32((dacx) + 0x0000001CU) /*!< DACx_OUT1 8-bit right-aligned data holding register */
#define DACC_R12DH(dacx) REG32((dacx) + 0x00000020U) /*!< DACx concurrent mode 12-bit right-aligned data holding register */
#define DACC_L12DH(dacx) REG32((dacx) + 0x00000024U) /*!< DACx concurrent mode 12-bit left-aligned data holding register */
#define DACC_R8DH(dacx) REG32((dacx) + 0x00000028U) /*!< DACx concurrent mode 8-bit right-aligned data holding register */
#define DAC_OUT0_DO(dacx) REG32((dacx) + 0x0000002CU) /*!< DACx_OUT0 data output register */
#define DAC_OUT1_DO(dacx) REG32((dacx) + 0x00000030U) /*!< DACx_OUT1 data output register */
#define DAC_STAT0(dacx) REG32((dacx) + 0x00000034U) /*!< DACx status register 0 */
#define DAC_CALR(dacx) REG32((dacx) + 0x00000038U) /*!< DACx calibration register */
#define DAC_MDCR(dacx) REG32((dacx) + 0x0000003CU) /*!< DACx mode control register */
#define DAC_SKSTR0(dacx) REG32((dacx) + 0x00000040U) /*!< DACx sample and keep sample time register 0 */
#define DAC_SKSTR1(dacx) REG32((dacx) + 0x00000044U) /*!< DACx sample and keep sample time register 1 */
#define DAC_SKKTR(dacx) REG32((dacx) + 0x00000048U) /*!< DACx sample and keep keep time register */
#define DAC_SKRTR(dacx) REG32((dacx) + 0x0000004CU) /*!< DACx sample and keep refresh time register */
/* bits definitions */
/* DAC_CTL0 */
#define DAC_CTL0_DEN0 BIT(0) /*!< DACx_OUT0 enable */
#define DAC_CTL0_DTEN0 BIT(1) /*!< DACx_OUT0 trigger enable */
#define DAC_CTL0_DTSEL0 BITS(2,3) /*!< DACx_OUT0 trigger selection */
#define DAC_CTL0_DWM0 BITS(6,7) /*!< DACx_OUT0 noise wave mode */
#define DAC_CTL0_DWBW0 BITS(8,11) /*!< DACx_OUT0 noise wave bit width */
#define DAC_CTL0_DDMAEN0 BIT(12) /*!< DACx_OUT0 DMA enable */
#define DAC_CTL0_DDUDRIE0 BIT(13) /*!< DACx_OUT0 DMA underrun interrupt enable */
#define DAC_CTL0_CALEN0 BIT(14) /*!< DACx_OUT0 calibration enable */
#define DAC_CTL0_DEN1 BIT(16) /*!< DACx_OUT1 enable bit */
#define DAC_CTL0_DTEN1 BIT(17) /*!< DACx_OUT1 trigger enable */
#define DAC_CTL0_DTSEL1 BITS(18,19) /*!< DACx_OUT1 trigger selection */
#define DAC_CTL0_DWM1 BITS(22,23) /*!< DACx_OUT1 noise wave mode */
#define DAC_CTL0_DWBW1 BITS(24,27) /*!< DACx_OUT1 noise wave bit width */
#define DAC_CTL0_DDMAEN1 BIT(28) /*!< DACx_OUT1 DMA enable */
#define DAC_CTL0_DDUDRIE1 BIT(29) /*!< DACx_OUT1 DMA underrun interrupt enable */
#define DAC_CTL0_CALEN1 BIT(30) /*!< DACx_OUT1 calibration enable */
/* DAC_SWT */
#define DAC_SWT_SWTR0 BIT(0) /*!< DACx_OUT0 software trigger */
#define DAC_SWT_SWTR1 BIT(1) /*!< DACx_OUT1 software trigger */
/* DAC0_R12DH */
#define DAC_OUT0_DH_R12 BITS(0,11) /*!< DACx_OUT0 12-bit right-aligned data */
/* DAC0_L12DH */
#define DAC_OUT0_DH_L12 BITS(4,15) /*!< DACx_OUT0 12-bit left-aligned data */
/* DAC0_R8DH */
#define DAC_OUT0_DH_R8DH BITS(0,7) /*!< DACx_OUT0 8-bit right-aligned data */
/* DAC1_R12DH */
#define DAC_OUT1_DH_R12 BITS(0,11) /*!< DACx_OUT1 12-bit right-aligned data */
/* DAC1_L12DH */
#define DAC_OUT1_DH_L12 BITS(4,15) /*!< DACx_OUT1 12-bit left-aligned data */
/* DAC1_R8DH */
#define DAC_OUT1_DH_R8 BITS(0,7) /*!< DACx_OUT1 8-bit right-aligned data */
/* DACC_R12DH */
#define DACC_OUT0_DH_R12 BITS(0,11) /*!< DAC concurrent mode DACx_OUT0 12-bit right-aligned data */
#define DACC_OUT1_DH_R12 BITS(16,27) /*!< DAC concurrent mode DACx_OUT1 12-bit right-aligned data */
/* DACC_L12DH */
#define DACC_OUT0_DH_L12 BITS(4,15) /*!< DAC concurrent mode DACx_OUT0 12-bit left-aligned data */
#define DACC_OUT1_DH_L12 BITS(20,31) /*!< DAC concurrent mode DACx_OUT1 12-bit left-aligned data */
/* DACC_R8DH */
#define DACC_OUT0_DH_R8 BITS(0,7) /*!< DAC concurrent mode DACx_OUT0 8-bit right-aligned data */
#define DACC_OUT1_DH_R8 BITS(8,15) /*!< DAC concurrent mode DACx_OUT1 8-bit right-aligned data */
/* DAC0_DO */
#define DAC_OUT0_DO_BITS BITS(0,11) /*!< DACx_OUT0 12-bit output data */
/* DAC1_DO */
#define DAC_OUT1_DO_BITS BITS(0,11) /*!< DACx_OUT1 12-bit output data */
/* DAC_STAT0 */
#define DAC_STAT0_DDUDR0 BIT(13) /*!< DACx_OUT0 DMA underrun flag */
#define DAC_STAT0_CALF0 BIT(14) /*!< DACx_OUT0 calibration offset flag */
#define DAC_STAT0_BWT0 BIT(15) /*!< DACx_OUT0 SKSTR0 writing flag */
#define DAC_STAT0_DDUDR1 BIT(29) /*!< DACx_OUT1 DMA underrun flag */
#define DAC_STAT0_CALF1 BIT(30) /*!< DACx_OUT1 calibration offset flag */
#define DAC_STAT0_BWT1 BIT(31) /*!< DACx_OUT1 SKSTR1 writing flag */
/* DAC_CALR */
#define DAC_CALR_OTV0 BITS(0,4) /*!< DACx_OUT0 offset calibration value */
#define DAC_CALR_OTV1 BITS(16,20) /*!< DACx_OUT1 offset calibration value */
/* DAC_MDCR */
#define DAC_MDCR_MODE0 BITS(0,2) /*!< DACx_OUT0 mode */
#define DAC_MDCR_MODE1 BITS(16,18) /*!< DACx_OUT1 mode */
/* DAC_SKSTR0 */
#define DAC_SKSTR0_TSAMP0 BITS(0,9) /*!< DACx_OUT0 sample time */
/* DAC_SKSTR1 */
#define DAC_SKSTR1_TSAMP1 BITS(0,9) /*!< DACx_OUT1 sample time */
/* DAC_SKKTR */
#define DAC_SKKTR_TKEEP0 BITS(0,9) /*!< DACx_OUT0 keep time */
#define DAC_SKKTR_TKEEP1 BITS(16,25) /*!< DACx_OUT1 keep time */
/* DAC_SKRTR */
#define DAC_SKRTR_TREF0 BITS(0,7) /*!< DACx_OUT0 refresh time */
#define DAC_SKRTR_TREF1 BITS(16,23) /*!< DACx_OUT1 refresh time */
/* constants definitions */
/* DAC trigger source */
#define CTL0_DTSEL(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U))
#define DAC_TRIGGER_EXTERNAL CTL0_DTSEL(0) /*!< external trigger selected from TRIGSEL */
#define DAC_TRIGGER_SOFTWARE CTL0_DTSEL(1) /*!< software trigger */
/* DAC noise wave mode */
#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disabled */
#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */
#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */
/* DAC noise wave bit width */
#define DWBW(regval) (BITS(8, 11) & ((uint32_t)(regval) << 8))
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
/* unmask LFSR bits in DAC LFSR noise mode */
#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
/* triangle amplitude in DAC triangle noise mode */
#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
/* DAC data alignment */
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< 12-bit right-aligned data */
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< 12-bit left-aligned data */
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< 8-bit right-aligned data */
/* DAC mode */
#define MODE(regval) (BITS(0,2) & ((uint32_t)(regval)))
#define NORMAL_PIN_BUFFON MODE(0) /*!< DACx_OUTy work in normal mode and connect to external pin with buffer enable */
#define NORMAL_PIN_PERIPH_BUFFON MODE(1) /*!< DACx_OUTy work in normal mode and connect to external pin and on chip peripherals with buffer enable */
#define NORMAL_PIN_BUFFOFF MODE(2) /*!< DACx_OUTy work in normal mode and connect to external pin with buffer disable */
#define NORMAL_PERIPH_BUFFOFF MODE(3) /*!< DACx_OUTy work in normal mode and connect to on chip peripherals with buffer disable */
#define SAMPLEKEEP_PIN_BUFFON MODE(4) /*!< DACx_OUTy work in sample and keep mode and connect to external pin with buffer enable */
#define SAMPLEKEEP_PIN_PERIPH_BUFFON MODE(5) /*!< DACx_OUTy work in sample and keep mode and connect to external pin and on chip peripherals with buffer enable */
#define SAMPLEKEEP_PIN_BUFFOFF MODE(6) /*!< DACx_OUTy work in sample and keep mode and connect to external pin and on chip peripherals with buffer disable */
#define SAMPLEKEEP_PERIPH_BUFFOFF MODE(7) /*!< DACx_OUTy work in sample and keep mode and connect to on chip peripherals with buffer disable */
/* DAC output channel definitions */
#define DAC_OUT0 ((uint8_t)0x00U) /*!< DACx_OUT0 channel */
#define DAC_OUT1 ((uint8_t)0x01U) /*!< DACx_OUT1 channel */
/* DAC interrupt */
#define DAC_INT_DDUDR0 DAC_CTL0_DDUDRIE0 /*!< DACx_OUT0 DMA underrun interrupt enable */
#define DAC_INT_DDUDR1 DAC_CTL0_DDUDRIE1 /*!< DACx_OUT1 DMA underrun interrupt enable */
/* DAC interrupt flag */
#define DAC_INT_FLAG_DDUDR0 DAC_STAT0_DDUDR0 /*!< DACx_OUT0 DMA underrun interrupt flag */
#define DAC_INT_FLAG_DDUDR1 DAC_STAT0_DDUDR1 /*!< DACx_OUT1 DMA underrun interrupt flag */
/* DAC flags */
#define DAC_FLAG_DDUDR0 DAC_STAT0_DDUDR0 /*!< DACx_OUT0 DMA underrun flag */
#define DAC_FLAG_CALF0 DAC_STAT0_CALF0 /*!< DACx_OUT0 calibration offset flag */
#define DAC_FLAG_BWT0 DAC_STAT0_BWT0 /*!< DACx_OUT0 sample and keep wtire enable flag */
#define DAC_FLAG_DDUDR1 DAC_STAT0_DDUDR1 /*!< DACx_OUT1 DMA underrun flag */
#define DAC_FLAG_CALF1 DAC_STAT0_CALF1 /*!< DACx_OUT1 calibration offset flag */
#define DAC_FLAG_BWT1 DAC_STAT0_BWT1 /*!< DACx_OUT1 sample and keep wtire enable flag */
#define NOT_DAC_PERIPH(dac_periph) (((dac_periph) != DAC0))
#define NOT_DAC_OUT(dac_out) (((dac_out) != DAC_OUT0) && ((dac_out) != DAC_OUT1))
#define NOT_DAC_MODE(mode) (((mode) != NORMAL_PIN_BUFFON) && ((mode) != NORMAL_PIN_PERIPH_BUFFON) && \
((mode) != NORMAL_PIN_BUFFOFF) && ((mode) != NORMAL_PERIPH_BUFFOFF) && \
((mode) != SAMPLEKEEP_PIN_BUFFON) && ((mode) != SAMPLEKEEP_PIN_PERIPH_BUFFON) && \
((mode) != SAMPLEKEEP_PIN_BUFFOFF) && ((mode) != SAMPLEKEEP_PERIPH_BUFFOFF))
/* check the counter value */
#define DAC_TRIM_HIGH_VALUE ((uint32_t)0x0000001FU) /*!< maximum psc value */
#define NOT_DAC_TRIM_VALUE(trim_value) (DAC_TRIM_HIGH_VALUE < (trim_value))
#define NOT_DAC_ALIGN(dac_align) (((dac_align) != DAC_ALIGN_12B_R) && ((dac_align) != DAC_ALIGN_12B_L) && \
((dac_align) != DAC_ALIGN_8B_R))
#define NOT_DAC_TRIGGER(triggersource) (((triggersource) != DAC_TRIGGER_EXTERNAL) && ((triggersource) != DAC_TRIGGER_SOFTWARE))
#define NOT_DAC_WAVE_MODE(wave_mode) (((wave_mode) != DAC_WAVE_DISABLE) && ((wave_mode) != DAC_WAVE_MODE_LFSR) && \
((wave_mode) != DAC_WAVE_MODE_TRIANGLE))
#define NOT_DAC_UNMASK_BITS(unmask_bits) (((unmask_bits) != DAC_LFSR_BIT0) && ((unmask_bits) != DAC_LFSR_BITS1_0) && \
((unmask_bits) != DAC_LFSR_BITS2_0) && ((unmask_bits) != DAC_LFSR_BITS3_0) && \
((unmask_bits) != DAC_LFSR_BITS4_0) && ((unmask_bits) != DAC_LFSR_BITS5_0) && \
((unmask_bits) != DAC_LFSR_BITS6_0) && ((unmask_bits) != DAC_LFSR_BITS7_0) && \
((unmask_bits) != DAC_LFSR_BITS8_0) && ((unmask_bits) != DAC_LFSR_BITS9_0) && \
((unmask_bits) != DAC_LFSR_BITS10_0) && ((unmask_bits) != DAC_LFSR_BITS11_0))
#define NOT_DAC_TRIANGLE_AMPLITUDE(amplitude) (((amplitude) != DAC_TRIANGLE_AMPLITUDE_1) && ((amplitude) != DAC_TRIANGLE_AMPLITUDE_3) && \
((amplitude) != DAC_TRIANGLE_AMPLITUDE_7) && ((amplitude) != DAC_TRIANGLE_AMPLITUDE_15) && \
((amplitude) != DAC_TRIANGLE_AMPLITUDE_31) && ((amplitude) != DAC_TRIANGLE_AMPLITUDE_63) && \
((amplitude) != DAC_TRIANGLE_AMPLITUDE_127) && ((amplitude) != DAC_TRIANGLE_AMPLITUDE_255) && \
((amplitude) != DAC_TRIANGLE_AMPLITUDE_511) && ((amplitude) != DAC_TRIANGLE_AMPLITUDE_1023) && \
((amplitude) != DAC_TRIANGLE_AMPLITUDE_2047) && ((amplitude) != DAC_TRIANGLE_AMPLITUDE_4095))
#define DAC_SAMPLE_TIME_HIGH_VALUE ((uint32_t)0x000001FFU) /*!< maximum psc value */
#define NOT_DAC_SAMPLE_TIME_VALUE(sample_time) (DAC_SAMPLE_TIME_HIGH_VALUE < (sample_time))
#define DAC_KEEP_TIME_HIGH_VALUE ((uint32_t)0x000001FFU) /*!< maximum psc value */
#define NOT_DAC_KEEP_TIME_VALUE(keep_time) (DAC_KEEP_TIME_HIGH_VALUE < (keep_time))
#define DAC_REFRESH_TIME_HIGH_VALUE ((uint32_t)0x000000FFU) /*!< maximum psc value */
#define NOT_DAC_REFRESH_TIME_VALUE(refresh_time) (DAC_REFRESH_TIME_HIGH_VALUE < (refresh_time))
#define NOT_DAC_FLAG(flag) (((flag) != DAC_FLAG_DDUDR0) && ((flag) != DAC_FLAG_CALF0) && \
((flag) != DAC_FLAG_BWT0) && ((flag) != DAC_FLAG_DDUDR1) && \
((flag) != DAC_FLAG_CALF1) && ((flag) != DAC_FLAG_BWT1))
#define NOT_DAC_INTERRUPT(interrupt) (((interrupt) != DAC_INT_DDUDR0) && ((interrupt) != DAC_INT_DDUDR1))
#define NOT_DAC_INT_FLAG(int_flag) (((int_flag) != DAC_INT_FLAG_DDUDR0) && ((int_flag) != DAC_INT_FLAG_DDUDR1))
/* function declarations */
/* DAC initialization functions */
/* deinitialize DAC */
void dac_deinit(uint32_t dac_periph);
/* enable DAC */
void dac_enable(uint32_t dac_periph, uint8_t dac_out);
/* disable DAC */
void dac_disable(uint32_t dac_periph, uint8_t dac_out);
/* enable DAC DMA function */
void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out);
/* disable DAC DMA function */
void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out);
/* DAC buffer functions */
/* configure DAC mode */
void dac_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t mode);
/* get the DACx trimming value */
uint32_t dac_trimming_value_get(uint32_t dac_periph, uint32_t dac_out);
/* set the DACx trimming value */
void dac_trimming_value_set(uint32_t dac_periph, uint32_t dac_out, uint32_t trim_value);
/* enable the DACx trimming */
void dac_trimming_enable(uint32_t dac_periph, uint32_t dac_out);
/* read and write operation functions */
/* get DAC output value */
uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out);
/* set DAC data holding register value */
void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data);
/* DAC trigger configuration */
/* enable DAC trigger */
void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out);
/* disable DAC trigger */
void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out);
/* configure DAC trigger source */
void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource);
/* enable DAC software trigger */
void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out);
/* DAC wave mode configuration */
/* configure DAC wave mode */
void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode);
/* configure DAC LFSR noise mode */
void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits);
/* configure DAC triangle noise mode */
void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude);
/* DAC concurrent mode configuration */
/* enable DAC concurrent mode */
void dac_concurrent_enable(uint32_t dac_periph);
/* disable DAC concurrent mode */
void dac_concurrent_disable(uint32_t dac_periph);
/* enable DAC concurrent software trigger */
void dac_concurrent_software_trigger_enable(uint32_t dac_periph);
/* set DAC concurrent mode data holding register value */
void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data0, uint16_t data1);
/* DAC sample and keep functions */
/* DAC sample and keep mode config */
void dac_sample_keep_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t sample_time, uint32_t keep_time, uint32_t refresh_time);
/* DAC interrupt and flag functions */
/* get DAC flag */
FlagStatus dac_flag_get(uint32_t dac_periph, uint32_t flag);
/* clear DAC flag */
void dac_flag_clear(uint32_t dac_periph, uint32_t flag);
/* enable DAC interrupt */
void dac_interrupt_enable(uint32_t dac_periph, uint32_t interrupt);
/* disable DAC interrupt */
void dac_interrupt_disable(uint32_t dac_periph, uint32_t interrupt);
/* get DAC interrupt flag */
FlagStatus dac_interrupt_flag_get(uint32_t dac_periph, uint32_t int_flag);
/* clear DAC interrupt flag */
void dac_interrupt_flag_clear(uint32_t dac_periph, uint32_t int_flag);
#endif /* GD32H75E_DAC_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_dbg.h
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/*!
\file gd32h75e_dbg.h
\brief definitions for the DBG
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_DBG_H
#define GD32H75E_DBG_H
#include "gd32h75e.h"
/* DBG definitions */
#define DBG DBG_BASE /*!< DBG base address */
/* registers definitions */
#define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */
#define DBG_CTL0 REG32(DBG + 0x00000004U) /*!< DBG control register 0 */
#define DBG_CTL1 REG32(DBG + 0x00000034U) /*!< DBG control register 1 */
#define DBG_CTL2 REG32(DBG + 0x0000003CU) /*!< DBG control register 2 */
#define DBG_CTL3 REG32(DBG + 0x0000004CU) /*!< DBG control register 3 */
#define DBG_CTL4 REG32(DBG + 0x00000054U) /*!< DBG control register 4 */
/* bits definitions */
/* DBG_ID */
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
/* DBG_CTL0 */
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
#define DBG_CTL0_TRACE_MODE BITS(18,19) /*!< trace pin mode selection */
#define DBG_CTL0_TRACECLKEN BIT(20) /*!< enable trace pin assignment */
/* DBG_CTL1 */
#define DBG_CTL1_WWDGT_HOLD BIT(6) /*!< debug WWDGT kept when core is halted */
/* DBG_CTL2 */
#define DBG_CTL2_TIMER1_HOLD BIT(0) /*!< debug TIMER1 kept when core is halted */
#define DBG_CTL2_TIMER2_HOLD BIT(1) /*!< debug TIMER2 kept when core is halted */
#define DBG_CTL2_TIMER3_HOLD BIT(2) /*!< debug TIMER3 kept when core is halted */
#define DBG_CTL2_TIMER4_HOLD BIT(3) /*!< debug TIMER4 kept when core is halted */
#define DBG_CTL2_TIMER5_HOLD BIT(4) /*!< debug TIMER5 kept when core is halted */
#define DBG_CTL2_TIMER6_HOLD BIT(5) /*!< debug TIMER6 kept when core is halted */
#define DBG_CTL2_TIMER22_HOLD BIT(6) /*!< debug TIMER22 kept when core is halted */
#define DBG_CTL2_TIMER23_HOLD BIT(7) /*!< debug TIMER23 kept when core is halted */
#define DBG_CTL2_TIMER50_HOLD BIT(10) /*!< debug TIMER50 kept when core is halted */
#define DBG_CTL2_TIMER51_HOLD BIT(11) /*!< debug TIMER51 kept when core is halted */
#define DBG_CTL2_I2C0_HOLD BIT(21) /*!< debug I2C0 kept when core is halted */
#define DBG_CTL2_I2C1_HOLD BIT(22) /*!< debug I2C1 kept when core is halted */
#define DBG_CTL2_I2C2_HOLD BIT(23) /*!< debug I2C2 kept when core is halted */
#define DBG_CTL2_I2C3_HOLD BIT(24) /*!< debug I2C3 kept when core is halted */
/* DBG_CTL3 */
#define DBG_CTL3_TIMER0_HOLD BIT(0) /*!< debug TIMER0 kept when core is halted */
#define DBG_CTL3_TIMER7_HOLD BIT(1) /*!< debug TIMER7 kept when core is halted */
#define DBG_CTL3_CAN0_HOLD BIT(2) /*!< debug CAN0 kept when core is halted */
#define DBG_CTL3_CAN1_HOLD BIT(3) /*!< debug CAN1 kept when core is halted */
#define DBG_CTL3_CAN2_HOLD BIT(4) /*!< debug CAN2 kept when core is halted */
#define DBG_CTL3_TIMER14_HOLD BIT(16) /*!< debug TIMER14 kept when core is halted */
#define DBG_CTL3_TIMER15_HOLD BIT(17) /*!< debug TIMER15 kept when core is halted */
#define DBG_CTL3_TIMER16_HOLD BIT(18) /*!< debug TIMER16 kept when core is halted */
#define DBG_CTL3_TIMER40_HOLD BIT(19) /*!< debug TIMER40 kept when core is halted */
#define DBG_CTL3_TIMER41_HOLD BIT(20) /*!< debug TIMER41 kept when core is halted */
#define DBG_CTL3_TIMER42_HOLD BIT(21) /*!< debug TIMER42 kept when core is halted */
#define DBG_CTL3_TIMER43_HOLD BIT(22) /*!< debug TIMER43 kept when core is halted */
#define DBG_CTL3_TIMER44_HOLD BIT(23) /*!< debug TIMER44 kept when core is halted */
/* DBG_CTL4 */
#define DBG_CTL4_RTC_HOLD BIT(16) /*!< debug RTC kept when core is halted */
#define DBG_CTL4_FWDGT_HOLD BIT(18) /*!< debug FWDGT kept when core is halted */
/* constants definitions */
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
/* define the peripheral debug hold bit position and its register index offset */
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
/* register index */
typedef enum
{
DBG_IDX_CTL1 = 0x34U, /*!< DBG control register 1 offset */
DBG_IDX_CTL2 = 0x3CU, /*!< DBG control register 2 offset */
DBG_IDX_CTL3 = 0x4CU, /*!< DBG control register 3 offset */
DBG_IDX_CTL4 = 0x54U /*!< DBG control register 4 offset */
}dbg_reg_idx;
/* peripherals hold bit */
typedef enum
{
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< debug WWDGT kept when core is halted */
DBG_I2C3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 24U), /*!< debug I2C3 kept when core is halted */
DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 23U), /*!< debug I2C2 kept when core is halted */
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 22U), /*!< debug I2C1 kept when core is halted */
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 21U), /*!< debug I2C0 kept when core is halted */
DBG_TIMER51_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 11U), /*!< debug TIMER51 kept when core is halted */
DBG_TIMER50_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 10U), /*!< debug TIMER50 kept when core is halted */
DBG_TIMER23_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 7U), /*!< debug TIMER23 kept when core is halted */
DBG_TIMER22_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 6U), /*!< debug TIMER22 kept when core is halted */
DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 5U), /*!< debug TIMER6 kept when core is halted */
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 4U), /*!< debug TIMER5 kept when core is halted */
DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 3U), /*!< debug TIMER4 kept when core is halted */
DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 2U), /*!< debug TIMER3 kept when core is halted */
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< debug TIMER2 kept when core is halted */
DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< debug TIMER1 kept when core is halted */
DBG_TIMER44_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 23U), /*!< debug TIMER44 kept when core is halted */
DBG_TIMER43_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 22U), /*!< debug TIMER43 kept when core is halted */
DBG_TIMER42_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 21U), /*!< debug TIMER42 kept when core is halted */
DBG_TIMER41_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 20U), /*!< debug TIMER41 kept when core is halted */
DBG_TIMER40_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 19U), /*!< debug TIMER40 kept when core is halted */
DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 18U), /*!< debug TIMER16 kept when core is halted */
DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 17U), /*!< debug TIMER15 kept when core is halted */
DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 16U), /*!< debug TIMER14 kept when core is halted */
DBG_CAN2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 4U), /*!< debug CAN2 kept when core is halted */
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 3U), /*!< debug CAN1 kept when core is halted */
DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 2U), /*!< debug CAN0 kept when core is halted */
DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 1U), /*!< debug TIMER7 kept when core is halted */
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 0U), /*!< debug TIMER0 kept when core is halted */
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL4, 18U), /*!< debug FWDGT kept when core is halted */
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL4, 16U) /*!< debug RTC kept when core is halted */
}dbg_periph_enum;
#define CTL0_TRACE_MODE(regval) (BITS(18,19) & ((uint32_t)(regval) << 18U))
#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */
#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check DBG LOW power parameter */
#define NOT_DBG_LOW_POWER_PARAMETER(parameter) (((parameter) != DBG_LOW_POWER_SLEEP) && ((parameter) != DBG_LOW_POWER_DEEPSLEEP) && \
((parameter) != DBG_LOW_POWER_STANDBY))
#define NOT_DBG_TRACE_MODE_PARAMETER(trace_mode) (((trace_mode) != TRACE_MODE_ASYNC) && ((trace_mode) != TRACE_MODE_SYNC_DATASIZE_1) && \
((trace_mode) != TRACE_MODE_SYNC_DATASIZE_2) && ((trace_mode) != TRACE_MODE_SYNC_DATASIZE_4))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* deinitialize the DBG */
void dbg_deinit(void);
/* read DBG_ID code register */
uint32_t dbg_id_get(void);
/*enable low power behavior when the mcu is in debug mode*/
void dbg_low_power_enable(uint32_t dbg_low_power);
/*disable low power behavior when the mcu is in debug mode*/
void dbg_low_power_disable(uint32_t dbg_low_power);
/*enable trace pin assignment*/
void dbg_trace_pin_enable(void);
/*disable trace pin assignment*/
void dbg_trace_pin_disable(void);
/* set trace pin mode */
void dbg_trace_pin_mode_set(uint32_t trace_mode);
/* enable peripheral behavior when the MCU is in debug mode */
void dbg_periph_enable(dbg_periph_enum dbg_periph);
/* disable peripheral behavior when the MCU is in debug mode */
void dbg_periph_disable(dbg_periph_enum dbg_periph);
#endif /* GD32H75E_DBG_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_dma.h
+1099
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828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_edout.h
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/*!
\file gd32h75e_edout.c
\brief definitions for the EDOUT
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_EDOUT_H
#define GD32H75E_EDOUT_H
#include "gd32h75e.h"
/* EDOUT definition */
#define EDOUT EDOUT_BASE /*!< EDOUT base address */
/* registers definitions */
#define EDOUT_CTL REG32((EDOUT) + 0x00000000U) /*!< EDOUT control register */
#define EDOUT_ENABLE REG32((EDOUT) + 0x00000004U) /*!< EDOUT enable register */
#define EDOUT_LOC REG32((EDOUT) + 0x00000008U) /*!< EDOUT location register */
#define EDOUT_OCNT REG32((EDOUT) + 0x0000000CU) /*!< EDOUT output counter register */
#define EDOUT_LCNT REG32((EDOUT) + 0x00000010U) /*!< EDOUT location counter register */
#define EDOUT_ZCR REG32((EDOUT) + 0x00000014U) /*!< EDOUT Z-phase configure register */
/* bits definitions */
/* EDOUT_CTL */
#define EDOUT_CTL_POL BIT(0) /*!< active polarity of the B-phase output signal selection */
/* EDOUT_ENABLE */
#define EDOUT_ENABLE_EDOUTEN BIT(0) /*!< EDOUT enable bit */
/* EDOUT_LOC */
#define EDOUT_LOC_LOCMAX BITS(0,15) /*!< maximum location value for one rotation */
/* EDOUT_OCNT */
#define EDOUT_OCNT_EDGC BITS(0,15) /*!< number of edges of the A-phase and the B-phase signal for the next update period */
#define EDOUT_OCNT_PDC BITS(16,31) /*!< phase difference between the A-phase and the B-phase signal for the next update period */
/* EDOUT_LCNT */
#define EDOUT_LCNT_LOCCNT BITS(0,15) /*!< current location value */
/* EDOUT_ZCR */
#define EDOUT_ZCR_ZOSP BITS(0,15) /*!< Z-phase output start location */
#define EDOUT_ZCR_ZOWH BITS(16,23) /*!< Z-phase output width */
#define EDOUT_ZCR_ZOMD BIT(24) /*!< Z-phase output mode */
/* constants definitions */
/* EDOUT_CTL */
#define EDOUT_POL_POSITIVE ((uint32_t)0x00000000U) /*!< active polarity is positive */
#define EDOUT_POL_NEGATIVE EDOUT_CTL_POL /*!< active polarity is negative */
/* EDOUT_ENABLE */
#define EDOUT_STATE_DISABLE ((uint32_t)0x00000000U) /*!< disable EDOUT */
#define EDOUT_STATE_ENABLE EDOUT_ENABLE_EDOUTEN /*!< enable EDOUT */
/* EDOUT_ZCR */
#define EDOUT_Z_OUTPUT_MODE0 ((uint32_t)0x00000000U) /*!< Z-phase output according to the current location */
#define EDOUT_Z_OUTPUT_MODE1 EDOUT_ZCR_ZOMD /*!< Z-phase output according to the number of edges */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check the B-phase active polarity */
#define NOT_EDOUT_B_PHASE_ACTIVE_POL(pol) (((pol) != EDOUT_POL_POSITIVE) && ((pol) != EDOUT_POL_NEGATIVE))
/* check the maximum location value */
#define LOCATION_LOW_VALUE ((uint32_t)0x0000000FU) /*!< minimum location value */
#define LOCATION_HIGH_VALUE ((uint32_t)0x0000FFFFU) /*!< maximum location value */
#define NOT_EDOUT_MAX_LOCATION_VAL(loc) ((LOCATION_HIGH_VALUE < (loc)) || \
(LOCATION_LOW_VALUE > (loc)) || \
(0U != (((loc) + 1U) % 4U)))
/* check the current location value */
#define NOT_EDOUT_CUR_LOCATION_VAL(loc) (LOCATION_HIGH_VALUE < (loc))
/* check the phase difference value */
#define PHASE_DIFF_LOW_VALUE ((uint16_t)0x0002U) /*!< minimum phase difference value */
#define NOT_EDOUT_PHASE_DIFF_VAL(phase_diff) (PHASE_DIFF_LOW_VALUE > (phase_diff))
/* check the Z-phase output mode */
#define NOT_EDOUT_Z_PHASE_OUTPUT_MODE(mode) (((mode) != EDOUT_Z_OUTPUT_MODE0) && ((mode) != EDOUT_Z_OUTPUT_MODE1))
/* check the Z-phase output start location value */
#define START_LOCATION_HIGH_VALUE ((uint32_t)0x0000FFFFU) /*!< maximum start location value */
#define NOT_EDOUT_Z_PHASE_START_LOCATION_VAL(loc) (START_LOCATION_HIGH_VALUE < (loc))
/* check the Z-phase output width value */
#define WIDTH_HIGH_VALUE ((uint32_t)0x0000FFFFU) /*!< maximum width value */
#define NOT_EDOUT_Z_PHASE_WIDTH_VAL(width) (WIDTH_HIGH_VALUE < (width))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* deinitialize EDOUT */
void edout_deinit(void);
/* initialize EDOUT */
void edout_init(uint32_t pol, uint32_t max_loc, uint32_t cur_loc);
/* enable EDOUT */
void edout_enable(void);
/* disable EDOUT */
void edout_disable(void);
/* set B-phase active polarity */
void edout_polarity_config(uint32_t pol);
/* set the maximum location value for one rotation */
void edout_max_location_value_config(uint32_t max_loc);
/* update the output counter, used to set the phase difference and the number of edges for the next update period */
void edout_output_counter_update(int16_t num_edges, uint16_t phase_diff);
/* set the current location value */
void edout_current_location_config(uint32_t cur_loc);
/* get the current location value */
uint16_t edout_current_location_get(void);
/* configure Z-phase output mode */
void edout_z_output_mode_config(uint32_t mode);
/* configure Z-phase output start location and width */
void edout_z_output_start_loc_and_width_config(uint32_t start_loc, uint32_t width);
#endif /* GD32H75E_EDOUT_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_efuse.h
+292
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/*!
\file gd32h75e_efuse.h
\brief definitions for the EFUSE
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_EFUSE_H
#define GD32H75E_EFUSE_H
#include "gd32h75e.h"
/* EFUSE definitions */
#define EFUSE EFUSE_BASE /*!< EFUSE base address */
/* registers definitions */
#define EFUSE_CTL REG32(EFUSE + 0x00000000U) /*!< EFUSE control register */
#define EFUSE_ADDR REG32(EFUSE + 0x00000004U) /*!< EFUSE address register */
#define EFUSE_STAT REG32(EFUSE + 0x0000000CU) /*!< EFUSE status register */
#define EFUSE_STATC REG32(EFUSE + 0x00000010U) /*!< EFUSE status clear register */
#define EFUSE_USER_CTL REG32(EFUSE + 0x00000014U) /*!< EFUSE user control register */
#define EFUSE_MCU_RSV REG32(EFUSE + 0x00000018U) /*!< EFUSE MCU reserved register */
#define EFUSE_DP0 REG32(EFUSE + 0x0000001CU) /*!< EFUSE debug password register 0 */
#define EFUSE_DP1 REG32(EFUSE + 0x00000020U) /*!< EFUSE debug password register 1 */
#define EFUSE_AES_KEY0 REG32(EFUSE + 0x00000024U) /*!< EFUSE firmware AES key register 0 */
#define EFUSE_AES_KEY1 REG32(EFUSE + 0x00000028U) /*!< EFUSE firmware AES key register 1 */
#define EFUSE_AES_KEY2 REG32(EFUSE + 0x0000002CU) /*!< EFUSE firmware AES key register 2 */
#define EFUSE_AES_KEY3 REG32(EFUSE + 0x00000030U) /*!< EFUSE firmware AES key register3 */
#define EFUSE_USER_DATA0 REG32(EFUSE + 0x00000034U) /*!< EFUSE user data register 0 */
#define EFUSE_USER_DATA1 REG32(EFUSE + 0x00000038U) /*!< EFUSE user data register 1 */
#define EFUSE_USER_DATA2 REG32(EFUSE + 0x0000003CU) /*!< EFUSE user data register 2 */
#define EFUSE_USER_DATA3 REG32(EFUSE + 0x00000040U) /*!< EFUSE user data register 3 */
/* bits definitions */
/* EFUSE_CTL */
#define EFUSE_CTL_EFSTR BIT(0) /*!< start EFUSE operation */
#define EFUSE_CTL_EFRW BIT(1) /*!< selection of EFUSE operation */
#define EFUSE_CTL_MPVEN BIT(15) /*!< enable bit for program-voltage monitoring function */
#define EFUSE_CTL_IAERRIE BIT(16) /*!< enable bit for illegal access error interrupt */
#define EFUSE_CTL_PGIE BIT(17) /*!< enable bit for program complete interrupt */
#define EFUSE_CTL_RDIE BIT(18) /*!< enable bit for read complete interrupt */
#define EFUSE_CTL_PVIE BIT(19) /*!< enable bit for program voltage setting error interrupt */
#define EFUSE_CTL_AES_KEY_CRC BITS(24,31) /*!< 8-bits CRC calculation result value of AES key bits */
/* EFUSE_ADDR */
#define EFUSE_ADDR_EFADDR BITS(0,9) /*!< read or write EFUSE data start address */
#define EFUSE_ADDR_EFSIZE BITS(10,14) /*!< read or write EFUSE data size */
/* EFUSE_STAT */
#define EFUSE_STAT_IAERRIF BIT(0) /*!< illegal access error flag */
#define EFUSE_STAT_PGIF BIT(1) /*!< program complete flag */
#define EFUSE_STAT_RDIF BIT(2) /*!< read complete flag */
#define EFUSE_STAT_PVIF BIT(3) /*!< program voltage setting error flag */
#define EFUSE_STAT_LDO_RDY BIT(4) /*!< EFUSE LDO ready signal */
/* EFUSE_STATC */
#define EFUSE_STATC_IAERRIC BIT(0) /*!< clear bit for illegal access error interrupt */
#define EFUSE_STATC_PGIC BIT(1) /*!< clear bit for program complete interrupt flag */
#define EFUSE_STATC_RDIC BIT(2) /*!< clear bit for read complete interrupt flag */
#define EFUSE_STATC_PVIC BIT(3) /*!< clear bit for program voltage setting error interrupt flag */
/* EFUSE_USER_CTL */
#define EFUSE_USER_CTL_DPLK BIT(0) /*!< EFUSE_DP register lock bit */
#define EFUSE_USER_CTL_SCRLK BIT(1) /*!< secure-access area start/end address lock bit */
#define EFUSE_USER_CTL_UCLK BIT(2) /*!< low 16 bits of EFUSE_USER_CTL register lock bit */
#define EFUSE_USER_CTL_AESEN BIT(3) /*!< lock EFUSE_AES_KEY register and enable AES decrypt function */
#define EFUSE_USER_CTL_UDLK BIT(4) /*!< EFUSE_USER_DATA register lock bit */
#define EFUSE_USER_CTL_NDBG BITS(8,9) /*!< debug mode setting bit */
#define EFUSE_USER_CTL_JTAGNSW BIT(10) /*!< debugger select bit */
#define EFUSE_USER_CTL_SPC_L BIT(11) /*!< low security protection */
#define EFUSE_USER_CTL_SPC_H BIT(12) /*!< high security protection */
#define EFUSE_USER_CTL_SCR BIT(13) /*!< secure access mode enable bit */
#define EFUSE_USER_CTL_ESPI_START_MODE BITS(14,15) /*!< external SPI start mode */
#define EFUSE_USER_CTL_SCR_AREA_START BITS(16,23) /*!< secure-access area start address */
#define EFUSE_USER_CTL_SCR_AREA_END BITS(24,31) /*!< secure-access area end address */
/* EFUSE_MCU_RSV */
#define EFUSE_MCU_RSV_DISLFI BIT(6) /*!< disable bit for licensed firmware install (LFI) */
#define EFUSE_MCU_RSV_VFIMG BIT(7) /*!< enable bit for verify firmware image */
#define EFUSE_MCU_RSV_MCURSVLK BIT(8) /*!< lock bit for low 16 bits of EFUSE_MCU_RSV register */
#define EFUSE_MCU_RSV_DCRPLK BIT(9) /*!< lock bit for DCRP area start/end address */
#define EFUSE_MCU_RSV_MCU_RSV BITS(10,15) /*!< MCU reserved value */
#define EFUSE_MCU_RSV_DCRP_AREA_START BITS(16,23) /*!< DCRP area start address */
#define EFUSE_MCU_RSV_DCRP_AREA_END BITS(24,31) /*!< DCRP area end address */
/* EFUSE_DP */
#define EFUSE_DP_DP BITS(0,31) /*!< EFUSE Debug password value */
/* EFUSE_AES_KEY */
#define EFUSE_AES_KEY_AESKEY BITS(0,31) /*!< EFUSE AES key value */
/* EFUSE_USER_DATA */
#define EFUSE_USER_DATA_USERDATA BITS(0,31) /*!< EFUSE USER_DATA value */
/* constants definitions */
/* define the EFUSE bit position and its register index offset */
#define EFUSE_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define EFUSE_REG_VAL(offset) (REG32(EFUSE + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
#define EFUSE_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
#define EFUSE_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define EFUSE_REG_VAL2(offset) (REG32(EFUSE + ((uint32_t)(offset) >> 22)))
#define EFUSE_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
/* register offset */
#define EFUSE_CTL_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */
#define EFUSE_STAT_REG_OFFSET ((uint32_t)0x0000000CU) /*!< STAT register offset */
#define EFUSE_STATC_REG_OFFSET ((uint32_t)0x00000010U) /*!< STATC register offset */
/* EFUSE interrupt flags */
typedef enum {
EFUSE_INT_FLAG_ILLEGAL_ACCESS_ERR = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 16U, EFUSE_STAT_REG_OFFSET, 0U), /*!< illegal access error interrupt flag */
EFUSE_INT_FLAG_PROGRAM_COMPLETE = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 17U, EFUSE_STAT_REG_OFFSET, 1U), /*!< programming operation completion interrupt flag */
EFUSE_INT_FLAG_READ_COMPLETE = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 18U, EFUSE_STAT_REG_OFFSET, 2U), /*!< read operation completion interrupt flag */
EFUSE_INT_FLAG_PROGRAM_VOLTAGE_ERR = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 19U, EFUSE_STAT_REG_OFFSET, 3U), /*!< program voltage setting error flag */
} efuse_interrupt_flag_enum;
/* EFUSE flag */
#define EFUSE_FLAG_LDO_READY EFUSE_STAT_LDO_RDY /*!< EFUSE LDO ready signal flag */
#define EFUSE_FLAG_ILLEGAL_ACCESS_ERR EFUSE_STAT_IAERRIF /*!< illegal access error flag */
#define EFUSE_FLAG_PROGRAM_COMPLETE EFUSE_STAT_PGIF /*!< programming operation completion flag */
#define EFUSE_FLAG_READ_COMPLETE EFUSE_STAT_RDIF /*!< read operation completion flag */
#define EFUSE_FLAG_PROGRAM_VOLTAGE_ERR EFUSE_STAT_PVIF /*!< program voltage setting error flag */
/* EFUSE flag clear */
#define EFUSE_FLAG_ILLEGAL_ACCESS_ERR_CLR EFUSE_STATC_IAERRIC /*!< clear illegal access error flag */
#define EFUSE_FLAG_PROGRAM_COMPLETE_CLR EFUSE_STATC_PGIC /*!< clear programming operation completion flag */
#define EFUSE_FLAG_READ_COMPLETE_CLR EFUSE_STATC_RDIC /*!< clear read operation completion flag */
#define EFUSE_FLAG_PROGRAM_VOLTAGE_ERR_CLR EFUSE_STATC_PVIC /*!< clear program voltage setting error interrupt flag */
/* EFUSE interrupt enable */
#define EFUSE_INT_ILLEGAL_ACCESS_ERR EFUSE_CTL_IAERRIE /*!< illegal access error interrupt enable */
#define EFUSE_INT_PROGRAM_COMPLETE EFUSE_CTL_PGIE /*!< programming operation completion interrupt enable */
#define EFUSE_INT_READ_COMPLETE EFUSE_CTL_RDIE /*!< read operation completion interrupt enable */
#define EFUSE_INT_PROGRAM_VOLTAGE_ERR EFUSE_CTL_PVIE /*!< program voltage setting error interrupt enable */
/* EFUSE interrupt flag clear */
#define EFUSE_INT_FLAG_ILLEGAL_ACCESS_ERR_CLR EFUSE_STATC_IAERRIC /*!< clear illegal access error interrupt flag */
#define EFUSE_INT_FLAG_PROGRAM_COMPLETE_CLR EFUSE_STATC_PGIC /*!< clear programming operation completion interrupt flag */
#define EFUSE_INT_FLAG_READ_COMPLETE_CLR EFUSE_STATC_RDIC /*!< clear read operation completion interrupt flag */
#define EFUSE_INT_FLAG_PROGRAM_VOLTAGE_ERR_CLR EFUSE_STATC_PVIC /*!< clear program voltage setting error interrupt flag */
/* EFUSE system parameter size enum, in byte unit */
typedef enum {
USER_CTL_MCU_RESERVED_SIZE = 4U, /*!< user control parameter size,MCU reserved parameter size */
DP_SIZE = 8U, /*!< debug password parameter size */
AES_KEY_SIZE = 16U, /*!< AES key parameter size */
USER_DATA_SIZE = 16U, /*!< user data parameter size */
} efuse_system_para_size_enum;
/* EFUSE system parameter index */
typedef enum {
USER_CTL_IDX = 0U, /*!< index of user control parameter */
MCU_RESERVED_IDX = 1U, /*!< index of MCU reserved parameter */
DP_IDX = 2U, /*!< index of debug password parameter */
AES_KEY_IDX = 3U, /*!< index of AES key parameter */
USER_DATA_IDX = 4U, /*!< index of user data parameter */
} efuse_system_para_index_enum;
/* EFUSE state */
typedef enum {
EFUSE_READY = 0U, /*!< operation has been completed */
EFUSE_BUSY, /*!< operation is in progress */
EFUSE_IAERR, /*!< illegal access error */
EFUSE_PVERR, /*!< program voltage setting error */
EFUSE_TOERR, /*!< timeout error */
} efuse_state_enum;
/* EFADDR of EFUSE system parameters */
#define USER_CTL_EFADDR ((uint32_t)0x00000000U) /*!< user control parameter start address */
#define MCU_RESERVED_EFADDR ((uint32_t)0x00000020U) /*!< MCU reserved parameter start address */
#define DP_EFADDR ((uint32_t)0x00000040U) /*!< debug password parameter start address */
#define AES_KEY_EFADDR ((uint32_t)0x00000080U) /*!< AES key parameter start address */
#define USER_DATA_EFADDR ((uint32_t)0x00000100U) /*!< user data parameter start address */
#define MAX_EFADDR ((uint32_t)0x0000017FU) /*!< max efuse address */
#define EFUSE_PARA_CNT ((uint32_t)0x00000005U) /*!< the count of system parameters in EFUSE */
/* EFUSE parameters' register address */
#define EFUSE_USER_CTL_REG_ADDR (EFUSE + 0x00000014U) /*!< user control register address */
#define EFUSE_MCU_RSV_REG_ADDR (EFUSE + 0x00000018U) /*!< MCU reserved register address */
#define EFUSE_DP_REG_ADDR (EFUSE + 0x0000001CU) /*!< debug password register address */
#define EFUSE_AES_KEY_REG_ADDR (EFUSE + 0x00000024U) /*!< AES key register address */
#define EFUSE_USER_DATA_REG_ADDR (EFUSE + 0x00000034U) /*!< user data register address */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check efuse addresss to be read */
#define NOT_EFUSE_ADDR(addr) (((addr) != USER_CTL_EFADDR) && ((addr) != MCU_RESERVED_EFADDR) && \
((addr) != DP_EFADDR) && ((addr) != USER_DATA_EFADDR))
/* check efuse size to be read*/
#define NOT_EFUSE_SIZE(size) (((size) != USER_CTL_MCU_RESERVED_SIZE) && ((size) != DP_SIZE) && ((size) != USER_DATA_SIZE))
/* check efuse size to be programmed*/
#define NOT_EFUSE_VALID_SIZE(size) (((size) == 0U) || ((size) > 16U))
/* check efuse addresss to be programmed */
#define NOT_EFUSE_VALID_ADDR(addr) ((((addr) % 8U) != 0U) || ((addr) > MAX_EFADDR))
/* check efuse addresss configuration */
#define NOT_EFUSE_VALID_ADDR_CONFIG5(ef_addr, size) (((ef_addr) >= USER_DATA_EFADDR) && (((ef_addr) + (size) * 8U - 1U) > MAX_EFADDR))
/* check efuse addresss configuration */
#define NOT_EFUSE_VALID_ADDR_CONFIG4(ef_addr, size) (((ef_addr) >= AES_KEY_EFADDR) && ((ef_addr) < USER_DATA_EFADDR) && (((ef_addr) + (size) * 8U - 1U) > USER_DATA_EFADDR))
/* check efuse addresss configuration */
#define NOT_EFUSE_VALID_ADDR_CONFIG3(ef_addr, size) (((ef_addr) >= DP_EFADDR) && ((ef_addr) < AES_KEY_EFADDR) && (((ef_addr) + ((size) * 8U - 1U)) > AES_KEY_EFADDR))
/* check efuse addresss configuration */
#define NOT_EFUSE_VALID_ADDR_CONFIG2(ef_addr, size) (((ef_addr) >= MCU_RESERVED_EFADDR) && ((ef_addr) < DP_EFADDR) && (((ef_addr) + (size) * 8U - 1U) > DP_EFADDR))
/* check efuse addresss configuration */
#define NOT_EFUSE_VALID_ADDR_CONFIG1(ef_addr, size) (((ef_addr) < MCU_RESERVED_EFADDR) && (((ef_addr) + (size) * 8U - 1U) > MCU_RESERVED_EFADDR))
/* check efuse addresss configuration */
#define NOT_EFUSE_VALID_ADDR_CONFIG0(ef_addr, size) (((ef_addr) >= AES_KEY_EFADDR) && ((ef_addr) < USER_DATA_EFADDR) && ((size) != AES_KEY_SIZE))
/* check efuse flag */
#define NOT_EFUSE_FLAG(flag) (((flag) != EFUSE_FLAG_ILLEGAL_ACCESS_ERR) && ((flag) != EFUSE_FLAG_PROGRAM_COMPLETE) && \
((flag) != EFUSE_FLAG_READ_COMPLETE) && ((flag) != EFUSE_FLAG_PROGRAM_VOLTAGE_ERR))
/* check efuse flag clear */
#define NOT_EFUSE_FLAG_CLR(flag_clear) (((flag_clear) != EFUSE_FLAG_ILLEGAL_ACCESS_ERR_CLR) && ((flag_clear) != EFUSE_FLAG_PROGRAM_COMPLETE_CLR) && \
((flag_clear) != EFUSE_FLAG_READ_COMPLETE_CLR) && ((flag_clear) != EFUSE_FLAG_PROGRAM_VOLTAGE_ERR_CLR))
/* check efuse interrupt */
#define NOT_EFUSE_INT(int_en) (((int_en) != EFUSE_INT_ILLEGAL_ACCESS_ERR) && ((int_en) != EFUSE_INT_PROGRAM_COMPLETE) && \
((int_en) != EFUSE_INT_READ_COMPLETE) && ((int_en) != EFUSE_INT_PROGRAM_VOLTAGE_ERR))
/* check efuse interrupt flag clear */
#define NOT_EFUSE_INT_FLAG_CLR(int_flag_clear) (((int_flag_clear) != EFUSE_INT_FLAG_ILLEGAL_ACCESS_ERR_CLR) && ((int_flag_clear) != EFUSE_INT_FLAG_PROGRAM_COMPLETE_CLR) && \
((int_flag_clear) != EFUSE_INT_FLAG_READ_COMPLETE_CLR) && ((int_flag_clear) != EFUSE_INT_FLAG_PROGRAM_VOLTAGE_ERR_CLR))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* EFUSE operation functions */
/* read system parameters from EFUSE macro to registers */
ErrStatus efuse_read(uint32_t ef_addr, uint32_t size, uint32_t buf[]);
/* program register values to EFUSE macro system parameters */
ErrStatus efuse_write(uint32_t ef_addr, uint32_t size, uint8_t *buf);
/* program all user control parameters */
ErrStatus efuse_user_control_write(uint8_t *buf);
/* program all MCU reserved parameters */
ErrStatus efuse_mcu_reserved_write(uint8_t *buf);
/* program all debug password parameters */
ErrStatus efuse_dp_write(uint8_t *buf);
/* program all AES key parameters */
ErrStatus efuse_aes_key_write(uint8_t *buf);
/* program all user data parameters */
ErrStatus efuse_user_data_write(uint8_t *buf);
/* FMC universal functions */
/* get 8-bits CRC calculation result value of AES key */
uint8_t efuse_aes_key_crc_get(void);
/* enable monitor program voltage function */
void efuse_monitor_program_voltage_enable(void);
/* disable monitor program voltage function */
void efuse_monitor_program_voltage_disable(void);
/* get monitor program voltage function */
FlagStatus efuse_monitor_program_voltage_get(void);
/* get ldo ready signal */
FlagStatus efuse_ldo_ready_get(void);
/* flag and interrupt functions */
/* check EFUSE flag is set or not */
FlagStatus efuse_flag_get(uint32_t flag);
/* clear EFUSE pending flag */
void efuse_flag_clear(uint32_t flag);
/* enable EFUSE interrupt */
void efuse_interrupt_enable(uint32_t interrupt);
/* disable EFUSE interrupt */
void efuse_interrupt_disable(uint32_t interrupt);
/* check EFUSE interrupt flag is set or not */
FlagStatus efuse_interrupt_flag_get(efuse_interrupt_flag_enum int_flag);
/* clear EFUSE pending interrupt flag */
void efuse_interrupt_flag_clear(uint32_t int_flag);
#endif /* GD32H75E_EFUSE_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_exmc.h
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/*!
\file gd32h75e_exmc.h
\brief definitions for the EXMC
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_EXMC_H
#define GD32H75E_EXMC_H
#include "gd32h75e.h"
/* EXMC definitions */
#define EXMC EXMC_BASE /*!< EXMC register base address */
/* registers definitions */
/* NOR/PSRAM */
#define EXMC_SNCTL0 REG32(EXMC + 0x00000000U) /*!< EXMC SRAM/NOR flash control register for region0 */
#define EXMC_SNTCFG0 REG32(EXMC + 0x00000004U) /*!< EXMC SRAM/NOR flash timing configuration register for region0 */
#define EXMC_SNWTCFG0 REG32(EXMC + 0x00000104U) /*!< EXMC SRAM/NOR flash write timing configuration register for region0 */
#define EXMC_SNCTL1 REG32(EXMC + 0x00000008U) /*!< EXMC SRAM/NOR flash control register for region1 */
#define EXMC_SNTCFG1 REG32(EXMC + 0x0000000CU) /*!< EXMC SRAM/NOR flash timing configuration register for region1 */
#define EXMC_SNWTCFG1 REG32(EXMC + 0x0000010CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region1 */
#define EXMC_SNCTL2 REG32(EXMC + 0x00000010U) /*!< EXMC SRAM/NOR flash control register for region2 */
#define EXMC_SNTCFG2 REG32(EXMC + 0x00000014U) /*!< EXMC SRAM/NOR flash timing configuration register for region2 */
#define EXMC_SNWTCFG2 REG32(EXMC + 0x00000114U) /*!< EXMC SRAM/NOR flash write timing configuration register for region2 */
#define EXMC_SNCTL3 REG32(EXMC + 0x00000018U) /*!< EXMC SRAM/NOR flash control register for region3 */
#define EXMC_SNTCFG3 REG32(EXMC + 0x0000001CU) /*!< EXMC SRAM/NOR flash timing configuration register for region3 */
#define EXMC_SNWTCFG3 REG32(EXMC + 0x0000011CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region3 */
/* NAND */
#define EXMC_NCTL REG32(EXMC + 0x00000080U) /*!< EXMC NAND control register */
#define EXMC_NINTEN REG32(EXMC + 0x00000084U) /*!< EXMC NAND interrupt enable register */
#define EXMC_NCTCFG REG32(EXMC + 0x00000088U) /*!< EXMC NAND common space timing configuration register */
#define EXMC_NATCFG REG32(EXMC + 0x0000008CU) /*!< EXMC NAND attribute space timing configuration register */
#define EXMC_NECC REG32(EXMC + 0x00000094U) /*!< EXMC NAND ECC register */
/* SDRAM */
#define EXMC_SDCTL0 REG32(EXMC + 0x00000140U) /*!< EXMC SDRAM control register for device0 */
#define EXMC_SDTCFG0 REG32(EXMC + 0x00000148U) /*!< EXMC SDRAM timing configuration register register for device0 */
#define EXMC_SDCTL1 REG32(EXMC + 0x00000144U) /*!< EXMC SDRAM control register for device1 */
#define EXMC_SDTCFG1 REG32(EXMC + 0x0000014CU) /*!< EXMC SDRAM timing configuration register register for device1 */
#define EXMC_SDCMD REG32(EXMC + 0x00000150U) /*!< EXMC SDRAM command register */
#define EXMC_SDARI REG32(EXMC + 0x00000154U) /*!< EXMC SDRAM auto-refresh interval register */
#define EXMC_SDSTAT REG32(EXMC + 0x00000158U) /*!< EXMC SDRAM status register */
#define EXMC_SDRSCTL REG32(EXMC + 0x00000180U) /*!< EXMC SDRAM read sample control register */
/* bits definitions */
/* EXMC_SNCTLx,x=0..3 */
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR region enable */
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR region memory address/data multiplexing enable */
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR region memory type */
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR region memory data bus width */
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */
#define EXMC_SNCTL_WEN BIT(12) /*!< write enable */
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */
#define EXMC_SNCTL_ASYNCWTEN BIT(15) /*!< asynchronous wait enable */
#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */
#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write configuration */
#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock configuration */
#define EXMC_SNCTL_BKREMAP BITS(24,25) /*!< bank remap */
/* EXMC_SNTCFGx,x=0..3 */
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */
#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */
/* EXMC_SNWTCFGx,x=0..3 */
#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */
#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */
#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */
#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */
#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */
/* EXMC_NCTL */
#define EXMC_NCTL_NDWTEN BIT(1) /*!< wait function enable */
#define EXMC_NCTL_NDBKEN BIT(2) /*!< NAND bank enable */
#define EXMC_NCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */
#define EXMC_NCTL_ECCEN BIT(6) /*!< ECC enable */
#define EXMC_NCTL_CTR BITS(9,12) /*!< CLE to RE delay */
#define EXMC_NCTL_ATR BITS(13,16) /*!< ALE to RE delay */
#define EXMC_NCTL_ECCSZ BITS(17,19) /*!< ECC size */
/* EXMC_NINTEN */
#define EXMC_NINTEN_INTRS BIT(0) /*!< rising edge interrupt status bit */
#define EXMC_NINTEN_INTHS BIT(1) /*!< high-level interrupt status bit */
#define EXMC_NINTEN_INTFS BIT(2) /*!< falling edge interrupt status bit */
#define EXMC_NINTEN_INTREN BIT(3) /*!< rising edge detection interrupt enable bit */
#define EXMC_NINTEN_INTHEN BIT(4) /*!< high-level detection interrupt enable bit */
#define EXMC_NINTEN_INTFEN BIT(5) /*!< falling edge detection interrupt enable bit */
#define EXMC_NINTEN_FFEPT BIT(6) /*!< FIFO empty flag */
/* EXMC_NCTCFG */
#define EXMC_NCTCFG_COMSET BITS(0,7) /*!< common memory setup time */
#define EXMC_NCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */
#define EXMC_NCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */
#define EXMC_NCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */
/* EXMC_NATCFG */
#define EXMC_NATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */
#define EXMC_NATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */
#define EXMC_NATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */
#define EXMC_NATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */
/* EXMC_NECC */
#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */
/* EXMC_SDCTLx,(x=0,1) */
#define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */
#define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */
#define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */
#define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */
#define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */
#define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */
#define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */
#define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read enable bit */
#define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */
#define EXMC_SDCTL_SDCLK_2 BIT(15) /*!< bit 2 SDCLK */
/* EXMC_SDTCFGx,(x=0,1) */
#define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */
#define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */
#define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */
#define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */
#define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */
#define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */
#define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */
/* EXMC_SDCMD */
#define EXMC_SDCMD_CMD BITS(0,2) /*!< command */
#define EXMC_SDCMD_DS1 BIT(3) /*!< select device1 */
#define EXMC_SDCMD_DS0 BIT(4) /*!< select device0 */
#define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */
#define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */
/* EXMC_SDARI */
#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */
#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */
#define EXMC_SDARI_REIE BIT(14) /*!< refresh error interrupt enable bit */
/* EXMC_SDSTAT */
#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */
#define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device0 status */
#define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device1 status */
#define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */
/* EXMC_SDRSCTL */
#define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable bit */
#define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */
#define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */
/* constants definitions */
/* EXMC NOR/SRAM timing initialize structure */
typedef struct {
uint32_t asyn_access_mode; /*!< asynchronous access mode */
uint32_t syn_data_latency; /*!< configure the data latency */
uint32_t syn_clk_division; /*!< configure the clock divide ratio */
uint32_t bus_latency; /*!< configure the bus latency */
uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */
uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */
uint32_t asyn_address_setuptime; /*!< configure the address setup time, asynchronous access mode valid */
} exmc_norsram_timing_parameter_struct;
/* EXMC NOR/SRAM initialize structure */
typedef struct {
uint32_t norsram_region; /*!< select the region of EXMC NOR/PSRAM region */
uint32_t address_data_mux; /*!< specify whether the data bus and address bus are multiplexed */
uint32_t memory_type; /*!< specify the type of external memory */
uint32_t databus_width; /*!< specify the databus width of external memory */
uint32_t burst_mode; /*!< enable or disable the burst mode */
uint32_t nwait_polarity; /*!< specify the polarity of NWAIT signal from memory */
uint32_t nwait_config; /*!< NWAIT signal configuration */
uint32_t memory_write; /*!< enable or disable the write operation */
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */
uint32_t extended_mode; /*!< enable or disable the extended mode */
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
uint32_t cram_page_size; /*!< specify CRAM page size */
uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */
exmc_norsram_timing_parameter_struct
*read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing
parameters for read if the extendedmode is used */
exmc_norsram_timing_parameter_struct *write_timing; /*!< timing parameters for write when the extendedmode is used */
} exmc_norsram_parameter_struct;
/* EXMC NAND timing initialize structure */
typedef struct {
uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */
uint32_t waittime; /*!< configure the minimum wait time */
uint32_t setuptime; /*!< configure the address setup time */
} exmc_nand_timing_parameter_struct;
/* EXMC NAND initialize structure */
typedef struct {
uint32_t ecc_size; /*!< the page size for the ECC calculation */
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */
uint32_t databus_width; /*!< the NAND flash databus width */
uint32_t wait_feature; /*!< enable or disable the wait feature */
exmc_nand_timing_parameter_struct *common_space_timing; /*!< the timing parameters for NAND flash common space */
exmc_nand_timing_parameter_struct *attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
} exmc_nand_parameter_struct;
/* EXMC SDRAM timing initialize structure */
typedef struct {
uint32_t row_to_column_delay; /*!< configure the row to column delay */
uint32_t row_precharge_delay; /*!< configure the row precharge delay */
uint32_t write_recovery_delay; /*!< configure the write recovery delay */
uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */
uint32_t row_address_select_delay; /*!< configure the row address select delay */
uint32_t exit_selfrefresh_delay; /*!< configure the exit self-refresh delay */
uint32_t load_mode_register_delay; /*!< configure the load mode register delay */
} exmc_sdram_timing_parameter_struct;
/* EXMC SDRAM initialize structure */
typedef struct {
uint32_t sdram_device; /*!< device of SDRAM */
uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in CK_EXMC clock cycles */
uint32_t burst_read_switch; /*!< enable or disable the burst read */
uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM devices */
uint32_t write_protection; /*!< enable or disable SDRAM device write protection function */
uint32_t cas_latency; /*!< configure the SDRAM CAS latency */
uint32_t internal_bank_number; /*!< the number of internal bank */
uint32_t data_width; /*!< the databus width of SDRAM memory */
uint32_t row_address_width; /*!< the bit width of a row address */
uint32_t column_address_width; /*!< the bit width of a column address */
exmc_sdram_timing_parameter_struct *timing; /*!< the timing parameters for write and read SDRAM */
} exmc_sdram_parameter_struct;
/* EXMC SDRAM command initialize structure */
typedef struct {
uint32_t mode_register_content; /*!< the SDRAM mode register content */
uint32_t auto_refresh_number; /*!< the number of successive auto-refresh cycles will be send when CMD = 011 */
uint32_t bank_select; /*!< the bank which command will be sent to */
uint32_t command; /*!< the commands that will be sent to SDRAM */
} exmc_sdram_command_parameter_struct;
/* EXMC_register address */
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */
#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */
#define EXMC_SDCTL(device) REG32(EXMC + 0x140U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM control registers,device = 0,1 */
#define EXMC_SDTCFG(device) REG32(EXMC + 0x148U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM timing configuration registers,device = 0,1 */
/* bank remap */
#define SNCTL_BKREMAP(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
#define EXMC_BANK_REMAP_DEFAULT SNCTL_BKREMAP(0) /*!< default mapping */
#define EXMC_BANK_NORPSRAM_SDRAM_SWAP SNCTL_BKREMAP(1) /*!< swap NOR/PSRAM bank and SDRAM device 0 address mapping */
/* CRAM page size */
#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */
#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */
#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */
#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */
#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */
/* NOR region memory data bus width */
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */
/* NOR region memory type */
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
/* asynchronous access mode */
#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */
#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */
#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */
#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */
/* data latency for NOR flash */
#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */
#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */
#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */
#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */
#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */
#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */
#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */
#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */
#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */
#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */
#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */
#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */
#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */
#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */
#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */
#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */
/* synchronous clock divide ratio */
#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< no EXMC_CLK output */
#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK period = 2*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK period = 3*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK period = 4*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK period = 5*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK period = 6*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK period = 7*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK period = 8*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK period = 9*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK period = 10*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK period = 11*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK period = 12*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK period = 13*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK period = 14*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK period = 15*CK_EXMC period */
#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK period = 16*CK_EXMC period */
/* ECC size */
#define NCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
#define EXMC_ECC_SIZE_256BYTES NCTL_ECCSZ(0) /* ECC size is 256 bytes */
#define EXMC_ECC_SIZE_512BYTES NCTL_ECCSZ(1) /* ECC size is 512 bytes */
#define EXMC_ECC_SIZE_1024BYTES NCTL_ECCSZ(2) /* ECC size is 1024 bytes */
#define EXMC_ECC_SIZE_2048BYTES NCTL_ECCSZ(3) /* ECC size is 2048 bytes */
#define EXMC_ECC_SIZE_4096BYTES NCTL_ECCSZ(4) /* ECC size is 4096 bytes */
#define EXMC_ECC_SIZE_8192BYTES NCTL_ECCSZ(5) /* ECC size is 8192 bytes */
/* ALE to RE delay */
#define NCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13))
#define EXMC_ALE_RE_DELAY_1_CK_EXMC NCTL_ATR(0) /* ALE to RE delay = 1*CK_EXMC */
#define EXMC_ALE_RE_DELAY_2_CK_EXMC NCTL_ATR(1) /* ALE to RE delay = 2*CK_EXMC */
#define EXMC_ALE_RE_DELAY_3_CK_EXMC NCTL_ATR(2) /* ALE to RE delay = 3*CK_EXMC */
#define EXMC_ALE_RE_DELAY_4_CK_EXMC NCTL_ATR(3) /* ALE to RE delay = 4*CK_EXMC */
#define EXMC_ALE_RE_DELAY_5_CK_EXMC NCTL_ATR(4) /* ALE to RE delay = 5*CK_EXMC */
#define EXMC_ALE_RE_DELAY_6_CK_EXMC NCTL_ATR(5) /* ALE to RE delay = 6*CK_EXMC */
#define EXMC_ALE_RE_DELAY_7_CK_EXMC NCTL_ATR(6) /* ALE to RE delay = 7*CK_EXMC */
#define EXMC_ALE_RE_DELAY_8_CK_EXMC NCTL_ATR(7) /* ALE to RE delay = 8*CK_EXMC */
#define EXMC_ALE_RE_DELAY_9_CK_EXMC NCTL_ATR(8) /* ALE to RE delay = 9*CK_EXMC */
#define EXMC_ALE_RE_DELAY_10_CK_EXMC NCTL_ATR(9) /* ALE to RE delay = 10*CK_EXMC */
#define EXMC_ALE_RE_DELAY_11_CK_EXMC NCTL_ATR(10) /* ALE to RE delay = 11*CK_EXMC */
#define EXMC_ALE_RE_DELAY_12_CK_EXMC NCTL_ATR(11) /* ALE to RE delay = 12*CK_EXMC */
#define EXMC_ALE_RE_DELAY_13_CK_EXMC NCTL_ATR(12) /* ALE to RE delay = 13*CK_EXMC */
#define EXMC_ALE_RE_DELAY_14_CK_EXMC NCTL_ATR(13) /* ALE to RE delay = 14*CK_EXMC */
#define EXMC_ALE_RE_DELAY_15_CK_EXMC NCTL_ATR(14) /* ALE to RE delay = 15*CK_EXMC */
#define EXMC_ALE_RE_DELAY_16_CK_EXMC NCTL_ATR(15) /* ALE to RE delay = 16*CK_EXMC */
/* CLE to RE delay */
#define NCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9))
#define EXMC_CLE_RE_DELAY_1_CK_EXMC NCTL_CTR(0) /* CLE to RE delay = 1*CK_EXMC */
#define EXMC_CLE_RE_DELAY_2_CK_EXMC NCTL_CTR(1) /* CLE to RE delay = 2*CK_EXMC */
#define EXMC_CLE_RE_DELAY_3_CK_EXMC NCTL_CTR(2) /* CLE to RE delay = 3*CK_EXMC */
#define EXMC_CLE_RE_DELAY_4_CK_EXMC NCTL_CTR(3) /* CLE to RE delay = 4*CK_EXMC */
#define EXMC_CLE_RE_DELAY_5_CK_EXMC NCTL_CTR(4) /* CLE to RE delay = 5*CK_EXMC */
#define EXMC_CLE_RE_DELAY_6_CK_EXMC NCTL_CTR(5) /* CLE to RE delay = 6*CK_EXMC */
#define EXMC_CLE_RE_DELAY_7_CK_EXMC NCTL_CTR(6) /* CLE to RE delay = 7*CK_EXMC */
#define EXMC_CLE_RE_DELAY_8_CK_EXMC NCTL_CTR(7) /* CLE to RE delay = 8*CK_EXMC */
#define EXMC_CLE_RE_DELAY_9_CK_EXMC NCTL_CTR(8) /* CLE to RE delay = 9*CK_EXMC */
#define EXMC_CLE_RE_DELAY_10_CK_EXMC NCTL_CTR(9) /* CLE to RE delay = 10*CK_EXMC */
#define EXMC_CLE_RE_DELAY_11_CK_EXMC NCTL_CTR(10) /* CLE to RE delay = 11*CK_EXMC */
#define EXMC_CLE_RE_DELAY_12_CK_EXMC NCTL_CTR(11) /* CLE to RE delay = 12*CK_EXMC */
#define EXMC_CLE_RE_DELAY_13_CK_EXMC NCTL_CTR(12) /* CLE to RE delay = 13*CK_EXMC */
#define EXMC_CLE_RE_DELAY_14_CK_EXMC NCTL_CTR(13) /* CLE to RE delay = 14*CK_EXMC */
#define EXMC_CLE_RE_DELAY_15_CK_EXMC NCTL_CTR(14) /* CLE to RE delay = 15*CK_EXMC */
#define EXMC_CLE_RE_DELAY_16_CK_EXMC NCTL_CTR(15) /* CLE to RE delay = 16*CK_EXMC */
/* NAND bank memory data bus width */
#define NCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define EXMC_NAND_DATABUS_WIDTH_8B NCTL_NDW(0) /*!< NAND data width is 8 bits */
#define EXMC_NAND_DATABUS_WIDTH_16B NCTL_NDW(1) /*!< NAND data width is 16 bits */
/* SDRAM pipeline delay */
#define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13))
#define EXMC_PIPELINE_DELAY_0_CK_EXMC SDCTL_PIPED(0) /*!< 0 CK_EXMC clock cycle delay */
#define EXMC_PIPELINE_DELAY_1_CK_EXMC SDCTL_PIPED(1) /*!< 1 CK_EXMC clock cycle delay */
#define EXMC_PIPELINE_DELAY_2_CK_EXMC SDCTL_PIPED(2) /*!< 2 CK_EXMC clock cycle delay */
/* SDRAM clock configuration */
#define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10))
#define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */
#define EXMC_SDCLK_PERIODS_2_CK_EXMC SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*CK_EXMC */
#define EXMC_SDCLK_PERIODS_3_CK_EXMC SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*CK_EXMC */
#define EXMC_SDCLK_PERIODS_4_CK_EXMC (EXMC_SDCTL_SDCLK_2 | SDCTL_SDCLK(2)) /*!< SDCLK memory period = 4*CK_EXMC */
#define EXMC_SDCLK_PERIODS_5_CK_EXMC (EXMC_SDCTL_SDCLK_2 | SDCTL_SDCLK(3)) /*!< SDCLK memory period = 5*CK_EXMC */
/* CAS latency */
#define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7))
#define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */
#define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */
#define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */
/* SDRAM data bus width */
#define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */
#define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */
#define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */
/* SDRAM row address bit width */
#define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
#define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */
#define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */
#define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */
/* SDRAM column address bit width */
#define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */
#define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */
#define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */
#define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */
/* SDRAM number of successive auto-refresh */
#define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */
#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */
#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */
/* SDRAM command selection */
#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */
#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */
#define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */
#define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */
#define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */
#define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */
#define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */
/* SDRAM the delayed sample clock of read data */
#define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
#define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */
#define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */
#define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */
#define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */
#define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */
#define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */
#define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */
#define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */
#define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */
#define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */
#define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */
#define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */
#define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */
#define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */
#define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */
#define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */
/* EXMC NOR/SRAM bank region definition */
#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */
#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */
#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */
/* EXMC consecutive clock */
#define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */
#define EXMC_CLOCK_UNCONDITIONALLY EXMC_SNCTL_CCK /*!< EXMC_CLK is generated unconditionally */
/* EXMC NOR/SRAM write mode */
#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */
#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */
/* EXMC NWAIT signal configuration */
#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */
#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */
/* EXMC NWAIT signal polarity configuration */
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */
/* EXMC NAND bank definition */
#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< NAND flash bank2 */
/* EXMC SDRAM bank definition */
#define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */
#define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */
/* EXMC SDRAM internal banks */
#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */
#define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */
/* SDRAM device0 select */
#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device0 unselect */
#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< SDRAM device0 select */
/* SDRAM device1 select */
#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device1 unselect */
#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< SDRAM device1 select */
/* SDRAM device status */
#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */
#define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */
#define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */
/* sample cycle of read data */
#define EXMC_SDRAM_READSAMPLE_0_EXTRACK ((uint32_t)0x00000000U) /*!< add 0 extra CK_EXMC cycle to the read data sample clock besides the delay chain */
#define EXMC_SDRAM_READSAMPLE_1_EXTRACK EXMC_SDRSCTL_SSCR /*!< add 1 extra CK_EXMC cycle to the read data sample clock besides the delay chain */
/* EXMC flag bits */
#define EXMC_NAND_FLAG_RISE EXMC_NINTEN_INTRS /*!< rising edge interrupt status */
#define EXMC_NAND_FLAG_LEVEL EXMC_NINTEN_INTHS /*!< high-level interrupt status */
#define EXMC_NAND_FLAG_FALL EXMC_NINTEN_INTFS /*!< falling edge interrupt status */
#define EXMC_NAND_FLAG_FIFOE EXMC_NINTEN_FFEPT /*!< FIFO empty flag */
#define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */
#define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */
/* EXMC interrupt bits */
#define EXMC_NAND_INT_RISE EXMC_NINTEN_INTREN /*!< rising edge interrupt */
#define EXMC_NAND_INT_LEVEL EXMC_NINTEN_INTHEN /*!< high-level interrupt */
#define EXMC_NAND_INT_FALL EXMC_NINTEN_INTFEN /*!< falling edge interrupt */
#define EXMC_SDRAM_INT_REFRESH EXMC_SDARI_REIE /*!< refresh error interrupt */
/* EXMC interrupt flag bits */
#define EXMC_NAND_INT_FLAG_RISE EXMC_NINTEN_INTREN /*!< rising edge interrupt flag */
#define EXMC_NAND_INT_FLAG_LEVEL EXMC_NINTEN_INTHEN /*!< high-level interrupt flag */
#define EXMC_NAND_INT_FLAG_FALL EXMC_NINTEN_INTFEN /*!< falling edge interrupt flag */
#define EXMC_SDRAM_INT_FLAG_REFRESH EXMC_SDARI_REIE /*!< refresh error interrupt flag */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
#define NOT_EXMC_BANK0_NORSRAM_REGION(xxx) (((xxx) != EXMC_BANK0_NORSRAM_REGION0) && ((xxx) != EXMC_BANK0_NORSRAM_REGION1) && \
((xxx) != EXMC_BANK0_NORSRAM_REGION2) && ((xxx) != EXMC_BANK0_NORSRAM_REGION3))
#define NOT_EXMC_ASYN_SYN_WRITE(xxx) (((xxx) != EXMC_ASYN_WRITE) && ((xxx) != EXMC_SYN_WRITE))
#define NOT_EXMC_ENABLE_DISABLE(xxx) (((xxx) != ENABLE) && ((xxx) != DISABLE))
#define NOT_EXMC_NWAIT_CONFIG(xxx) (((xxx) != EXMC_NWAIT_CONFIG_BEFORE) && ((xxx) != EXMC_NWAIT_CONFIG_DURING))
#define NOT_EXMC_NWAIT_POLARITY(xxx) (((xxx) != EXMC_NWAIT_POLARITY_LOW) && ((xxx) != EXMC_NWAIT_POLARITY_HIGH))
#define NOT_EXMC_NOR_DATABUS_WIDTH(xxx) (((xxx) != EXMC_NOR_DATABUS_WIDTH_8B) && ((xxx) != EXMC_NOR_DATABUS_WIDTH_16B))
#define NOT_EXMC_MEMORY_TYPE(xxx) (((xxx) != EXMC_MEMORY_TYPE_SRAM) && ((xxx) != EXMC_MEMORY_TYPE_PSRAM) && \
((xxx) != EXMC_MEMORY_TYPE_NOR))
#define NOT_EXMC_CRAM_PAGE_SIZE(xxx) (((xxx) != EXMC_CRAM_AUTO_SPLIT) && ((xxx) != EXMC_CRAM_PAGE_SIZE_128_BYTES) && \
((xxx) != EXMC_CRAM_PAGE_SIZE_256_BYTES) && ((xxx) != EXMC_CRAM_PAGE_SIZE_512_BYTES) && \
((xxx) != EXMC_CRAM_PAGE_SIZE_1024_BYTES))
#define NOT_EXMC_ACCESS_MODE(xxx) (((xxx) != EXMC_ACCESS_MODE_A) && ((xxx) != EXMC_ACCESS_MODE_B) && \
((xxx) != EXMC_ACCESS_MODE_C) && ((xxx) != EXMC_ACCESS_MODE_D))
#define NOT_EXMC_DATALAT_CLK(xxx) (((xxx) != EXMC_DATALAT_2_CLK) && ((xxx) != EXMC_DATALAT_3_CLK) && \
((xxx) != EXMC_DATALAT_4_CLK) && ((xxx) != EXMC_DATALAT_5_CLK) && \
((xxx) != EXMC_DATALAT_6_CLK) && ((xxx) != EXMC_DATALAT_7_CLK) && \
((xxx) != EXMC_DATALAT_8_CLK) && ((xxx) != EXMC_DATALAT_9_CLK) && \
((xxx) != EXMC_DATALAT_10_CLK) && ((xxx) != EXMC_DATALAT_11_CLK) && \
((xxx) != EXMC_DATALAT_12_CLK) && ((xxx) != EXMC_DATALAT_13_CLK) && \
((xxx) != EXMC_DATALAT_14_CLK) && ((xxx) != EXMC_DATALAT_15_CLK) && \
((xxx) != EXMC_DATALAT_16_CLK) && ((xxx) != EXMC_DATALAT_17_CLK))
#define NOT_EXMC_SYN_CLOCK_RATIO_CLK(xxx) (((xxx) != EXMC_SYN_CLOCK_RATIO_DISABLE) && ((xxx) != EXMC_SYN_CLOCK_RATIO_2_CLK) && \
((xxx) != EXMC_SYN_CLOCK_RATIO_3_CLK) && ((xxx) != EXMC_SYN_CLOCK_RATIO_4_CLK) && \
((xxx) != EXMC_SYN_CLOCK_RATIO_5_CLK) && ((xxx) != EXMC_SYN_CLOCK_RATIO_6_CLK) && \
((xxx) != EXMC_SYN_CLOCK_RATIO_7_CLK) && ((xxx) != EXMC_SYN_CLOCK_RATIO_8_CLK) && \
((xxx) != EXMC_SYN_CLOCK_RATIO_9_CLK) && ((xxx) != EXMC_SYN_CLOCK_RATIO_10_CLK) && \
((xxx) != EXMC_SYN_CLOCK_RATIO_11_CLK) && ((xxx) != EXMC_SYN_CLOCK_RATIO_12_CLK) && \
((xxx) != EXMC_SYN_CLOCK_RATIO_13_CLK) && ((xxx) != EXMC_SYN_CLOCK_RATIO_14_CLK) && \
((xxx) != EXMC_SYN_CLOCK_RATIO_15_CLK) && ((xxx) != EXMC_SYN_CLOCK_RATIO_16_CLK))
#define NOT_EXMC_NAND_ECC_SIZE(xxx) (((xxx) != EXMC_ECC_SIZE_256BYTES) && ((xxx) != EXMC_ECC_SIZE_512BYTES) && \
((xxx) != EXMC_ECC_SIZE_1024BYTES) && ((xxx) != EXMC_ECC_SIZE_2048BYTES) && \
((xxx) != EXMC_ECC_SIZE_4096BYTES) && ((xxx) != EXMC_ECC_SIZE_8192BYTES))
#define NOT_EXMC_NAND_ALE_RE_DELAY(xxx) (((xxx) != EXMC_ALE_RE_DELAY_1_CK_EXMC) && ((xxx) != EXMC_ALE_RE_DELAY_2_CK_EXMC) && \
((xxx) != EXMC_ALE_RE_DELAY_3_CK_EXMC) && ((xxx) != EXMC_ALE_RE_DELAY_4_CK_EXMC) && \
((xxx) != EXMC_ALE_RE_DELAY_5_CK_EXMC) && ((xxx) != EXMC_ALE_RE_DELAY_6_CK_EXMC) && \
((xxx) != EXMC_ALE_RE_DELAY_7_CK_EXMC) && ((xxx) != EXMC_ALE_RE_DELAY_8_CK_EXMC) && \
((xxx) != EXMC_ALE_RE_DELAY_9_CK_EXMC) && ((xxx) != EXMC_ALE_RE_DELAY_10_CK_EXMC) && \
((xxx) != EXMC_ALE_RE_DELAY_11_CK_EXMC) && ((xxx) != EXMC_ALE_RE_DELAY_12_CK_EXMC) && \
((xxx) != EXMC_ALE_RE_DELAY_13_CK_EXMC) && ((xxx) != EXMC_ALE_RE_DELAY_14_CK_EXMC) && \
((xxx) != EXMC_ALE_RE_DELAY_15_CK_EXMC) && ((xxx) != EXMC_ALE_RE_DELAY_16_CK_EXMC))
#define NOT_EXMC_NAND_CLE_RE_DELAY(xxx) (((xxx) != EXMC_CLE_RE_DELAY_1_CK_EXMC) && ((xxx) != EXMC_CLE_RE_DELAY_2_CK_EXMC) && \
((xxx) != EXMC_CLE_RE_DELAY_3_CK_EXMC) && ((xxx) != EXMC_CLE_RE_DELAY_4_CK_EXMC) && \
((xxx) != EXMC_CLE_RE_DELAY_5_CK_EXMC) && ((xxx) != EXMC_CLE_RE_DELAY_6_CK_EXMC) && \
((xxx) != EXMC_CLE_RE_DELAY_7_CK_EXMC) && ((xxx) != EXMC_CLE_RE_DELAY_8_CK_EXMC) && \
((xxx) != EXMC_CLE_RE_DELAY_9_CK_EXMC) && ((xxx) != EXMC_CLE_RE_DELAY_10_CK_EXMC) && \
((xxx) != EXMC_CLE_RE_DELAY_11_CK_EXMC) && ((xxx) != EXMC_CLE_RE_DELAY_12_CK_EXMC) && \
((xxx) != EXMC_CLE_RE_DELAY_13_CK_EXMC) && ((xxx) != EXMC_CLE_RE_DELAY_14_CK_EXMC) && \
((xxx) != EXMC_CLE_RE_DELAY_15_CK_EXMC) && ((xxx) != EXMC_CLE_RE_DELAY_16_CK_EXMC))
#define NOT_EXMC_NAND_DATABUS_WIDTH(xxx) (((xxx) != EXMC_NAND_DATABUS_WIDTH_8B) && ((xxx) != EXMC_NAND_DATABUS_WIDTH_16B))
#define NOT_EXMC_SDRAM_DEVICE(xxx) (((xxx) != EXMC_SDRAM_DEVICE0) && ((xxx) != EXMC_SDRAM_DEVICE1))
#define NOT_EXMC_SDRAM_PIPELINE_DELAY(xxx) (((xxx) != EXMC_PIPELINE_DELAY_0_CK_EXMC) && ((xxx) != EXMC_PIPELINE_DELAY_1_CK_EXMC) && \
((xxx) != EXMC_PIPELINE_DELAY_2_CK_EXMC))
#define NOT_EXMC_SDCLK(xxx) (((xxx) != EXMC_SDCLK_DISABLE) && ((xxx) != EXMC_SDCLK_PERIODS_2_CK_EXMC) && \
((xxx) != EXMC_SDCLK_PERIODS_3_CK_EXMC) && ((xxx) != EXMC_SDCLK_PERIODS_4_CK_EXMC) && \
((xxx) != EXMC_SDCLK_PERIODS_5_CK_EXMC))
#define NOT_EXMC_SDRAM_CAS_LATENCY(xxx) (((xxx) != EXMC_CAS_LATENCY_1_SDCLK) && ((xxx) != EXMC_CAS_LATENCY_2_SDCLK) && \
((xxx) != EXMC_CAS_LATENCY_3_SDCLK))
#define NOT_EXMC_SDRAM_INTER_BANK(xxx) (((xxx) != EXMC_SDRAM_2_INTER_BANK) && ((xxx) != EXMC_SDRAM_4_INTER_BANK))
#define NOT_EXMC_SDRAM_DATABUS_WIDTH(xxx) (((xxx) != EXMC_SDRAM_DATABUS_WIDTH_8B) && ((xxx) != EXMC_SDRAM_DATABUS_WIDTH_16B) && \
((xxx) != EXMC_SDRAM_DATABUS_WIDTH_32B))
#define NOT_EXMC_SDRAM_ROW_ADDRESS(xxx) (((xxx) != EXMC_SDRAM_ROW_ADDRESS_11) && ((xxx) != EXMC_SDRAM_ROW_ADDRESS_12) && \
((xxx) != EXMC_SDRAM_ROW_ADDRESS_13))
#define NOT_EXMC_SDRAM_COW_ADDRESS(xxx) (((xxx) != EXMC_SDRAM_COW_ADDRESS_8) && ((xxx) != EXMC_SDRAM_COW_ADDRESS_9) && \
((xxx) != EXMC_SDRAM_COW_ADDRESS_10) && ((xxx) != EXMC_SDRAM_COW_ADDRESS_11))
#define NOT_EXMC_BANK_REMAP(xxx) (((xxx) != EXMC_BANK_REMAP_DEFAULT) && ((xxx) != EXMC_BANK_NORPSRAM_SDRAM_SWAP))
#define NOT_EXMC_CLOCK_MODE(xxx) (((xxx) != EXMC_CLOCK_SYN_MODE) && ((xxx) != EXMC_CLOCK_UNCONDITIONALLY))
#define NOT_EXMC_SDRAM_DELAY_CELL(xxx) (((xxx) != EXMC_SDRAM_0_DELAY_CELL) && ((xxx) != EXMC_SDRAM_1_DELAY_CELL) && \
((xxx) != EXMC_SDRAM_2_DELAY_CELL) && ((xxx) != EXMC_SDRAM_3_DELAY_CELL) && \
((xxx) != EXMC_SDRAM_4_DELAY_CELL) && ((xxx) != EXMC_SDRAM_5_DELAY_CELL) && \
((xxx) != EXMC_SDRAM_6_DELAY_CELL) && ((xxx) != EXMC_SDRAM_7_DELAY_CELL) && \
((xxx) != EXMC_SDRAM_8_DELAY_CELL) && ((xxx) != EXMC_SDRAM_9_DELAY_CELL) && \
((xxx) != EXMC_SDRAM_10_DELAY_CELL) && ((xxx) != EXMC_SDRAM_11_DELAY_CELL) && \
((xxx) != EXMC_SDRAM_12_DELAY_CELL) && ((xxx) != EXMC_SDRAM_13_DELAY_CELL) && \
((xxx) != EXMC_SDRAM_14_DELAY_CELL) && ((xxx) != EXMC_SDRAM_15_DELAY_CELL))
#define NOT_EXMC_SDRAM_READSAMPLE(xxx) (((xxx) != EXMC_SDRAM_READSAMPLE_0_EXTRACK) && ((xxx) != EXMC_SDRAM_READSAMPLE_1_EXTRACK))
#define NOT_EXMC_SDRAM_AUTO_REFLESH(xxx) (((xxx) != EXMC_SDRAM_AUTO_REFLESH_1_SDCLK) && ((xxx) != EXMC_SDRAM_AUTO_REFLESH_2_SDCLK) && \
((xxx) != EXMC_SDRAM_AUTO_REFLESH_3_SDCLK) && ((xxx) != EXMC_SDRAM_AUTO_REFLESH_4_SDCLK) && \
((xxx) != EXMC_SDRAM_AUTO_REFLESH_5_SDCLK) && ((xxx) != EXMC_SDRAM_AUTO_REFLESH_6_SDCLK) && \
((xxx) != EXMC_SDRAM_AUTO_REFLESH_7_SDCLK) && ((xxx) != EXMC_SDRAM_AUTO_REFLESH_8_SDCLK) && \
((xxx) != EXMC_SDRAM_AUTO_REFLESH_9_SDCLK) && ((xxx) != EXMC_SDRAM_AUTO_REFLESH_10_SDCLK) && \
((xxx) != EXMC_SDRAM_AUTO_REFLESH_11_SDCLK) && ((xxx) != EXMC_SDRAM_AUTO_REFLESH_12_SDCLK) && \
((xxx) != EXMC_SDRAM_AUTO_REFLESH_13_SDCLK) && ((xxx) != EXMC_SDRAM_AUTO_REFLESH_14_SDCLK) && \
((xxx) != EXMC_SDRAM_AUTO_REFLESH_15_SDCLK))
#define NOT_EXMC_SDRAM_DEVICE_SELECT(xxx) (((xxx) != EXMC_SDRAM_DEVICE0_SELECT) && ((xxx) != EXMC_SDRAM_DEVICE1_SELECT))
#define NOT_EXMC_SDRAM_COMMAND(xxx) (((xxx) != EXMC_SDRAM_NORMAL_OPERATION) && ((xxx) != EXMC_SDRAM_CLOCK_ENABLE) && \
((xxx) != EXMC_SDRAM_PRECHARGE_ALL) && ((xxx) != EXMC_SDRAM_AUTO_REFRESH) && \
((xxx) != EXMC_SDRAM_LOAD_MODE_REGISTER) && ((xxx) != EXMC_SDRAM_SELF_REFRESH) && \
((xxx) != EXMC_SDRAM_POWERDOWN_ENTRY))
#define NOT_EXMC_BANK(xxx) (((xxx) != EXMC_BANK2_NAND) && ((xxx) != EXMC_SDRAM_DEVICE0) && \
((xxx) != EXMC_SDRAM_DEVICE1))
#define NOT_EXMC_NAND_SDRAM_FLAG(xxx) (((xxx) != EXMC_NAND_FLAG_RISE) && ((xxx) != EXMC_NAND_FLAG_LEVEL) && \
((xxx) != EXMC_NAND_FLAG_FALL) && ((xxx) != EXMC_NAND_FLAG_FIFOE) && \
((xxx) != EXMC_SDRAM_FLAG_REFRESH) && ((xxx) != EXMC_SDRAM_FLAG_NREADY))
#define NOT_EXMC_NAND_SDRAM_FLAG_CLR(xxx) (((xxx) != EXMC_NAND_FLAG_RISE) && ((xxx) != EXMC_NAND_FLAG_LEVEL) && \
((xxx) != EXMC_NAND_FLAG_FALL) && ((xxx) != EXMC_NAND_FLAG_FIFOE) && \
((xxx) != EXMC_SDRAM_FLAG_REFRESH))
#define NOT_EXMC_NAND_SDRAM_INT(xxx) (((xxx) != EXMC_NAND_INT_RISE) && ((xxx) != EXMC_NAND_INT_LEVEL) && \
((xxx) != EXMC_NAND_INT_FALL) && ((xxx) != EXMC_SDRAM_INT_REFRESH))
#define NOT_EXMC_NAND_SDRAM_INT_FLAG(xxx) (((xxx) != EXMC_NAND_INT_FLAG_RISE) && ((xxx) != EXMC_NAND_INT_FLAG_LEVEL) && \
((xxx) != EXMC_NAND_INT_FLAG_FALL) && ((xxx) != EXMC_SDRAM_INT_FLAG_REFRESH))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* initialization functions */
/* NOR/SRAM */
/* deinitialize EXMC NOR/SRAM region */
void exmc_norsram_deinit(uint32_t exmc_norsram_region);
/* initialize exmc_norsram_parameter_struct with the default values */
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct);
/* initialize EXMC NOR/SRAM region */
void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct);
/* enable EXMC NOR/SRAM region */
void exmc_norsram_enable(uint32_t exmc_norsram_region);
/* disable EXMC NOR/SRAM region */
void exmc_norsram_disable(uint32_t exmc_norsram_region);
/* NAND */
/* deinitialize EXMC NAND bank */
void exmc_nand_deinit(void);
/* initialize exmc_nand_parameter_struct with the default values */
void exmc_nand_struct_para_init(exmc_nand_parameter_struct *exmc_nand_init_struct);
/* initialize EXMC NAND bank */
void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct);
/* enable EXMC NAND bank */
void exmc_nand_enable(void);
/* disable EXMC NAND bank */
void exmc_nand_disable(void);
/* SDRAM */
/* deinitialize EXMC SDRAM device */
void exmc_sdram_deinit(uint32_t exmc_sdram_device);
/* initialize exmc_sdram_parameter_struct with the default values */
void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct);
/* initialize EXMC SDRAM device */
void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct);
/* configuration functions */
/* NOR/SRAM */
/* configure NOR/PSRAM and SDRAM remap */
void exmc_norsram_sdram_remap_config(uint32_t bank_remap);
/* get NOR/PSRAM and SDRAM remap configuration */
uint32_t exmc_norsram_sdram_remap_get(void);
/* configure consecutive clock mode (only supported in EXMC BANK0 REGION0) */
void exmc_norsram_consecutive_clock_config(uint32_t clock_mode);
/* configure CRAM page size */
void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size);
/* NAND */
/* enable or disable the EXMC NAND ECC function */
void exmc_nand_ecc_config(ControlStatus newvalue);
/* get NAND ECC value */
uint32_t exmc_ecc_get(void);
/* SDRAM */
/* enable read sample function */
void exmc_sdram_readsample_enable(void);
/* disable read sample function */
void exmc_sdram_readsample_disable(void);
/* configure the delayed sample clock of read data */
void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_clk);
/* configure the SDRAM memory command */
void exmc_sdram_command_config(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct);
/* set auto-refresh interval */
void exmc_sdram_refresh_count_set(uint32_t exmc_count);
/* set the number of successive auto-refresh command */
void exmc_sdram_autorefresh_number_set(uint32_t exmc_number);
/* configure the write protection function */
void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue);
/* get the status of SDRAM device0 or device1 */
uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device);
/* interrupt & flag functions */
/* get EXMC flag status */
FlagStatus exmc_flag_get(uint32_t exmc_bank, uint32_t flag);
/* clear EXMC flag status */
void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag);
/* enable EXMC interrupt */
void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt);
/* disable EXMC interrupt */
void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt);
/* get EXMC interrupt flag */
FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt);
/* clear EXMC interrupt flag */
void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt);
#endif /* GD32H75E_EXMC_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_exti.h
+413
View File
@@ -0,0 +1,413 @@
/*!
\file gd32h75e_exti.h
\brief definitions for the EXTI
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_EXTI_H
#define GD32H75E_EXTI_H
#include "gd32h75e.h"
/* EXTI definition */
#define EXTI EXTI_BASE /*!< EXTI base address */
/* registers definitions */
#define EXTI_INTEN0 REG32(EXTI + 0x00000000U) /*!< interrupt enable register 0 */
#define EXTI_EVEN0 REG32(EXTI + 0x00000004U) /*!< event enable register 0 */
#define EXTI_RTEN0 REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register 0 */
#define EXTI_FTEN0 REG32(EXTI + 0x0000000CU) /*!< falling edge trigger enable register 0 */
#define EXTI_SWIEV0 REG32(EXTI + 0x00000010U) /*!< software interrupt event register 0 */
#define EXTI_PD0 REG32(EXTI + 0x00000014U) /*!< pending register 0 */
#define EXTI_INTEN1 REG32(EXTI + 0x00000018U) /*!< interrupt enable register 1 */
#define EXTI_EVEN1 REG32(EXTI + 0x0000001CU) /*!< event enable register 1 */
#define EXTI_RTEN1 REG32(EXTI + 0x00000020U) /*!< rising edge trigger enable register 1 */
#define EXTI_FTEN1 REG32(EXTI + 0x00000024U) /*!< falling edge trigger enable register 1 */
#define EXTI_SWIEV1 REG32(EXTI + 0x00000028U) /*!< software interrupt event register 1 */
#define EXTI_PD1 REG32(EXTI + 0x0000002CU) /*!< pending register 1 */
/* bits definitions */
/* EXTI_INTEN0 */
#define EXTI_INTEN0_INTEN0 BIT(0) /*!< interrupt from line 0 */
#define EXTI_INTEN0_INTEN1 BIT(1) /*!< interrupt from line 1 */
#define EXTI_INTEN0_INTEN2 BIT(2) /*!< interrupt from line 2 */
#define EXTI_INTEN0_INTEN3 BIT(3) /*!< interrupt from line 3 */
#define EXTI_INTEN0_INTEN4 BIT(4) /*!< interrupt from line 4 */
#define EXTI_INTEN0_INTEN5 BIT(5) /*!< interrupt from line 5 */
#define EXTI_INTEN0_INTEN6 BIT(6) /*!< interrupt from line 6 */
#define EXTI_INTEN0_INTEN7 BIT(7) /*!< interrupt from line 7 */
#define EXTI_INTEN0_INTEN8 BIT(8) /*!< interrupt from line 8 */
#define EXTI_INTEN0_INTEN9 BIT(9) /*!< interrupt from line 9 */
#define EXTI_INTEN0_INTEN10 BIT(10) /*!< interrupt from line 10 */
#define EXTI_INTEN0_INTEN11 BIT(11) /*!< interrupt from line 11 */
#define EXTI_INTEN0_INTEN12 BIT(12) /*!< interrupt from line 12 */
#define EXTI_INTEN0_INTEN13 BIT(13) /*!< interrupt from line 13 */
#define EXTI_INTEN0_INTEN14 BIT(14) /*!< interrupt from line 14 */
#define EXTI_INTEN0_INTEN15 BIT(15) /*!< interrupt from line 15 */
#define EXTI_INTEN0_INTEN16 BIT(16) /*!< interrupt from line 16 */
#define EXTI_INTEN0_INTEN17 BIT(17) /*!< interrupt from line 17 */
#define EXTI_INTEN0_INTEN18 BIT(18) /*!< interrupt from line 18 */
#define EXTI_INTEN0_INTEN19 BIT(19) /*!< interrupt from line 19 */
#define EXTI_INTEN0_INTEN20 BIT(20) /*!< interrupt from line 20 */
#define EXTI_INTEN0_INTEN21 BIT(21) /*!< interrupt from line 21 */
#define EXTI_INTEN0_INTEN22 BIT(22) /*!< interrupt from line 22 */
#define EXTI_INTEN0_INTEN23 BIT(23) /*!< interrupt from line 23 */
#define EXTI_INTEN0_INTEN24 BIT(24) /*!< interrupt from line 24 */
#define EXTI_INTEN0_INTEN25 BIT(25) /*!< interrupt from line 25 */
#define EXTI_INTEN0_INTEN26 BIT(26) /*!< interrupt from line 26 */
#define EXTI_INTEN0_INTEN27 BIT(27) /*!< interrupt from line 27 */
#define EXTI_INTEN0_INTEN28 BIT(28) /*!< interrupt from line 28 */
#define EXTI_INTEN0_INTEN29 BIT(29) /*!< interrupt from line 29 */
#define EXTI_INTEN0_INTEN30 BIT(30) /*!< interrupt from line 30 */
#define EXTI_INTEN0_INTEN31 BIT(31) /*!< interrupt from line 31 */
/* EXTI_EVEN0 */
#define EXTI_EVEN0_EVEN0 BIT(0) /*!< event from line 0 */
#define EXTI_EVEN0_EVEN1 BIT(1) /*!< event from line 1 */
#define EXTI_EVEN0_EVEN2 BIT(2) /*!< event from line 2 */
#define EXTI_EVEN0_EVEN3 BIT(3) /*!< event from line 3 */
#define EXTI_EVEN0_EVEN4 BIT(4) /*!< event from line 4 */
#define EXTI_EVEN0_EVEN5 BIT(5) /*!< event from line 5 */
#define EXTI_EVEN0_EVEN6 BIT(6) /*!< event from line 6 */
#define EXTI_EVEN0_EVEN7 BIT(7) /*!< event from line 7 */
#define EXTI_EVEN0_EVEN8 BIT(8) /*!< event from line 8 */
#define EXTI_EVEN0_EVEN9 BIT(9) /*!< event from line 9 */
#define EXTI_EVEN0_EVEN10 BIT(10) /*!< event from line 10 */
#define EXTI_EVEN0_EVEN11 BIT(11) /*!< event from line 11 */
#define EXTI_EVEN0_EVEN12 BIT(12) /*!< event from line 12 */
#define EXTI_EVEN0_EVEN13 BIT(13) /*!< event from line 13 */
#define EXTI_EVEN0_EVEN14 BIT(14) /*!< event from line 14 */
#define EXTI_EVEN0_EVEN15 BIT(15) /*!< event from line 15 */
#define EXTI_EVEN0_EVEN16 BIT(16) /*!< event from line 16 */
#define EXTI_EVEN0_EVEN17 BIT(17) /*!< event from line 17 */
#define EXTI_EVEN0_EVEN18 BIT(18) /*!< event from line 18 */
#define EXTI_EVEN0_EVEN19 BIT(19) /*!< event from line 19 */
#define EXTI_EVEN0_EVEN20 BIT(20) /*!< event from line 20 */
#define EXTI_EVEN0_EVEN21 BIT(21) /*!< event from line 21 */
#define EXTI_EVEN0_EVEN22 BIT(22) /*!< event from line 22 */
#define EXTI_EVEN0_EVEN23 BIT(23) /*!< event from line 23 */
#define EXTI_EVEN0_EVEN24 BIT(24) /*!< event from line 24 */
#define EXTI_EVEN0_EVEN25 BIT(25) /*!< event from line 25 */
#define EXTI_EVEN0_EVEN26 BIT(26) /*!< event from line 26 */
#define EXTI_EVEN0_EVEN27 BIT(27) /*!< event from line 27 */
#define EXTI_EVEN0_EVEN28 BIT(28) /*!< event from line 28 */
#define EXTI_EVEN0_EVEN29 BIT(29) /*!< event from line 29 */
#define EXTI_EVEN0_EVEN30 BIT(30) /*!< event from line 30 */
#define EXTI_EVEN0_EVEN31 BIT(31) /*!< event from line 31 */
/* EXTI_RTEN0 */
#define EXTI_RTEN0_RTEN0 BIT(0) /*!< rising edge from line 0 */
#define EXTI_RTEN0_RTEN1 BIT(1) /*!< rising edge from line 1 */
#define EXTI_RTEN0_RTEN2 BIT(2) /*!< rising edge from line 2 */
#define EXTI_RTEN0_RTEN3 BIT(3) /*!< rising edge from line 3 */
#define EXTI_RTEN0_RTEN4 BIT(4) /*!< rising edge from line 4 */
#define EXTI_RTEN0_RTEN5 BIT(5) /*!< rising edge from line 5 */
#define EXTI_RTEN0_RTEN6 BIT(6) /*!< rising edge from line 6 */
#define EXTI_RTEN0_RTEN7 BIT(7) /*!< rising edge from line 7 */
#define EXTI_RTEN0_RTEN8 BIT(8) /*!< rising edge from line 8 */
#define EXTI_RTEN0_RTEN9 BIT(9) /*!< rising edge from line 9 */
#define EXTI_RTEN0_RTEN10 BIT(10) /*!< rising edge from line 10 */
#define EXTI_RTEN0_RTEN11 BIT(11) /*!< rising edge from line 11 */
#define EXTI_RTEN0_RTEN12 BIT(12) /*!< rising edge from line 12 */
#define EXTI_RTEN0_RTEN13 BIT(13) /*!< rising edge from line 13 */
#define EXTI_RTEN0_RTEN14 BIT(14) /*!< rising edge from line 14 */
#define EXTI_RTEN0_RTEN15 BIT(15) /*!< rising edge from line 15 */
#define EXTI_RTEN0_RTEN16 BIT(16) /*!< rising edge from line 16 */
#define EXTI_RTEN0_RTEN17 BIT(17) /*!< rising edge from line 17 */
#define EXTI_RTEN0_RTEN18 BIT(18) /*!< rising edge from line 18 */
#define EXTI_RTEN0_RTEN19 BIT(19) /*!< rising edge from line 19 */
#define EXTI_RTEN0_RTEN20 BIT(20) /*!< rising edge from line 20 */
#define EXTI_RTEN0_RTEN21 BIT(21) /*!< rising edge from line 21 */
#define EXTI_RTEN0_RTEN22 BIT(22) /*!< rising edge from line 22 */
#define EXTI_RTEN0_RTEN23 BIT(23) /*!< rising edge from line 23 */
#define EXTI_RTEN0_RTEN24 BIT(24) /*!< rising edge from line 24 */
#define EXTI_RTEN0_RTEN25 BIT(25) /*!< rising edge from line 25 */
#define EXTI_RTEN0_RTEN26 BIT(26) /*!< rising edge from line 26 */
#define EXTI_RTEN0_RTEN27 BIT(27) /*!< rising edge from line 27 */
#define EXTI_RTEN0_RTEN28 BIT(28) /*!< rising edge from line 28 */
#define EXTI_RTEN0_RTEN29 BIT(29) /*!< rising edge from line 29 */
#define EXTI_RTEN0_RTEN30 BIT(30) /*!< rising edge from line 30 */
#define EXTI_RTEN0_RTEN31 BIT(31) /*!< rising edge from line 31 */
/* EXTI_FTEN0 */
#define EXTI_FTEN0_FTEN0 BIT(0) /*!< falling edge from line 0 */
#define EXTI_FTEN0_FTEN1 BIT(1) /*!< falling edge from line 1 */
#define EXTI_FTEN0_FTEN2 BIT(2) /*!< falling edge from line 2 */
#define EXTI_FTEN0_FTEN3 BIT(3) /*!< falling edge from line 3 */
#define EXTI_FTEN0_FTEN4 BIT(4) /*!< falling edge from line 4 */
#define EXTI_FTEN0_FTEN5 BIT(5) /*!< falling edge from line 5 */
#define EXTI_FTEN0_FTEN6 BIT(6) /*!< falling edge from line 6 */
#define EXTI_FTEN0_FTEN7 BIT(7) /*!< falling edge from line 7 */
#define EXTI_FTEN0_FTEN8 BIT(8) /*!< falling edge from line 8 */
#define EXTI_FTEN0_FTEN9 BIT(9) /*!< falling edge from line 9 */
#define EXTI_FTEN0_FTEN10 BIT(10) /*!< falling edge from line 10 */
#define EXTI_FTEN0_FTEN11 BIT(11) /*!< falling edge from line 11 */
#define EXTI_FTEN0_FTEN12 BIT(12) /*!< falling edge from line 12 */
#define EXTI_FTEN0_FTEN13 BIT(13) /*!< falling edge from line 13 */
#define EXTI_FTEN0_FTEN14 BIT(14) /*!< falling edge from line 14 */
#define EXTI_FTEN0_FTEN15 BIT(15) /*!< falling edge from line 15 */
#define EXTI_FTEN0_FTEN16 BIT(16) /*!< falling edge from line 16 */
#define EXTI_FTEN0_FTEN17 BIT(17) /*!< falling edge from line 17 */
#define EXTI_FTEN0_FTEN18 BIT(18) /*!< falling edge from line 18 */
#define EXTI_FTEN0_FTEN19 BIT(19) /*!< falling edge from line 19 */
#define EXTI_FTEN0_FTEN20 BIT(20) /*!< falling edge from line 20 */
#define EXTI_FTEN0_FTEN21 BIT(21) /*!< falling edge from line 21 */
#define EXTI_FTEN0_FTEN22 BIT(22) /*!< falling edge from line 22 */
#define EXTI_FTEN0_FTEN23 BIT(23) /*!< falling edge from line 23 */
#define EXTI_FTEN0_FTEN24 BIT(24) /*!< falling edge from line 24 */
#define EXTI_FTEN0_FTEN25 BIT(25) /*!< falling edge from line 25 */
#define EXTI_FTEN0_FTEN26 BIT(26) /*!< falling edge from line 26 */
#define EXTI_FTEN0_FTEN27 BIT(27) /*!< falling edge from line 27 */
#define EXTI_FTEN0_FTEN28 BIT(28) /*!< falling edge from line 28 */
#define EXTI_FTEN0_FTEN29 BIT(29) /*!< falling edge from line 29 */
#define EXTI_FTEN0_FTEN30 BIT(30) /*!< falling edge from line 30 */
#define EXTI_FTEN0_FTEN31 BIT(31) /*!< falling edge from line 31 */
/* EXTI_SWIEV0 */
#define EXTI_SWIEV0_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
#define EXTI_SWIEV0_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
#define EXTI_SWIEV0_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
#define EXTI_SWIEV0_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
#define EXTI_SWIEV0_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
#define EXTI_SWIEV0_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
#define EXTI_SWIEV0_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
#define EXTI_SWIEV0_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
#define EXTI_SWIEV0_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
#define EXTI_SWIEV0_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
#define EXTI_SWIEV0_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
#define EXTI_SWIEV0_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
#define EXTI_SWIEV0_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
#define EXTI_SWIEV0_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
#define EXTI_SWIEV0_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
#define EXTI_SWIEV0_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
#define EXTI_SWIEV0_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
#define EXTI_SWIEV0_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
#define EXTI_SWIEV0_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
#define EXTI_SWIEV0_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
#define EXTI_SWIEV0_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */
#define EXTI_SWIEV0_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */
#define EXTI_SWIEV0_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */
#define EXTI_SWIEV0_SWIEV23 BIT(23) /*!< software interrupt/event request from line 23 */
#define EXTI_SWIEV0_SWIEV24 BIT(24) /*!< software interrupt/event request from line 24 */
#define EXTI_SWIEV0_SWIEV25 BIT(25) /*!< software interrupt/event request from line 25 */
#define EXTI_SWIEV0_SWIEV26 BIT(26) /*!< software interrupt/event request from line 26 */
#define EXTI_SWIEV0_SWIEV27 BIT(27) /*!< software interrupt/event request from line 27 */
#define EXTI_SWIEV0_SWIEV28 BIT(28) /*!< software interrupt/event request from line 28 */
#define EXTI_SWIEV0_SWIEV29 BIT(29) /*!< software interrupt/event request from line 29 */
#define EXTI_SWIEV0_SWIEV30 BIT(30) /*!< software interrupt/event request from line 30 */
#define EXTI_SWIEV0_SWIEV31 BIT(31) /*!< software interrupt/event request from line 31 */
/* EXTI_PD0 */
#define EXTI_PD0_PD0 BIT(0) /*!< interrupt pending status from line 0 */
#define EXTI_PD0_PD1 BIT(1) /*!< interrupt pending status from line 1 */
#define EXTI_PD0_PD2 BIT(2) /*!< interrupt pending status from line 2 */
#define EXTI_PD0_PD3 BIT(3) /*!< interrupt pending status from line 3 */
#define EXTI_PD0_PD4 BIT(4) /*!< interrupt pending status from line 4 */
#define EXTI_PD0_PD5 BIT(5) /*!< interrupt pending status from line 5 */
#define EXTI_PD0_PD6 BIT(6) /*!< interrupt pending status from line 6 */
#define EXTI_PD0_PD7 BIT(7) /*!< interrupt pending status from line 7 */
#define EXTI_PD0_PD8 BIT(8) /*!< interrupt pending status from line 8 */
#define EXTI_PD0_PD9 BIT(9) /*!< interrupt pending status from line 9 */
#define EXTI_PD0_PD10 BIT(10) /*!< interrupt pending status from line 10 */
#define EXTI_PD0_PD11 BIT(11) /*!< interrupt pending status from line 11 */
#define EXTI_PD0_PD12 BIT(12) /*!< interrupt pending status from line 12 */
#define EXTI_PD0_PD13 BIT(13) /*!< interrupt pending status from line 13 */
#define EXTI_PD0_PD14 BIT(14) /*!< interrupt pending status from line 14 */
#define EXTI_PD0_PD15 BIT(15) /*!< interrupt pending status from line 15 */
#define EXTI_PD0_PD16 BIT(16) /*!< interrupt pending status from line 16 */
#define EXTI_PD0_PD17 BIT(17) /*!< interrupt pending status from line 17 */
#define EXTI_PD0_PD18 BIT(18) /*!< interrupt pending status from line 18 */
#define EXTI_PD0_PD19 BIT(19) /*!< interrupt pending status from line 19 */
#define EXTI_PD0_PD20 BIT(20) /*!< interrupt pending status from line 20 */
#define EXTI_PD0_PD21 BIT(21) /*!< interrupt pending status from line 21 */
#define EXTI_PD0_PD22 BIT(22) /*!< interrupt pending status from line 22 */
#define EXTI_PD0_PD23 BIT(23) /*!< interrupt pending status from line 23 */
#define EXTI_PD0_PD24 BIT(24) /*!< interrupt pending status from line 24 */
#define EXTI_PD0_PD25 BIT(25) /*!< interrupt pending status from line 25 */
#define EXTI_PD0_PD26 BIT(26) /*!< interrupt pending status from line 26 */
#define EXTI_PD0_PD27 BIT(27) /*!< interrupt pending status from line 27 */
#define EXTI_PD0_PD28 BIT(28) /*!< interrupt pending status from line 28 */
#define EXTI_PD0_PD29 BIT(29) /*!< interrupt pending status from line 29 */
#define EXTI_PD0_PD30 BIT(30) /*!< interrupt pending status from line 30 */
#define EXTI_PD0_PD31 BIT(31) /*!< interrupt pending status from line 31 */
/* EXTI_INTEN1 */
#define EXTI_INTEN1_INTEN32 BIT(0) /*!< interrupt from line 32 */
#define EXTI_INTEN1_INTEN33 BIT(1) /*!< interrupt from line 33 */
#define EXTI_INTEN1_INTEN34 BIT(2) /*!< interrupt from line 34 */
#define EXTI_INTEN1_INTEN35 BIT(3) /*!< interrupt from line 35 */
#define EXTI_INTEN1_INTEN36 BIT(4) /*!< interrupt from line 36 */
#define EXTI_INTEN1_INTEN37 BIT(5) /*!< interrupt from line 37 */
/* EXTI_EVEN1 */
#define EXTI_EVEN1_EVEN32 BIT(0) /*!< event from line 32 */
#define EXTI_EVEN1_EVEN33 BIT(1) /*!< event from line 33 */
#define EXTI_EVEN1_EVEN34 BIT(2) /*!< event from line 34 */
#define EXTI_EVEN1_EVEN35 BIT(3) /*!< event from line 35 */
#define EXTI_EVEN1_EVEN36 BIT(4) /*!< event from line 36 */
#define EXTI_EVEN1_EVEN37 BIT(5) /*!< event from line 37 */
/* EXTI_RTEN1 */
#define EXTI_RTEN1_RTEN32 BIT(0) /*!< rising edge from line 32 */
#define EXTI_RTEN1_RTEN33 BIT(1) /*!< rising edge from line 33 */
#define EXTI_RTEN1_RTEN34 BIT(2) /*!< rising edge from line 34 */
#define EXTI_RTEN1_RTEN35 BIT(3) /*!< rising edge from line 35 */
#define EXTI_RTEN1_RTEN36 BIT(4) /*!< rising edge from line 36 */
#define EXTI_RTEN1_RTEN37 BIT(5) /*!< rising edge from line 37 */
/* EXTI_FTEN1 */
#define EXTI_FTEN1_FTEN32 BIT(0) /*!< falling edge from line 32 */
#define EXTI_FTEN1_FTEN33 BIT(1) /*!< falling edge from line 33 */
#define EXTI_FTEN1_FTEN34 BIT(2) /*!< falling edge from line 34 */
#define EXTI_FTEN1_FTEN35 BIT(3) /*!< falling edge from line 35 */
#define EXTI_FTEN1_FTEN36 BIT(4) /*!< falling edge from line 36 */
#define EXTI_FTEN1_FTEN37 BIT(5) /*!< falling edge from line 37 */
/* EXTI_SWIEV1 */
#define EXTI_SWIEV1_SWIEV32 BIT(0) /*!< software interrupt/event request from line 32 */
#define EXTI_SWIEV1_SWIEV33 BIT(1) /*!< software interrupt/event request from line 33 */
#define EXTI_SWIEV1_SWIEV34 BIT(2) /*!< software interrupt/event request from line 34 */
#define EXTI_SWIEV1_SWIEV35 BIT(3) /*!< software interrupt/event request from line 35 */
#define EXTI_SWIEV1_SWIEV36 BIT(4) /*!< software interrupt/event request from line 36 */
#define EXTI_SWIEV1_SWIEV37 BIT(5) /*!< software interrupt/event request from line 37 */
/* EXTI_PD1 */
#define EXTI_PD1_PD32 BIT(0) /*!< interrupt pending status from line 32 */
#define EXTI_PD1_PD33 BIT(1) /*!< interrupt pending status from line 33 */
#define EXTI_PD1_PD34 BIT(2) /*!< interrupt pending status from line 34 */
#define EXTI_PD1_PD35 BIT(3) /*!< interrupt pending status from line 35 */
#define EXTI_PD1_PD36 BIT(4) /*!< interrupt pending status from line 36 */
#define EXTI_PD1_PD37 BIT(5) /*!< interrupt pending status from line 37 */
/* constants definitions */
/* define the EXTI bit position and its register group index offset */
#define EXTI_GROUPIDX_BIT(groupidx, bitpos) (((uint32_t)(groupidx) << 8U) | (uint32_t)(bitpos))
#define EXTI_REG_VAL(linex) (EXTI + ((uint32_t)(linex) >> 8U))
#define EXTI_BIT_POS(linex) BIT((uint32_t)(linex) & 0x1FU)
/* define the EXTI register groups*/
#define EXTI_GROUP0_OFFSET 0x00000000U /*!< the index offset of EXTI group0 */
#define EXTI_GROUP1_OFFSET 0x00000018U /*!< the index offset of EXTI group1 */
/* define the registers in the group*/
#define EXTI_INTEN(exti_group) REG32((uint32_t)(exti_group) + 0x00000000U) /*!< the index offset of register INTEN in the registe group */
#define EXTI_EVEN(exti_group) REG32((uint32_t)(exti_group) + 0x00000004U) /*!< the index offset of register EVEN in the registe group */
#define EXTI_RTEN(exti_group) REG32((uint32_t)(exti_group) + 0x00000008U) /*!< the index offset of register RTEN in the registe group */
#define EXTI_FTEN(exti_group) REG32((uint32_t)(exti_group) + 0x0000000CU) /*!< the index offset of register FTEN in the registe group */
#define EXTI_SWIEV(exti_group) REG32((uint32_t)(exti_group) + 0x00000010U) /*!< the index offset of register SWIEV in the registe group */
#define EXTI_PD(exti_group) REG32((uint32_t)(exti_group) + 0x00000014U) /*!< the index offset of register PD in the registe group */
/* EXTI line number */
typedef enum {
EXTI_0 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 0U), /*!< EXTI line 0 */
EXTI_1 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 1U), /*!< EXTI line 1 */
EXTI_2 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 2U), /*!< EXTI line 2 */
EXTI_3 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 3U), /*!< EXTI line 3 */
EXTI_4 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 4U), /*!< EXTI line 4 */
EXTI_5 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 5U), /*!< EXTI line 5 */
EXTI_6 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 6U), /*!< EXTI line 6 */
EXTI_7 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 7U), /*!< EXTI line 7 */
EXTI_8 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 8U), /*!< EXTI line 8 */
EXTI_9 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 9U), /*!< EXTI line 9 */
EXTI_10 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 10U), /*!< EXTI line 10 */
EXTI_11 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 11U), /*!< EXTI line 11 */
EXTI_12 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 12U), /*!< EXTI line 12 */
EXTI_13 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 13U), /*!< EXTI line 13 */
EXTI_14 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 14U), /*!< EXTI line 14 */
EXTI_15 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 15U), /*!< EXTI line 15 */
EXTI_16 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 16U), /*!< EXTI line 16 */
EXTI_17 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 17U), /*!< EXTI line 17 */
EXTI_18 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 18U), /*!< EXTI line 18 */
EXTI_19 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 19U), /*!< EXTI line 19 */
EXTI_20 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 20U), /*!< EXTI line 20 */
EXTI_21 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 21U), /*!< EXTI line 21 */
EXTI_22 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 22U), /*!< EXTI line 22 */
EXTI_23 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 23U), /*!< EXTI line 23 */
EXTI_24 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 24U), /*!< EXTI line 24 */
EXTI_25 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 25U), /*!< EXTI line 25 */
EXTI_26 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 26U), /*!< EXTI line 26 */
EXTI_27 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 27U), /*!< EXTI line 27 */
EXTI_28 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 28U), /*!< EXTI line 28 */
EXTI_29 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 29U), /*!< EXTI line 29 */
EXTI_30 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 30U), /*!< EXTI line 30 */
EXTI_31 = EXTI_GROUPIDX_BIT(EXTI_GROUP0_OFFSET, 31U), /*!< EXTI line 31 */
EXTI_32 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 32U), /*!< EXTI line 32 */
EXTI_33 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 33U), /*!< EXTI line 33 */
EXTI_34 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 34U), /*!< EXTI line 34 */
EXTI_35 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 35U), /*!< EXTI line 35 */
EXTI_36 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 36U), /*!< EXTI line 36 */
EXTI_37 = EXTI_GROUPIDX_BIT(EXTI_GROUP1_OFFSET, 37U) /*!< EXTI line 37 */
} exti_line_enum;
/* external interrupt and event */
typedef enum {
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
EXTI_EVENT /*!< EXTI event mode */
} exti_mode_enum;
/* interrupt and event trigger mode */
typedef enum {
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */
} exti_trig_type_enum;
/* function declarations */
/* initialization, EXTI lines configuration functions */
/* deinitialize the EXTI */
void exti_deinit(void);
/* initialize the EXTI line x */
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
/* enable the interrupts from EXTI line x */
void exti_interrupt_enable(exti_line_enum linex);
/* disable the interrupts from EXTI line x */
void exti_interrupt_disable(exti_line_enum linex);
/* enable the events from EXTI line x */
void exti_event_enable(exti_line_enum linex);
/* disable the events from EXTI line x */
void exti_event_disable(exti_line_enum linex);
/* enable the software interrupt event from EXTI line x */
void exti_software_interrupt_enable(exti_line_enum linex);
/* disable the software interrupt event from EXTI line x */
void exti_software_interrupt_disable(exti_line_enum linex);
/* interrupt & flag functions */
/* get EXTI line x interrupt pending flag */
FlagStatus exti_flag_get(exti_line_enum linex);
/* clear EXTI line x interrupt pending flag */
void exti_flag_clear(exti_line_enum linex);
/* get EXTI line x interrupt pending flag */
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
/* clear EXTI line x interrupt pending flag */
void exti_interrupt_flag_clear(exti_line_enum linex);
#endif /* GD32H75E_EXTI_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_fac.h
+282
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/*!
\file gd32h75e_fac.c
\brief definitions for the FAC
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_FAC_H
#define GD32H75E_FAC_H
#include "gd32h75e.h"
/* FAC definitions */
#define FAC FAC_BASE /*!< FAC base address */
#define REG16_INT(addr) (*(volatile int16_t *)(uint32_t)(addr))
#define REG32_FLOAT(addr) (*(volatile float *)(uint32_t)(addr))
/* registers definitions */
#define FAC_X0BCFG REG32((FAC) + 0x00000000U) /*!< FAC X0 buffer configure register */
#define FAC_X1BCFG REG32((FAC) + 0x00000004U) /*!< FAC X1 buffer configure register */
#define FAC_YBCFG REG32((FAC) + 0x00000008U) /*!< FAC Y buffer configure register */
#define FAC_PARACFG REG32((FAC) + 0x0000000CU) /*!< FAC Parameter configure register */
#define FAC_CTL REG32((FAC) + 0x00000010U) /*!< FAC Control register */
#define FAC_STAT REG32((FAC) + 0x00000014U) /*!< FAC Status register */
#define FAC_WDATA REG32((FAC) + 0x00000018U) /*!< FAC write data register */
#define FAC_RDATA REG32((FAC) + 0x0000001CU) /*!< FAC read data register */
#define FAC_WDATA_INT REG16_INT((FAC) + 0x00000018U) /*!< FAC write data register */
#define FAC_WDATA_FLOAT REG32_FLOAT((FAC) + 0x00000018U)/*!< FAC write data register */
#define FAC_RDATA_INT REG16_INT((FAC) + 0x0000001CU) /*!< FAC read data register */
#define FAC_RDATA_FLOAT REG32_FLOAT((FAC) + 0x0000001CU)/*!< FAC read data register */
/* bits definitions */
/* FAC_X0BCFG */
#define FAC_X0BCFG_X0B_ADDR BITS(0,7) /*!< X0 buffer base address */
#define FAC_X0BCFG_X0B_SIZE BITS(8,15) /*!< X0 buffer allocated size */
#define FAC_X0BCFG_X0_WBFF BITS(24,25) /*!< watermark for buffer full flag */
/* FAC_X1BCFG */
#define FAC_X1BCFG_X1B_ADDR BITS(0,7) /*!< X1 buffer base address */
#define FAC_X1BCFG_X1B_SIZE BITS(8,15) /*!< X1 buffer allocated size */
/* FAC_YBCFG */
#define FAC_YBCFG_YB_ADDR BITS(0,7) /*!< Y buffer base address */
#define FAC_YBCFG_YB_SIZE BITS(8,15) /*!< Y buffer allocated size */
#define FAC_YBCFG_Y_WBEF BITS(24,25) /*!< watermark for buffer empty flag */
/* FAC_PARACFG */
#define FAC_PARACFG_IPP BITS(0,7) /*!< input parameter IPP */
#define FAC_PARACFG_IPQ BITS(8,15) /*!< input parameter IPQ */
#define FAC_PARACFG_IPR BITS(16,23) /*!< input parameter IPR */
#define FAC_PARACFG_FUN BITS(24,30) /*!< function */
#define FAC_PARACFG_EXE BIT(31) /*!< execution */
/* FAC_CTL */
#define FAC_CTL_RIE BIT(0) /*!< read interrupt enable */
#define FAC_CTL_WIE BIT(1) /*!< write interrupt enable */
#define FAC_CTL_OFEIE BIT(2) /*!< overflow error interrupt enable */
#define FAC_CTL_UFEIE BIT(3) /*!< underflow error interrupt enable */
#define FAC_CTL_STEIE BIT(4) /*!< saturation error interrupt enable */
#define FAC_CTL_GSTEIE BIT(5) /*!< gain saturation error interrupt enable */
#define FAC_CTL_DREN BIT(8) /*!< DMA read channel enable */
#define FAC_CTL_DWEN BIT(9) /*!< DMA write channel enable */
#define FAC_CTL_FLTEN BIT(14) /*!< floating point format enable */
#define FAC_CTL_CPEN BIT(15) /*!< clipping enable */
#define FAC_CTL_RST BIT(16) /*!< reset FAC unit */
/* FAC_STAT */
#define FAC_STAT_YBEF BIT(0) /*!< Y buffer empty flag */
#define FAC_STAT_X0BFF BIT(1) /*!< X0 buffer full flag */
#define FAC_STAT_OFEF BIT(8) /*!< overflow error flag */
#define FAC_STAT_UFEF BIT(9) /*!< underflow error flag */
#define FAC_STAT_STEF BIT(10) /*!< saturation error flag */
#define FAC_STAT_GSTEF BIT(11) /*!< gain saturation error flag */
/* FAC_WDATA */
#define FAC_WDATA_WDATA BITS(0,15) /*!< Write data */
/* FAC_RDATA */
#define FAC_RDATA_RDATA BITS(0,15) /*!< Read data */
/* constants definitions */
/* structure for fac filter parameters */
typedef struct
{
uint8_t input_addr; /*!< base address of the input buffer (X0) */
uint8_t input_size; /*!< size of input buffer */
uint8_t coeff_addr; /*!< base address of the coefficient buffer (X1) */
uint8_t coeff_size; /*!< size of coefficient buffer */
uint8_t output_addr; /*!< base address of the output buffer (Y) */
uint8_t output_size; /*!< size of output buffer */
uint8_t ipp; /*!< value P (vector length, number of filter taps, etc.) */
uint8_t ipq; /*!< value Q (vector length, etc.) */
uint8_t ipr; /*!< value R (gain, etc.) */
uint32_t input_threshold; /*!< threshold of input buffer full */
uint32_t output_threshold; /*!< threshold of output buffer empty */
uint32_t clip; /*!< enable or disable the clipping feature */
uint32_t func; /*!< FAC functions select */
}fac_parameter_struct;
/* structure for fac fixed data preload parameters */
typedef struct
{
uint8_t coeffa_size; /*!< size of the coefficient vector A */
int16_t *coeffa_ctx; /*!< [IIR only] content of the coefficient vector A */
uint8_t coeffb_size; /*!< size of the coefficient vector B */
int16_t *coeffb_ctx; /*!< content of the coefficient vector B */
uint8_t input_size; /*!< Size of the input data */
int16_t *input_ctx; /*!< content of the input data */
uint8_t output_size; /*!< size of the output data */
int16_t *output_ctx; /*!< content of the output data */
}fac_fixed_data_preload_struct;
/* structure for fac float data preload parameters */
typedef struct
{
uint8_t coeffa_size; /*!< size of the coefficient vector A */
float *coeffa_ctx; /*!< [IIR only] content of the coefficient vector A */
uint8_t coeffb_size; /*!< size of the coefficient vector B */
float *coeffb_ctx; /*!< content of the coefficient vector B */
uint8_t input_size; /*!< size of the input data */
float *input_ctx; /*!< content of the input data */
uint8_t output_size; /*!< size of the output data */
float *output_ctx; /*!< content of the output data */
}fac_float_data_preload_struct;
/* FAC function select definitions */
#define PARACFG_FUN(regval) (FAC_PARACFG_FUN & ((uint32_t)(regval) << 24))
#define FUNC_LOAD_X0 PARACFG_FUN(1) /*!< load_X0_buffer */
#define FUNC_LOAD_X1 PARACFG_FUN(2) /*!< load_X1_buffer */
#define FUNC_LOAD_Y PARACFG_FUN(3) /*!< load_Y_buffer */
#define FUNC_CONVO_FIR PARACFG_FUN(8) /*!< convolution (FIR filter) */
#define FUNC_IIR_DIRECT_FORM_1 PARACFG_FUN(9) /*!< IIR filter (direct form 1) */
/* FAC watermark setting definitions */
#define X0BCFG_X0_WBFF(regval) (FAC_X0BCFG_X0_WBFF & ((uint32_t)(regval) << 24))
#define FAC_THRESHOLD_1 X0BCFG_X0_WBFF(0) /*!< full/empty flag when buffer less than 1 */
#define FAC_THRESHOLD_2 X0BCFG_X0_WBFF(1) /*!< full/empty flag when buffer less than 2 */
#define FAC_THRESHOLD_4 X0BCFG_X0_WBFF(2) /*!< full/empty flag when buffer less than 4 */
#define FAC_THRESHOLD_8 X0BCFG_X0_WBFF(3) /*!< full/empty flag when buffer less than 8 */
/* FAC clip function definitions */
#define FAC_CP_DISABLE ((uint8_t)0x00U) /*!< clipping disabled */
#define FAC_CP_ENABLE ((uint8_t)0x01U) /*!< clipping enabled */
/* FAC function execution definitions */
#define PARACFG_EXE(regval) (FAC_PARACFG_EXE & ((uint32_t)(regval) << 31))
#define FAC_FUNC_START PARACFG_EXE(0) /*!< start execution function */
#define FAC_FUNC_STOP PARACFG_EXE(1) /*!< stop execution function */
/* FAC DMA mdoe definitions */
#define FAC_DMA_READ FAC_CTL_DREN /*!< enable dma read */
#define FAC_DMA_WRITE FAC_CTL_DWEN /*!< enable dma write */
/* FAC interrupt flag definitions */
#define FAC_INT_FLAG_YBEF ((uint8_t)0x00U) /*!< Y buffer empty interrupt flag */
#define FAC_INT_FLAG_X0BFF ((uint8_t)0x01U) /*!< X0 buffer full interrupt flag */
#define FAC_INT_FLAG_OFEF ((uint8_t)0x02U) /*!< Overflow error interrupt flag */
#define FAC_INT_FLAG_UFEF ((uint8_t)0x03U) /*!< underflow error interrupt flag */
#define FAC_INT_FLAG_STEF ((uint8_t)0x04U) /*!< saturation error interrupt flag */
#define FAC_INT_FLAG_GSTEF ((uint8_t)0x05U) /*!< gain saturation error interrupt flag */
/* FAC flag definitions */
#define FAC_FLAG_YBEF FAC_STAT_YBEF /*!< Y buffer empty flag */
#define FAC_FLAG_X0BFF FAC_STAT_X0BFF /*!< X0 buffer full flag */
#define FAC_FLAG_OFEF FAC_STAT_OFEF /*!< overflow error flag */
#define FAC_FLAG_UFEF FAC_STAT_UFEF /*!< underflow error flag */
#define FAC_FLAG_STEF FAC_STAT_STEF /*!< saturation error flag */
#define FAC_FLAG_GSTEF FAC_STAT_GSTEF /*!< gain saturation error flag */
#define NOT_FAC_THRESHOLD(input_threshold) (((input_threshold) != FAC_THRESHOLD_1) && ((input_threshold) != FAC_THRESHOLD_2) && \
((input_threshold) != FAC_THRESHOLD_4) && ((input_threshold) != FAC_THRESHOLD_8))
#define NOT_FAC_CPMODE(cpmod) (((cpmod) != FAC_CP_ENABLE) && ((cpmod) != FAC_CP_DISABLE))
#define NOT_FAC_DMA_REQ(dma_req) (((dma_req) != FAC_DMA_READ) && ((dma_req) != FAC_DMA_WRITE))
#define NOT_FAC_FUNC(func) (((func) != FUNC_CONVO_FIR) && ((func) != FUNC_IIR_DIRECT_FORM_1))
#define NOT_FAC_INTERRUPT(interrupt) (((interrupt) != FAC_CTL_RIE) && ((interrupt) != FAC_CTL_WIE) && \
((interrupt) != FAC_CTL_OFEIE) && ((interrupt) != FAC_CTL_UFEIE) && \
((interrupt) != FAC_CTL_STEIE) && ((interrupt) != FAC_CTL_GSTEIE))
#define NOT_FAC_INTERRUPT_FLAG(interrupt) (((interrupt) != FAC_INT_FLAG_YBEF) && ((interrupt) != FAC_INT_FLAG_X0BFF) && \
((interrupt) != FAC_INT_FLAG_OFEF) && ((interrupt) != FAC_INT_FLAG_UFEF) && \
((interrupt) != FAC_INT_FLAG_STEF) && ((interrupt) != FAC_INT_FLAG_GSTEF))
#define NOT_FAC_FLAG(flag) (((flag) != FAC_FLAG_YBEF) && ((flag) != FAC_FLAG_X0BFF) && \
((flag) != FAC_FLAG_OFEF) && ((flag) != FAC_FLAG_UFEF) && \
((flag) != FAC_FLAG_STEF) && ((flag) != FAC_FLAG_GSTEF))
/* FAC function declarations */
/* initialization functions */
/* reset the FAC peripheral */
void fac_deinit(void);
/* initialize the FAC filter parameter struct with the default values */
void fac_struct_para_init(fac_parameter_struct* fac_parameter);
/* initialize the FAC fixed data preload parameter struct with the default values */
void fac_fixed_data_preload_init(fac_fixed_data_preload_struct *init_struct);
/* initialize the FAC float data preload parameter struct with the default values */
void fac_float_data_preload_init(fac_float_data_preload_struct *init_struct);
/* initialize the FAC peripheral */
void fac_init(fac_parameter_struct* fac_parameter);
/* FAC preload X0 X1 Y fixed buffer */
void fac_fixed_buffer_preload(fac_fixed_data_preload_struct* init_struct);
/* FAC preload X0 X1 Y float buffer*/
void fac_float_buffer_preload(fac_float_data_preload_struct* init_struct);
/* FAC preload data */
void fac_fixed_data_preload(uint8_t size, int16_t array[]);
/* FAC preload float data */
void fac_float_data_preload(uint8_t size, float array[]);
/* configuration functions */
/* FAC reset write and read pointers */
void fac_reset(void);
/* config the FAC clip feature */
void fac_clip_config(uint8_t cpmod);
/* enable FAC float point format */
void fac_float_enable(void);
/* disable FAC float point format */
void fac_float_disable(void);
/* enable the FAC dma */
void fac_dma_enable(uint32_t dma_req);
/* disable the FAC dma */
void fac_dma_disable(uint32_t dma_req);
/* FAC config input buffer */
void fac_x0_config(uint32_t watermark, uint8_t baseaddr, uint8_t bufsize);
/* FAC config coefficient buffer */
void fac_x1_config(uint8_t baseaddr, uint8_t bufsize);
/* FAC config output buffer */
void fac_y_config(uint32_t watermark, uint8_t baseaddr, uint8_t bufsize);
/* FAC config function execute */
void fac_function_config(fac_parameter_struct* fac_parameter);
/* start the FAC */
void fac_start(void);
/* stop the FAC */
void fac_stop(void);
/* finish the filter calculate */
void fac_finish_calculate(void);
/* FAC data write and read */
/* FAC write data with fixed ponit format */
void fac_fixed_data_write(int16_t data);
/* FAC read data with fixed point format */
int16_t fac_fixed_data_read(void);
/* FAC write data with float ponit format */
void fac_float_data_write(float data);
/* FAC read data with fixed point format */
float fac_float_data_read(void);
/* interrupt & flag functions */
/* enable the FAC interrupt */
void fac_interrupt_enable(uint32_t interrupt);
/* disable the FAC interrupt */
void fac_interrupt_disable(uint32_t interrupt);
/* get the FAC interrupt flag status */
FlagStatus fac_interrupt_flag_get(uint8_t interrupt);
/* get the FAC flag status */
FlagStatus fac_flag_get(uint32_t flag);
#endif /* GD32H75E_FAC_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_fmc.h
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/*!
\file gd32h75e_fmc.h
\brief definitions for the FMC
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_FMC_H
#define GD32H75E_FMC_H
#include "gd32h75e.h"
/* FMC definition */
#define FMC FMC_BASE /*!< FMC register base address */
/* registers definitions */
#define FMC_KEY REG32((FMC) + 0x00000004U) /*!< FMC unlock key register */
#define FMC_OBKEY REG32((FMC) + 0x00000008U) /*!< FMC option byte unlock key register */
#define FMC_CTL REG32((FMC) + 0x0000000CU) /*!< FMC control register */
#define FMC_STAT REG32((FMC) + 0x00000010U) /*!< FMC status register */
#define FMC_ADDR REG32((FMC) + 0x00000014U) /*!< FMC address register */
#define FMC_OBCTL REG32((FMC) + 0x00000018U) /*!< FMC option byte control register */
#define FMC_OBSTAT0_EFT REG32((FMC) + 0x0000001CU) /*!< FMC effective option byte status 0 register */
#define FMC_OBSTAT0_MDF REG32((FMC) + 0x00000020U) /*!< FMC modified option byte status 0 register */
#define FMC_DCRPADDR_EFT REG32((FMC) + 0x00000028U) /*!< FMC effective DCRP address register */
#define FMC_DCRPADDR_MDF REG32((FMC) + 0x0000002CU) /*!< FMC modified DCRP address register */
#define FMC_SCRADDR_EFT REG32((FMC) + 0x00000030U) /*!< FMC effective secure address register */
#define FMC_SCRADDR_MDF REG32((FMC) + 0x00000034U) /*!< FMC modified secure address register */
#define FMC_WP_EFT REG32((FMC) + 0x00000038U) /*!< FMC effective erase/program protection register */
#define FMC_WP_MDF REG32((FMC) + 0x0000003CU) /*!< FMC modified erase/program protection register */
#define FMC_BTADDR_EFT REG32((FMC) + 0x00000040U) /*!< FMC effective boot address register */
#define FMC_BTADDR_MDF REG32((FMC) + 0x00000044U) /*!< FMC modified boot address register */
#define FMC_OBSTAT1_EFT REG32((FMC) + 0x00000050U) /*!< FMC effective option byte status 1 register */
#define FMC_OBSTAT1_MDF REG32((FMC) + 0x00000054U) /*!< FMC modified option byte status 1 register */
#define FMC_NODEC REG32((FMC) + 0x00000060U) /*!< FMC NO-RTDEC area register */
#define FMC_ECCADDR REG32((FMC) + 0x00000064U) /*!< FMC ECC error address register */
#define FMC_AESIV0_EFT REG32((FMC) + 0x00000068U) /*!< FMC effective AES IV 0 register */
#define FMC_AESIV1_EFT REG32((FMC) + 0x0000006CU) /*!< FMC effective AES IV 1 register */
#define FMC_AESIV2_EFT REG32((FMC) + 0x00000070U) /*!< FMC effective AES IV 2 register */
#define FMC_AESIV0_MDF REG32((FMC) + 0x00000074U) /*!< FMC modified AES IV 0 register */
#define FMC_AESIV1_MDF REG32((FMC) + 0x00000078U) /*!< FMC modified AES IV 1 register */
#define FMC_AESIV2_MDF REG32((FMC) + 0x0000007CU) /*!< FMC modified AES IV 2 register */
#define FMC_PID0 REG32((FMC) + 0x00000100U) /*!< FMC product ID register 0 */
#define FMC_PID1 REG32((FMC) + 0x00000104U) /*!< FMC product ID register 1 */
/* bits definitions */
/* FMC_KEY */
#define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key bits */
/* FMC_OBKEY */
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option byte unlock key bits */
/* FMC_CTL */
#define FMC_CTL_LK BIT(0) /*!< FMC_CTL lock bit */
#define FMC_CTL_PG BIT(1) /*!< main flash program command bit */
#define FMC_CTL_SER BIT(2) /*!< main flash sector erase command bit */
#define FMC_CTL_MER BIT(3) /*!< main flash mass erase command bit */
#define FMC_CTL_PGCHEN BIT(4) /*!< check programming area enable bit */
#define FMC_CTL_START BIT(7) /*!< send erase command to FMC bit */
#define FMC_CTL_ENDIE BIT(16) /*!< end of operation interrupt enable bit */
#define FMC_CTL_WPERRIE BIT(17) /*!< erase/program protection error interrupt enable bit */
#define FMC_CTL_PGSERRIE BIT(18) /*!< program sequence error interrupt enable bit */
#define FMC_CTL_RPERRIE BIT(23) /*!< read protection error interrupt enable bit */
#define FMC_CTL_RSERRIE BIT(24) /*!< read secure error interrupt enable bit */
#define FMC_CTL_ECCCORIE BIT(25) /*!< one bit correct error interrupt enable bit */
#define FMC_CTL_ECCDETIE BIT(26) /*!< two bits detect error interrupt enable bit */
/* FMC_STAT */
#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */
#define FMC_STAT_ENDF BIT(16) /*!< end of operation flag bit */
#define FMC_STAT_WPERR BIT(17) /*!< erase/program protection error flag bit */
#define FMC_STAT_PGSERR BIT(18) /*!< program sequence error flag bit */
#define FMC_STAT_RPERR BIT(23) /*!< read protection error flag bit */
#define FMC_STAT_RSERR BIT(24) /*!< read secure error flag bit */
#define FMC_STAT_ECCCOR BIT(25) /*!< one bit correct error flag bit */
#define FMC_STAT_ECCDET BIT(26) /*!< two bits detect error flag bit */
#define FMC_STAT_OBMERR BIT(30) /*!< option byte modify error flag */
#define FMC_STAT_FECCF BIT(31) /*!< flash ECC function flag */
/* FMC_ADDR */
#define FMC_ADDR_ADDR BITS(0,31) /*!< address of flash to be erased */
/* FMC_OBCTL */
#define FMC_OBCTL_OBLK BIT(0) /*!< FMC_OBCTL lock bit */
#define FMC_OBCTL_OBSTART BIT(1) /*!< send option bytes modification start command to FMC */
#define FMC_OBCTL_OBMERRIE BIT(30) /*!< option byte modify error interrupt enable bit */
/* FMC_OBSTAT0_EFT */
#define FMC_OBSTAT0_EFT_BOR_TH BITS(2,3) /*!< effective option byte brownout reset threshold value */
#define FMC_OBSTAT0_EFT_NWDG_HW BIT(4) /*!< effective option byte watchdog value */
#define FMC_OBSTAT0_EFT_NRST_DPSLP BIT(6) /*!< effective option byte deepsleep reset value */
#define FMC_OBSTAT0_EFT_NRST_STDBY BIT(7) /*!< effective option byte standby reset value */
#define FMC_OBSTAT0_EFT_SPC BITS(8,15) /*!< effective option byte security protection code */
#define FMC_OBSTAT0_EFT_FWDGSPD_DPSLP BIT(17) /*!< effective option byte watchdog suspend status in deepsleep mode */
#define FMC_OBSTAT0_EFT_FWDGSPD_STDBY BIT(18) /*!< effective option byte watchdog suspend status in standby mode */
#define FMC_OBSTAT0_EFT_SCR BIT(21) /*!< effective option byte security access mode status bit */
#define FMC_OBSTAT0_EFT_ITCMECCEN BIT(22) /*!< effective option byte ITCM ECC function enable status bit */
#define FMC_OBSTAT0_EFT_DTCM0ECCEN BIT(23) /*!< effective option byte DTCM0 ECC function enable status bit */
#define FMC_OBSTAT0_EFT_DTCM1ECCEN BIT(24) /*!< effective option byte DTCM1 ECC function enable status bit */
#define FMC_OBSTAT0_EFT_IOSPDOPEN BIT(29) /*!< effective option byte I/O speed optimization, high-speed at low-voltage enable status bit */
/* FMC_OBSTAT0_MDF */
#define FMC_OBSTAT0_MDF_BOR_TH BITS(2,3) /*!< modified option byte brownout reset threshold value */
#define FMC_OBSTAT0_MDF_NWDG_HW BIT(4) /*!< modified option byte watchdog value */
#define FMC_OBSTAT0_MDF_NRST_DPSLP BIT(6) /*!< modified option byte deepsleep reset value */
#define FMC_OBSTAT0_MDF_NRST_STDBY BIT(7) /*!< modified option byte standby reset value */
#define FMC_OBSTAT0_MDF_SPC BITS(8,15) /*!< modified option byte security protection code */
#define FMC_OBSTAT0_MDF_FWDGSPD_DPSLP BIT(17) /*!< modified option byte watchdog suspend status in deepsleep mode */
#define FMC_OBSTAT0_MDF_FWDGSPD_STDBY BIT(18) /*!< modified option byte watchdog suspend status in standby mode */
#define FMC_OBSTAT0_MDF_SCR BIT(21) /*!< modified option byte security access mode status bit */
#define FMC_OBSTAT0_MDF_ITCMECCEN BIT(22) /*!< modified option byte ITCM ECC function enable status bit */
#define FMC_OBSTAT0_MDF_DTCM0ECCEN BIT(23) /*!< modified option byte DTCM0 ECC function enable status bit */
#define FMC_OBSTAT0_MDF_DTCM1ECCEN BIT(24) /*!< modified option byte DTCM1 ECC function enable status bit */
#define FMC_OBSTAT0_MDF_IOSPDOPEN BIT(29) /*!< modified option byte I/O speed optimization, high-speed at low-voltage enable status bit */
/* FMC_DCRPADDR_EFT */
#define FMC_DCRPADDR_EFT_DCRP_AREA_START BITS(0,10) /*!< effective option byte DCRP area start status bits */
#define FMC_DCRPADDR_EFT_DCRP_AREA_END BITS(16,26) /*!< effective option byte DCRP area end status bits */
#define FMC_DCRPADDR_EFT_DCRP_EREN BIT(31) /*!< effective option byte DCRP area erase enable bit */
/* FMC_DCRPADDR_MDF */
#define FMC_DCRPADDR_MDF_DCRP_AREA_START BITS(0,10) /*!< modified option byte DCRP area start status bits */
#define FMC_DCRPADDR_MDF_DCRP_AREA_END BITS(16,26) /*!< modified option byte DCRP area end status bits */
#define FMC_DCRPADDR_MDF_DCRP_EREN BIT(31) /*!< modified option byte DCRP area erase enable bit */
/* FMC_SCRADDR_EFT */
#define FMC_SCRADDR_EFT_SCR_AREA_START BITS(0,10) /*!< effective option byte secure-access area start status bits */
#define FMC_SCRADDR_EFT_SCR_AREA_END BITS(16,26) /*!< effective option byte secure-access area end status bits */
#define FMC_SCRADDR_EFT_SCR_EREN BIT(31) /*!< effective option byte secure-access area erase enable bit */
/* FMC_SCRADDR_MDF */
#define FMC_SCRADDR_MDF_SCR_AREA_START BITS(0,10) /*!< modified option byte secure-access area start status bits */
#define FMC_SCRADDR_MDF_SCR_AREA_END BITS(16,26) /*!< modified option byte secure-access area end status bits */
#define FMC_SCRADDR_MDF_SCR_EREN BIT(31) /*!< modified option byte secure-access area erase enable bit */
/* FMC_WP_EFT */
#define FMC_WP_EFT_WP BITS(0,29) /*!< effective option byte erase/program protection status bits */
/* FMC_WP_MDF */
#define FMC_WP_MDF_WP BITS(0,29) /*!< modified option byte erase/program protection status bits */
/* FMC_BTADDR_EFT */
#define FMC_BTADDR_EFT_BOOT_ADDR0 BITS(0,15) /*!< effective option byte boot address 0 */
#define FMC_BTADDR_EFT_BOOT_ADDR1 BITS(16,31) /*!< effective option byte boot address 1 */
/* FMC_BTADDR_MDF */
#define FMC_BTADDR_MDF_BOOT_ADDR0 BITS(0,15) /*!< modified option byte boot address 0 */
#define FMC_BTADDR_MDF_BOOT_ADDR1 BITS(16,31) /*!< modified option byte boot address 1 */
/* FMC_OBSTAT1_EFT */
#define FMC_OBSTAT1_EFT_ITCM_SZ_SHRRAM BITS(0,3) /*!< effective option byte ITCM size of shared RAM */
#define FMC_OBSTAT1_EFT_DTCM_SZ_SHRRAM BITS(4,7) /*!< effective option byte DTCM size of shared RAM */
#define FMC_OBSTAT1_EFT_DATA BITS(16,31) /*!< effective option byte user data value */
/* FMC_OBSTAT1_MDF */
#define FMC_OBSTAT1_MDF_ITCM_SZ_SHRRAM BITS(0,3) /*!< modified option byte ITCM size of shared RAM */
#define FMC_OBSTAT1_MDF_DTCM_SZ_SHRRAM BITS(4,7) /*!< modified option byte DTCM size of shared RAM */
#define FMC_OBSTAT1_MDF_DATA BITS(16,31) /*!< modified option byte user data value */
/* FMC_NODEC */
#define FMC_NODEC_NODEC_AREA_START BITS(0,10) /*!< NO-RTDEC area start status bits */
#define FMC_NODEC_NODEC_AREA_END BITS(16,26) /*!< NO-RTDEC area end status bits */
/* FMC_ECCADDR */
#define FMC_ECCADDR_ECCADDR BITS(0,31) /*!< address of byte where an ECC error is detected */
/* FMC_AESIV0_EFT */
#define FMC_AESIV0_EFT_AESIV BITS(0,31) /*!< AES initialization vector status value 0 */
/* FMC_AESIV1_EFT */
#define FMC_AESIV1_EFT_AESIV BITS(0,31) /*!< AES initialization vector status value 1 */
/* FMC_AESIV2_EFT */
#define FMC_AESIV2_EFT_AESIV BITS(0,31) /*!< AES initialization vector status value 2 */
/* FMC_AESIV0_MDF */
#define FMC_AESIV0_MDF_AESIV BITS(0,31) /*!< AES initialization vector configuration value 0 */
/* FMC_AESIV1_MDF */
#define FMC_AESIV1_MDF_AESIV BITS(0,31) /*!< AES initialization vector configuration value 1 */
/* FMC_AESIV2_MDF */
#define FMC_AESIV2_MDF_AESIV BITS(0,31) /*!< AES initialization vector configuration value 2 */
/* FMC_PID0 */
#define FMC_PID0_PID BITS(0,31) /*!< product ID 0 */
/* FMC_PID1 */
#define FMC_PID1_PID BITS(0,31) /*!< product ID 1 */
/* constants definitions */
/* FMC state */
typedef enum {
FMC_READY = 0U, /*!< the operation has been completed */
FMC_BUSY, /*!< the operation is in progress */
FMC_WPERR, /*!< erase/program protection error */
FMC_PGSERR, /*!< program sequence error */
FMC_RPERR, /*!< read protection error */
FMC_RSERR, /*!< read secure error */
FMC_ECCCOR, /*!< one bit correct error */
FMC_ECCDET, /*!< two bits detect error */
FMC_OBMERR, /*!< option byte modify error */
FMC_TOERR /*!< timeout error */
} fmc_state_enum;
/* define the FMC bit position and its register index offset */
#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define FMC_REG_VAL(offset) (REG32(FMC + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
#define FMC_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define FMC_REG_VAL2(offset) (REG32(FMC + ((uint32_t)(offset) >> 22)))
#define FMC_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
/* register offset */
#define FMC_STAT_REG_OFFSET ((uint32_t)0x00000010U) /*!< STAT register offset */
#define FMC_CTL_REG_OFFSET ((uint32_t)0x0000000CU) /*!< CTL register offset */
#define FMC_OBCTL_REG_OFFSET ((uint32_t)0x00000018U) /*!< OBCTL register offset */
/* FMC flags */
typedef enum {
/* flags in STAT register */
FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 0U), /*!< flash busy flag */
FMC_FLAG_END = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 16U), /*!< flash end of operation flag */
FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 17U), /*!< flash erase/program protection error flag */
FMC_FLAG_PGSERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 18U), /*!< flash program sequence error flag */
FMC_FLAG_RPERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 23U), /*!< flash read protection error flag */
FMC_FLAG_RSERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 24U), /*!< flash read secure error flag */
FMC_FLAG_ECCCOR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 25U), /*!< flash one bit correct error flag */
FMC_FLAG_ECCDET = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 26U), /*!< flash two bits detect error flag */
FMC_FLAG_OBMERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 30U), /*!< option byte modify error flag */
FMC_FLAG_FECC = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 31U) /*!< flash ECC function flag */
} fmc_flag_enum;
/* FMC interrupt flags */
typedef enum {
/* interrupt flags in STAT register */
FMC_INT_FLAG_END = FMC_REGIDX_BIT2(FMC_CTL_REG_OFFSET, 16U, FMC_STAT_REG_OFFSET, 16U), /*!< flash end of operation interrupt flag */
FMC_INT_FLAG_WPERR = FMC_REGIDX_BIT2(FMC_CTL_REG_OFFSET, 17U, FMC_STAT_REG_OFFSET, 17U), /*!< flash erase/program protection error interrupt flag */
FMC_INT_FLAG_PGSERR = FMC_REGIDX_BIT2(FMC_CTL_REG_OFFSET, 18U, FMC_STAT_REG_OFFSET, 18U), /*!< flash program sequence error interrupt flag */
FMC_INT_FLAG_RPERR = FMC_REGIDX_BIT2(FMC_CTL_REG_OFFSET, 23U, FMC_STAT_REG_OFFSET, 23U), /*!< flash read protection error interrupt flag */
FMC_INT_FLAG_RSERR = FMC_REGIDX_BIT2(FMC_CTL_REG_OFFSET, 24U, FMC_STAT_REG_OFFSET, 24U), /*!< flash read secure error interrupt flag */
FMC_INT_FLAG_ECCCOR = FMC_REGIDX_BIT2(FMC_CTL_REG_OFFSET, 25U, FMC_STAT_REG_OFFSET, 25U), /*!< flash one bit error detected and correct interrupt flag */
FMC_INT_FLAG_ECCDET = FMC_REGIDX_BIT2(FMC_CTL_REG_OFFSET, 26U, FMC_STAT_REG_OFFSET, 26U), /*!< flash two bit errors detect interrupt flag */
FMC_INT_FLAG_OBMERR = FMC_REGIDX_BIT2(FMC_OBCTL_REG_OFFSET, 30U, FMC_STAT_REG_OFFSET, 30U) /*!< option byte modify error flag */
} fmc_interrupt_flag_enum;
/* FMC interrupt */
typedef enum {
/* interrupt in CTL register */
FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 16U), /*!< FMC end of operation interrupt */
FMC_INT_WPERR = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 17U), /*!< FMC erase/program protection error interrupt */
FMC_INT_PGSERR = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 18U), /*!< FMC program sequence error interrupt */
FMC_INT_RPERR = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 23U), /*!< FMC read protection error interrupt */
FMC_INT_RSERR = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 24U), /*!< FMC read secure error interrupt */
FMC_INT_ECCCOR = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 25U), /*!< FMC one bit correct error interrupt */
FMC_INT_ECCDET = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 26U), /*!< FMC two bits detect error interrupt */
/* interrupt in OBCTL register */
FMC_INT_OBMERR = FMC_REGIDX_BIT(FMC_OBCTL_REG_OFFSET, 30U) /*!< FMC option byte modify error interrupt */
} fmc_interrupt_enum;
/* unlock key */
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
/* option byte unlock key */
#define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< option byte unlock key 0 */
#define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< option byte unlock key 1 */
/* option byte BOR threshold value */
#define OBSTAT0_BOR_TH(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U))
#define OB_BOR_TH_OFF OBSTAT0_BOR_TH(0) /*!< no BOR function */
#define OB_BOR_TH_VALUE1 OBSTAT0_BOR_TH(1) /*!< BOR threshold value 1 */
#define OB_BOR_TH_VALUE2 OBSTAT0_BOR_TH(2) /*!< BOR threshold value 2 */
#define OB_BOR_TH_VALUE3 OBSTAT0_BOR_TH(3) /*!< BOR threshold value 3 */
/* option byte software/hardware free watchdog timer */
#define OBSTAT0_NWDG_HW(regval) (BIT(4) & ((uint32_t)(regval) << 4U))
#define OB_FWDGT_HW OBSTAT0_NWDG_HW(0) /*!< hardware free watchdog */
#define OB_FWDGT_SW OBSTAT0_NWDG_HW(1) /*!< software free watchdog */
/* option byte reset or not entering deep sleep mode */
#define OBSTAT0_NRST_DPSLP(regval) (BIT(6) & ((uint32_t)(regval) << 6U))
#define OB_DEEPSLEEP_RST OBSTAT0_NRST_DPSLP(0) /*!< generate a reset instead of entering deepsleep mode */
#define OB_DEEPSLEEP_NRST OBSTAT0_NRST_DPSLP(1) /*!< no reset when entering deepsleep mode */
/* option byte reset or not entering standby mode */
#define OBSTAT0_NRST_STDBY(regval) (BIT(7) & ((uint32_t)(regval) << 7U))
#define OB_STDBY_RST OBSTAT0_NRST_STDBY(0) /*!< generate a reset instead of entering standby mode */
#define OB_STDBY_NRST OBSTAT0_NRST_STDBY(1) /*!< no reset when entering standby mode */
/* option byte FWDGT status in deep-sleep mode */
#define OBSTAT0_FWDGSPD_DPSLP(regval) (BIT(17) & ((uint32_t)(regval)<< 17U))
#define OB_DPSLP_FWDGT_SUSPEND OBSTAT0_FWDGSPD_DPSLP(0) /*!< free watchdog is suspended in deepsleep mode */
#define OB_DPSLP_FWDGT_RUN OBSTAT0_FWDGSPD_DPSLP(1) /*!< free watchdog is running in deepsleep mode */
/* option byte FWDGT status in standby mode */
#define OBSTAT0_FWDGSPD_STDBY(regval) (BIT(18) & ((uint32_t)(regval) << 18U))
#define OB_STDBY_FWDGT_SUSPEND OBSTAT0_FWDGSPD_STDBY(0) /*!< free watchdog is suspended in standby mode */
#define OB_STDBY_FWDGT_RUN OBSTAT0_FWDGSPD_STDBY(1) /*!< free watchdog is running in standby mode */
/* option byte security access mode configuration */
#define OBSTAT0_SCR(regval) (BIT(21) & ((uint32_t)(regval) << 21U))
#define OB_SECURE_MODE_DISABLE OBSTAT0_SCR(0) /*!< secure access mode disable */
#define OB_SECURE_MODE_ENABLE OBSTAT0_SCR(1) /*!< secure access mode enable */
/* option byte ITCM ECC function enable configuration */
#define OBSTAT0_ITCMECCEN(regval) (BIT(22) & ((uint32_t)(regval) << 22U))
#define OB_ITCMECCEN_DISABLE OBSTAT0_ITCMECCEN(0) /*!< ITCM ECC function disable */
#define OB_ITCMECCEN_ENABLE OBSTAT0_ITCMECCEN(1) /*!< ITCM ECC function enable */
/* option byte DTCM0 ECC function enable configuration */
#define OBSTAT0_DTCM0ECCEN(regval) (BIT(23) & ((uint32_t)(regval) << 23U))
#define OB_DTCM0ECCEN_DISABLE OBSTAT0_DTCM0ECCEN(0) /*!< DTCM0 ECC function disable */
#define OB_DTCM0ECCEN_ENABLE OBSTAT0_DTCM0ECCEN(1) /*!< DTCM0 ECC function enable */
/* option byte DTCM1 ECC function enable configuration */
#define OBSTAT0_DTCM1ECCEN(regval) (BIT(24) & ((uint32_t)(regval) << 24U))
#define OB_DTCM1ECCEN_DISABLE OBSTAT0_DTCM1ECCEN(0) /*!< DTCM1 ECC function disable */
#define OB_DTCM1ECCEN_ENABLE OBSTAT0_DTCM1ECCEN(1) /*!< DTCM1 ECC function enable */
/* option byte I/O speed optimization configuration */
#define OBSTAT0_IOSPDOPEN(regval) (BIT(29) & ((uint32_t)(regval) << 29U))
#define OB_IOSPDOPEN_DISABLE OBSTAT0_IOSPDOPEN(0) /*!< I/O speed optimization, high-speed at low-voltage diable */
#define OB_IOSPDOPEN_ENABLE OBSTAT0_IOSPDOPEN(1) /*!< I/O speed optimization, high-speed at low-voltage enable */
/* option byte security protection configuration */
#define FMC_NSPC ((uint8_t)0xAAU) /*!< no protection */
#define FMC_LSPC ((uint8_t)0xBBU) /*!< protection level low */
#define FMC_HSPC ((uint8_t)0xCCU) /*!< protection level high */
/* option byte DCRP erase enable configuration */
#define OB_DCRPADDR_DCRP_EREN(regval) (BIT(31) & ((uint32_t)(regval) << 31U))
#define OB_DCRP_AREA_ERASE_DISABLE OB_DCRPADDR_DCRP_EREN(0) /*!< DCRP area erase disable */
#define OB_DCRP_AREA_ERASE_ENABLE OB_DCRPADDR_DCRP_EREN(1) /*!< DCRP area erase enable */
/* option byte secure-access erase enable configuration */
#define OB_SCRADDR_SCR_EREN(regval) (BIT(31) & ((uint32_t)(regval) << 31U))
#define OB_SCR_AREA_ERASE_DISABLE OB_SCRADDR_SCR_EREN(0) /*!< secure-access area erase disable */
#define OB_SCR_AREA_ERASE_ENABLE OB_SCRADDR_SCR_EREN(1) /*!< secure-access area erase enable */
/* option byte erase/program protection */
#define OB_WP_0 BIT(0) /*!< erase/program protection of sector 0~15 */
#define OB_WP_1 BIT(1) /*!< erase/program protection of sector 16~31 */
#define OB_WP_2 BIT(2) /*!< erase/program protection of sector 32~47 */
#define OB_WP_3 BIT(3) /*!< erase/program protection of sector 48~63 */
#define OB_WP_4 BIT(4) /*!< erase/program protection of sector 64~79 */
#define OB_WP_5 BIT(5) /*!< erase/program protection of sector 80~95 */
#define OB_WP_6 BIT(6) /*!< erase/program protection of sector 96~111 */
#define OB_WP_7 BIT(7) /*!< erase/program protection of sector 112~127 */
#define OB_WP_8 BIT(8) /*!< erase/program protection of sector 128~143 */
#define OB_WP_9 BIT(9) /*!< erase/program protection of sector 144~159 */
#define OB_WP_10 BIT(10) /*!< erase/program protection of sector 160~175 */
#define OB_WP_11 BIT(11) /*!< erase/program protection of sector 176~191 */
#define OB_WP_12 BIT(12) /*!< erase/program protection of sector 192~207 */
#define OB_WP_13 BIT(13) /*!< erase/program protection of sector 208~223 */
#define OB_WP_14 BIT(14) /*!< erase/program protection of sector 224~239 */
#define OB_WP_15 BIT(15) /*!< erase/program protection of sector 240~255 */
#define OB_WP_16 BIT(16) /*!< erase/program protection of sector 256~383 */
#define OB_WP_17 BIT(17) /*!< erase/program protection of sector 384~511 */
#define OB_WP_18 BIT(18) /*!< erase/program protection of sector 512~639 */
#define OB_WP_19 BIT(19) /*!< erase/program protection of sector 640~767 */
#define OB_WP_20 BIT(20) /*!< erase/program protection of sector 768~895 */
#define OB_WP_21 BIT(21) /*!< erase/program protection of sector 896~1023 */
#define OB_WP_ALL BITS(0,29) /*!< erase/program protection of all sectors */
/* option byte DTCM size of shared RAM */
#define OBSTAT1_DTCM_SZ_SHRRAM(regval) (BITS(4,7) & ((uint32_t)(regval) << 4U))
#define OB_DTCM_SHARED_RAM_0KB OBSTAT1_DTCM_SZ_SHRRAM(0) /*!< DTCM shared RAM size is 0KB */
#define OB_DTCM_SHARED_RAM_64KB OBSTAT1_DTCM_SZ_SHRRAM(7) /*!< DTCM shared RAM size is 64KB */
#define OB_DTCM_SHARED_RAM_128KB OBSTAT1_DTCM_SZ_SHRRAM(8) /*!< DTCM shared RAM size is 128KB */
#define OB_DTCM_SHARED_RAM_256KB OBSTAT1_DTCM_SZ_SHRRAM(9) /*!< DTCM shared RAM size is 256KB */
#define OB_DTCM_SHARED_RAM_512KB OBSTAT1_DTCM_SZ_SHRRAM(10) /*!< DTCM shared RAM size is 512KB */
/* option byte ITCM size of shared RAM */
#define OBSTAT1_ITCM_SZ_SHRRAM(regval) (BITS(0,3) & ((uint32_t)(regval)))
#define OB_ITCM_SHARED_RAM_0KB OBSTAT1_ITCM_SZ_SHRRAM(0) /*!< ITCM shared RAM size is 0KB */
#define OB_ITCM_SHARED_RAM_64KB OBSTAT1_ITCM_SZ_SHRRAM(7) /*!< ITCM shared RAM size is 64KB */
#define OB_ITCM_SHARED_RAM_128KB OBSTAT1_ITCM_SZ_SHRRAM(8) /*!< ITCM shared RAM size is 128KB */
#define OB_ITCM_SHARED_RAM_256KB OBSTAT1_ITCM_SZ_SHRRAM(9) /*!< ITCM shared RAM size is 256KB */
#define OB_ITCM_SHARED_RAM_512KB OBSTAT1_ITCM_SZ_SHRRAM(10) /*!< ITCM shared RAM size is 512KB */
/* boot pin value definitions */
#define BOOT_PIN_0 ((uint8_t)0x00U) /*!< boot pin value is 0 */
#define BOOT_PIN_1 ((uint8_t)0x01U) /*!< boot pin value is 1 */
#define MAIN_FLASH_BASE_ADDRESS ((uint32_t)0x08000000U) /*!< main flash base address */
#define SCR_SIZE_UNIT ((uint32_t)0x00001000U) /*!< secure-access area granularity */
#define DCRP_SIZE_UNIT ((uint32_t)0x00001000U) /*!< DCRP area granularity */
#define FMC_TIMEOUT_COUNT ((uint32_t)0xFFFFFFFFU) /*!< count to judge of FMC timeout */
#define INVLD_AREA_ADDRESS ((uint8_t)0x00U) /*!< the area address is invalid */
#define VLD_AREA_ADDRESS ((uint8_t)0x01U) /*!< the area address is valid */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check erase address */
#define NOT_FMC_VALID_PAGEERASE_ADDR(addr) (((addr) < 0x08000000U) || ((addr) > 0x083BFFFFU))
/* check program address */
#define NOT_FMC_VALID_PROGRAM_ADDR(addr) (((addr) < 0x08000000U) || ((addr) > 0x083BFFFFU))
/* check security protection value */
#define NOT_FMC_SPC_VALUE(ob_spc) (((ob_spc) != FMC_NSPC) && ((ob_spc) != FMC_LSPC) && ((ob_spc) != FMC_HSPC))
/* check BOR threshold value */
#define NOT_FMC_BOR_TH(ob_bor_th) (((ob_bor_th) != OB_BOR_TH_VALUE3) && ((ob_bor_th) != OB_BOR_TH_VALUE2) && \
((ob_bor_th) != OB_BOR_TH_VALUE1) && ((ob_bor_th) != OB_BOR_TH_OFF))
/* check watchdog value */
#define NOT_FMC_FWDGT_VALUE(ob_fwdgt) (((ob_fwdgt) != OB_FWDGT_SW) && ((ob_fwdgt) != OB_FWDGT_HW))
/* check deepsleep reset value */
#define NOT_FMC_DEEPSLEEP_VALUE(ob_deepsleep) (((ob_deepsleep) != OB_DEEPSLEEP_NRST) && ((ob_deepsleep) != OB_DEEPSLEEP_RST))
/* check standby reset value */
#define NOT_FMC_STDBY_VALUE(ob_stdby) (((ob_stdby) != OB_STDBY_NRST) && ((ob_stdby) != OB_STDBY_RST))
/* check FWDG suspend status in deep-sleep mode */
#define NOT_FMC_DPSLP_FWDGT_VALUE(fwdg_deepsleep) (((fwdg_deepsleep) != OB_DPSLP_FWDGT_SUSPEND) && ((fwdg_deepsleep) != OB_DPSLP_FWDGT_RUN))
/* check FWDG suspend status in standby mode */
#define NOT_FMC_STDBY_FWDGT_VALUE(fwdg_standby) (((fwdg_standby) != OB_STDBY_FWDGT_SUSPEND) && ((fwdg_standby) != OB_STDBY_FWDGT_RUN))
/* check ITCM ECC function enable bit */
#define NOT_FMC_ITCMECCEN_VALUE(ob_itcmecc) (((ob_itcmecc) != OB_ITCMECCEN_DISABLE) && ((ob_itcmecc) != OB_ITCMECCEN_ENABLE))
/* check DTCM0 ECC function enable bit */
#define NOT_FMC_DTCM0ECCEN_VALUE(ob_dtcm0ecc) (((ob_dtcm0ecc) != OB_DTCM0ECCEN_DISABLE) && ((ob_dtcm0ecc) != OB_DTCM0ECCEN_ENABLE))
/* check DTCM1 ECC function enable bit */
#define NOT_FMC_DTCM1ECCEN_VALUE(ob_dtcm1ecc) (((ob_dtcm1ecc) != OB_DTCM1ECCEN_DISABLE) && ((ob_dtcm1ecc) != OB_DTCM1ECCEN_ENABLE))
/* check I/O speed optimization */
#define NOT_FMC_IOSPDOPEN_VALUE(ob_iospeed_op) (((ob_iospeed_op) != OB_IOSPDOPEN_DISABLE) && ((ob_iospeed_op) != OB_IOSPDOPEN_ENABLE))
/* check ITCM shared RAM size */
#define NOT_FMC_ITCM_SHARED_RAM_VALUE(itcm_ram_size) (((itcm_ram_size) != OB_ITCM_SHARED_RAM_0KB) && ((itcm_ram_size) != OB_ITCM_SHARED_RAM_64KB) && \
((itcm_ram_size) != OB_ITCM_SHARED_RAM_128KB) && ((itcm_ram_size) != OB_ITCM_SHARED_RAM_256KB) && \
((itcm_ram_size) != OB_ITCM_SHARED_RAM_512KB))
/* check DTCM shared RAM size */
#define NOT_FMC_DTCM_SHARED_RAM_VALUE(dtcm_ram_size) (((dtcm_ram_size) != OB_DTCM_SHARED_RAM_0KB) && ((dtcm_ram_size) != OB_DTCM_SHARED_RAM_64KB) && \
((dtcm_ram_size) != OB_DTCM_SHARED_RAM_128KB) && ((dtcm_ram_size) != OB_DTCM_SHARED_RAM_256KB) && \
((dtcm_ram_size) != OB_DTCM_SHARED_RAM_512KB))
/* check boot pin configuration */
#define NOT_FMC_BOOT_PIN_VALUE(boot_pin) (((boot_pin) != BOOT_PIN_0) && ((boot_pin) != BOOT_PIN_1))
/* check DCRP area erase enable bit */
#define NOT_FMC_DCRP_AREA_ERASE_STATUS(dcrp_eren) (((dcrp_eren) != OB_DCRP_AREA_ERASE_DISABLE) && ((dcrp_eren) != OB_DCRP_AREA_ERASE_ENABLE))
/* check DCRP area start address */
#define NOT_FMC_DCRP_AREA_START(dcrp_start) ((dcrp_start) > 0x3BFU)
/* check DCRP area end address */
#define NOT_FMC_DCRP_AREA_END(dcrp_end) ((dcrp_end) > 0x3BFU)
/* check SCR area erase enable bit */
#define NOT_FMC_SCR_AREA_ERASE_STATUS(scr_eren) (((scr_eren) != OB_SCR_AREA_ERASE_DISABLE) && ((scr_eren) != OB_SCR_AREA_ERASE_ENABLE))
/* check SCR area start address */
#define NOT_FMC_SCR_AREA_START(scr_start) ((scr_start) > 0x3BFU)
/* check SCR area end address */
#define NOT_FMC_SCR_AREA_END(scr_end) ((scr_end) > 0x3BFU)
/* check erase/program protect sector */
#define NOT_FMC_OB_WP_VALUE(ob_wp) (((ob_wp) != OB_WP_0) && ((ob_wp) != OB_WP_1) && ((ob_wp) != OB_WP_2) && ((ob_wp) != OB_WP_3) && ((ob_wp) != OB_WP_4)&& \
((ob_wp) != OB_WP_5) && ((ob_wp) != OB_WP_6) && ((ob_wp) != OB_WP_7) && ((ob_wp) != OB_WP_8) && ((ob_wp) != OB_WP_9) && \
((ob_wp) != OB_WP_10) && ((ob_wp) != OB_WP_11) && ((ob_wp) != OB_WP_12) && ((ob_wp) != OB_WP_13) && ((ob_wp) != OB_WP_14) && \
((ob_wp) != OB_WP_15) && ((ob_wp) != OB_WP_16) && ((ob_wp) != OB_WP_17) && ((ob_wp) != OB_WP_18) && ((ob_wp) != OB_WP_19) && \
((ob_wp) != OB_WP_20) && ((ob_wp) != OB_WP_21) && ((ob_wp) != OB_WP_ALL))
/* check boot pin configuration */
#define NOT_FMC_BOOT_PIN(boot_pin) (((boot_pin) != BOOT_PIN_0) && ((boot_pin) != BOOT_PIN_1))
/* check DCRP area start address */
#define NOT_FMC_NODEC_AREA_START(nodec_start) ((nodec_start) > 0x3BFU)
/* check SCR area end address */
#define NOT_FMC_NODEC_AREA_END(nodec_end) ((nodec_end) > 0x3BFU)
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* FMC operation functions */
/* unlock FMC_CTL register */
void fmc_unlock(void);
/* lock FMC_CTL register */
void fmc_lock(void);
/* FMC erase sector */
fmc_state_enum fmc_sector_erase(uint32_t address);
/* FMC typical mass erase */
fmc_state_enum fmc_typical_mass_erase(void);
/* FMC protection-removed mass erase */
fmc_state_enum fmc_protection_removed_mass_erase(void);
/* FMC program a word at the corresponding address */
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
/* FMC program a double-word at the corresponding address */
fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data);
/* enable check programming area */
fmc_state_enum fmc_check_programming_area_enable(void);
/* disable check programming area */
fmc_state_enum fmc_check_programming_area_disable(void);
/* FMC option bytes operation functions */
/* unlock the option byte operation */
void ob_unlock(void);
/* lock the option byte operation */
void ob_lock(void);
/* send option bytes modification start command */
fmc_state_enum ob_start(void);
/* modify option byte to factory value */
fmc_state_enum ob_factory_value_config(void);
/* enable secure access mode */
fmc_state_enum ob_secure_access_mode_enable(void);
/* disable secure access mode */
fmc_state_enum ob_secure_access_mode_disable(void);
/* configure the option byte security protection level */
fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
/* configure option byte BOR threshold value */
fmc_state_enum ob_bor_threshold_config(uint32_t ob_bor_th);
/* configure low power related option byte */
fmc_state_enum ob_low_power_config(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby, uint32_t ob_fwdg_suspend_deepsleep,
uint32_t ob_fwdg_suspend_standby);
/* configure TCM ECC option byte */
fmc_state_enum ob_tcm_ecc_config(uint32_t ob_itcmecc, uint32_t ob_dtcm0ecc, uint32_t ob_dtcm1ecc);
/* configure I/O speed optimization option byte */
fmc_state_enum ob_iospeed_optimize_config(uint32_t ob_iospeed_op);
/* configure option byte TCM shared RAM size */
fmc_state_enum ob_tcm_shared_ram_config(uint32_t itcm_shared_ram_size, uint32_t dtcm_shared_ram_size);
/* modify option byte DATA */
fmc_state_enum ob_data_program(uint16_t ob_data);
/* configure boot address */
fmc_state_enum ob_boot_address_config(uint8_t boot_pin, uint16_t boot_address);
/* configure DCRP area */
fmc_state_enum ob_dcrp_area_config(uint32_t dcrp_eren, uint32_t dcrp_start, uint32_t dcrp_end);
/* configure secure-access area */
fmc_state_enum ob_secure_area_config(uint32_t scr_eren, uint32_t scr_start, uint32_t scr_end);
/* enable erase/program protection */
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
/* disable erase/program protection */
fmc_state_enum ob_write_protection_disable(uint32_t ob_wp);
/* get the option byte secure access mode */
FlagStatus ob_secure_mode_get(void);
/* get the option byte security protection level */
FlagStatus ob_security_protection_flag_get(void);
/* get the option byte BOR threshold value */
uint32_t ob_bor_threshold_get(void);
/* get low power related option byte */
void ob_low_power_get(uint32_t *fwdgt, uint32_t *deepsleep, uint32_t *standby, uint32_t *fwdg_suspend_deepsleep, uint32_t *fwdg_suspend_standby);
/* get TCM ECC configuration */
void ob_tcm_ecc_get(uint32_t *itcmecc_option, uint32_t *dtcm0ecc_option, uint32_t *dtcm1ecc_option);
/* get IO speed optimize configuration */
FlagStatus ob_iospeed_optimize_get(void);
/* get ITCM shared RAM size */
uint32_t ob_itcm_shared_ram_size_get(void);
/* get DTCM shared RAM size */
uint32_t ob_dtcm_shared_ram_size_get(void);
/* get user data value */
uint16_t ob_data_get(void);
/* get boot address */
uint32_t ob_boot_address_get(uint8_t boot_pin);
/* get DCRP area configuration */
uint8_t ob_dcrp_area_get(uint32_t *dcrp_erase_option, uint32_t *dcrp_area_start_addr, uint32_t *dcrp_area_end_addr);
/* get secure-access area configuration */
uint8_t ob_secure_area_get(uint32_t *secure_area_option, uint32_t *scr_area_start_addr, uint32_t *scr_area_end_addr);
/* get the option byte erase/program protection state */
uint32_t ob_write_protection_get(void);
/* FMC universal functions */
/* configure NO-RTDEC area */
fmc_state_enum fmc_no_rtdec_config(uint32_t nodec_area_start, uint32_t nodec_area_end);
/* configure aes initialization vector */
fmc_state_enum fmc_aes_iv_config(uint32_t *aes_iv);
/* get Flash ECC function enable flag */
FlagStatus fmc_flash_ecc_get(void);
/* get NO-RTDEC area */
void fmc_no_rtdec_get(uint32_t *nodec_area_start, uint32_t *nodec_area_end);
/* get AES initialization vector */
void fmc_aes_iv_get(uint32_t *aes_iv);
/* get product ID */
void fmc_pid_get(uint32_t *pid);
/* interrupt & flag functions */
/* get FMC flag status */
FlagStatus fmc_flag_get(fmc_flag_enum flag);
/* clear FMC flag status */
void fmc_flag_clear(fmc_flag_enum flag);
/* enable FMC interrupt */
void fmc_interrupt_enable(fmc_interrupt_enum interrupt);
/* disable FMC interrupt */
void fmc_interrupt_disable(fmc_interrupt_enum interrupt);
/* get FMC interrupt flag status */
FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum int_flag);
/* clear FMC interrupt flag status */
void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum int_flag);
#endif /* GD32H75E_FMC_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_fwdgt.h
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/*!
\file gd32h75e_fwdgt.h
\brief definitions for the FWDGT
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_FWDGT_H
#define GD32H75E_FWDGT_H
#include "gd32h75e.h"
/* FWDGT definitions */
#define FWDGT FWDGT_BASE
/* registers definitions */
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
#define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */
/* bits definitions */
/* FWDGT_CTL */
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
/* FWDGT_PSC */
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
/* FWDGT_RLD */
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
/* FWDGT_STAT */
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */
/* FWDGT_WND */
#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */
/* constants definitions */
/* FWDGT_PSC register value */
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
/* control value */
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
/* FWDGT timeout value */
#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
/* FWDGT flag definitions */
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */
#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check FWDGT counter reload value */
#define NOT_FWDGT_RELOAD_VALUE(value) (((value) > 0x0FFFU))
/* check FWDGT counter window value */
#define NOT_FWDGT_WINDOW_VALUE(value) (((value) > 0x0FFFU))
/* check FWDGT counter prescaler value */
#define NOT_FWDGT_PSC_DIV(prescaler_value) (((prescaler_value) != FWDGT_PSC_DIV4) && ((prescaler_value) != FWDGT_PSC_DIV8) && ((prescaler_value) != FWDGT_PSC_DIV16) && \
((prescaler_value) != FWDGT_PSC_DIV32) && ((prescaler_value) != FWDGT_PSC_DIV64) && \
((prescaler_value) != FWDGT_PSC_DIV128) && ((prescaler_value) != FWDGT_PSC_DIV256))
/* check flag state of FWDGT */
#define NOT_FWDGT_FLAG(flag) (((flag) != FWDGT_FLAG_PUD) && ((flag) != FWDGT_FLAG_RUD) && ((flag) != FWDGT_FLAG_WUD))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* enable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND */
void fwdgt_write_enable(void);
/* disable write access to FWDGT_PSC, FWDGT_RLD and FWDGT_WND */
void fwdgt_write_disable(void);
/* start the FWDGT counter */
void fwdgt_enable(void);
/* configure the FWDGT counter prescaler value */
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
/* configure the FWDGT counter reload value */
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
/* configure the FWDGT counter window value */
ErrStatus fwdgt_window_value_config(uint16_t window_value);
/* reload the counter of FWDGT */
void fwdgt_counter_reload(void);
/* configure counter reload value, and prescaler divider value */
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
/* get flag state of FWDGT */
FlagStatus fwdgt_flag_get(uint16_t flag);
#endif /* GD32H75E_FWDGT_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_gpio.h
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/*!
\file gd32h75e_gpio.h
\brief definitions for the GPIO
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_GPIO_H
#define GD32H75E_GPIO_H
#include "gd32h75e.h"
/* GPIOx(x = A,B,C,D,E,F,G,H,J,K) definitions */
#define GPIOA (GPIO_BASE + 0x00000000U)
#define GPIOB (GPIO_BASE + 0x00000400U)
#define GPIOC (GPIO_BASE + 0x00000800U)
#define GPIOD (GPIO_BASE + 0x00000C00U)
#define GPIOE (GPIO_BASE + 0x00001000U)
#define GPIOF (GPIO_BASE + 0x00001400U)
#define GPIOG (GPIO_BASE + 0x00001800U)
#define GPIOH (GPIO_BASE + 0x00001C00U)
#define GPIOJ (GPIO_BASE + 0x00002400U)
#define GPIOK (GPIO_BASE + 0x00002800U)
/* registers definitions */
#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00000000U) /*!< GPIO port control register */
#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x00000004U) /*!< GPIO port output mode register */
#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x00000008U) /*!< GPIO port output speed register */
#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0000000CU) /*!< GPIO port pull-up/pull-down register */
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x00000010U) /*!< GPIO port input status register */
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x00000014U) /*!< GPIO port output control register */
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x00000018U) /*!< GPIO port bit operation register */
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x0000001CU) /*!< GPIO port configuration lock register */
#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x00000020U) /*!< GPIO alternate function selected register 0 */
#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x00000024U) /*!< GPIO alternate function selected register 1 */
#define GPIO_BC(gpiox) REG32((gpiox) + 0x00000028U) /*!< GPIO bit clear register */
#define GPIO_TG(gpiox) REG32((gpiox) + 0x0000002CU) /*!< GPIO port bit toggle register */
#define GPIO_IFL(gpiox) REG32((gpiox) + 0x00000030U) /*!< GPIO input filtering register */
#define GPIO_IFTP(gpiox) REG32((gpiox) + 0x00000034U) /*!< GPIO input filtering type register */
/* bits definitions */
/* GPIO_CTL */
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */
#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */
#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */
#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */
#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */
#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */
#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */
#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */
#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */
#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */
#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */
#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */
#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */
#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */
#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */
/* GPIO_OMODE */
#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */
#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */
#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */
#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */
#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */
#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */
#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */
#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */
#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */
#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */
#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */
#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */
#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */
#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */
#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */
#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */
/* GPIO_OSPD */
#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */
#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */
#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */
#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */
#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */
#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */
#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */
#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */
#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */
#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */
#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */
#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */
#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */
#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */
#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */
#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */
/* GPIO_PUD */
#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */
#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */
#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */
#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */
#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */
#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */
#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */
#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */
#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */
#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */
#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */
#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */
#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */
#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */
#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */
#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */
/* GPIO_ISTAT */
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
/* GPIO_OCTL */
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
/* GPIO_BOP */
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
/* GPIO_LOCK */
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
/* GPIO_AFSEL0 */
#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */
#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */
#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */
#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */
#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */
#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */
#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */
#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */
/* GPIO_AFSEL1 */
#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */
#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */
#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */
#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */
#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */
#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */
#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */
#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */
/* GPIO_BC */
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
/* GPIO_TG */
#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */
#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */
#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */
#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */
#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */
#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */
#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */
#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */
#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */
#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */
#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */
#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */
#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */
#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */
#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */
#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */
/* GPIO_IFL */
#define GPIO_IFL_FLPRD0 BITS(0,7) /*!< filter sampling period for GPIO1 to GPIO7 */
#define GPIO_IFL_FLPRD1 BITS(8,15) /*!< filter sampling period for GPIO8 to GPIO15 */
/* GPIO_IFTP */
#define GPIO_IFTP_IFTP0 BITS(0,1) /*!< pin 0 input filtering type bits */
#define GPIO_IFTP_IFTP1 BITS(2,3) /*!< pin 1 input filtering type bits */
#define GPIO_IFTP_IFTP2 BITS(4,5) /*!< pin 2 input filtering type bits */
#define GPIO_IFTP_IFTP3 BITS(6,7) /*!< pin 3 input filtering type bits */
#define GPIO_IFTP_IFTP4 BITS(8,9) /*!< pin 4 input filtering type bits */
#define GPIO_IFTP_IFTP5 BITS(10,11) /*!< pin 5 input filtering type bits */
#define GPIO_IFTP_IFTP6 BITS(12,13) /*!< pin 6 input filtering type bits */
#define GPIO_IFTP_IFTP7 BITS(14,15) /*!< pin 7 input filtering type bits */
#define GPIO_IFTP_IFTP8 BITS(16,17) /*!< pin 8 input filtering type bits */
#define GPIO_IFTP_IFTP9 BITS(18,19) /*!< pin 9 input filtering type bits */
#define GPIO_IFTP_IFTP10 BITS(20,21) /*!< pin 10 input filtering type bits */
#define GPIO_IFTP_IFTP11 BITS(22,23) /*!< pin 11 input filtering type bits */
#define GPIO_IFTP_IFTP12 BITS(24,25) /*!< pin 12 input filtering type bits */
#define GPIO_IFTP_IFTP13 BITS(26,27) /*!< pin 13 input filtering type bits */
#define GPIO_IFTP_IFTP14 BITS(28,29) /*!< pin 14 input filtering type bits */
#define GPIO_IFTP_IFTP15 BITS(30,31) /*!< pin 15 input filtering type bits */
/* constants definitions */
typedef FlagStatus bit_status;
/* output mode definitions */
#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */
#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */
#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */
#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */
/* pull-up/pull-down definitions */
#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */
#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */
#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */
/* GPIO pin definitions */
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */
/* GPIO mode configuration values */
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n))))
#define GPIO_MODE_MASK(n) (0x3U << (2U * (n)))
/* GPIO pull-up/pull-down values */
#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n)))
/* GPIO output speed values */
#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n))))
#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n)))
/* GPIO output type */
#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */
#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */
/* GPIO output max speed value */
#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_OSPEED_12MHZ OSPD_OSPD0(0) /*!< output max speed 12MHz */
#define GPIO_OSPEED_60MHZ OSPD_OSPD0(1) /*!< output max speed 60MHz */
#define GPIO_OSPEED_85MHZ OSPD_OSPD0(2) /*!< output max speed 85MHz */
#define GPIO_OSPEED_100_220MHZ OSPD_OSPD0(3) /*!< output max speed 100/220MHz */
/* GPIO input filter type values */
#define GPIO_IFTYPE_SET(n, type) ((uint32_t)((uint32_t)(type) << (2U * (n))))
#define GPIO_IFTYPE_MASK(n) (0x3U << (2U * (n)))
/* GPIO input filter sample period */
#define IFL_FLPRD0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
#define GPIO_ISPERIOD(vle) IFL_FLPRD0(vle) /*!< input filter sample period */
/* GPIO input filtering type */
#define IFTYPE_IFTP0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_IFTYPE_SYNC IFTYPE_IFTP0(0) /*!< input filter type synchronization */
#define GPIO_IFTYPE_3_SAMPLE IFTYPE_IFTP0(1) /*!< input filter type filter 3 samples */
#define GPIO_IFTYPE_6_SAMPLE IFTYPE_IFTP0(2) /*!< input filter type filter 6 samples */
#define GPIO_IFTYPE_ASYNC IFTYPE_IFTP0(3) /*!< input filter type asynchronous */
/* GPIO alternate function values */
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
#define GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
/* GPIO alternate function */
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */
#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */
#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */
#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */
#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected */
#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected */
#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected */
#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected */
#define GPIO_AF_8 AF(8) /*!< alternate function 8 selected */
#define GPIO_AF_9 AF(9) /*!< alternate function 9 selected */
#define GPIO_AF_10 AF(10) /*!< alternate function 10 selected */
#define GPIO_AF_11 AF(11) /*!< alternate function 11 selected */
#define GPIO_AF_12 AF(12) /*!< alternate function 12 selected */
#define GPIO_AF_13 AF(13) /*!< alternate function 13 selected */
#define GPIO_AF_14 AF(14) /*!< alternate function 14 selected */
#define GPIO_AF_15 AF(15) /*!< alternate function 15 selected */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check peripherals */
#define NOT_GPIO_PERIPH(periph) (((periph) != GPIOA) && \
((periph) != GPIOB) && \
((periph) != GPIOC) && \
((periph) != GPIOD) && \
((periph) != GPIOE) && \
((periph) != GPIOF) && \
((periph) != GPIOG) && \
((periph) != GPIOH) && \
((periph) != GPIOJ) && \
((periph) != GPIOK))
/* check GPIO pin modes */
#define NOT_GPIO_MODE(mode) (((mode) != GPIO_MODE_INPUT) && \
((mode) != GPIO_MODE_OUTPUT) && \
((mode) != GPIO_MODE_AF) && \
((mode) != GPIO_MODE_ANALOG))
/* check GPIO pin pull modes */
#define NOT_GPIO_PULL_MODE(pull_up_down) (((pull_up_down) != GPIO_PUPD_NONE) && \
((pull_up_down) != GPIO_PUPD_PULLUP) && \
((pull_up_down) != GPIO_PUPD_PULLDOWN))
/* check GPIO pin */
#define NOT_GPIO_PIN(pin) (((pin) == 0x00000000U) || ((pin) > 0x0000FFFFU))
/* check GPIO pin output mode */
#define NOT_GPIO_OTYPE(otype) (((otype) != GPIO_OTYPE_PP) && \
((otype) != GPIO_OTYPE_OD))
/* check GPIO pin speed */
#define NOT_GPIO_SPEED(speed) (((speed) != GPIO_OSPEED_12MHZ) && \
((speed) != GPIO_OSPEED_60MHZ) && \
((speed) != GPIO_OSPEED_85MHZ) && \
((speed) != GPIO_OSPEED_100_220MHZ))
/* check reset and set value */
#define NOT_RESET_SET(value) (((value) != RESET) && \
((value) != SET))
/* check GPIO pin AF */
#define NOT_GPIO_AF(alt_func_num) (((alt_func_num) != GPIO_AF_0) && \
((alt_func_num) != GPIO_AF_1) && \
((alt_func_num) != GPIO_AF_2) && \
((alt_func_num) != GPIO_AF_3) && \
((alt_func_num) != GPIO_AF_4) && \
((alt_func_num) != GPIO_AF_5) && \
((alt_func_num) != GPIO_AF_6) && \
((alt_func_num) != GPIO_AF_7) && \
((alt_func_num) != GPIO_AF_8) && \
((alt_func_num) != GPIO_AF_9) && \
((alt_func_num) != GPIO_AF_10) && \
((alt_func_num) != GPIO_AF_11) && \
((alt_func_num) != GPIO_AF_12) && \
((alt_func_num) != GPIO_AF_13) && \
((alt_func_num) != GPIO_AF_14) && \
((alt_func_num) != GPIO_AF_15))
/* check maximum interrupt filter type */
#define NOT_FLITER_TYPE(iftype) (((iftype) != GPIO_IFTYPE_SYNC) && \
((iftype) != GPIO_IFTYPE_3_SAMPLE) && \
((iftype) != GPIO_IFTYPE_6_SAMPLE) && \
((iftype) != GPIO_IFTYPE_ASYNC))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* reset GPIO port */
void gpio_deinit(uint32_t gpio_periph);
/* set GPIO mode */
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin);
/* set GPIO output type and speed */
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin);
/* set GPIO pin bit */
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
/* reset GPIO pin bit */
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
/* write data to the specified GPIO pin */
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
/* write data to the specified GPIO port */
void gpio_port_write(uint32_t gpio_periph, uint16_t data);
/* set GPIO input filter */
void gpio_input_filter_set(uint32_t gpio_periph, uint8_t speriod, uint32_t iftype, uint32_t pin);
/* get GPIO pin input status */
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
/* get GPIO port input status */
uint16_t gpio_input_port_get(uint32_t gpio_periph);
/* get GPIO pin output status */
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
/* get GPIO port output status */
uint16_t gpio_output_port_get(uint32_t gpio_periph);
/* set GPIO alternate function */
void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin);
/* lock GPIO pin bit */
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
/* toggle GPIO pin status */
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin);
/* toggle GPIO port status */
void gpio_port_toggle(uint32_t gpio_periph);
#endif /* GD32H75E_GPIO_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_hpdf.h
+879
View File
@@ -0,0 +1,879 @@
/*!
\file gd32h75e_hpdf.h
\brief definitions for the HPDF
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_HPDF_H
#define GD32H75E_HPDF_H
#include "gd32h75e.h"
/* HPDF definitions */
#define HPDF HPDF_BASE /*!< HPDF base address */
/* registers definitions */
#define HPDF_CHXCTL(chx) REG32((HPDF) + 0x00000000U + ((chx) * 0x00000020U)) /*!< HPDF Channel x control register */
#define HPDF_CHXCFG0(chx) REG32((HPDF) + 0x00000004U + ((chx) * 0x00000020U)) /*!< HPDF Channel x configuration register 0 */
#define HPDF_CHXCFG1(chx) REG32((HPDF) + 0x00000008U + ((chx) * 0x00000020U)) /*!< HPDF Channel x configuration register 1 */
#define HPDF_CHXTMFDT(chx) REG32((HPDF) + 0x0000000CU + ((chx) * 0x00000020U)) /*!< HPDF Channel x threshold monitor filter data register */
#define HPDF_CHXPDI(chx) REG32((HPDF) + 0x00000010U + ((chx) * 0x00000020U)) /*!< HPDF Channel x parallel data input register */
#define HPDF_CHXPS(chx) REG32((HPDF) + 0x00000014U + ((chx) * 0x00000020U)) /*!< HPDF Channel x pulse skip register */
#define HPDF_FLTYCTL0(flty) REG32((HPDF) + 0x00000100U + ((flty) * 0x00000080U)) /*!< HPDF Filter y control register 0 */
#define HPDF_FLTYCTL1(flty) REG32((HPDF) + 0x00000104U + ((flty) * 0x00000080U)) /*!< HPDF Filter y control register 1 */
#define HPDF_FLTYSTAT(flty) REG32((HPDF) + 0x00000108U + ((flty) * 0x00000080U)) /*!< HPDF Filter y status register */
#define HPDF_FLTYINTC(flty) REG32((HPDF) + 0x0000010CU + ((flty) * 0x00000080U)) /*!< HPDF Filter y interrupt flag clear register */
#define HPDF_FLTYICGS(flty) REG32((HPDF) + 0x00000110U + ((flty) * 0x00000080U)) /*!< HPDF Filter y inserted channel group selection register */
#define HPDF_FLTYSFCFG(flty) REG32((HPDF) + 0x00000114U + ((flty) * 0x00000080U)) /*!< HPDF Filter y sinc filter configuration register */
#define HPDF_FLTYIDATA(flty) REG32((HPDF) + 0x00000118U + ((flty) * 0x00000080U)) /*!< HPDF Filter y inserted group conversion data register */
#define HPDF_FLTYRDATA(flty) REG32((HPDF) + 0x0000011CU + ((flty) * 0x00000080U)) /*!< HPDF Filter y regular channel conversion data register */
#define HPDF_FLTYTMHT(flty) REG32((HPDF) + 0x00000120U + ((flty) * 0x00000080U)) /*!< HPDF Filter y threshold monitor high threshold register */
#define HPDF_FLTYTMLT(flty) REG32((HPDF) + 0x00000124U + ((flty) * 0x00000080U)) /*!< HPDF Filter y threshold monitor low threshold register */
#define HPDF_FLTYTMSTAT(flty) REG32((HPDF) + 0x00000128U + ((flty) * 0x00000080U)) /*!< HPDF Filter y threshold monitor status register */
#define HPDF_FLTYTMFC(flty) REG32((HPDF) + 0x0000012CU + ((flty) * 0x00000080U)) /*!< HPDF Filter y threshold monitor flag clear register */
#define HPDF_FLTYEMMAX(flty) REG32((HPDF) + 0x00000130U + ((flty) * 0x00000080U)) /*!< HPDF Filter y extremes monitor maximum register */
#define HPDF_FLTYEMMIN(flty) REG32((HPDF) + 0x00000134U + ((flty) * 0x00000080U)) /*!< HPDF Filter y extremes monitor minimum register */
#define HPDF_FLTYCT(flty) REG32((HPDF) + 0x00000138U + ((flty) * 0x00000080U)) /*!< HPDF Filter y conversion timer register */
/* bits definitions */
/* HPDF_CHXCTL */
#define HPDF_CHXCTL_SITYP BITS(0,1) /*!< serial interface type */
#define HPDF_CHXCTL_SPICKSS BITS(2,3) /*!< SPI clock source select */
#define HPDF_CHXCTL_MMEN BIT(5) /*!< malfunction monitor detector enable */
#define HPDF_CHXCTL_CKLEN BIT(6) /*!< clock loss detector enable */
#define HPDF_CHXCTL_CHEN BIT(7) /*!< channel enable */
#define HPDF_CHXCTL_CHPINSEL BIT(8) /*!< channel inputs pins selection */
#define HPDF_CHXCTL_CMSD BITS(12,13) /*!< channel multiplexer select input data source */
#define HPDF_CHXCTL_DPM BITS(14,15) /*!< data packing mode for HPDF_CHXPDI register */
/* only available in HPDF_CH0CTL */
#define HPDF_CH0CTL_CKOUTDIV BITS(16,23) /*!< serial clock output divider */
#define HPDF_CH0CTL_CKOUTDM BIT(29) /*!< serial clock output duty mode */
#define HPDF_CH0CTL_CKOUTSEL BIT(30) /*!< serial clock output source selection */
#define HPDF_CH0CTL_HPDFEN BIT(31) /*!< HPDF peripheral enable */
/* HPDF_CHXCFG0 */
#define HPDF_CHXCFG0_DTRS BITS(3,7) /*!< data right bit-shift */
#define HPDF_CHXCFG0_CALOFF BITS(8,31) /*!< 24-bit calibration offset */
/* HPDF_CHXCFG1 */
#define HPDF_CHXCFG1_MMCT BITS(0,7) /*!< malfunction monitor counter threshold */
#define HPDF_CHXCFG1_MMBSD BITS(12,15) /*!< malfunction monitor break signal distribution */
#define HPDF_CHXCFG1_TMFOR BITS(16,20) /*!< threshold monitor filter oversampling rate */
#define HPDF_CHXCFG1_TMSFO BITS(22,23) /*!< threshold monitor Sinc filter order selection */
/* HPDF_CHXTMFDT */
#define HPDF_CHXTMFDT_TMDATA BITS(0,15) /*!< threshold monitor data */
/* HPDF_CHXPDI */
#define HPDF_CHXPDI_DATAIN0 BITS(0,15) /*!< data input for channel x or channel x+1 */
#define HPDF_CHXPDI_DATAIN1 BITS(16,31) /*!< data input for channel x */
/* HPDF_CHXPS */
#define HPDF_CHXPS_PLSK BITS(0,5) /*!< pulses to skip for input data skipping function */
/* HPDF_FLTYCTL0 */
#define HPDF_FLTYCTL0_FLTEN BIT(0) /*!< HPDF_FLTy enable */
#define HPDF_FLTYCTL0_SICC BIT(1) /*!< start inserted group channel conversion */
#define HPDF_FLTYCTL0_ICSYN BIT(3) /*!< inserted conversion synchronously with the HPDF_FLT0 SICC trigger */
#define HPDF_FLTYCTL0_SCMOD BIT(4) /*!< scan conversion mode of inserted conversions */
#define HPDF_FLTYCTL0_ICDMAEN BIT(5) /*!< DMA channel enabled to read data for the inserted channel group */
#define HPDF_FLTYCTL0_ICTSSEL BITS(8,12) /*!< inserted conversions trigger signal selection */
#define HPDF_FLTYCTL0_ICTEEN BITS(13,14) /*!< inserted conversions trigger edge enable */
#define HPDF_FLTYCTL0_SRCS BIT(17) /*!< start regular channel conversion by software */
#define HPDF_FLTYCTL0_RCCM BIT(18) /*!< regular conversions continuous mode */
#define HPDF_FLTYCTL0_RCSYN BIT(19) /*!< regular conversion synchronously with HPDF_FLT0 */
#define HPDF_FLTYCTL0_RCDMAEN BIT(21) /*!< DMA channel enabled to read data for the regular conversion */
#define HPDF_FLTYCTL0_RCS BITS(24,26) /*!< regular conversion channel selection*/
#define HPDF_FLTYCTL0_FAST BIT(29) /*!< fast conversion mode enable for regular conversions */
#define HPDF_FLTYCTL0_TMFM BIT(30) /*!< threshold monitor fast mode */
/* HPDF_FLTYCTL1 */
#define HPDF_FLTYCTL1_ICEIE BIT(0) /*!< inserted conversion end interrupt enable */
#define HPDF_FLTYCTL1_RCEIE BIT(1) /*!< regular conversion end interrupt enable */
#define HPDF_FLTYCTL1_ICDOIE BIT(2) /*!< inserted conversion data overflow interrupt enable */
#define HPDF_FLTYCTL1_RCDOIE BIT(3) /*!< regular conversion data overflow interrupt enable */
#define HPDF_FLTYCTL1_TMIE BIT(4) /*!< threshold monitor interrupt enable */
#define HPDF_FLTYCTL1_EMCS BITS(8,15) /*!< extremes monitor channel selection */
#define HPDF_FLTYCTL1_TMCHEN BITS(16,23) /*!< threshold monitor channel enable */
/* only available in HPDF_FLT0CTL1 */
#define HPDF_FLT0CTL1_MMIE BIT(5) /*!< malfunction monitor detector interrupt enable */
#define HPDF_FLT0CTL1_CKLIE BIT(6) /*!< clock loss interrupt enable */
/* HPDF_FLTYSTAT */
#define HPDF_FLTYSTAT_ICEF BIT(0) /*!< inserted conversion end flag */
#define HPDF_FLTYSTAT_RCEF BIT(1) /*!< regular conversion end flag */
#define HPDF_FLTYSTAT_ICDOF BIT(2) /*!< inserted conversion data overflow flag */
#define HPDF_FLTYSTAT_RCDOF BIT(3) /*!< regular conversion data overflow flag */
#define HPDF_FLTYSTAT_TMEOF BIT(4) /*!< threshold monitor event occurred flag */
#define HPDF_FLTYSTAT_ICPF BIT(13) /*!< inserted conversion in progress flag */
#define HPDF_FLTYSTAT_RCPF BIT(14) /*!< regular conversion in progress flag */
/* only available in HPDF_FLT0STAT */
#define HPDF_FLT0STAT_CKLF BITS(16,23) /*!< clock loss flag */
#define HPDF_FLT0STAT_MMF BITS(24,31) /*!< malfunction monitor detection flag */
/* HPDF_FLTYINTC */
#define HPDF_FLTYINTC_ICDOFC BIT(2) /*!< clear the inserted conversion data overflow flag */
#define HPDF_FLTYINTC_RCDOFC BIT(3) /*!< clear the regular conversion data overflow flag */
/* only available in HPDF_FLT0INTC */
#define HPDF_FLT0INTC_CKLFC BITS(16,23) /*!< clear the clock loss flag */
#define HPDF_FLT0INTC_MMFC BITS(24,31) /*!< clear the malfunction monitor detection flag */
/* HPDF_FLTYICGS */
#define HPDF_FLTYICGS_ICGSEL BITS(0,7) /*!< inserted channel group selection */
/* HPDF_FLTYSFCFG */
#define HPDF_FLTYSFCFG_IOR BITS(0,7) /*!< integrator oversampling ratio */
#define HPDF_FLTYSFCFG_SFOR BITS(16,25) /*!< Sinc filter oversampling rate (decimation rate) */
#define HPDF_FLTYSFCFG_SFO BITS(29,31) /*!< Sinc filter order */
/* HPDF_FLTYIDATA */
#define HPDF_FLTYIDATA_ICCH BITS(0,2) /*!< inserted channel most recently converted */
#define HPDF_FLTYIDATA_IDTAT BITS(8,31) /*!< inserted group conversion data */
/* HPDF_FLTYRDATA */
#define HPDF_FLTYRDATA_RCCH BITS(0,2) /*!< regular channel most recently converted */
#define HPDF_FLTYRDATA_RCHPDT BIT(4) /*!< regular channel pending data*/
#define HPDF_FLTYRDATA_RDATA BITS(8,31) /*!< regular channel conversion data */
/* HPDF_FLTYTMHT */
#define HPDF_FLTYTMHT_HTBSD BITS(0,3) /*!< high threshold event break signal distribution */
#define HPDF_FLTYTMHT_HTVAL BITS(8,31) /*!< threshold monitor high threshold value */
/* HPDF_FLTYTMLT */
#define HPDF_FLTYTMLT_LTBSD BITS(0,3) /*!< low threshold event break signal distribution */
#define HPDF_FLTYTMLT_LTVAL BITS(8,31) /*!< threshold monitor low threshold value */
/* HPDF_FLTYTMSTAT */
#define HPDF_FLTYTMSTAT_LTF BITS(0,7) /*!< threshold monitor low threshold flag */
#define HPDF_FLTYTMSTAT_HTF BITS(8,15) /*!< threshold monitor high threshold flag */
/* HPDF_FLTYTMFC */
#define HPDF_FLTYTMFC_LTFC BITS(0,7) /*!< clear the threshold monitor low threshold flag */
#define HPDF_FLTYTMFC_HTFC BITS(8,15) /*!< clear the threshold monitor high threshold flag */
/* HPDF_FLTYEMMAX */
#define HPDF_FLTYEMMAX_MAXDC BIT(0,2) /*!< extremes monitor maximum data channel */
#define HPDF_FLTYEMMAX_MAXVAL BITS(8,31) /*!< extremes monitor maximum value */
/* HPDF_FLTYEMMIN */
#define HPDF_FLTYEMMIN_MINDC BIT(0,2) /*!< extremes monitor minimum data channel */
#define HPDF_FLTYEMMIN_MINVAL BITS(8,31) /*!< extremes monitor minimum value */
/* HPDF_FLTYCT */
#define HPDF_FLTYCT_CTCNT BIT(4,31) /*!< conversion time measured by HPDFCLK */
/* register offset */
#define FLTYCTL1_REG_OFFSET ((uint16_t)0x0004U) /*!< the offset of FLTYCTL1 register */
#define FLTYSTAT_REG_OFFSET ((uint16_t)0x0008U) /*!< the offset of FLTYSTAT register */
#define FLTYRDATA_REG_OFFSET ((uint16_t)0x001CU) /*!< the offset of FLTYRDATA register */
#define FLTYTMSTAT_REG_OFFSET ((uint16_t)0x0028U) /*!< the offset of FLTYTMSTAT register */
/* HPDF flags and interrupt definitions */
/* define the HPDF bit position and its register index offset */
#define HPDF_FLT0 (HPDF + 0x00000100U)
#define HPDF_FLT1 (HPDF + 0x00000180U)
#define HPDF_FLT2 (HPDF + 0x00000200U)
#define HPDF_FLT3 (HPDF + 0x00000280U)
#define HPDF_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define HPDF_REG_VAL(regidx, offset) (REG32((regidx) + (((uint32_t)(offset) & 0x0000FFC0U) >> 6)))
#define HPDF_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
#define HPDF_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define HPDF_REG_VAL2(regidx, offset) (REG32((regidx) + ((uint32_t)(offset) >> 22)))
#define HPDF_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
/* constants definitions */
/* parameter struct definitions */
/* channel configuration params */
typedef struct {
uint32_t data_packing_mode; /*!< data packing mode for HPDF_CHXPDI register */
uint32_t channel_multiplexer; /*!< channel multiplexer select input data source */
uint32_t channel_pin_select; /*!< channel inputs pins selection */
uint32_t ck_loss_detector; /*!< clock loss detector */
uint32_t malfunction_monitor; /*!< malfunction monitor */
uint32_t spi_ck_source; /*!< SPI clock source select */
uint32_t serial_interface; /*!< serial interface type */
int32_t calibration_offset; /*!< 24-bit calibration offset */
uint32_t right_bit_shift; /*!< data right bit-shift */
uint32_t tm_filter; /*!< threshold monitor Sinc filter order selection */
uint32_t tm_filter_oversample; /*!< threshold monitor filter oversampling rate */
uint32_t mm_break_signal; /*!< malfunction monitor break signal distribution */
uint32_t mm_counter_threshold; /*!< malfunction monitor counter threshold */
uint32_t plsk_value; /*!< the number of serial input samples that will be skipped */
} hpdf_channel_parameter_struct;
/* filter configuration params */
typedef struct {
uint32_t tm_fast_mode; /*!< threshold monitor fast mode */
uint32_t tm_channel; /*!< threshold monitor channel */
int32_t tm_high_threshold; /*!< threshold monitor high threshold */
int32_t tm_low_threshold; /*!< threshold monitor low threshold value */
uint32_t extreme_monitor_channel; /*!< extremes monitor channel */
uint32_t sinc_filter; /*!< sinc filter order */
uint32_t sinc_oversample; /*!< sinc filter oversampling rate */
uint32_t integrator_oversample; /*!< integrator oversampling rate */
uint32_t ht_break_signal; /*!< high threshold event break signal distribution */
uint32_t lt_break_signal; /*!< low threshold event break signal distribution */
} hpdf_filter_parameter_struct;
/* regular conversions configuration params */
typedef struct {
uint32_t fast_mode; /*!< fast conversion mode enable for regular conversions */
uint32_t rcs_channel; /*!< regular conversion channel */
uint32_t rcdmaen; /*!< DMA channel enabled to read data for the regular conversion */
uint32_t rcsyn; /*!< regular conversion synchronously */
uint32_t continuous_mode; /*!< regular conversions continuous mode */
} hpdf_rc_parameter_struct;
/* inserted conversions configuration params */
typedef struct {
uint32_t trigger_edge; /*!< inserted conversions trigger edge */
uint32_t trigger_signal; /*!< inserted conversions trigger signal */
uint32_t icdmaen; /*!< DMA channel enabled to read data for the inserted channel group */
uint32_t scmod; /*!< scan conversion mode of inserted conversions */
uint32_t icsyn; /*!< inserted conversion synchronously */
uint32_t ic_channel_group; /*!< inserted channel group selection */
} hpdf_ic_parameter_struct;
/* enum definitions */
/* HPDF channel */
typedef enum {
CHANNEL0 = 0, /*!< HPDF channel0 */
CHANNEL1, /*!< HPDF channel1 */
CHANNEL2, /*!< HPDF channel2 */
CHANNEL3, /*!< HPDF channel3 */
CHANNEL4, /*!< HPDF channel4 */
CHANNEL5, /*!< HPDF channel5 */
CHANNEL6, /*!< HPDF channel6 */
CHANNEL7 /*!< HPDF channel7 */
} hpdf_channel_enum;
/* HPDF filter */
typedef enum {
FLT0 = 0, /*!< HPDF filter0 */
FLT1, /*!< HPDF filter1 */
FLT2, /*!< HPDF filter2 */
FLT3 /*!< HPDF filter3 */
} hpdf_filter_enum;
/* HPDF flags */
typedef enum {
/* flags in FLTYSTAT register */
HPDF_FLAG_FLTY_ICEF = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 0U), /*!< inserted conversion end flag */
HPDF_FLAG_FLTY_RCEF = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 1U), /*!< regular conversion end flag */
HPDF_FLAG_FLTY_ICDOF = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 2U), /*!< inserted conversion overflow flag */
HPDF_FLAG_FLTY_RCDOF = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 3U), /*!< regular conversion overflow flag */
HPDF_FLAG_FLTY_TMEOF = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 4U), /*!< threshold monitor event occurred flag */
HPDF_FLAG_FLTY_ICPF = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 13U), /*!< inserted conversion in progress flag */
HPDF_FLAG_FLTY_RCPF = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 14U), /*!< regular conversion in progress flag */
HPDF_FLAG_FLT0_CKLF0 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 16U), /*!< clock loss on channel 0 flag */
HPDF_FLAG_FLT0_CKLF1 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 17U), /*!< clock loss on channel 1 flag */
HPDF_FLAG_FLT0_CKLF2 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 18U), /*!< clock loss on channel 2 flag */
HPDF_FLAG_FLT0_CKLF3 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 19U), /*!< clock loss on channel 3 flag */
HPDF_FLAG_FLT0_CKLF4 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 20U), /*!< clock loss on channel 4 flag */
HPDF_FLAG_FLT0_CKLF5 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 21U), /*!< clock loss on channel 5 flag */
HPDF_FLAG_FLT0_CKLF6 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 22U), /*!< clock loss on channel 6 flag */
HPDF_FLAG_FLT0_CKLF7 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 23U), /*!< clock loss on channel 7 flag */
HPDF_FLAG_FLT0_MMF0 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 24U), /*!< malfunction event occurred on channel 0 flag */
HPDF_FLAG_FLT0_MMF1 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 25U), /*!< malfunction event occurred on channel 1 flag */
HPDF_FLAG_FLT0_MMF2 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 26U), /*!< malfunction event occurred on channel 2 flag */
HPDF_FLAG_FLT0_MMF3 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 27U), /*!< malfunction event occurred on channel 3 flag */
HPDF_FLAG_FLT0_MMF4 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 28U), /*!< malfunction event occurred on channel 4 flag */
HPDF_FLAG_FLT0_MMF5 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 29U), /*!< malfunction event occurred on channel 5 flag */
HPDF_FLAG_FLT0_MMF6 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 30U), /*!< malfunction event occurred on channel 6 flag */
HPDF_FLAG_FLT0_MMF7 = HPDF_REGIDX_BIT(FLTYSTAT_REG_OFFSET, 31U), /*!< malfunction event occurred on channel 7 flag */
/* flags in FLT0RDATA register */
HPDF_FLAG_FLTY_RCHPDT = HPDF_REGIDX_BIT(FLTYRDATA_REG_OFFSET, 4U), /*!< regular channel pending data */
/* flags in FLTYTMSTAT register */
HPDF_FLAG_FLTY_LTF0 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 0U), /*!< threshold monitor low threshold on channel 0 flag */
HPDF_FLAG_FLTY_LTF1 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 1U), /*!< threshold monitor low threshold on channel 1 flag */
HPDF_FLAG_FLTY_LTF2 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 2U), /*!< threshold monitor low threshold on channel 2 flag */
HPDF_FLAG_FLTY_LTF3 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 3U), /*!< threshold monitor low threshold on channel 3 flag */
HPDF_FLAG_FLTY_LTF4 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 4U), /*!< threshold monitor low threshold on channel 4 flag */
HPDF_FLAG_FLTY_LTF5 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 5U), /*!< threshold monitor low threshold on channel 5 flag */
HPDF_FLAG_FLTY_LTF6 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 6U), /*!< threshold monitor low threshold on channel 6 flag */
HPDF_FLAG_FLTY_LTF7 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 7U), /*!< threshold monitor low threshold on channel 7 flag */
HPDF_FLAG_FLTY_HTF0 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 8U), /*!< threshold monitor high threshold on channel 0 flag */
HPDF_FLAG_FLTY_HTF1 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 9U), /*!< threshold monitor high threshold on channel 1 flag */
HPDF_FLAG_FLTY_HTF2 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 10U), /*!< threshold monitor high threshold on channel 2 flag */
HPDF_FLAG_FLTY_HTF3 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 11U), /*!< threshold monitor high threshold on channel 3 flag */
HPDF_FLAG_FLTY_HTF4 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 12U), /*!< threshold monitor high threshold on channel 4 flag */
HPDF_FLAG_FLTY_HTF5 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 13U), /*!< threshold monitor high threshold on channel 5 flag */
HPDF_FLAG_FLTY_HTF6 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 14U), /*!< threshold monitor high threshold on channel 6 flag */
HPDF_FLAG_FLTY_HTF7 = HPDF_REGIDX_BIT(FLTYTMSTAT_REG_OFFSET, 15U) /*!< threshold monitor high threshold on channel 7 flag */
} hpdf_flag_enum;
/* HPDF interrput flags */
typedef enum {
/* interrput flags in FLTYSTAT register */
HPDF_INT_FLAG_FLTY_ICEF = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 0U, FLTYSTAT_REG_OFFSET, 0U), /*!< inserted conversion end interrupt flag */
HPDF_INT_FLAG_FLTY_RCEF = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 1U, FLTYSTAT_REG_OFFSET, 1U), /*!< regular conversion end interruptflag */
HPDF_INT_FLAG_FLTY_ICDOF = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 2U, FLTYSTAT_REG_OFFSET, 2U), /*!< inserted conversion overflow interrupt flag */
HPDF_INT_FLAG_FLTY_RCDOF = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 3U, FLTYSTAT_REG_OFFSET, 3U), /*!< regular conversion overflow interrupt flag */
HPDF_INT_FLAG_FLTY_TMEOF = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 4U, FLTYSTAT_REG_OFFSET, 4U), /*!< threshold monitor event occurred interrupt flag */
HPDF_INT_FLAG_FLT0_CKLF0 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 6U, FLTYSTAT_REG_OFFSET, 16U), /*!< clock loss on channel 0 interrupt flag */
HPDF_INT_FLAG_FLT0_CKLF1 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 6U, FLTYSTAT_REG_OFFSET, 17U), /*!< clock loss on channel 1 interrupt flag */
HPDF_INT_FLAG_FLT0_CKLF2 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 6U, FLTYSTAT_REG_OFFSET, 18U), /*!< clock loss on channel 2 interrupt flag */
HPDF_INT_FLAG_FLT0_CKLF3 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 6U, FLTYSTAT_REG_OFFSET, 19U), /*!< clock loss on channel 3 interrupt flag */
HPDF_INT_FLAG_FLT0_CKLF4 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 6U, FLTYSTAT_REG_OFFSET, 20U), /*!< clock loss on channel 4 interrupt flag */
HPDF_INT_FLAG_FLT0_CKLF5 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 6U, FLTYSTAT_REG_OFFSET, 21U), /*!< clock loss on channel 5 interrupt flag */
HPDF_INT_FLAG_FLT0_CKLF6 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 6U, FLTYSTAT_REG_OFFSET, 22U), /*!< clock loss on channel 6 interrupt flag */
HPDF_INT_FLAG_FLT0_CKLF7 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 6U, FLTYSTAT_REG_OFFSET, 23U), /*!< clock loss on channel 7 interrupt flag */
HPDF_INT_FLAG_FLT0_MMF0 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 5U, FLTYSTAT_REG_OFFSET, 24U), /*!< malfunction monitor detection on channel 0 interrupt flag */
HPDF_INT_FLAG_FLT0_MMF1 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 5U, FLTYSTAT_REG_OFFSET, 25U), /*!< malfunction monitor detection on channel 1 interrupt flag */
HPDF_INT_FLAG_FLT0_MMF2 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 5U, FLTYSTAT_REG_OFFSET, 26U), /*!< malfunction monitor detection on channel 2 interrupt flag */
HPDF_INT_FLAG_FLT0_MMF3 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 5U, FLTYSTAT_REG_OFFSET, 27U), /*!< malfunction monitor detection on channel 3 interrupt flag */
HPDF_INT_FLAG_FLT0_MMF4 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 5U, FLTYSTAT_REG_OFFSET, 28U), /*!< malfunction monitor detection on channel 4 interrupt flag */
HPDF_INT_FLAG_FLT0_MMF5 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 5U, FLTYSTAT_REG_OFFSET, 29U), /*!< malfunction monitor detection on channel 5 interrupt flag */
HPDF_INT_FLAG_FLT0_MMF6 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 5U, FLTYSTAT_REG_OFFSET, 30U), /*!< malfunction monitor detection on channel 6 interrupt flag */
HPDF_INT_FLAG_FLT0_MMF7 = HPDF_REGIDX_BIT2(FLTYCTL1_REG_OFFSET, 5U, FLTYSTAT_REG_OFFSET, 31U) /*!< malfunction monitor detection on channel 7 interrupt flag */
} hpdf_interrput_flag_enum;
/* HPDF interrput */
typedef enum {
/* interrput in FLTYCTL1 register */
HPDF_INT_FLTY_ICEIE = HPDF_REGIDX_BIT(FLTYCTL1_REG_OFFSET, 0U), /*!< inserted conversion end interrupt enable */
HPDF_INT_FLTY_RCEIE = HPDF_REGIDX_BIT(FLTYCTL1_REG_OFFSET, 1U), /*!< regular conversion end interrupt enable */
HPDF_INT_FLTY_ICDOIE = HPDF_REGIDX_BIT(FLTYCTL1_REG_OFFSET, 2U), /*!< inserted conversion data overflow interrupt enable */
HPDF_INT_FLTY_RCDOIE = HPDF_REGIDX_BIT(FLTYCTL1_REG_OFFSET, 3U), /*!< regular conversion data overflow interrupt enable */
HPDF_INT_FLTY_TMIE = HPDF_REGIDX_BIT(FLTYCTL1_REG_OFFSET, 4U), /*!< threshold monitor interrupt enable */
HPDF_INT_FLT0_MMIE = HPDF_REGIDX_BIT(FLTYCTL1_REG_OFFSET, 5U), /*!< malfunction monitor interrupt enable */
HPDF_INT_FLT0_CKLIE = HPDF_REGIDX_BIT(FLTYCTL1_REG_OFFSET, 6U) /*!< clock loss interrupt enable */
} hpdf_interrput_enum;
/* HPDF channel definitions */
/* serial clock output source definitions */
#define SERIAL_SYSTEM_CLK ((uint32_t)0x00000000U) /*!< serial clock output source is from system clock */
#define SERIAL_AUDIO_CLK HPDF_CH0CTL_CKOUTSEL /*!< serial clock output source is from audio clock */
/* serial clock output duty mode definitions */
#define CKOUTDM_DISABLE ((uint32_t)0x00000000U) /*!< serial clock output duty mode disable */
#define CKOUTDM_ENABLE HPDF_CH0CTL_CKOUTDM /*!< serial clock output duty mode enable */
/* data packing mode definitions */
#define DPM(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< select data packing mode */
#define DPM_STANDARD_MODE DPM(0) /*!< standard mode */
#define DPM_INTERLEAVED_MODE DPM(1) /*!< interleaved mode */
#define DPM_DUAL_MODE DPM(2) /*!< dual mode */
/* input data source for channel definitions */
#define IDATASEL(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< select channel y multiplexer input data source */
#define SERIAL_INPUT IDATASEL(0) /*!< input data source for channel is taken from serial inputs */
#define ADC_INPUT IDATASEL(1) /*!< input data source for channel is taken from ADC output register */
#define INTERNAL_INPUT IDATASEL(2) /*!< input data source for channel is taken from internal HPDF_CHXPDI register */
/* channel inputs pins definitions */
#define CHPINSEL_CURRENT ((uint32_t)0x00000000U) /*!< channel inputs select pins of the current channel */
#define CHPINSEL_NEXT HPDF_CHXCTL_CHPINSEL /*!< channel inputs select pins of the next channel */
/* clock loss detector definitions */
#define CLK_LOSS_DISABLE ((uint32_t)0x00000000U) /*!< clock loss detector disable */
#define CLK_LOSS_ENABLE HPDF_CHXCTL_CKLEN /*!< clock loss detector enable */
/* SPI clock source definitions */
#define SPICKSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) /*!< select SPI clock source */
#define EXTERNAL_CKIN SPICKSS(0) /*!< external CKINy input */
#define INTERNAL_CKOUT SPICKSS(1) /*!< internal CKOUT output */
#define HALF_CKOUT_FALLING_EDGE SPICKSS(2) /*!< internal CKOUT output, sampling point on each second CKOUT falling edge. */
#define HALF_CKOUT_RISING_EDGE SPICKSS(3) /*!< internal CKOUT output, sampling point on each second CKOUT rising edge */
/* serial interface type definitions */
#define SITYP(regval) (BITS(0,1) & ((uint32_t)(regval))) /*!< select serial interface type */
#define SPI_RISING_EDGE SITYP(0) /*!< SPI interface, sample data on rising edge */
#define SPI_FALLING_EDGE SITYP(1) /*!< SPI interface, sample data on rising edge */
#define MANCHESTER_CODE0 SITYP(2) /*!< manchester coded input: rising edge = logic 0, falling edge = logic 1 */
#define MANCHESTER_CODE1 SITYP(3) /*!< manchester coded input: rising edge = logic 1, falling edge = logic 0 */
/* malfunction monitor detector definitions */
#define MM_DISABLE ((uint32_t)0x00000000U) /*!< malfunction monitor disable */
#define MM_ENABLE HPDF_CHXCTL_MMEN /*!< malfunction monitor enable */
/* malfunction monitor detector break signal definitions */
#define MMBSD(regval) (BITS(12,15) & ((uint32_t)(regval)<< 12)) /*!< select break signal on channel */
#define NO_MM_BREAK MMBSD(0) /*!< break signal is not distributed to malfunction monitor on channel */
#define MM_BREAK0 MMBSD(1) /*!< break signal 0 is distributed to malfunction monitor on channel */
#define MM_BREAK1 MMBSD(2) /*!< break signal 1 is distributed to malfunction monitor on channel */
#define MM_BREAK2 MMBSD(4) /*!< break signal 2 is distributed to malfunction monitor on channel */
#define MM_BREAK3 MMBSD(8) /*!< break signal 3 is distributed to malfunction monitor on channel */
/* threshold monitor fast mode definitions */
#define TMFM_DISABLE ((uint32_t)0x00000000U) /*!< threshold monitor fast mode disable */
#define TMFM_ENABLE HPDF_FLTYCTL0_TMFM /*!< threshold monitor fast mode enable */
/* regular conversions configuration definitions */
/* fast conversion mode definitions */
#define FAST_DISABLE ((uint32_t)0x00000000U) /*!< fast conversion mode disable */
#define FAST_ENABLE HPDF_FLTYCTL0_FAST /*!< fast conversion mode enable */
/* regular conversion channel selection definitions */
#define RCS(regval) (BITS(24,26) & ((uint32_t)(regval)<< 24 )) /*!< select regular conversion channel */
#define RCS_CHANNEL0 RCS(0) /*!< channel 0 is selected as the regular conversion channel */
#define RCS_CHANNEL1 RCS(1) /*!< channel 1 is selected as the regular conversion channel */
#define RCS_CHANNEL2 RCS(2) /*!< channel 2 is selected as the regular conversion channel */
#define RCS_CHANNEL3 RCS(3) /*!< channel 3 is selected as the regular conversion channel */
#define RCS_CHANNEL4 RCS(4) /*!< channel 4 is selected as the regular conversion channel */
#define RCS_CHANNEL5 RCS(5) /*!< channel 5 is selected as the regular conversion channel */
#define RCS_CHANNEL6 RCS(6) /*!< channel 6 is selected as the regular conversion channel */
#define RCS_CHANNEL7 RCS(7) /*!< channel 7 is selected as the regular conversion channel */
/* DMA channel of regular conversion definitions */
#define RCDMAEN_DISABLE ((uint32_t)0x00000000U) /*!< disable the DMA channel to read regular data */
#define RCDMAEN_ENABLE HPDF_FLTYCTL0_RCDMAEN /*!< enable the DMA channel to read regular data */
/* regular conversion synchronously definitions */
#define RCSYN_DISABLE ((uint32_t)0x00000000U) /*!< do not launch a regular conversion synchronously */
#define RCSYN_ENABLE HPDF_FLTYCTL0_RCSYN /*!< launch a regular conversion synchronously */
/* regular conversions continuous mode definitions */
#define RCCM_DISABLE ((uint32_t)0x00000000U) /*!< regular conversions continuous mode */
#define RCCM_ENABLE HPDF_FLTYCTL0_RCCM /*!< regular conversions continuous mode */
/* inserted conversions trigger edge definitions */
#define ICTEEN(regval) (BITS(13,14) & ((uint32_t)(regval)<< 13)) /*!< select inserted conversions trigger edge */
#define TRG_DISABLE ICTEEN(0) /*!< disable trigger detection */
#define RISING_EDGE_TRG ICTEEN(1) /*!< each rising edge on the trigger signal */
#define FALLING_EDGE_TRG ICTEEN(2) /*!< each falling edge on the trigger signal */
#define EDGE_TRG ICTEEN(3) /*!< the edge (rising edges and falling edges) on the trigger signal */
/* inserted conversions trigger signal definitions */
#define ICTSSEL(regval) (BITS(8,12) & ((uint32_t)(regval)<< 8)) /*!< select inserted conversions trigger signal */
#define HPDF_ITRG0 ICTSSEL(0) /*!< HPDF_ITRG0 (TIMER0_TRGO0) */
#define HPDF_ITRG1 ICTSSEL(1) /*!< HPDF_ITRG1 (TIMER0_TRGO1) */
#define HPDF_ITRG2 ICTSSEL(2) /*!< HPDF_ITRG2 (TIMER7_TRGO0) */
#define HPDF_ITRG3 ICTSSEL(3) /*!< HPDF_ITRG3 (TIMER7_TRGO1) */
#define HPDF_ITRG4 ICTSSEL(4) /*!< HPDF_ITRG4 (TIMER2_TRGO0) */
#define HPDF_ITRG5 ICTSSEL(5) /*!< HPDF_ITRG5 (TIMER3_TRGO0) */
#define HPDF_ITRG6 ICTSSEL(6) /*!< HPDF_ITRG6 (TIMER15_CH1) */
#define HPDF_ITRG7 ICTSSEL(7) /*!< HPDF_ITRG7 (TIMER5_TRGO0) */
#define HPDF_ITRG8 ICTSSEL(8) /*!< HPDF_ITRG8 (TIMER6_TRGO0) */
#define HPDF_ITRG11 ICTSSEL(11) /*!< HPDF_ITRG11 (TIMER22_TRGO0) */
#define HPDF_ITRG12 ICTSSEL(12) /*!< HPDF_ITRG12 (TIMER23_TRGO0) */
#define HPDF_ITRG24 ICTSSEL(24) /*!< HPDF_ITRG24 (EXTI11) */
#define HPDF_ITRG25 ICTSSEL(25) /*!< HPDF_ITRG25 (EXTI15) */
#define HPDF_ITRG31 ICTSSEL(31) /*!< HPDF_ITRG31 (HPDF_ITRG) */
/* inserted channel DMA enable definitions */
#define ICDMAEN_DISABLE ((uint32_t)0x00000000U) /*!< disable DMA channel to read inserted conversions data */
#define ICDMAEN_ENABLE HPDF_FLTYCTL0_ICDMAEN /*!< enable DMA channel to read inserted conversions data */
/* scan conversion mode */
#define SCMOD_DISABLE ((uint32_t)0x00000000U) /*!< scan conversion mode disable */
#define SCMOD_ENABLE HPDF_FLTYCTL0_SCMOD /*!< scan conversion mode enable */
/* inserted conversion synchronously definitions */
#define ICSYN_DISABLE ((uint32_t)0x00000000U) /*!< do not launch an inserted conversion synchronously */
#define ICSYN_ENABLE HPDF_FLTYCTL0_ICSYN /*!< launch an inserted conversion synchronously */
/* inserted channel group definitions */
#define ICGSEL(regval) (BITS(0,7) & ((uint32_t)(regval)<< 0)) /*!< inserted channel group selection */
#define ICGSEL_CHANNEL0 ICGSEL(0x01) /*!< channel 0 belongs to the inserted group */
#define ICGSEL_CHANNEL1 ICGSEL(0x02) /*!< channel 1 belongs to the inserted group */
#define ICGSEL_CHANNEL2 ICGSEL(0x04) /*!< channel 2 belongs to the inserted group */
#define ICGSEL_CHANNEL3 ICGSEL(0x08) /*!< channel 3 belongs to the inserted group */
#define ICGSEL_CHANNEL4 ICGSEL(0x10) /*!< channel 4 belongs to the inserted group */
#define ICGSEL_CHANNEL5 ICGSEL(0x20) /*!< channel 5 belongs to the inserted group */
#define ICGSEL_CHANNEL6 ICGSEL(0x40) /*!< channel 6 belongs to the inserted group */
#define ICGSEL_CHANNEL7 ICGSEL(0x80) /*!< channel 7 belongs to the inserted group */
/* Sinc fliter definitions */
/* Sinc fliter order and type definitions */
#define SFO(regval) (BITS(29,31) & ((uint32_t)(regval)<< 29)) /*!< select Sinc filter order */
#define FLT_FASTSINC SFO(0) /*!< FastSinc filter type */
#define FLT_SINC1 SFO(1) /*!< Sinc1 filter type */
#define FLT_SINC2 SFO(2) /*!< Sinc2 filter type */
#define FLT_SINC3 SFO(3) /*!< Sinc3 filter type */
#define FLT_SINC4 SFO(4) /*!< Sinc4 filter type */
#define FLT_SINC5 SFO(5) /*!< Sinc4 filter type */
/* Sinc fliter and bypass definitions */
#define FLT_SINC_BYPASS ((uint32_t)0x00000001U) /*!< the filter will be bypass. */
#define INTEGRATOR_BYPASS ((uint32_t)0x00000001U) /*!< the integrator will be bypass. */
/* threshold monitor definitions */
/* threshold monitor Sinc filter order definitions */
#define TMSFO(regval) (BITS(22,23) & ((uint32_t)(regval)<< 22)) /*!< select threshold monitor Sinc filter order */
#define TM_FASTSINC TMSFO(0) /*!< FastSinc filter */
#define TM_SINC1 TMSFO(1) /*!< Sinc1 filter */
#define TM_SINC2 TMSFO(2) /*!< Sinc2 filter */
#define TM_SINC3 TMSFO(3) /*!< Sinc3 filter */
/* threshold monitor channel definitions */
#define TMCHEN(regval) (BITS(16,23) & ((uint32_t)(regval)<< 16)) /*!< select threshold monitor channel */
#define TMCHEN_DISABLE TMCHEN(0) /*!< threshold monitor is disabled on channel 0 and channel 1 */
#define TMCHEN_CHANNEL0 TMCHEN(0x01) /*!< threshold monitor is enabled on channel 0 */
#define TMCHEN_CHANNEL1 TMCHEN(0x02) /*!< threshold monitor is enabled on channel 1 */
#define TMCHEN_CHANNEL2 TMCHEN(0x04) /*!< threshold monitor is enabled on channel 2 */
#define TMCHEN_CHANNEL3 TMCHEN(0x08) /*!< threshold monitor is enabled on channel 3 */
#define TMCHEN_CHANNEL4 TMCHEN(0x10) /*!< threshold monitor is enabled on channel 4 */
#define TMCHEN_CHANNEL5 TMCHEN(0x20) /*!< threshold monitor is enabled on channel 5 */
#define TMCHEN_CHANNEL6 TMCHEN(0x40) /*!< threshold monitor is enabled on channel 6 */
#define TMCHEN_CHANNEL7 TMCHEN(0x80) /*!< threshold monitor is enabled on channel 7 */
/* threshold monitor high threshold event break signal definitions */
#define HTBSD(regval) (BITS(0,1) & ((uint32_t)(regval)<< 1)) /*!< select high threshold event break signal */
#define NO_TM_HT_BREAK HTBSD(0) /*!< break signal is not distributed to an threshold monitor high threshold event */
#define TM_HT_BREAK0 HTBSD(1) /*!< break signal 0 is distributed to an threshold monitor high threshold event */
#define TM_HT_BREAK1 HTBSD(2) /*!< break signal 1 is distributed to an threshold monitor high threshold event */
#define TM_HT_BREAK2 HTBSD(4) /*!< break signal 2 is distributed to an threshold monitor high threshold event */
#define TM_HT_BREAK3 HTBSD(8) /*!< break signal 3 is distributed to an threshold monitor high threshold event */
/* threshold monitor low threshold event break signal definitions */
#define LTBSD(regval) (BITS(0,1) & ((uint32_t)(regval)<< 1)) /*!< select low threshold event break signal */
#define NO_TM_LT_BREAK LTBSD(0) /*!< break signal is not distributed to an threshold monitor low threshold event */
#define TM_LT_BREAK0 LTBSD(1) /*!< break signal 0 is distributed to an threshold monitor low threshold event */
#define TM_LT_BREAK1 LTBSD(2) /*!< break signal 1 is distributed to an threshold monitor low threshold event */
#define TM_LT_BREAK2 LTBSD(4) /*!< break signal 2 is distributed to an threshold monitor low threshold event */
#define TM_LT_BREAK3 LTBSD(8) /*!< break signal 3 is distributed to an threshold monitor low threshold event */
/* threshold monitor bypass definitions */
#define TM_FLT_BYPASS ((uint32_t)0x00000001U) /*!< the threshold monitor filter is bypassed. */
/* extremes monitor definitions */
/* extremes monitor channel definitions */
#define EMCS(regval) (BITS(8,15) & ((uint32_t)(regval)<< 8)) /*!< select extremes monitor channel */
#define EM_CHANNEL_DISABLE EMCS(0) /*!< extremes monitor y does not accept data from channel 0 and channel 1 */
#define EM_CHANNEL0 EMCS(0x01) /*!< extremes monitor y accepts data from channel 0 */
#define EM_CHANNEL1 EMCS(0x02) /*!< extremes monitor y accepts data from channel 1 */
#define EM_CHANNEL2 EMCS(0x04) /*!< extremes monitor y accepts data from channel 2 */
#define EM_CHANNEL3 EMCS(0x08) /*!< extremes monitor y accepts data from channel 3 */
#define EM_CHANNEL4 EMCS(0x10) /*!< extremes monitor y accepts data from channel 4 */
#define EM_CHANNEL5 EMCS(0x20) /*!< extremes monitor y accepts data from channel 5 */
#define EM_CHANNEL6 EMCS(0x40) /*!< extremes monitor y accepts data from channel 6 */
#define EM_CHANNEL7 EMCS(0x80) /*!< extremes monitor y accepts data from channel 7 */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check HPDFCLK source */
#define NOT_HPDFCLK_SOURCE(source) (((source) != SERIAL_SYSTEM_CLK) && ((source) != SERIAL_AUDIO_CLK))
/* check HPDF ckout mode */
#define NOT_CKOUT_MOD(mode) (((mode) != CKOUTDM_DISABLE) && ((mode) != CKOUTDM_ENABLE))
/* check HPDF SPI clock source */
#define NOT_SPICLOCK_SOURCE(clock_source) (((clock_source) != EXTERNAL_CKIN) && ((clock_source) != INTERNAL_CKOUT) && \
((clock_source) != HALF_CKOUT_FALLING_EDGE) && ((clock_source) != HALF_CKOUT_RISING_EDGE))
/* check HPDF serial interface type */
#define NOT_SERIALIF_TYPE(type) (((type) != SPI_RISING_EDGE) && ((type) != SPI_FALLING_EDGE) && \
((type) != MANCHESTER_CODE0) && ((type) != MANCHESTER_CODE1))
/* check input data source */
#define NOT_INPUT_DATA_SOURCE(data_source) (((data_source) != SERIAL_INPUT) && ((data_source) != ADC_INPUT) && ((data_source) != INTERNAL_INPUT))
/* check parallel data packing mode */
#define NOT_PARA_DATA_SOURCE(data_source) (((data_source) != SERIAL_INPUT) && ((data_source) != ADC_INPUT) && ((data_source) != INTERNAL_INPUT))
/* check not right shift bit */
#define RIGHT_SHIFT_LOW ((uint32_t)0x00000000U)
#define RIGHT_SHIFT_HIGH ((uint32_t)0x0000001FU)
#define NOT_RIGHT_SHIFT(right_shift) (RIGHT_SHIFT_HIGH < (right_shift))
/* check 24-bit calibration offset */
#define CALI_OFFSET_LOW ((int32_t)-8388608)
#define CALI_OFFSET_HIGH ((int32_t)8388607)
#define NOT_CALI_OFFSET(offset) ((CALI_OFFSET_HIGH < (offset)) && ((offset) < CALI_OFFSET_LOW))
/* check malfunction monitor break signal */
#define NOT_MM_BREAK_SIGNAL(break_signal) (((break_signal) != NO_MM_BREAK) && ((break_signal) != MM_BREAK0) && \
((break_signal) != MM_BREAK1) && ((break_signal) != MM_BREAK2) && \
((break_signal) != MM_BREAK3))
/* check data packing mode */
#define NOT_PARADATA_PACK_MOD(mode) (((mode) != DPM_STANDARD_MODE) && ((mode) != DPM_INTERLEAVED_MODE) && ((mode) != DPM_DUAL_MODE))
/* check malfunction monitor counter threshold */
#define COUNT_THRESHOLD_LOW ((uint32_t)0x00000000U)
#define COUNT_THRESHOLD_HIGH ((uint32_t)0x0000001FU)
#define NOT_COUNT_THRESHOLD(threshold) (COUNT_THRESHOLD_HIGH < (threshold))
/* sinc filter order */
#define NOT_FILTER_ORDER(order) (((order) != FLT_FASTSINC) && ((order) != FLT_SINC1) && \
((order) != FLT_SINC2) && ((order) != FLT_SINC3) && \
((order) != FLT_SINC4) && ((order) != FLT_SINC5))
/* check Sinc filter oversampling rate */
#define OVERSAMPLE_LOW ((uint32_t)0x00000001U)
#define OVERSAMPLE_HIGH ((uint32_t)0x00000400U)
#define NOT_OVERSAMPLE(oversample) ((OVERSAMPLE_HIGH < (oversample)) && ((oversample) == 0U))
/* check Sinc filter oversampling rate */
#define INTER_OVERSAMPLE_LOW ((uint32_t)0x00000001U)
#define INTER_OVERSAMPLE_HIGH ((uint32_t)0x00000100U)
#define NOT_INTER_OVERSAMPLE(oversample) ((INTER_OVERSAMPLE_HIGH < (oversample)) && ((oversample) == 0U))
/* sinc filter order */
#define NOT_TM_ORDER(order) (((order) != TM_FASTSINC) && ((order) != TM_SINC1) && \
((order) != TM_SINC2) && ((order) != TM_SINC3))
/* check Sinc filter oversampling rate */
#define TM_OVERSAMPLE_LOW ((uint32_t)0x00000001U)
#define TM_OVERSAMPLE_HIGH ((uint32_t)0x00000020U)
#define NOT_TM_OVERSAMPLE(oversample) ((TM_OVERSAMPLE_HIGH < (oversample)) && ((oversample) == 0U ))
/* check threshold monitor channel */
#define NOT_TM_CHANNEL(channel) (((channel) != TMCHEN_DISABLE) && ((channel) != TMCHEN_CHANNEL0) && \
((channel) != TMCHEN_CHANNEL1) && ((channel) != TMCHEN_CHANNEL2) && \
((channel) != TMCHEN_CHANNEL3) && ((channel) != TMCHEN_CHANNEL4) && \
((channel) != TMCHEN_CHANNEL5) && ((channel) != TMCHEN_CHANNEL6) && \
((channel) != TMCHEN_CHANNEL7))
/* check high threshold value */
#define TM_VALUE_LOW ((int32_t)0x00800000U)
#define TM_VALUE_HIGH ((int32_t)0x007FFFFFU)
#define NOT_TM_VALUE(value) ((TM_VALUE_HIGH < (value)) && ((value) < TM_VALUE_LOW))
/* check HPDF break signal */
#define NOT_TM_BREAK_SIGNAL(break_signal) (((break_signal) != NO_TM_HT_BREAK) && ((break_signal) != TM_HT_BREAK0) && \
((break_signal) != TM_HT_BREAK1) && ((break_signal) != TM_HT_BREAK2) && \
((break_signal) != TM_HT_BREAK3))
/* check extremes monitor channel */
#define NOT_EM_CHANNEL(channel) (((channel) != EM_CHANNEL_DISABLE) && ((channel) != EM_CHANNEL0) && \
((channel) != EM_CHANNEL1) && ((channel) != EM_CHANNEL2) && \
((channel) != EM_CHANNEL3) && ((channel) != EM_CHANNEL4) && \
((channel) != EM_CHANNEL5) && ((channel) != EM_CHANNEL6) && \
((channel) != EM_CHANNEL7))
/* check regular conversion channel selection */
#define NOT_RCS_CHANNEL(channel) (((channel) != RCS_CHANNEL0) && ((channel) != RCS_CHANNEL1) && \
((channel) != RCS_CHANNEL2) && ((channel) != RCS_CHANNEL3) && \
((channel) != RCS_CHANNEL4) && ((channel) != RCS_CHANNEL5) && \
((channel) != RCS_CHANNEL6) && ((channel) != RCS_CHANNEL7))
/* check inserted conversions trigger signal */
#define NOT_IC_TRIG(trigger) (((trigger) != HPDF_ITRG0) && ((trigger) != HPDF_ITRG1) && \
((trigger) != HPDF_ITRG2) && ((trigger) != HPDF_ITRG3) && \
((trigger) != HPDF_ITRG4) && ((trigger) != HPDF_ITRG5) && \
((trigger) != HPDF_ITRG6) && ((trigger) != HPDF_ITRG7) && \
((trigger) != HPDF_ITRG8) && ((trigger) != HPDF_ITRG11) && \
((trigger) != HPDF_ITRG12) && ((trigger) != HPDF_ITRG24) && \
((trigger) != HPDF_ITRG25) && ((trigger) != HPDF_ITRG31))
/* check inserted conversions trigger edge */
#define NOT_IC_TRIG_EDGE(trigger_edge) (((trigger_edge) != TRG_DISABLE) && ((trigger) != RISING_EDGE_TRG) && \
((trigger_edge) != FALLING_EDGE_TRG) && ((trigger) != EDGE_TRG))
/* check inserted group channel */
#define NOT_ICS_CHANNEL(channel) (((channel) != ICGSEL_CHANNEL0) && ((channel) != ICGSEL_CHANNEL1) && \
((channel) != ICGSEL_CHANNEL2) && ((channel) != ICGSEL_CHANNEL3) && \
((channel) != ICGSEL_CHANNEL4) && ((channel) != ICGSEL_CHANNEL5) && \
((channel) != ICGSEL_CHANNEL6) && ((channel) != ICGSEL_CHANNEL7))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* initialize HPDF channel and filter registers */
/* reset HPDF */
void hpdf_deinit(void);
/* initialize the parameters of HPDF channel struct with the default values */
void hpdf_channel_struct_para_init(hpdf_channel_parameter_struct *init_struct);
/* initialize the parameters of HPDF filter struct with the default values */
void hpdf_filter_struct_para_init(hpdf_filter_parameter_struct *init_struct);
/* initialize the parameters of regular conversion struct with the default values */
void hpdf_rc_struct_para_init(hpdf_rc_parameter_struct *init_struct);
/* initialize the parameters of inserted conversion struct with the default values */
void hpdf_ic_struct_para_init(hpdf_ic_parameter_struct *init_struct);
/* enable the HPDF module globally */
void hpdf_enable(void);
/* disable the HPDF module globally */
void hpdf_disable(void);
/* initialize the HPDF channel */
void hpdf_channel_init(hpdf_channel_enum channelx, hpdf_channel_parameter_struct *init_struct);
/* initialize the HPDF filter */
void hpdf_filter_init(hpdf_filter_enum filtery, hpdf_filter_parameter_struct *init_struct);
/* initialize the regular conversion */
void hpdf_rc_init(hpdf_filter_enum filtery, hpdf_rc_parameter_struct *init_struct);
/* initialize the inserted conversion */
void hpdf_ic_init(hpdf_filter_enum filtery, hpdf_ic_parameter_struct *init_struct);
/* configure the HPDF clock output */
/* configure serial output clock */
void hpdf_clock_output_config(uint32_t source, uint8_t divider, uint32_t mode);
/* configure serial clock output source */
void hpdf_clock_output_source_config(uint32_t source);
/* disable serial clock output duty mode */
void hpdf_clock_output_duty_mode_disable(void);
/* enable serial clock output duty mode */
void hpdf_clock_output_duty_mode_enable(void);
/* configure serial clock output divider */
void hpdf_clock_output_divider_config(uint8_t divider);
/* configure HPDF channel */
/* enable channel */
void hpdf_channel_enable(hpdf_channel_enum channelx);
/* disable channel */
void hpdf_channel_disable(hpdf_channel_enum channelx);
/* configure SPI clock source */
void hpdf_spi_clock_source_config(hpdf_channel_enum channelx, uint32_t clock_source);
/* configure serial interface type */
void hpdf_serial_interface_type_config(hpdf_channel_enum channelx, uint32_t type);
/* disable malfunction monitor */
void hpdf_malfunction_monitor_disable(hpdf_channel_enum channelx);
/* enable malfunction monitor */
void hpdf_malfunction_monitor_enable(hpdf_channel_enum channelx);
/* disable clock loss detector */
void hpdf_clock_loss_disable(hpdf_channel_enum channelx);
/* enable clock loss detector */
void hpdf_clock_loss_enable(hpdf_channel_enum channelx);
/* disable channel inputs pins redirection */
void hpdf_channel_pin_redirection_disable(hpdf_channel_enum channelx);
/* enable channel inputs pins redirection */
void hpdf_channel_pin_redirection_enable(hpdf_channel_enum channelx);
/* configure channel multiplexer select input data source */
void hpdf_channel_multiplexer_config(hpdf_channel_enum channelx, uint32_t data_source);
/* configure data packing mode */
void hpdf_data_pack_mode_config(hpdf_channel_enum channelx, uint32_t mode);
/* configure data right bit-shift */
void hpdf_data_right_bit_shift_config(hpdf_channel_enum channelx, uint8_t right_shift);
/* configure calibration offset */
void hpdf_calibration_offset_config(hpdf_channel_enum channelx, int32_t offset);
/* configure malfunction monitor break signal */
void hpdf_malfunction_break_signal_config(hpdf_channel_enum channelx, uint32_t break_signal);
/* configure malfunction monitor counter threshold */
void hpdf_malfunction_counter_config(hpdf_channel_enum channelx, uint8_t threshold);
/* write the parallel data on standard mode of data packing */
void hpdf_write_parallel_data_standard_mode(hpdf_channel_enum channelx, int16_t data);
/* write the parallel data on interleaved mode of data packing */
void hpdf_write_parallel_data_interleaved_mode(hpdf_channel_enum channelx, int32_t data);
/* write the parallel data on dual mode of data packing */
void hpdf_write_parallel_data_dual_mode(hpdf_channel_enum channelx, int32_t data);
/* update the number of pulses to skip */
void hpdf_pulse_skip_update(hpdf_channel_enum channelx, uint8_t number);
/* read the number of pulses to skip */
uint8_t hpdf_pulse_skip_read(hpdf_channel_enum channelx);
/* HPDF filter configuration */
/* enable filter */
void hpdf_filter_enable(hpdf_filter_enum filtery);
/* disable filter */
void hpdf_filter_disable(hpdf_filter_enum filtery);
/* configure sinc filter order and oversample */
void hpdf_filter_config(hpdf_filter_enum filtery, uint32_t order, uint16_t oversample);
/* configure integrator oversampling rate */
void hpdf_integrator_oversample(hpdf_filter_enum filtery, uint16_t oversample);
/* HPDF threshold monitor configuration */
/* configure threshold monitor filter order and oversample */
void hpdf_threshold_monitor_filter_config(hpdf_channel_enum channelx, uint32_t order, uint8_t oversample);
/* read the threshold monitor filter data */
int16_t hpdf_threshold_monitor_filter_read_data(hpdf_channel_enum channelx);
/* disable threshold monitor fast mode */
void hpdf_threshold_monitor_fast_mode_disable(hpdf_filter_enum filtery);
/* enable threshold monitor fast mode */
void hpdf_threshold_monitor_fast_mode_enable(hpdf_filter_enum filtery);
/* configure threshold monitor channel */
void hpdf_threshold_monitor_channel(hpdf_filter_enum filtery, uint32_t channel);
/* configure threshold monitor high threshold value */
void hpdf_threshold_monitor_high_threshold(hpdf_filter_enum filtery, int32_t value);
/* configure threshold monitor low threshold value */
void hpdf_threshold_monitor_low_threshold(hpdf_filter_enum filtery, int32_t value);
/* configure threshold monitor high threshold event break signal */
void hpdf_high_threshold_break_signal(hpdf_filter_enum filtery, uint32_t break_signal);
/* configure threshold monitor low threshold event break signal */
void hpdf_low_threshold_break_signal(hpdf_filter_enum filtery, uint32_t break_signal);
/* configure HPDF extremes monitor */
/* configure extremes monitor channel */
void hpdf_extremes_monitor_channel(hpdf_filter_enum filtery, uint32_t channel);
/* get the extremes monitor maximum value */
int32_t hpdf_extremes_monitor_maximum_get(hpdf_filter_enum filtery);
/* get the extremes monitor minimum value */
int32_t hpdf_extremes_monitor_minimum_get(hpdf_filter_enum filtery);
/* get the conversion timer value */
uint32_t hpdf_conversion_time_get(hpdf_filter_enum filtery);
/* configure HPDF regular conversions */
/* disable regular conversions continuous mode */
void hpdf_rc_continuous_disable(hpdf_filter_enum filtery);
/* enable regular conversions continuous mode */
void hpdf_rc_continuous_enable(hpdf_filter_enum filtery);
/* start regular channel conversion by software */
void hpdf_rc_start_by_software(hpdf_filter_enum filtery);
/* disable regular conversion synchronously */
void hpdf_rc_syn_disable(hpdf_filter_enum filtery);
/* enable regular conversion synchronously */
void hpdf_rc_syn_enable(hpdf_filter_enum filtery);
/* disable regular conversion DMA channel */
void hpdf_rc_dma_disable(hpdf_filter_enum filtery);
/* enable regular conversion DMA channel */
void hpdf_rc_dma_enable(hpdf_filter_enum filtery);
/* configure regular conversion channel */
void hpdf_rc_channel_config(hpdf_filter_enum filtery, uint32_t channel);
/* disable regular conversion fast conversion mode */
void hpdf_rc_fast_mode_disable(hpdf_filter_enum filtery);
/* enable regular conversion fast conversion mode */
void hpdf_rc_fast_mode_enable(hpdf_filter_enum filtery);
/* get the regular conversion data */
int32_t hpdf_rc_data_get(hpdf_filter_enum filtery);
/* get the channel of regular channel most recently converted */
uint8_t hpdf_rc_channel_get(hpdf_filter_enum filtery);
/* configure HPDF inserted conversions */
/* start inserted channel conversion by software */
void hpdf_ic_start_by_software(hpdf_filter_enum filtery);
/* disable inserted conversion synchronously */
void hpdf_ic_syn_disable(hpdf_filter_enum filtery);
/* enable inserted conversion synchronously */
void hpdf_ic_syn_enable(hpdf_filter_enum filtery);
/* disable inserted conversion DMA channel */
void hpdf_ic_dma_disable(hpdf_filter_enum filtery);
/* enable inserted conversion DMA channel */
void hpdf_ic_dma_enable(hpdf_filter_enum filtery);
/* disable scan conversion mode */
void hpdf_ic_scan_mode_disable(hpdf_filter_enum filtery);
/* enable scan conversion mode */
void hpdf_ic_scan_mode_enable(hpdf_filter_enum filtery);
/* disable inserted conversions trigger siganl */
void hpdf_ic_trigger_signal_disable(hpdf_filter_enum filtery);
/* configure inserted conversions trigger siganl and trigger edge */
void hpdf_ic_trigger_signal_config(hpdf_filter_enum filtery, uint32_t trigger, uint32_t trigger_edge);
/* configure inserted group conversions channel */
void hpdf_ic_channel_config(hpdf_filter_enum filtery, uint32_t channel);
/* get the inserted conversions data */
int32_t hpdf_ic_data_get(hpdf_filter_enum filtery);
/* get the channel of inserted group channel most recently converted */
uint8_t hpdf_ic_channel_get(hpdf_filter_enum filtery);
/* flag and interrupt functions */
/* get the HPDF flags */
FlagStatus hpdf_flag_get(hpdf_filter_enum filtery, hpdf_flag_enum flag);
/* clear the HPDF flags */
void hpdf_flag_clear(hpdf_filter_enum filtery, hpdf_flag_enum flag);
/* enable HPDF interrupt */
void hpdf_interrupt_enable(hpdf_filter_enum filtery, hpdf_interrput_enum interrupt);
/* disable HPDF interrupt */
void hpdf_interrupt_disable(hpdf_filter_enum filtery, hpdf_interrput_enum interrupt);
/* get the HPDF interrupt flags */
FlagStatus hpdf_interrupt_flag_get(hpdf_filter_enum filtery, hpdf_interrput_flag_enum int_flag);
/* clear the HPDF interrupt flags */
void hpdf_interrupt_flag_clear(hpdf_filter_enum filtery, hpdf_interrput_flag_enum int_flag);
#endif /* GD32H75E_HPDF_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_i2c.h
+516
View File
@@ -0,0 +1,516 @@
/*!
\file gd32h75e_i2c.h
\brief definitions for the I2C
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_I2C_H
#define GD32H75E_I2C_H
#include "gd32h75e.h"
/* I2Cx(x=0,1,2,3) definitions */
#define I2C0 I2C_BASE /*!< I2C0 base address */
#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
#define I2C2 (I2C_BASE + 0x00006C00U) /*!< I2C2 base address */
#define I2C3 (I2C_BASE + 0x00000800U) /*!< I2C3 base address */
/* registers definitions */
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */
#define I2C_TIMING(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C timing register */
#define I2C_TIMEOUT(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C timeout register */
#define I2C_STAT(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C status register */
#define I2C_STATC(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C status clear register */
#define I2C_PEC(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C PEC register */
#define I2C_RDATA(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C receive data register */
#define I2C_TDATA(i2cx) REG32((i2cx) + 0x00000028U) /*!< I2C transmit data register */
#define I2C_CTL2(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C control register 2 */
/* bits definitions */
/* I2Cx_CTL0 */
#define I2C_CTL0_I2CEN BIT(0) /*!< I2C peripheral enable */
#define I2C_CTL0_TIE BIT(1) /*!< transmit interrupt enable */
#define I2C_CTL0_RBNEIE BIT(2) /*!< receive interrupt enable */
#define I2C_CTL0_ADDMIE BIT(3) /*!< address match interrupt enable in slave mode */
#define I2C_CTL0_NACKIE BIT(4) /*!< not acknowledge received interrupt enable */
#define I2C_CTL0_STPDETIE BIT(5) /*!< stop detection interrupt enable */
#define I2C_CTL0_TCIE BIT(6) /*!< transfer complete interrupt enable */
#define I2C_CTL0_ERRIE BIT(7) /*!< error interrupt enable */
#define I2C_CTL0_DNF BITS(8,11) /*!< digital noise filter */
#define I2C_CTL0_ANOFF BIT(12) /*!< analog noise filter */
#define I2C_CTL0_DENT BIT(14) /*!< DMA enable for transmission */
#define I2C_CTL0_DENR BIT(15) /*!< DMA enable for reception */
#define I2C_CTL0_SBCTL BIT(16) /*!< slave byte control */
#define I2C_CTL0_SS BIT(17) /*!< whether to stretch SCL low when data is not ready in slave mode */
#define I2C_CTL0_WUEN BIT(18) /*!< wakeup from deep-sleep mode enable */
#define I2C_CTL0_GCEN BIT(19) /*!< whether or not to response to a general call (0x00) */
#define I2C_CTL0_SMBHAEN BIT(20) /*!< SMBus host address enable */
#define I2C_CTL0_SMBDAEN BIT(21) /*!< SMBus device default address enable */
#define I2C_CTL0_SMBALTEN BIT(22) /*!< SMBus alert enable */
#define I2C_CTL0_PECEN BIT(23) /*!< PEC calculation switch */
/* I2Cx_CTL1 */
#define I2C_CTL1_SADDRESS BITS(0,9) /*!< slave address to be sent */
#define I2C_CTL1_TRDIR BIT(10) /*!< transfer direction in master mode */
#define I2C_CTL1_ADD10EN BIT(11) /*!< 10-bit addressing mode enable in master mode */
#define I2C_CTL1_HEAD10R BIT(12) /*!< 10-bit address header executes read direction only in master receive mode */
#define I2C_CTL1_START BIT(13) /*!< generate a START condition on I2C bus */
#define I2C_CTL1_STOP BIT(14) /*!< generate a STOP condition on I2C bus */
#define I2C_CTL1_NACKEN BIT(15) /*!< generate NACK in slave mode */
#define I2C_CTL1_BYTENUM BITS(16,23) /*!< number of bytes to be transferred */
#define I2C_CTL1_RELOAD BIT(24) /*!< reload mode enable */
#define I2C_CTL1_AUTOEND BIT(25) /*!< automatic end mode in master mode */
#define I2C_CTL1_PECTRANS BIT(26) /*!< PEC transfer */
/* I2Cx_SADDR0 */
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
#define I2C_SADDR0_ADDFORMAT BIT(10) /*!< address mode for the I2C slave */
#define I2C_SADDR0_ADDRESSEN BIT(15) /*!< I2C address enable */
/* I2Cx_SADDR1 */
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave */
#define I2C_SADDR1_ADDMSK2 BITS(8,10) /*!< ADDRESS2[7:1] mask */
#define I2C_SADDR1_ADDRESS2EN BIT(15) /*!< second I2C address enable */
/* I2Cx_TIMING */
#define I2C_TIMING_SCLL BITS(0,7) /*!< SCL low period */
#define I2C_TIMING_SCLH BITS(8,15) /*!< SCL high period */
#define I2C_TIMING_SDADELY BITS(16,19) /*!< data hold time */
#define I2C_TIMING_SCLDELY BITS(20,23) /*!< data setup time */
#define I2C_TIMING_PSC BITS(28,31) /*!< timing prescaler */
/* I2Cx_TIMEOUT */
#define I2C_TIMEOUT_BUSTOA BITS(0,11) /*!< bus timeout A */
#define I2C_TIMEOUT_TOIDLE BIT(12) /*!< idle clock timeout detection */
#define I2C_TIMEOUT_TOEN BIT(15) /*!< clock timeout detection enable */
#define I2C_TIMEOUT_BUSTOB BITS(16,27) /*!< bus timeout B */
#define I2C_TIMEOUT_EXTOEN BIT(31) /*!< extended clock timeout detection enable */
/* I2Cx_STAT */
#define I2C_STAT_TBE BIT(0) /*!< I2C_TDATA is empty during transmitting */
#define I2C_STAT_TI BIT(1) /*!< transmit interrupt */
#define I2C_STAT_RBNE BIT(2) /*!< I2C_RDATA is not empty during receiving */
#define I2C_STAT_ADDSEND BIT(3) /*!< address received matches in slave mode */
#define I2C_STAT_NACK BIT(4) /*!< not acknowledge flag */
#define I2C_STAT_STPDET BIT(5) /*!< STOP condition detected in slave mode */
#define I2C_STAT_TC BIT(6) /*!< transfer complete in master mode */
#define I2C_STAT_TCR BIT(7) /*!< transfer complete reload */
#define I2C_STAT_BERR BIT(8) /*!< bus error */
#define I2C_STAT_LOSTARB BIT(9) /*!< arbitration lost */
#define I2C_STAT_OUERR BIT(10) /*!< overrun/underrun error in slave mode */
#define I2C_STAT_PECERR BIT(11) /*!< PEC error */
#define I2C_STAT_TIMEOUT BIT(12) /*!< timeout flag */
#define I2C_STAT_SMBALT BIT(13) /*!< SMBus alert */
#define I2C_STAT_I2CBSY BIT(15) /*!< busy flag */
#define I2C_STAT_TR BIT(16) /*!< whether the I2C is a transmitter or a receiver in slave mode */
#define I2C_STAT_READDR BITS(17,23) /*!< received match address in slave mode */
/* I2Cx_STATC */
#define I2C_STATC_ADDSENDC BIT(3) /*!< ADDSEND flag clear */
#define I2C_STATC_NACKC BIT(4) /*!< not acknowledge flag clear */
#define I2C_STATC_STPDETC BIT(5) /*!< STPDET flag clear */
#define I2C_STATC_BERRC BIT(8) /*!< bus error flag clear */
#define I2C_STATC_LOSTARBC BIT(9) /*!< arbitration Lost flag clear */
#define I2C_STATC_OUERRC BIT(10) /*!< overrun/underrun flag clear */
#define I2C_STATC_PECERRC BIT(11) /*!< PEC error flag clear */
#define I2C_STATC_TIMEOUTC BIT(12) /*!< TIMEOUT flag clear */
#define I2C_STATC_SMBALTC BIT(13) /*!< SMBus alert flag clear */
/* I2Cx_PEC */
#define I2C_PEC_PECV BITS(0,7) /*!< Packet Error Checking Value that calculated by hardware when PEC is enabled */
/* I2Cx_RDATA */
#define I2C_RDATA_RDATA BITS(0,7) /*!< receive data value */
/* I2Cx_TDATA */
#define I2C_TDATA_TDATA BITS(0,7) /*!< transmit data value */
/* I2Cx_CTL2 */
#define I2C_CTL2_ADDM BITS(9,15) /*!< address bits compare select */
/* constants definitions */
/* define the I2C bit position and its register index offset */
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
/* register offset */
#define I2C_CTL0_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */
#define I2C_STAT_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT register offset */
/* I2C interrupt flags */
typedef enum {
I2C_INT_FLAG_TI = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 1U, I2C_STAT_REG_OFFSET, 1U), /*!< transmit interrupt flag */
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 2U, I2C_STAT_REG_OFFSET, 2U), /*!< I2C_RDATA is not empty during receiving interrupt flag */
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 3U, I2C_STAT_REG_OFFSET, 3U), /*!< address received matches in slave mode interrupt flag */
I2C_INT_FLAG_NACK = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 4U, I2C_STAT_REG_OFFSET, 4U), /*!< not acknowledge interrupt flag */
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 5U, I2C_STAT_REG_OFFSET, 5U), /*!< stop condition detected in slave mode interrupt flag */
I2C_INT_FLAG_TC = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 6U, I2C_STAT_REG_OFFSET, 6U), /*!< transfer complete in master mode interrupt flag */
I2C_INT_FLAG_TCR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 6U, I2C_STAT_REG_OFFSET, 7U), /*!< transfer complete reload interrupt flag */
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 8U), /*!< bus error interrupt flag */
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 9U), /*!< arbitration lost interrupt flag */
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 10U), /*!< overrun/underrun error in slave mode interrupt flag */
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 11U), /*!< PEC error interrupt flag */
I2C_INT_FLAG_TIMEOUT = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 12U), /*!< timeout interrupt flag */
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 13U) /*!< SMBus Alert interrupt flag */
} i2c_interrupt_flag_enum;
/* I2C DMA constants definitions */
#define I2C_DMA_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C transmit data use DMA */
#define I2C_DMA_RECEIVE ((uint32_t)0x00000001U) /*!< I2C receive data use DMA */
/* I2C interrupt enable or disable */
#define I2C_INT_ERR I2C_CTL0_ERRIE /*!< error interrupt enable */
#define I2C_INT_TC I2C_CTL0_TCIE /*!< transfer complete interrupt enable */
#define I2C_INT_STPDET I2C_CTL0_STPDETIE /*!< stop detection interrupt enable */
#define I2C_INT_NACK I2C_CTL0_NACKIE /*!< not acknowledge received interrupt enable */
#define I2C_INT_ADDM I2C_CTL0_ADDMIE /*!< address match interrupt enable */
#define I2C_INT_RBNE I2C_CTL0_RBNEIE /*!< receive interrupt enable */
#define I2C_INT_TI I2C_CTL0_TIE /*!< transmit interrupt enable */
/* I2C transfer direction in master mode */
#define I2C_MASTER_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C master transmit */
#define I2C_MASTER_RECEIVE I2C_CTL1_TRDIR /*!< I2C master receive */
/* address mode for the I2C slave */
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */
/* the length of filter spikes */
#define FILTER_DISABLE ((uint32_t)0x00000000U) /*!< digital filter is disabled */
#define FILTER_LENGTH_1 ((uint32_t)0x00000001U) /*!< digital filter is enabled and filter spikes with a length of up to 1 tI2CCLK */
#define FILTER_LENGTH_2 ((uint32_t)0x00000002U) /*!< digital filter is enabled and filter spikes with a length of up to 2 tI2CCLK */
#define FILTER_LENGTH_3 ((uint32_t)0x00000003U) /*!< digital filter is enabled and filter spikes with a length of up to 3 tI2CCLK */
#define FILTER_LENGTH_4 ((uint32_t)0x00000004U) /*!< digital filter is enabled and filter spikes with a length of up to 4 tI2CCLK */
#define FILTER_LENGTH_5 ((uint32_t)0x00000005U) /*!< digital filter is enabled and filter spikes with a length of up to 5 tI2CCLK */
#define FILTER_LENGTH_6 ((uint32_t)0x00000006U) /*!< digital filter is enabled and filter spikes with a length of up to 6 tI2CCLK */
#define FILTER_LENGTH_7 ((uint32_t)0x00000007U) /*!< digital filter is enabled and filter spikes with a length of up to 7 tI2CCLK */
#define FILTER_LENGTH_8 ((uint32_t)0x00000008U) /*!< digital filter is enabled and filter spikes with a length of up to 8 tI2CCLK */
#define FILTER_LENGTH_9 ((uint32_t)0x00000009U) /*!< digital filter is enabled and filter spikes with a length of up to 9 tI2CCLK */
#define FILTER_LENGTH_10 ((uint32_t)0x0000000AU) /*!< digital filter is enabled and filter spikes with a length of up to 10 tI2CCLK */
#define FILTER_LENGTH_11 ((uint32_t)0x0000000BU) /*!< digital filter is enabled and filter spikes with a length of up to 11 tI2CCLK */
#define FILTER_LENGTH_12 ((uint32_t)0x0000000CU) /*!< digital filter is enabled and filter spikes with a length of up to 12 tI2CCLK */
#define FILTER_LENGTH_13 ((uint32_t)0x0000000DU) /*!< digital filter is enabled and filter spikes with a length of up to 13 tI2CCLK */
#define FILTER_LENGTH_14 ((uint32_t)0x0000000EU) /*!< digital filter is enabled and filter spikes with a length of up to 14 tI2CCLK */
#define FILTER_LENGTH_15 ((uint32_t)0x0000000FU) /*!< digital filter is enabled and filter spikes with a length of up to 15 tI2CCLK */
/* defines which bits of register ADDRESS[7:1] are compared with an incoming address byte */
#define ADDRESS_BIT1_COMPARE ((uint32_t)0x00000200U) /*!< address bit1 needs compare */
#define ADDRESS_BIT2_COMPARE ((uint32_t)0x00000400U) /*!< address bit2 needs compare */
#define ADDRESS_BIT3_COMPARE ((uint32_t)0x00000800U) /*!< address bit3 needs compare */
#define ADDRESS_BIT4_COMPARE ((uint32_t)0x00001000U) /*!< address bit4 needs compare */
#define ADDRESS_BIT5_COMPARE ((uint32_t)0x00002000U) /*!< address bit5 needs compare */
#define ADDRESS_BIT6_COMPARE ((uint32_t)0x00004000U) /*!< address bit6 needs compare */
#define ADDRESS_BIT7_COMPARE ((uint32_t)0x00008000U) /*!< address bit7 needs compare */
/* defines which bits of ADDRESS2[7:1] are compared with an incoming address byte, and which bits are masked (do not care) */
#define ADDRESS2_NO_MASK ((uint32_t)0x00000000U) /*!< no mask, all the bits must be compared */
#define ADDRESS2_MASK_BIT1 ((uint32_t)0x00000001U) /*!< ADDRESS2[1] is masked, only ADDRESS2[7:2] are compared */
#define ADDRESS2_MASK_BIT1_2 ((uint32_t)0x00000002U) /*!< ADDRESS2[2:1] is masked, only ADDRESS2[7:3] are compared */
#define ADDRESS2_MASK_BIT1_3 ((uint32_t)0x00000003U) /*!< ADDRESS2[3:1] is masked, only ADDRESS2[7:4] are compared */
#define ADDRESS2_MASK_BIT1_4 ((uint32_t)0x00000004U) /*!< ADDRESS2[4:1] is masked, only ADDRESS2[7:5] are compared */
#define ADDRESS2_MASK_BIT1_5 ((uint32_t)0x00000005U) /*!< ADDRESS2[5:1] is masked, only ADDRESS2[7:6] are compared */
#define ADDRESS2_MASK_BIT1_6 ((uint32_t)0x00000006U) /*!< ADDRESS2[6:1] is masked, only ADDRESS2[7] are compared */
#define ADDRESS2_MASK_ALL ((uint32_t)0x00000007U) /*!< all the ADDRESS2[7:1] bits are masked */
/* idle clock timeout detection */
#define BUSTOA_DETECT_SCL_LOW ((uint32_t)0x00000000U) /*!< BUSTOA is used to detect SCL low timeout */
#define BUSTOA_DETECT_IDLE I2C_TIMEOUT_TOIDLE /*!< BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle */
/* I2C flag definitions */
#define I2C_FLAG_TBE I2C_STAT_TBE /*!< I2C_TDATA is empty during transmitting */
#define I2C_FLAG_TI I2C_STAT_TI /*!< transmit interrupt */
#define I2C_FLAG_RBNE I2C_STAT_RBNE /*!< I2C_RDATA is not empty during receiving */
#define I2C_FLAG_ADDSEND I2C_STAT_ADDSEND /*!< address received matches in slave mode */
#define I2C_FLAG_NACK I2C_STAT_NACK /*!< not acknowledge flag */
#define I2C_FLAG_STPDET I2C_STAT_STPDET /*!< STOP condition detected in slave mode */
#define I2C_FLAG_TC I2C_STAT_TC /*!< transfer complete in master mode */
#define I2C_FLAG_TCR I2C_STAT_TCR /*!< transfer complete reload */
#define I2C_FLAG_BERR I2C_STAT_BERR /*!< bus error */
#define I2C_FLAG_LOSTARB I2C_STAT_LOSTARB /*!< arbitration lost */
#define I2C_FLAG_OUERR I2C_STAT_OUERR /*!< overrun/underrun error in slave mode */
#define I2C_FLAG_PECERR I2C_STAT_PECERR /*!< PEC error */
#define I2C_FLAG_TIMEOUT I2C_STAT_TIMEOUT /*!< timeout flag */
#define I2C_FLAG_SMBALT I2C_STAT_SMBALT /*!< SMBus Alert */
#define I2C_FLAG_I2CBSY I2C_STAT_I2CBSY /*!< busy flag */
#define I2C_FLAG_TR I2C_STAT_TR /*!< whether the I2C is a transmitter or a receiver in slave mode */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check peripherals */
#define NOT_I2C_PERIPH(periph) (((periph) != I2C0) && ((periph) != I2C1) && ((periph) != I2C2) && ((periph) != I2C3))
/* check the frequency division factor */
#define I2C_PSC_HIGH_VALUE ((uint32_t)0x0000000FU) /*!< maximum prescaler value */
#define NOT_I2C_PSC(psc) (I2C_PSC_HIGH_VALUE < (psc))
/* check data setup time */
#define SCL_DELY_HIGH_VALUE ((uint32_t)0x0000000FU) /*!< maximum SCL delay value */
#define NOT_I2C_SCL_DELY(scl_dely) (SCL_DELY_HIGH_VALUE < (scl_dely))
/* check data hold time */
#define SDA_DELY_HIGH_VALUE ((uint32_t)0x0000000FU) /*!< maximum SDA delay value */
#define NOT_I2C_SDA_DELY(sda_dely) (SDA_DELY_HIGH_VALUE < (sda_dely))
/* check the length of filter spikes */
#define FILTER_LENGTH_HIGH_VALUE ((uint32_t)0x0000000FU) /*!< maximum filter spikes length value */
#define NOT_I2C_FILTER_LENGTH(filter_length) (FILTER_LENGTH_HIGH_VALUE < (filter_length))
/* check SCL high period */
#define SCLH_HIGH_VALUE ((uint32_t)0x000000FFU) /*!< maximum SCL high period value */
#define NOT_I2C_SCLH(sclh) (SCLH_HIGH_VALUE < (sclh))
/* check SCL low period */
#define SCLL_HIGH_VALUE ((uint32_t)0x000000FFU) /*!< maximum SCL low period value */
#define NOT_I2C_SCLL(scll) (SCLL_HIGH_VALUE < (scll))
/* check I2C slave address */
#define ADDRESS_HIGH_VALUE ((uint32_t)0x000003FFU) /*!< maximum I2C slave address value */
#define NOT_I2C_ADDRESS(address) (ADDRESS_HIGH_VALUE < (address))
/* check I2C transfer direction in master mode */
#define NOT_I2C_TRANS_DIRECTION(trans_direction) (((trans_direction) != I2C_MASTER_TRANSMIT) && \
((trans_direction) != I2C_MASTER_RECEIVE))
/* check I2C slave address mode */
#define NOT_I2C_ADDR_FORMAT(addr_format) (((addr_format) != I2C_ADDFORMAT_7BITS) && \
((addr_format) != I2C_ADDFORMAT_10BITS))
/* check the bits need to compare */
#define CMOMPARE_BITS_HIGH_VALUE ((uint32_t)0x0000007F) /* maximum compared value */
#define NOT_I2C_COMPARE_BITS(compare_bits) (CMOMPARE_BITS_HIGH_VALUE < (compare_bits))
/* check I2C slave second address */
#define SECOND_ADDRESS_HIGH_VALUE ((uint32_t)0x000000FEU) /*!< maximum I2C slave second address value */
#define NOT_I2C_SECOND_ADDRESS(address) (SECOND_ADDRESS_HIGH_VALUE < (address))
/* check the bits not need to compare */
#define NOT_I2C_ADDR_MASK(addr_mask) (((addr_mask) != ADDRESS2_NO_MASK) && \
((addr_mask) != ADDRESS2_MASK_BIT1) && \
((addr_mask) != ADDRESS2_MASK_BIT1_2) && \
((addr_mask) != ADDRESS2_MASK_BIT1_3) && \
((addr_mask) != ADDRESS2_MASK_BIT1_4) && \
((addr_mask) != ADDRESS2_MASK_BIT1_5) && \
((addr_mask) != ADDRESS2_MASK_BIT1_6) && \
((addr_mask) != ADDRESS2_MASK_ALL))
/* check the bits not need to compare */
#define NOT_I2C_DMA(dma) (((dma) != I2C_DMA_TRANSMIT) && \
((dma) != I2C_DMA_RECEIVE))
/* check bus timeout value */
#define TIMEOUT_HIGH_VALUE ((uint32_t)0x00000FFFU) /*!< maximum bus timeout value */
#define NOT_I2C_TIMEOUT(timeout) (TIMEOUT_HIGH_VALUE < (timeout))
/* check idle clock timeout detection content */
#define NOT_I2C_TIMEOUT_DET(timeout) (((timeout) != BUSTOA_DETECT_SCL_LOW) && \
((timeout) != BUSTOA_DETECT_IDLE))
/* check I2C flag status */
#define NOT_I2C_STAT_FALG(flag) (((flag) != I2C_FLAG_TBE) && \
((flag) != I2C_FLAG_TI) && \
((flag) != I2C_FLAG_RBNE) && \
((flag) != I2C_FLAG_ADDSEND) && \
((flag) != I2C_FLAG_NACK) && \
((flag) != I2C_FLAG_STPDET) && \
((flag) != I2C_FLAG_TC) && \
((flag) != I2C_FLAG_TCR) && \
((flag) != I2C_FLAG_BERR) && \
((flag) != I2C_FLAG_LOSTARB) && \
((flag) != I2C_FLAG_OUERR) && \
((flag) != I2C_FLAG_PECERR) && \
((flag) != I2C_FLAG_TIMEOUT) && \
((flag) != I2C_FLAG_SMBALT) && \
((flag) != I2C_FLAG_I2CBSY) && \
((flag) != I2C_FLAG_TR))
/* check I2C flag(which can be cleared) status */
#define NOT_I2C_STAT_CLEAR_FALG(flag) (((flag) != I2C_FLAG_ADDSEND) && \
((flag) != I2C_FLAG_NACK) && \
((flag) != I2C_FLAG_STPDET) && \
((flag) != I2C_FLAG_BERR) && \
((flag) != I2C_FLAG_LOSTARB) && \
((flag) != I2C_FLAG_OUERR) && \
((flag) != I2C_FLAG_PECERR) && \
((flag) != I2C_FLAG_TIMEOUT) && \
((flag) != I2C_FLAG_SMBALT))
/* check I2C interrupt */
#define NOT_I2C_INT(interrupt) (((interrupt) != I2C_INT_ERR) && \
((interrupt) != I2C_INT_TC) && \
((interrupt) != I2C_INT_STPDET) && \
((interrupt) != I2C_INT_NACK) && \
((interrupt) != I2C_INT_ADDM) && \
((interrupt) != I2C_INT_RBNE) && \
((interrupt) != I2C_INT_TI))
#endif
/* function declarations */
/* initialization functions */
/* reset I2C */
void i2c_deinit(uint32_t i2c_periph);
/* configure the timing parameters */
void i2c_timing_config(uint32_t i2c_periph, uint32_t psc, uint32_t scl_dely, uint32_t sda_dely);
/* configure digital noise filter */
void i2c_digital_noise_filter_config(uint32_t i2c_periph, uint32_t filter_length);
/* enable analog noise filter */
void i2c_analog_noise_filter_enable(uint32_t i2c_periph);
/* disable analog noise filter */
void i2c_analog_noise_filter_disable(uint32_t i2c_periph);
/* configure the SCL high and low period of clock in master mode */
void i2c_master_clock_config(uint32_t i2c_periph, uint32_t sclh, uint32_t scll);
/* configure I2C slave address and transfer direction in master mode */
void i2c_master_addressing(uint32_t i2c_periph, uint32_t address, uint32_t trans_direction);
/* application function declarations */
/* 10-bit address header executes read direction only in master receive mode */
void i2c_address10_header_enable(uint32_t i2c_periph);
/* 10-bit address header executes complete sequence in master receive mode */
void i2c_address10_header_disable(uint32_t i2c_periph);
/* enable 10-bit addressing mode in master mode */
void i2c_address10_enable(uint32_t i2c_periph);
/* disable 10-bit addressing mode in master mode */
void i2c_address10_disable(uint32_t i2c_periph);
/* enable I2C automatic end mode in master mode */
void i2c_automatic_end_enable(uint32_t i2c_periph);
/* disable I2C automatic end mode in master mode */
void i2c_automatic_end_disable(uint32_t i2c_periph);
/* enable the response to a general call */
void i2c_slave_response_to_gcall_enable(uint32_t i2c_periph);
/* disable the response to a general call */
void i2c_slave_response_to_gcall_disable(uint32_t i2c_periph);
/* enable to stretch SCL low when data is not ready in slave mode */
void i2c_stretch_scl_low_enable(uint32_t i2c_periph);
/* disable to stretch SCL low when data is not ready in slave mode */
void i2c_stretch_scl_low_disable(uint32_t i2c_periph);
/* configure I2C slave address */
void i2c_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_format);
/* define which bits of ADDRESS[7:1] need to compare with the incoming address byte */
void i2c_address_bit_compare_config(uint32_t i2c_periph, uint32_t compare_bits);
/* disable I2C address in slave mode */
void i2c_address_disable(uint32_t i2c_periph);
/* configure I2C second slave address */
void i2c_second_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_mask);
/* disable I2C second address in slave mode */
void i2c_second_address_disable(uint32_t i2c_periph);
/* get received match address in slave mode */
uint32_t i2c_recevied_address_get(uint32_t i2c_periph);
/* enable slave byte control */
void i2c_slave_byte_control_enable(uint32_t i2c_periph);
/* disable slave byte control */
void i2c_slave_byte_control_disable(uint32_t i2c_periph);
/* generate a NACK in slave mode */
void i2c_nack_enable(uint32_t i2c_periph);
/* enable wakeup from deep-sleep mode */
void i2c_wakeup_from_deepsleep_enable(uint32_t i2c_periph);
/* disable wakeup from deep-sleep mode */
void i2c_wakeup_from_deepsleep_disable(uint32_t i2c_periph);
/* enable I2C */
void i2c_enable(uint32_t i2c_periph);
/* disable I2C */
void i2c_disable(uint32_t i2c_periph);
/* generate a START condition on I2C bus */
void i2c_start_on_bus(uint32_t i2c_periph);
/* generate a STOP condition on I2C bus */
void i2c_stop_on_bus(uint32_t i2c_periph);
/* I2C transmit data */
void i2c_data_transmit(uint32_t i2c_periph, uint32_t data);
/* I2C receive data */
uint32_t i2c_data_receive(uint32_t i2c_periph);
/* enable I2C reload mode */
void i2c_reload_enable(uint32_t i2c_periph);
/* disable I2C reload mode */
void i2c_reload_disable(uint32_t i2c_periph);
/* configure number of bytes to be transferred */
void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint8_t byte_number);
/* enable I2C DMA for transmission or reception */
void i2c_dma_enable(uint32_t i2c_periph, uint8_t dma);
/* disable I2C DMA for transmission or reception */
void i2c_dma_disable(uint32_t i2c_periph, uint8_t dma);
/* I2C transfers PEC value */
void i2c_pec_transfer(uint32_t i2c_periph);
/* enable I2C PEC calculation */
void i2c_pec_enable(uint32_t i2c_periph);
/* disable I2C PEC calculation */
void i2c_pec_disable(uint32_t i2c_periph);
/* get packet error checking value */
uint32_t i2c_pec_value_get(uint32_t i2c_periph);
/* enable SMBus alert */
void i2c_smbus_alert_enable(uint32_t i2c_periph);
/* disable SMBus alert */
void i2c_smbus_alert_disable(uint32_t i2c_periph);
/* enable SMBus device default address */
void i2c_smbus_default_addr_enable(uint32_t i2c_periph);
/* disable SMBus device default address */
void i2c_smbus_default_addr_disable(uint32_t i2c_periph);
/* enable SMBus host address */
void i2c_smbus_host_addr_enable(uint32_t i2c_periph);
/* disable SMBus host address */
void i2c_smbus_host_addr_disable(uint32_t i2c_periph);
/* enable extended clock timeout detection */
void i2c_extented_clock_timeout_enable(uint32_t i2c_periph);
/* disable extended clock timeout detection */
void i2c_extented_clock_timeout_disable(uint32_t i2c_periph);
/* enable clock timeout detection */
void i2c_clock_timeout_enable(uint32_t i2c_periph);
/* disable clock timeout detection */
void i2c_clock_timeout_disable(uint32_t i2c_periph);
/* configure bus timeout B */
void i2c_bus_timeout_b_config(uint32_t i2c_periph, uint32_t timeout);
/* configure bus timeout A */
void i2c_bus_timeout_a_config(uint32_t i2c_periph, uint32_t timeout);
/* configure idle clock timeout detection */
void i2c_idle_clock_timeout_config(uint32_t i2c_periph, uint32_t timeout);
/* interrupt & flag functions */
/* get I2C flag status */
FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag);
/* clear I2C flag status */
void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag);
/* enable I2C interrupt */
void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t interrupt);
/* disable I2C interrupt */
void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t interrupt);
/* get I2C interrupt flag status */
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
/* clear I2C interrupt flag status */
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
#endif /* GD32H75E_I2C_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_lpdts.h
+234
View File
@@ -0,0 +1,234 @@
/*!
\file gd32h75e_lpdts.h
\brief definitions for the LPDTS
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_LPDTS_H
#define GD32H75E_LPDTS_H
#include "gd32h75e.h"
/* LPDTS definitions */
#define LPDTS LPDTS_BASE
/* registers definitions */
#define LPDTS_CFG REG32(LPDTS + 0x00000000U) /*!< LPDTS configuration register */
#define LPDTS_SDATA REG32(LPDTS + 0x00000008U) /*!< LPDTS sensor T0 data register */
#define LPDTS_RDATA REG32(LPDTS + 0x00000010U) /*!< LPDTS ramp data register */
#define LPDTS_IT REG32(LPDTS + 0x00000014U) /*!< LPDTS interrupt threshold register */
#define LPDTS_DATA REG32(LPDTS + 0x0000001CU) /*!< LPDTS temperature data register */
#define LPDTS_STAT REG32(LPDTS + 0x00000020U) /*!< LPDTS temperature sensor status register */
#define LPDTS_INTEN REG32(LPDTS + 0x00000024U) /*!< LPDTS interrupt enable register */
#define LPDTS_INTC REG32(LPDTS + 0x00000028U) /*!< LPDTS interrupt clear flag register */
#define LPDTS_OP REG32(LPDTS + 0x0000002CU) /*!< LPDTS option register */
/* bits definitions */
/* LPDTS_CFG */
#define LPDTS_CFG_TSEN BIT(0) /*!< temperature sensor enable */
#define LPDTS_CFG_TRGS BIT(4) /*!< software trigger */
#define LPDTS_CFG_ITSEL BITS(8,11) /*!< input trigger selection */
#define LPDTS_CFG_SPT BITS(16,19) /*!< sampling time */
#define LPDTS_CFG_REFSEL BIT(20) /*!< reference clock selection */
/* LPDTS_SDATA */
#define LPDTS_SDATA_FREQ BITS(0,15) /*!< frequency value at temperature T0 */
#define LPDTS_SDATA_VAL BITS(16,17) /*!< temperature T0 */
/* LPDTS_RDATA */
#define LPDTS_RDATA_RCVAL BITS(0,15) /*!< ramp coefficient */
/* LPDTS_IT */
#define LPDTS_IT_INTLT BITS(0,15) /*!< interrupt low threshold */
#define LPDTS_IT_INTHT BITS(16,31) /*!< interrupt high threshold */
/* LPDTS_DATA */
#define LPDTS_DATA_COVAL BITS(0,15) /*!< value of the counter output */
/* LPDTS_STAT */
#define LPDTS_STAT_EMIF BIT(0) /*!< end of measurement interrupt flag */
#define LPDTS_STAT_LTIF BIT(1) /*!< low threshold interrupt flag */
#define LPDTS_STAT_HTIF BIT(2) /*!< high threshold interrupt flag */
#define LPDTS_STAT_EMAIF BIT(4) /*!< end of measurement asynchronous interrupt flag */
#define LPDTS_STAT_LTAIF BIT(5) /*!< low threshold asynchronous interrupt flag */
#define LPDTS_STAT_HTAIF BIT(6) /*!< high threshold asynchronous interrupt flag */
#define LPDTS_STAT_TSRF BIT(15) /*!< temperature sensor ready flag */
/* LPDTS_INTEN */
#define LPDTS_INTEN_EMIE BIT(0) /*!< end of measurement interrupt enable */
#define LPDTS_INTEN_LTIE BIT(1) /*!< low threshold interrupt enable */
#define LPDTS_INTEN_HTIE BIT(2) /*!< high threshold interrupt enable */
#define LPDTS_INTEN_EMAIE BIT(4) /*!< end of measurement asynchronous interrupt enable */
#define LPDTS_INTEN_LTAIE BIT(5) /*!< low threshold asynchronous interrupt enable */
#define LPDTS_INTEN_HTAIE BIT(6) /*!< high threshold asynchronous interrupt enable */
/* LPDTS_INTC */
#define LPDTS_INTC_EMIC BIT(0) /*!< end of measurement interrupt clear */
#define LPDTS_INTC_LTIC BIT(1) /*!< low threshold interrupt clear */
#define LPDTS_INTC_HTIC BIT(2) /*!< high threshold interrupt clear */
#define LPDTS_INTC_EMAIC BIT(4) /*!< end of measure asynchronous interrupt clear */
#define LPDTS_INTC_LTAIC BIT(5) /*!< low threshold asynchronous interrupt clear */
#define LPDTS_INTC_HTAIC BIT(6) /*!< high threshold asynchronous interrupt clear */
/* LPDTS_OP */
#define LPDTS_OP_OP BITS(0,31) /*!< general purpose option */
/* constants definitions */
/* parameter struct definitions */
typedef struct {
uint32_t ref_clock; /*!< reference clock selection */
uint32_t trigger_input; /*!< input trigger selection */
uint32_t sampling_time; /*!< sampling time */
} lpdts_parameter_struct;
/* reference clock definitions */
#define REF_PCLK ((uint32_t)0x00000000U) /*!< high speed reference clock (PCLK) */
#define REF_LXTAL LPDTS_CFG_REFSEL /*!< low speed reference clock (LXTAL) */
/* input trigger selection definitions */
#define TRIGGER_SEL(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
#define NO_HARDWARE_TRIGGER TRIGGER_SEL(0) /*!< no hardware trigger signal */
#define LPDTS_TRG TRIGGER_SEL(4) /*!< select LPDTS_TRG as trigger signal */
/* sampling time definitions */
#define SMP_TIME(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
#define SPT_CLOCK_1 SMP_TIME(1) /*!< 1 LXTAL or FM(T) clocks */
#define SPT_CLOCK_2 SMP_TIME(2) /*!< 2 LXTAL or FM(T) clocks */
#define SPT_CLOCK_3 SMP_TIME(3) /*!< 3 LXTAL or FM(T) clocks */
#define SPT_CLOCK_4 SMP_TIME(4) /*!< 4 LXTAL or FM(T) clocks */
#define SPT_CLOCK_5 SMP_TIME(5) /*!< 5 LXTAL or FM(T) clocks */
#define SPT_CLOCK_6 SMP_TIME(6) /*!< 6 LXTAL or FM(T) clocks */
#define SPT_CLOCK_7 SMP_TIME(7) /*!< 7 LXTAL or FM(T) clocks */
#define SPT_CLOCK_8 SMP_TIME(8) /*!< 8 LXTAL or FM(T) clocks */
#define SPT_CLOCK_9 SMP_TIME(9) /*!< 9 LXTAL or FM(T) clocks */
#define SPT_CLOCK_10 SMP_TIME(10) /*!< 10 LXTAL or FM(T) clocks */
#define SPT_CLOCK_11 SMP_TIME(11) /*!< 11 LXTAL or FM(T) clocks */
#define SPT_CLOCK_12 SMP_TIME(12) /*!< 12 LXTAL or FM(T) clocks */
#define SPT_CLOCK_13 SMP_TIME(13) /*!< 13 LXTAL or FM(T) clocks */
#define SPT_CLOCK_14 SMP_TIME(14) /*!< 14 LXTAL or FM(T) clocks */
#define SPT_CLOCK_15 SMP_TIME(15) /*!< 15 LXTAL or FM(T) clocks */
/* LPDTS flags */
#define LPDTS_FLAG_TSR LPDTS_STAT_TSRF /*!< temperature sensor ready flag */
#define LPDTS_INT_FLAG_EM LPDTS_STAT_EMIF /*!< end of measurement interrupt flag */
#define LPDTS_INT_FLAG_LT LPDTS_STAT_LTIF /*!< low threshold interrupt flag */
#define LPDTS_INT_FLAG_HT LPDTS_STAT_HTIF /*!< high threshold interrupt flag */
#define LPDTS_INT_FLAG_EMA LPDTS_STAT_EMAIF /*!< end of measurement asynchronous interrupt flag */
#define LPDTS_INT_FLAG_LTA LPDTS_STAT_LTAIF /*!< low threshold asynchronous interrupt flag */
#define LPDTS_INT_FLAG_HTA LPDTS_STAT_HTAIF /*!< high threshold asynchronous interrupt flag */
/* LPDTS interrupt enable */
#define LPDTS_INT_EM LPDTS_INTEN_EMIE /*!< end of measurement interrupt enable */
#define LPDTS_INT_LT LPDTS_INTEN_LTIE /*!< low threshold interrupt enable */
#define LPDTS_INT_HT LPDTS_INTEN_HTIE /*!< high threshold interrupt enable */
#define LPDTS_INT_EMA LPDTS_INTEN_EMAIE /*!< end of measurement asynchronous interrupt enable */
#define LPDTS_INT_LTA LPDTS_INTEN_LTAIE /*!< low threshold asynchronous interrupt enable */
#define LPDTS_INT_HTA LPDTS_INTEN_HTAIE /*!< high threshold asynchronous interrupt enable */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check LPDTS the initialization data needed to initialize LPDTS_CFG */
#define NOT_LPDTS_INITIALIZATION_DATA(init_struct) (((((init_struct) -> ref_clock) != REF_PCLK) && (((init_struct) -> ref_clock) != REF_LXTAL)) || \
((((init_struct) -> trigger_input) != NO_HARDWARE_TRIGGER) && (((init_struct) -> trigger_input) != LPDTS_TRG)) || \
((((init_struct) -> sampling_time) != SPT_CLOCK_1) && (((init_struct) -> sampling_time) != SPT_CLOCK_2) && \
(((init_struct) -> sampling_time) != SPT_CLOCK_3) && (((init_struct) -> sampling_time) != SPT_CLOCK_4) && \
(((init_struct) -> sampling_time) != SPT_CLOCK_5) && (((init_struct) -> sampling_time) != SPT_CLOCK_6) && \
(((init_struct) -> sampling_time) != SPT_CLOCK_7) && (((init_struct) -> sampling_time) != SPT_CLOCK_8) && \
(((init_struct) -> sampling_time) != SPT_CLOCK_9) && (((init_struct) -> sampling_time) != SPT_CLOCK_10) && \
(((init_struct) -> sampling_time) != SPT_CLOCK_11) && (((init_struct) -> sampling_time) != SPT_CLOCK_12) && \
(((init_struct) -> sampling_time) != SPT_CLOCK_13) && (((init_struct) -> sampling_time) != SPT_CLOCK_14) && \
(((init_struct) -> sampling_time) != SPT_CLOCK_15)))
/* check LPDTS high threshold value */
#define NOT_LPDTS_HIGH_THRESHOLD(value) (((value) < 0) || ((value) > 65535))
/* check LPDTS low threshold value */
#define NOT_LPDTS_LOW_THRESHOLD(value) (((value) < 0) || ((value) > 65535))
/* check LPDTS reference clock selection */
#define NOT_LPDTS_REF_CLOCK_SOURCE(source) (((source) != REF_PCLK) && ((source) != REF_LXTAL))
/* check LPDTS flag */
#define NOT_LPDTS_FLAG(flag) (((flag) != LPDTS_FLAG_TSR))
/* check LPDTS interrupt */
#define NOT_LPDTS_INTERRUPT(interrupt) (((interrupt) != LPDTS_INT_EM) && ((interrupt) != LPDTS_INT_LT) && \
((interrupt) != LPDTS_INT_HT) && ((interrupt) != LPDTS_INT_EMA) && \
((interrupt) != LPDTS_INT_LTA) && ((interrupt) != LPDTS_INT_HTA))
/* check LPDTS interrupt */
#define NOT_LPDTS_INTERRUPT_FLAG(flag) (((flag) != LPDTS_INT_FLAG_EM) && ((flag) != LPDTS_INT_FLAG_LT) && \
((flag) != LPDTS_INT_FLAG_HT) && ((flag) != LPDTS_INT_FLAG_EMA) && \
((flag) != LPDTS_INT_FLAG_LTA) && ((flag) != LPDTS_INT_FLAG_HTA))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* initialization functions */
/* reset the LPDTS registers */
void lpdts_deinit(void);
/* initialize the parameters of LPDTS struct with the default values */
void lpdts_struct_para_init(lpdts_parameter_struct *init_struct);
/* initialize the LPDTS */
void lpdts_init(lpdts_parameter_struct *init_struct);
/* configuration functions */
/* enable LPDTS temperature sensor */
void lpdts_enable(void);
/* disable LPDTS temperature sensor */
void lpdts_disable(void);
/* enable LPDTS software trigger */
void lpdts_soft_trigger_enable(void);
/* disable LPDTS software trigger */
void lpdts_soft_trigger_disable(void);
/* configure LPDTS high threshold value */
void lpdts_high_threshold_set(int32_t value);
/* configure LPDTS low threshold value */
void lpdts_low_threshold_set(int32_t value);
/* configure LPDTS reference clock selection */
void lpdts_ref_clock_source_config(uint32_t source);
/* get temperature from LPDTS */
int32_t lpdts_temperature_get(void);
/* flag and interrupt functions */
/* get LPDTS flag */
FlagStatus lpdts_flag_get(uint32_t flag);
/* enable LPDTS interrupt */
void lpdts_interrupt_enable(uint32_t interrupt);
/* disable LPDTS interrupt */
void lpdts_interrupt_disable(uint32_t interrupt);
/* get LPDTS interrupt flag */
FlagStatus lpdts_interrupt_flag_get(uint32_t flag);
/* clear the LPDTS interrupt flag */
void lpdts_interrupt_flag_clear(uint32_t flag);
#endif /* GD32H75E_LPDTS_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_mdma.h
+584
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@@ -0,0 +1,584 @@
/*!
\file gd32h75e_mdma.h
\brief definitions for the MDMA
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_MDMA_H
#define GD32H75E_MDMA_H
#include "gd32h75e.h"
/* MDMA definitions */
#define MDMA (MDMA_BASE) /*!< MDMA base address */
/* registers definitions */
#define MDMA_GINTF REG32(MDMA + 0x00000000U) /*!< MDMA global interrupt flag register */
#define MDMA_CHXSTAT0(mdma_chx) REG32(MDMA + 0x00000040U + (0x40U * (mdma_chx))) /*!< MDMA channel x status register 0 */
#define MDMA_CHXSTATC(mdma_chx) REG32(MDMA + 0x00000044U + (0x40U * (mdma_chx))) /*!< MDMA channel x status clear register */
#define MDMA_CHXSTAT1(mdma_chx) REG32(MDMA + 0x00000048U + (0x40U * (mdma_chx))) /*!< MDMA channel x status register 1*/
#define MDMA_CHXCTL0(mdma_chx) REG32(MDMA + 0x0000004CU + (0x40U * (mdma_chx))) /*!< MDMA channel x control register 0 */
#define MDMA_CHXCFG(mdma_chx) REG32(MDMA + 0x00000050U + (0x40U * (mdma_chx))) /*!< MDMA channel x configure register */
#define MDMA_CHXBTCFG(mdma_chx) REG32(MDMA + 0x00000054U + (0x40U * (mdma_chx))) /*!< MDMA channel x block transfer configure register */
#define MDMA_CHXSADDR(mdma_chx) REG32(MDMA + 0x00000058U + (0x40U * (mdma_chx))) /*!< MDMA channel x source address register */
#define MDMA_CHXDADDR(mdma_chx) REG32(MDMA + 0x0000005CU + (0x40U * (mdma_chx))) /*!< MDMA channel x destination address register */
#define MDMA_CHXMBADDRU(mdma_chx) REG32(MDMA + 0x00000060U + (0x40U * (mdma_chx))) /*!< MDMA channel x multi-block address update register */
#define MDMA_CHXLADDR(mdma_chx) REG32(MDMA + 0x00000064U + (0x40U * (mdma_chx))) /*!< MDMA channel x link address register */
#define MDMA_CHXCTL1(mdma_chx) REG32(MDMA + 0x00000068U + (0x40U * (mdma_chx))) /*!< MDMA channel x control register 1 */
#define MDMA_CHXMADDR(mdma_chx) REG32(MDMA + 0x00000070U + (0x40U * (mdma_chx))) /*!< MDMA channel x mask address register */
#define MDMA_CHXMDATA(mdma_chx) REG32(MDMA + 0x00000074U + (0x40U * (mdma_chx))) /*!< MDMA channel x mask data register */
/* bits definitions */
/* MDMA_GINTF */
#define MDMA_GINTF_GIF0 BIT(0) /*!< global interrupt flag of channel 0 */
#define MDMA_GINTF_GIF1 BIT(1) /*!< global interrupt flag of channel 1 */
#define MDMA_GINTF_GIF2 BIT(2) /*!< global interrupt flag of channel 2 */
#define MDMA_GINTF_GIF3 BIT(3) /*!< global interrupt flag of channel 3 */
#define MDMA_GINTF_GIF4 BIT(4) /*!< global interrupt flag of channel 4 */
#define MDMA_GINTF_GIF5 BIT(5) /*!< global interrupt flag of channel 5 */
#define MDMA_GINTF_GIF6 BIT(6) /*!< global interrupt flag of channel 6 */
#define MDMA_GINTF_GIF7 BIT(7) /*!< global interrupt flag of channel 7 */
#define MDMA_GINTF_GIF8 BIT(8) /*!< global interrupt flag of channel 8 */
#define MDMA_GINTF_GIF9 BIT(9) /*!< global interrupt flag of channel 9 */
#define MDMA_GINTF_GIF10 BIT(10) /*!< global interrupt flag of channel 10 */
#define MDMA_GINTF_GIF11 BIT(11) /*!< global interrupt flag of channel 11 */
#define MDMA_GINTF_GIF12 BIT(12) /*!< global interrupt flag of channel 12 */
#define MDMA_GINTF_GIF13 BIT(13) /*!< global interrupt flag of channel 13 */
#define MDMA_GINTF_GIF14 BIT(14) /*!< global interrupt flag of channel 14 */
#define MDMA_GINTF_GIF15 BIT(15) /*!< global interrupt flag of channel 15 */
/* MDMA_CHxSTAT0,x=0..15 */
#define MDMA_CHXSTAT0_ERR BIT(0) /*!< channel x transfer error flag */
#define MDMA_CHXSTAT0_CHTCF BIT(1) /*!< channel x channel transfer complete flag */
#define MDMA_CHXSTAT0_MBTCF BIT(2) /*!< channel x multi-block transfer complete flag */
#define MDMA_CHXSTAT0_BTCF BIT(3) /*!< channel x block transfer complete flag */
#define MDMA_CHXSTAT0_TCF BIT(4) /*!< channel x buffer transfer complete flag */
#define MDMA_CHXSTAT0_REQAF BIT(16) /*!< channel x request active flag */
/* MDMA_CHxSTATC,x=0..15 */
#define MDMA_CHXSTATC_ERRC BIT(0) /*!< channel x transfer error flag clear */
#define MDMA_CHXSTATC_CHTCFC BIT(1) /*!< channel x channel transfer complete flag clear */
#define MDMA_CHXSTATC_MBTCFC BIT(2) /*!< channel x multi-block transfer complete flag clear */
#define MDMA_CHXSTATC_BTCFC BIT(3) /*!< channel x block transfer complete flag clear */
#define MDMA_CHXSTATC_TCFC BIT(4) /*!< channel x buffer transfer complete flag clear */
/* MDMA_CHxSTAT1,x=0..15 */
#define MDMA_CHXSTAT1_ERRADDR BITS(0,6) /*!< transfer error address */
#define MDMA_CHXSTAT1_TERRD BIT(7) /*!< transfer error direction */
#define MDMA_CHXSTAT1_LDTERR BIT(8) /*!< link data transfer error flag in the last transfer of the channel */
#define MDMA_CHXSTAT1_MDTERR BIT(9) /*!< mask data error flag */
#define MDMA_CHXSTAT1_ASERR BIT(10) /*!< address and size error flag */
#define MDMA_CHXSTAT1_BZERR BIT(11) /*!< block size error flag */
/* MDMA_CHxCTL0,x=0..15 */
#define MDMA_CHXCTL0_CHEN BIT(0) /*!< channel enable */
#define MDMA_CHXCTL0_ERRIE BIT(1) /*!< transfer error interrupt enable */
#define MDMA_CHXCTL0_CHTCIE BIT(2) /*!< channel transfer complete interrupt enable */
#define MDMA_CHXCTL0_MBTCIE BIT(3) /*!< multi-block transfer complete interrupt enable */
#define MDMA_CHXCTL0_BTCIE BIT(4) /*!< block transfer complete interrupt enable */
#define MDMA_CHXCTL0_TCIE BIT(5) /*!< buffer transfer complete interrupt enable */
#define MDMA_CHXCTL0_PRIO BITS(6,7) /*!< priority level */
#define MDMA_CHXCTL0_SMODEN BIT(8) /*!< secure mode enable */
#define MDMA_CHXCTL0_BES BIT(12) /*!< byte endianess swapping in half word */
#define MDMA_CHXCTL0_HWES BIT(13) /*!< half word endianess swapping in word */
#define MDMA_CHXCTL0_WES BIT(14) /*!< word endianess swapping in double word */
#define MDMA_CHXCTL0_SWREQ BIT(16) /*!< software request */
/* MDMA_CHxCFG,x=0..15 */
#define MDMA_CHXCFG_SIMOD BITS(0,1) /*!< source increment mode */
#define MDMA_CHXCFG_DIMOD BITS(2,3) /*!< destination increment mode */
#define MDMA_CHXCFG_SWIDTH BITS(4,5) /*!< data size of source */
#define MDMA_CHXCFG_DWIDTH BITS(6,7) /*!< data size of destination */
#define MDMA_CHXCFG_SIOS BITS(8,9) /*!< offset size of source increment */
#define MDMA_CHXCFG_DIOS BITS(10,11) /*!< offset size of destination increment */
#define MDMA_CHXCFG_SBURST BITS(12,14) /*!< transfer burst type of source */
#define MDMA_CHXCFG_DBURST BITS(15,17) /*!< transfer burst type of destination */
#define MDMA_CHXCFG_BTLEN BITS(18,24) /*!< buffer transfer length */
#define MDMA_CHXCFG_PKEN BIT(25) /*!< pack enable */
#define MDMA_CHXCFG_PAMOD BITS(26,27) /*!< padding and alignement mode */
#define MDMA_CHXCFG_TRIGMOD BITS(28,29) /*!< trigger mode */
#define MDMA_CHXCFG_SWREQMOD BIT(30) /*!< software request mode */
#define MDMA_CHXCFG_BWMOD BIT(31) /*!< bufferable write mode */
/* MDMA_CHxBTCFG,x=0..15 */
#define MDMA_CHXBTCFG_TBNUM BITS(0,16) /*!< transfer byte number in block */
#define MDMA_CHXBTCFG_SADDRUM BIT(18) /*!< multi-block source address update mode */
#define MDMA_CHXBTCFG_DADDRUM BIT(19) /*!< multi-block destination address update mode */
#define MDMA_CHXBTCFG_BRNUM BITS(20,31) /*!< multi-block number */
/* MDMA_CHxSADDR,x=0..15 */
#define MDMA_CHXSADDR_SADDR BITS(0,31) /*!< source address */
/* MDMA_CHxDADDR,x=0..15 */
#define MDMA_CHXDADDR_DADDR BITS(0,31) /*!< destination address */
/* MDMA_CHxMBADDRU,x=0..15 */
#define MDMA_CHXMBADDRU_SADDRUV BITS(0,15) /*!< source address update value */
#define MDMA_CHXMBADDRU_DADDRUV BITS(16,31) /*!< destination address update value */
/* MDMA_CHxLADDR,x=0..15 */
#define MDMA_CHXLADDR_LADDR BITS(0,31) /*!< link address */
/* MDMA_CHxCTL1,x=0..15 */
#define MDMA_CHXCTL1_TRIGSEL BITS(0,5) /*!< trigger select */
#define MDMA_CHXCTL1_SBSEL BIT(16) /*!< source bus select */
#define MDMA_CHXCTL1_DBSEL BIT(17) /*!< destination bus select */
/* MDMA_CHxMADDR,x=0..15 */
#define MDMA_CHXMADDR_MADDR BITS(0,31) /*!< mask address */
/* MDMA_CHxMDATA,x=0..15 */
#define MDMA_CHXMDATA_MDATA BITS(0,31) /*!< mask data */
/* constants definitions */
/* MDMA configuration structure definition */
typedef struct {
uint32_t request; /*!< specifies the MDMA request */
uint32_t trans_trig_mode; /*!< specifies the trigger transfer mode */
uint32_t priority; /*!< specifies the software priority for the MDMA channelx */
uint32_t endianness; /*!< specifies if the MDMA transactions preserve the little endianness */
uint32_t source_inc; /*!< specifies the source increment mode */
uint32_t dest_inc; /*!< specifies the destination increment mode */
uint32_t source_data_size; /*!< specifies the source data size */
uint32_t dest_data_size; /*!< specifies the destination data size */
uint32_t data_alignment; /*!< specifies the source to destination memory data packing/padding mode */
uint32_t buff_trans_len; /*!< specifies the buffer transfer length (number of bytes) */
uint32_t source_burst; /*!< specifies the burst transfer configuration for the source memory transfers */
uint32_t dest_burst; /*!< specifies the burst transfer configuration for the destination memory transfers */
uint32_t mask_addr; /*!< mask address */
uint32_t mask_data; /*!< mask data */
uint32_t source_addr; /*!< specifies the source address */
uint32_t dest_addr; /*!< specifies the destination address */
uint32_t tbytes_num_in_block; /*!< specifies the transfer bytes number in a buffer or block transfer */
uint32_t source_bus; /*!< specifies the source bus */
uint32_t dest_bus; /*!< specifies the destination bus */
uint32_t bufferable_write_mode; /*!< specifies the bufferable write mode */
} mdma_parameter_struct;
/* MDMA address update direction */
typedef enum {
UPDATE_DIR_INCREASE = 0, /*!< MDMA address update increase */
UPDATE_DIR_DECREASE = 1, /*!< MDMA address update decrease */
} mdma_add_update_dir_enum;
/* MDMA multi block transfer configuration structure definition */
typedef struct {
uint32_t block_num; /*!< multi-block number */
uint16_t saddr_update_val; /*!< source address update value */
uint16_t dstaddr_update_val; /*!< destination address update value */
mdma_add_update_dir_enum saddr_update_dir; /*!< source address update direction */
mdma_add_update_dir_enum dstaddr_update_dir; /*!< destination address update direction */
} mdma_multi_block_parameter_struct;
/* MDMA link node configuration structure definition */
typedef struct {
__IO uint32_t chxcfg_reg; /*!< channel x configure register */
__IO uint32_t chxbtcfg_reg; /*!< channel x block transfer configure register */
__IO uint32_t chxsaddr_reg; /*!< channel x source address register */
__IO uint32_t chxdaddr_reg; /*!< channel x destination address register */
__IO uint32_t chxmbaddru_reg; /*!< channel x multi-block address update register */
__IO uint32_t chxladdr_reg; /*!< channel x link address register */
__IO uint32_t chxctl1_reg; /*!< channel x control register 1 */
__IO uint32_t reserved; /*!< channel x reserved register */
__IO uint32_t chxmaddr_reg; /*!< channel x mask address register */
__IO uint32_t chxmdata_reg; /*!< channel x mask data register */
} mdma_link_node_parameter_struct;
/* MDMA channel select */
typedef enum {
MDMA_CH0 = 0, /*!< MDMA channel 0 */
MDMA_CH1, /*!< MDMA channel 1 */
MDMA_CH2, /*!< MDMA channel 2 */
MDMA_CH3, /*!< MDMA channel 3 */
MDMA_CH4, /*!< MDMA channel 4 */
MDMA_CH5, /*!< MDMA channel 5 */
MDMA_CH6, /*!< MDMA channel 6 */
MDMA_CH7, /*!< MDMA channel 7 */
MDMA_CH8, /*!< MDMA channel 8 */
MDMA_CH9, /*!< MDMA channel 9 */
MDMA_CH10, /*!< MDMA channel 10 */
MDMA_CH11, /*!< MDMA channel 11 */
MDMA_CH12, /*!< MDMA channel 12 */
MDMA_CH13, /*!< MDMA channel 13 */
MDMA_CH14, /*!< MDMA channel 14 */
MDMA_CH15 /*!< MDMA channel 15 */
} mdma_channel_enum;
/* MDMA request selection */
#define CHXCTL1_TRIGSEL(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< trigger select */
#define MDMA_REQUEST_DMA0_CH0_FTFIF CHXCTL1_TRIGSEL(0) /*!< MDMA hardware request is DMA0 channel 0 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH1_FTFIF CHXCTL1_TRIGSEL(1) /*!< MDMA hardware request is DMA0 channel 1 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH2_FTFIF CHXCTL1_TRIGSEL(2) /*!< MDMA hardware request is DMA0 channel 2 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH3_FTFIF CHXCTL1_TRIGSEL(3) /*!< MDMA hardware request is DMA0 channel 3 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH4_FTFIF CHXCTL1_TRIGSEL(4) /*!< MDMA hardware request is DMA0 channel 4 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH5_FTFIF CHXCTL1_TRIGSEL(5) /*!< MDMA hardware request is DMA0 channel 5 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH6_FTFIF CHXCTL1_TRIGSEL(6) /*!< MDMA hardware request is DMA0 channel 6 transfer complete flag */
#define MDMA_REQUEST_DMA0_CH7_FTFIF CHXCTL1_TRIGSEL(7) /*!< MDMA hardware request is DMA0 channel 7 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH0_FTFIF CHXCTL1_TRIGSEL(8) /*!< MDMA hardware request is DMA1 channel 0 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH1_FTFIF CHXCTL1_TRIGSEL(9) /*!< MDMA hardware request is DMA1 channel 1 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH2_FTFIF CHXCTL1_TRIGSEL(10) /*!< MDMA hardware request is DMA1 channel 2 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH3_FTFIF CHXCTL1_TRIGSEL(11) /*!< MDMA hardware request is DMA1 channel 3 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH4_FTFIF CHXCTL1_TRIGSEL(12) /*!< MDMA hardware request is DMA1 channel 4 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH5_FTFIF CHXCTL1_TRIGSEL(13) /*!< MDMA hardware request is DMA1 channel 5 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH6_FTFIF CHXCTL1_TRIGSEL(14) /*!< MDMA hardware request is DMA1 channel 6 transfer complete flag */
#define MDMA_REQUEST_DMA1_CH7_FTFIF CHXCTL1_TRIGSEL(15) /*!< MDMA hardware request is DMA1 channel 7 transfer complete flag */
#define MDMA_REQUEST_OSPI0_FT CHXCTL1_TRIGSEL(22) /*!< MDMA hardware request is OSPI0_FT */
#define MDMA_REQUEST_OSPI0_TC CHXCTL1_TRIGSEL(23) /*!< MDMA hardware request is OSPI0_TC */
#define MDMA_REQUEST_OSPI1_FT CHXCTL1_TRIGSEL(32) /*!< MDMA hardware request is OSPI1_FT */
#define MDMA_REQUEST_OSPI1_TC CHXCTL1_TRIGSEL(33) /*!< MDMA hardware request is OSPI1_TC */
#define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA software request */
/* MDMA transfer trigger mode */
#define CHCFG_TRIGMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28U)) /*!< trigger mode */
#define MDMA_BUFFER_TRANSFER CHCFG_TRIGMOD(0) /*!< software request or hardware request triggers a buffer transfer */
#define MDMA_BLOCK_TRANSFER CHCFG_TRIGMOD(1) /*!< software request or hardware request triggers a block transfer */
#define MDMA_MULTI_BLOCK_TRANSFER CHCFG_TRIGMOD(2) /*!< software request or hardware request triggers a multi-block transfer */
#define MDMA_COMPLETE_TRANSFER CHCFG_TRIGMOD(3) /*!< software request or hardware request triggers a complete data transfer (for example, link mode) */
/* channel priority level */
#define CHCTL0_PRIO(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U))
#define MDMA_PRIORITY_LOW CHCTL0_PRIO(0) /*!< priority level: low */
#define MDMA_PRIORITY_MEDIUM CHCTL0_PRIO(1) /*!< priority level: medium */
#define MDMA_PRIORITY_HIGH CHCTL0_PRIO(2) /*!< priority level: high */
#define MDMA_PRIORITY_ULTRA_HIGH CHCTL0_PRIO(3) /*!< priority level: very high */
/* MDMA endianness */
#define MDMA_LITTLE_ENDIANNESS ((uint32_t)0x00000000U) /*!< little endianness */
#define MDMA_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CHXCTL0_BES) /*!< exchange the order of the bytes in a half-word */
#define MDMA_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CHXCTL0_HWES) /*!< exchange the order of the half-words in a word */
#define MDMA_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CHXCTL0_WES) /*!< exchange the order of the words in a double word */
/* MDMA source address increased/decreased mode */
#define CHCFG_SIMOD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0U)) /*!< source increased/decreased mode */
#define CHCFG_SIOS(regval) (BITS(8,9) & ((uint32_t)(regval) << 8U)) /*!< offset size of source increment */
#define MDMA_SOURCE_INCREASE_DISABLE CHCFG_SIMOD(0) /*!< no increment */
#define MDMA_SOURCE_INCREASE_8BIT (CHCFG_SIMOD(2) | CHCFG_SIOS(0)) /*!< source address is increased by 8-bit */
#define MDMA_SOURCE_INCREASE_16BIT (CHCFG_SIMOD(2) | CHCFG_SIOS(1)) /*!< source address is increased by 16-bit */
#define MDMA_SOURCE_INCREASE_32BIT (CHCFG_SIMOD(2) | CHCFG_SIOS(2)) /*!< source address is increased by 32-bit */
#define MDMA_SOURCE_INCREASE_64BIT (CHCFG_SIMOD(2) | CHCFG_SIOS(3)) /*!< source address is increased by 64-bit */
#define MDMA_SOURCE_DECREASE_8BIT (CHCFG_SIMOD(3) | CHCFG_SIOS(0)) /*!< source address is decreased by 8-bit */
#define MDMA_SOURCE_DECREASE_16BIT (CHCFG_SIMOD(3) | CHCFG_SIOS(1)) /*!< source address is decreased by 16-bit */
#define MDMA_SOURCE_DECREASE_32BIT (CHCFG_SIMOD(3) | CHCFG_SIOS(2)) /*!< source address is decreased by 32-bit */
#define MDMA_SOURCE_DECREASE_64BIT (CHCFG_SIMOD(3) | CHCFG_SIOS(3)) /*!< source address is decreased by 64-bit */
/* MDMA destination addess increased/decreased mode*/
#define CHCFG_DIMOD(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U)) /*!< destination increased/decreased mode */
#define CHCFG_DIOS(regval) (BITS(10,11) & ((uint32_t)(regval) << 10U)) /*!< offset size of destination increment */
#define MDMA_DESTINATION_INCREASE_DISABLE CHCFG_DIMOD(0) /*!< no increment */
#define MDMA_DESTINATION_INCREASE_8BIT (CHCFG_DIMOD(2) | CHCFG_DIOS(0)) /*!< destination address is increased by 8-bit */
#define MDMA_DESTINATION_INCREASE_16BIT (CHCFG_DIMOD(2) | CHCFG_DIOS(1)) /*!< destination address is increased by 16-bit */
#define MDMA_DESTINATION_INCREASE_32BIT (CHCFG_DIMOD(2) | CHCFG_DIOS(2)) /*!< destination address is increased by 32-bit */
#define MDMA_DESTINATION_INCREASE_64BIT (CHCFG_DIMOD(2) | CHCFG_DIOS(3)) /*!< destination address is increased by 64-bit */
#define MDMA_DESTINATION_DECREASE_8BIT (CHCFG_DIMOD(3) | CHCFG_DIOS(0)) /*!< destination address is decreased by 8-bit */
#define MDMA_DESTINATION_DECREASE_16BIT (CHCFG_DIMOD(3) | CHCFG_DIOS(1)) /*!< destination address is decreased by 16-bit */
#define MDMA_DESTINATION_DECREASE_32BIT (CHCFG_DIMOD(3) | CHCFG_DIOS(2)) /*!< destination address is decreased by 32-bit */
#define MDMA_DESTINATION_DECREASE_64BIT (CHCFG_DIMOD(3) | CHCFG_DIOS(3)) /*!< destination address is decreased by 64-bit */
/* MDMA source data size */
#define CHCFG_SWIDTH(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U)) /*!< data size of source */
#define MDMA_SOURCE_DATASIZE_8BIT CHCFG_SWIDTH(0) /*!< data size of source is 8-bit */
#define MDMA_SOURCE_DATASIZE_16BIT CHCFG_SWIDTH(1) /*!< data size of source is 16-bit */
#define MDMA_SOURCE_DATASIZE_32BIT CHCFG_SWIDTH(2) /*!< data size of source is 32-bit */
#define MDMA_SOURCE_DATASIZE_64BIT CHCFG_SWIDTH(3) /*!< data size of source is 64-bit */
/* MDMA destination data size */
#define CHCFG_DWIDTH(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) /*!< data size of destination */
#define MDMA_DESTINATION_DATASIZE_8BIT CHCFG_DWIDTH(0) /*!< data size of destination is 8-bit */
#define MDMA_DESTINATION_DATASIZE_16BIT CHCFG_DWIDTH(1) /*!< data size of destination is 16-bit */
#define MDMA_DESTINATION_DATASIZE_32BIT CHCFG_DWIDTH(2) /*!< data size of destination is 32-bit */
#define MDMA_DESTINATION_DATASIZE_64BIT CHCFG_DWIDTH(3) /*!< data size of destination is 64-bit */
/* MDMA data alignment */
#define CHCFG_PAMOD(regval) (BITS(26,27) & ((uint32_t)(regval) << 26U)) /*!< padding and alignement mode */
#define MDMA_DATAALIGN_PKEN ((uint32_t)MDMA_CHXCFG_PKEN) /*!< pack/unpack the source data to match the destination data size */
#define MDMA_DATAALIGN_RIGHT CHCFG_PAMOD(0) /*!< right aligned, padded with 0s (default) */
#define MDMA_DATAALIGN_RIGHT_SIGNED CHCFG_PAMOD(1) /*!< right aligned with sign extended, note: this mode is allowed only if the source data size is smaller than destination data size */
#define MDMA_DATAALIGN_LEFT CHCFG_PAMOD(2) /*!< left aligned, padded with 0s in low bytes position when source data size smaller than destination data size, and only high byte of source is written when source data size larger than destination data size */
/* MDMA source burst */
#define CHCFG_SBURST(regval) (BITS(12,14) & ((uint32_t)(regval) << 12U)) /*!< transfer burst type of source */
#define MDMA_SOURCE_BURST_SINGLE CHCFG_SBURST(0) /*!< single burst */
#define MDMA_SOURCE_BURST_2BEATS CHCFG_SBURST(1) /*!< 2-beat incrementing burst */
#define MDMA_SOURCE_BURST_4BEATS CHCFG_SBURST(2) /*!< 4-beat incrementing burst */
#define MDMA_SOURCE_BURST_8BEATS CHCFG_SBURST(3) /*!< 8-beat incrementing burst */
#define MDMA_SOURCE_BURST_16BEATS CHCFG_SBURST(4) /*!< 16-beat incrementing burst */
#define MDMA_SOURCE_BURST_32BEATS CHCFG_SBURST(5) /*!< 32-beat incrementing burst */
#define MDMA_SOURCE_BURST_64BEATS CHCFG_SBURST(6) /*!< 64-beat incrementing burst */
#define MDMA_SOURCE_BURST_128BEATS CHCFG_SBURST(7) /*!< 128-beat incrementing burst */
/* MDMA destination burst */
#define CHCFG_DBURST(regval) (BITS(15,17) & ((uint32_t)(regval) << 15U)) /*!< transfer burst type of destination */
#define MDMA_DESTINATION_BURST_SINGLE CHCFG_DBURST(0) /*!< single burst */
#define MDMA_DESTINATION_BURST_2BEATS CHCFG_DBURST(1) /*!< 2-beat incrementing burst */
#define MDMA_DESTINATION_BURST_4BEATS CHCFG_DBURST(2) /*!< 4-beat incrementing burst */
#define MDMA_DESTINATION_BURST_8BEATS CHCFG_DBURST(3) /*!< 8-beat incrementing burst */
#define MDMA_DESTINATION_BURST_16BEATS CHCFG_DBURST(4) /*!< 16-beat incrementing burst */
#define MDMA_DESTINATION_BURST_32BEATS CHCFG_DBURST(5) /*!< 32-beat incrementing burst */
#define MDMA_DESTINATION_BURST_64BEATS CHCFG_DBURST(6) /*!< 64-beat incrementing burst */
#define MDMA_DESTINATION_BURST_128BEATS CHCFG_DBURST(7) /*!< 128-beat incrementing burst */
/* source bus select */
#define MDMA_SOURCE_AXI ((uint32_t)0x00000000U) /*!< source bus of channel x is the system bus or AXI bus */
#define MDMA_SOURCE_AHB_TCM MDMA_CHXCTL1_SBSEL /*!< source bus of channel x is AHB bus or TCM */
/* destination bus select */
#define MDMA_DESTINATION_AXI ((uint32_t)0x00000000U) /*!< destination bus of channel x is the system bus or AXI bus */
#define MDMA_DESTINATION_AHB_TCM MDMA_CHXCTL1_DBSEL /*!< destination bus of channel x is AHB bus or TCM */
/* MDMA access error direction */
#define MDMA_READ_ERROR ((uint32_t)0x00000000U) /*!< read access error */
#define MDMA_WRITE_ERROR MDMA_CHXSTAT1_TERRD /*!< write access error */
/* MDMA bufferable write mode */
#define MDMA_BUFFERABLE_WRITE_DISABLE ((uint32_t)0x00000000U) /*!< diable bufferable write mode */
#define MDMA_BUFFERABLE_WRITE_ENABLE MDMA_CHXCFG_BWMOD /*!< enable bufferable write mode */
/* MDMA flags */
#define STAT1_FLAG BIT(31) /*!< flag to indicate that flag is in STAT1 register */
#define MDMA_FLAG_ERR MDMA_CHXSTAT0_ERR /*!< channel x transfer error flag */
#define MDMA_FLAG_CHTCF MDMA_CHXSTAT0_CHTCF /*!< channel x channel transfer complete flag */
#define MDMA_FLAG_MBTCF MDMA_CHXSTAT0_MBTCF /*!< channel x multi-block transfer complete flag */
#define MDMA_FLAG_BTCF MDMA_CHXSTAT0_BTCF /*!< channel x block transfer complete flag */
#define MDMA_FLAG_TCF MDMA_CHXSTAT0_TCF /*!< channel x buffer transfer complete flag */
#define MDMA_FLAG_REQAF MDMA_CHXSTAT0_REQAF /*!< channel x request active flag */
#define MDMA_FLAG_LDTERR (MDMA_CHXSTAT1_LDTERR | STAT1_FLAG) /*!< link data transfer error flag in the last transfer of the channel */
#define MDMA_FLAG_MDTERR (MDMA_CHXSTAT1_MDTERR | STAT1_FLAG) /*!< mask data error flag */
#define MDMA_FLAG_ASERR (MDMA_CHXSTAT1_ASERR | STAT1_FLAG) /*!< address and size error flag */
#define MDMA_FLAG_BZERR (MDMA_CHXSTAT1_BZERR | STAT1_FLAG) /*!< block size error flag */
/* MDMA interrupt */
#define MDMA_INT_ERR MDMA_CHXCTL0_ERRIE /*!< transfer error interrupt */
#define MDMA_INT_CHTC MDMA_CHXCTL0_CHTCIE /*!< channel transfer complete interrupt */
#define MDMA_INT_MBTC MDMA_CHXCTL0_MBTCIE /*!< multi-block transfer complete interrupt */
#define MDMA_INT_BTC MDMA_CHXCTL0_BTCIE /*!< block transfer complete interrupt */
#define MDMA_INT_TC MDMA_CHXCTL0_TCIE /*!< buffer transfer complete interrupt */
/* MDMA interrupt flags */
#define MDMA_INT_FLAG_ERR MDMA_CHXSTAT0_ERR /*!< transfer error interrupt flag */
#define MDMA_INT_FLAG_CHTCF MDMA_CHXSTAT0_CHTCF /*!< channel transfer complete interrupt flag */
#define MDMA_INT_FLAG_MBTCF MDMA_CHXSTAT0_MBTCF /*!< multi-block transfer complete interrupt flag */
#define MDMA_INT_FLAG_BTCF MDMA_CHXSTAT0_BTCF /*!< block transfer complete interrupt flag */
#define MDMA_INT_FLAG_TCF MDMA_CHXSTAT0_TCF /*!< buffer transfer complete interrupt flag */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check MDMA request */
#define MDMA_REQUEST_HIGH MDMA_REQUEST_OSPI1_TC
#define NOT_MDMA_REQUEST(request) ((MDMA_REQUEST_HIGH < (request)) && (MDMA_REQUEST_SW != (request)))
/* check MDMA trigger transfer mode */
#define NOT_MDMA_TRANS_TRIG(trans_trig_mode) ((MDMA_BUFFER_TRANSFER != (trans_trig_mode)) && (MDMA_BLOCK_TRANSFER != (trans_trig_mode)) && \
(MDMA_MULTI_BLOCK_TRANSFER != (trans_trig_mode)) && (MDMA_COMPLETE_TRANSFER != (trans_trig_mode)))
/* check MDMA software priority */
#define NOT_MDMA_PRIORITY(priority) ((MDMA_PRIORITY_LOW != (priority)) && (MDMA_PRIORITY_MEDIUM != (priority)) && \
(MDMA_PRIORITY_HIGH != (priority)) && (MDMA_PRIORITY_ULTRA_HIGH != (priority)))
/* check MDMA endianness of transactions preserve */
#define NOT_MDMA_ENDIANNESS(endianness) ((MDMA_LITTLE_ENDIANNESS != (endianness)) && (MDMA_BYTE_ENDIANNESS_EXCHANGE != (endianness)) && \
(MDMA_HALFWORD_ENDIANNESS_EXCHANGE != (endianness)) && (MDMA_WORD_ENDIANNESS_EXCHANGE != (endianness)))
/* check MDMA source increment mode */
#define NOT_MDMA_SOURCE_INC(source_inc) ((MDMA_SOURCE_INCREASE_DISABLE != (source_inc)) && (MDMA_SOURCE_INCREASE_8BIT != (source_inc)) && \
(MDMA_SOURCE_INCREASE_16BIT != (source_inc)) && (MDMA_SOURCE_INCREASE_32BIT != (source_inc)) && \
(MDMA_SOURCE_INCREASE_64BIT != (source_inc)) && (MDMA_SOURCE_DECREASE_8BIT != (source_inc)) && \
(MDMA_SOURCE_DECREASE_16BIT != (source_inc)) && (MDMA_SOURCE_DECREASE_32BIT != (source_inc)) && \
(MDMA_SOURCE_DECREASE_64BIT != (source_inc)))
/* check MDMA destination increment mode */
#define NOT_MDMA_DEST_INC(dest_inc) ((MDMA_DESTINATION_INCREASE_DISABLE != (dest_inc)) && (MDMA_DESTINATION_INCREASE_8BIT != (dest_inc)) && \
(MDMA_DESTINATION_INCREASE_16BIT != (dest_inc)) && (MDMA_DESTINATION_INCREASE_32BIT != (dest_inc)) && \
(MDMA_DESTINATION_INCREASE_64BIT != (dest_inc)) && (MDMA_DESTINATION_DECREASE_8BIT != (dest_inc)) && \
(MDMA_DESTINATION_DECREASE_16BIT != (dest_inc)) && (MDMA_DESTINATION_DECREASE_32BIT != (dest_inc)) && \
(MDMA_DESTINATION_DECREASE_64BIT != (dest_inc)))
/* check MDMA source data size */
#define NOT_MDMA_SOURCE_DATA_SIZE(source_data_size) ((MDMA_SOURCE_DATASIZE_8BIT != (source_data_size)) && (MDMA_SOURCE_DATASIZE_16BIT != (source_data_size)) && \
(MDMA_SOURCE_DATASIZE_32BIT != (source_data_size)) && (MDMA_SOURCE_DATASIZE_64BIT != (source_data_size)))
/* check MDMA destination data size */
#define NOT_MDMA_DEST_DATA_SIZE(dest_data_size) ((MDMA_DESTINATION_DATASIZE_8BIT != (dest_data_size)) && (MDMA_DESTINATION_DATASIZE_16BIT != (dest_data_size)) && \
(MDMA_DESTINATION_DATASIZE_32BIT != (dest_data_size)) && (MDMA_DESTINATION_DATASIZE_64BIT != (dest_data_size)))
/* check MDMA source to destination memory data packing/padding mode */
#define NOT_MDMA_DATA_ALIGN(data_alignment) ((MDMA_DATAALIGN_PKEN != (data_alignment)) && (MDMA_DATAALIGN_RIGHT != (data_alignment)) && \
(MDMA_DATAALIGN_RIGHT_SIGNED != (data_alignment)) && (MDMA_DATAALIGN_LEFT != (data_alignment)))
/* check MDMA buffer transfer length */
#define NOT_MDMA_BUFF_TRANS_LEN_HIGH 127U
#define NOT_MDMA_BUFF_TRANS_LEN(buff_trans_len) (NOT_MDMA_BUFF_TRANS_LEN_HIGH < (buff_trans_len))
/* check MDMA burst transfer configuration for the source memory transfers */
#define NOT_MDMA_SOURCE_BURST(source_burst) ((MDMA_SOURCE_BURST_SINGLE != (source_burst)) && (MDMA_SOURCE_BURST_2BEATS != (source_burst)) && \
(MDMA_SOURCE_BURST_4BEATS != (source_burst)) && (MDMA_SOURCE_BURST_8BEATS != (source_burst)) && \
(MDMA_SOURCE_BURST_16BEATS != (source_burst)) && (MDMA_SOURCE_BURST_32BEATS != (source_burst)) && \
(MDMA_SOURCE_BURST_64BEATS != (source_burst)) && (MDMA_SOURCE_BURST_128BEATS != (source_burst)))
/* check MDMA burst transfer configuration for the destination memory transfers */
#define NOT_MDMA_DEST_BURST(dest_burst) ((MDMA_DESTINATION_BURST_SINGLE != (dest_burst)) && (MDMA_DESTINATION_BURST_2BEATS != (dest_burst)) && \
(MDMA_DESTINATION_BURST_4BEATS != (dest_burst)) && (MDMA_DESTINATION_BURST_8BEATS != (dest_burst)) && \
(MDMA_DESTINATION_BURST_16BEATS != (dest_burst)) && (MDMA_DESTINATION_BURST_32BEATS != (dest_burst)) && \
(MDMA_DESTINATION_BURST_64BEATS != (dest_burst)) && (MDMA_DESTINATION_BURST_128BEATS != (dest_burst)))
/* check MDMA transfer bytes number of buffer/block transfer mode */
#define NOT_MDMA_TBYTES_NUM_HIGH 0x0001FFFFU
#define NOT_MDMA_TBYTES_NUM(tbytes_num) (NOT_MDMA_TBYTES_NUM_HIGH < (tbytes_num))
/* check MDMA source bus */
#define NOT_MDMA_SOURCE_BUS(source_bus) ((MDMA_SOURCE_AXI != (source_bus)) && (MDMA_SOURCE_AHB_TCM != (source_bus)))
/* check MDMA destination bus */
#define NOT_MDMA_DEST_BUS(dest_bus) ((MDMA_DESTINATION_AXI != (dest_bus)) && (MDMA_DESTINATION_AHB_TCM != (dest_bus)))
/* check MDMA bufferable write mode */
#define NOT_MDMA_BUFFERABLE_WRITE(bufferable_write_mode) ((MDMA_BUFFERABLE_WRITE_ENABLE != (bufferable_write_mode)) && (MDMA_BUFFERABLE_WRITE_DISABLE != (bufferable_write_mode)))
/* check MDMA transfer bytes number of buffer/block transfer mode */
#define NOT_MDMA_TBNUM_OF_BLOCK_TRANS_MODE_HIGH 0x10000U
#define NOT_MDMA_TBNUM_OF_BLOCK_TRANS_MODE(tbnum) (NOT_MDMA_TBNUM_OF_BLOCK_TRANS_MODE_HIGH < (tbnum))
/* check MDMA transfer bytes number of multi block transfer mode */
#define NOT_MDMA_TBNUM_OF_MULTI_BLOCK_TRANS_MODE_HIGH 0xFFFU
#define NOT_MDMA_TBNUM_OF_MULTI_BLOCK_TRANS_MODE(tbnum) (NOT_MDMA_TBNUM_OF_MULTI_BLOCK_TRANS_MODE_HIGH < (tbnum))
/* check MDMA multi block number */
#define NOT_MDMA_MULTI_BLOCK_NUM_HIGH 0xFFFU
#define NOT_MDMA_MULTI_BLOCK_NUM(block_num) (NOT_MDMA_MULTI_BLOCK_NUM_HIGH < (block_num))
/* check MDMA flag */
#define NOT_MDMA_FLAG(flag) ((MDMA_FLAG_ERR != (flag)) && (MDMA_FLAG_CHTCF != (flag)) && \
(MDMA_FLAG_MBTCF != (flag)) && (MDMA_FLAG_BTCF != (flag)) && \
(MDMA_FLAG_TCF != (flag)) && (MDMA_FLAG_REQAF != (flag)) && \
(MDMA_FLAG_LDTERR != (flag)) && (MDMA_FLAG_MDTERR != (flag)) && \
(MDMA_FLAG_ASERR != (flag)) && (MDMA_FLAG_BZERR != (flag)))
/* check MDMA clear flag */
#define NOT_MDMA_CLEAR_FLAG(flag) ((MDMA_FLAG_ERR != (flag)) && (MDMA_FLAG_CHTCF != (flag)) && \
(MDMA_FLAG_MBTCF != (flag)) && (MDMA_FLAG_BTCF != (flag)) && \
(MDMA_FLAG_TCF != (flag)) && (MDMA_FLAG_LDTERR != (flag))&& \
(MDMA_FLAG_MDTERR != (flag)) && (MDMA_FLAG_ASERR != (flag))&& \
(MDMA_FLAG_BZERR != (flag)))
/* check MDMA interrupt */
#define NOT_MDMA_INT(interrupt) ((MDMA_INT_ERR != (interrupt)) && (MDMA_INT_CHTC != (interrupt)) && \
(MDMA_INT_MBTC != (interrupt)) && (MDMA_INT_BTC != (interrupt)) && \
(MDMA_INT_TC != (interrupt)))
/* check MDMA interrupt flag */
#define NOT_MDMA_INT_FLAG(int_flag) ((MDMA_INT_FLAG_ERR != (int_flag)) && (MDMA_INT_FLAG_CHTCF != (int_flag)) && \
(MDMA_INT_FLAG_MBTCF != (int_flag)) && (MDMA_INT_FLAG_BTCF != (int_flag)) && \
(MDMA_INT_FLAG_TCF != (int_flag)))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* MDMA deinitialization and initialization functions */
/* deinitialize MDMA */
void mdma_deinit(void);
/* deinitialize MDMA registers of a channel */
void mdma_channel_deinit(mdma_channel_enum channelx);
/* initialize the MDMA parameters struct with the default values */
void mdma_para_struct_init(mdma_parameter_struct *init_struct);
/* initialize the MDMA multi block transfer mode parameters struct with the default values */
void mdma_multi_block_para_struct_init(mdma_multi_block_parameter_struct *block_init_struct);
/* initialize the MDMA link node configuration struct with the default values */
void mdma_link_node_para_struct_init(mdma_link_node_parameter_struct *node);
/* initialize MDMA channel with MDMA parameter structure */
void mdma_init(mdma_channel_enum channelx, mdma_parameter_struct *init_struct);
/* configure MDMA buffer/block transfer mode */
void mdma_buffer_block_mode_config(mdma_channel_enum channelx, uint32_t saddr, uint32_t daddr, uint32_t tbnum);
/* configure MDMA multi block transfer mode */
void mdma_multi_block_mode_config(mdma_channel_enum channelx, uint32_t tbnum, mdma_multi_block_parameter_struct *block_init_struct);
/* create MDMA link list node */
void mdma_node_create(mdma_link_node_parameter_struct *node, mdma_multi_block_parameter_struct *block_init_struct, mdma_parameter_struct *init_struct);
/* MDMA add node to link list */
void mdma_node_add(mdma_link_node_parameter_struct *pre_node, mdma_link_node_parameter_struct *new_node);
/* MDMA disconnect link list node */
ErrStatus mdma_node_delete(mdma_link_node_parameter_struct *pre_node, mdma_link_node_parameter_struct *unused_node);
/* MDMA configuration functions */
/* configure MDMA destination base address */
void mdma_destination_address_config(mdma_channel_enum channelx, uint32_t address);
/* configure MDMA source base address */
void mdma_source_address_config(mdma_channel_enum channelx, uint32_t address);
/* configure MDMA destination bus */
void mdma_destination_bus_config(mdma_channel_enum channelx, uint32_t bus);
/* configure MDMA source bus */
void mdma_source_bus_config(mdma_channel_enum channelx, uint32_t bus);
/* configure priority level of MDMA channel */
void mdma_priority_config(mdma_channel_enum channelx, uint32_t priority);
/* configure endianness of MDMA channel */
void mdma_endianness_config(mdma_channel_enum channelx, uint32_t endianness);
/* configure data alignment of MDMA channel */
void mdma_alignment_config(mdma_channel_enum channelx, uint32_t alignment);
/* configure transfer burst beats of source */
void mdma_source_burst_beats_config(mdma_channel_enum channelx, uint32_t sbeat);
/* configure transfer burst beats of destination */
void mdma_destination_burst_beats_config(mdma_channel_enum channelx, uint32_t dbeat);
/* configure data size of source */
void mdma_source_width_config(mdma_channel_enum channelx, uint32_t swidth);
/* configure data size of destination */
void mdma_destination_width_config(mdma_channel_enum channelx, uint32_t dwidth);
/* configure source address increment mode */
void mdma_source_increment_config(mdma_channel_enum channelx, uint32_t sinc);
/* configure destination address increment mode */
void mdma_destination_increment_config(mdma_channel_enum channelx, uint32_t dinc);
/* enable MDMA channel bufferable write mode */
void mdma_channel_bufferable_write_enable(mdma_channel_enum channelx);
/* disable MDMA channel bufferable write mode */
void mdma_channel_bufferable_write_disable(mdma_channel_enum channelx);
/* enable MDMA channel software request */
void mdma_channel_software_request_enable(mdma_channel_enum channelx);
/* enable MDMA channel */
void mdma_channel_enable(mdma_channel_enum channelx);
/* disable MDMA channel */
void mdma_channel_disable(mdma_channel_enum channelx);
/* get MDMA transfer error direction */
uint32_t mdma_transfer_error_direction_get(mdma_channel_enum channelx);
/* get MDMA transfer error address */
uint32_t mdma_transfer_error_address_get(mdma_channel_enum channelx);
/* interrupt & flag functions */
/* get MDMA flag */
FlagStatus mdma_flag_get(mdma_channel_enum channelx, uint32_t flag);
/* clear MDMA flag */
void mdma_flag_clear(mdma_channel_enum channelx, uint32_t flag);
/* enable MDMA interrupt */
void mdma_interrupt_enable(mdma_channel_enum channelx, uint32_t interrupt);
/* disable MDMA interrupt */
void mdma_interrupt_disable(mdma_channel_enum channelx, uint32_t interrupt);
/* get MDMA interrupt flag */
FlagStatus mdma_interrupt_flag_get(mdma_channel_enum channelx, uint32_t int_flag);
/* clear MDMA interrupt flag */
void mdma_interrupt_flag_clear(mdma_channel_enum channelx, uint32_t int_flag);
#endif /* GD32H75E_MDMA_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_misc.h
+224
View File
@@ -0,0 +1,224 @@
/*!
\file gd32h75e_misc.h
\brief definitions for the MISC
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_MISC_H
#define GD32H75E_MISC_H
#include "gd32h75e.h"
#if (__MPU_PRESENT == 1)
/* MPU region init parameter struct definitions */
typedef struct {
uint32_t region_base_address; /*!< region base address */
uint8_t region_number; /*!< region number */
uint8_t region_size; /*!< region size */
uint8_t subregion_disable; /*!< subregion disable */
uint8_t tex_type; /*!< tex type */
uint8_t access_permission; /*!< access permissions(AP) field */
uint8_t access_shareable; /*!< shareable */
uint8_t access_cacheable; /*!< cacheable */
uint8_t access_bufferable; /*!< bufferable */
uint8_t instruction_exec; /*!< execute never */
} mpu_region_init_struct;
#endif /* __MPU_PRESENT */
/* constants definitions */
/* set the RAM and FLASH base address */
#define NVIC_VECTTAB_RAM ((uint32_t)0x24000000U) /*!< RAM base address */
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000U) /*!< Flash base address */
/* set the NVIC vector table offset mask */
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80U)
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U)
/* priority group - define the pre-emption priority and the subpriority */
#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x00000700U) /*!< 0 bits for pre-emption priority, 4 bits for subpriority */
#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x00000600U) /*!< 1 bits for pre-emption priority, 3 bits for subpriority */
#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x00000500U) /*!< 2 bits for pre-emption priority, 2 bits for subpriority */
#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x00000400U) /*!< 3 bits for pre-emption priority, 1 bits for subpriority */
#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x00000300U) /*!< 4 bits for pre-emption priority, 0 bits for subpriority */
/* choose the method to enter or exit the low power mode */
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /*!< choose the system whether enter low power mode by exiting from ISR */
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /*!< choose the system enter the DEEPSLEEP mode or SLEEP mode */
#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the low power mode */
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */
/* choose the systick clock source */
#define SYSTICK_CLKSOURCE_CKSYS_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from CK_SYS/8 */
#define SYSTICK_CLKSOURCE_CKSYS ((uint32_t)0x00000004U) /*!< systick clock source is from CK_SYS */
#if (__MPU_PRESENT == 1)
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) /*!< MPU region number 0 */
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) /*!< MPU region number 1 */
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) /*!< MPU region number 2 */
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) /*!< MPU region number 3 */
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) /*!< MPU region number 4 */
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) /*!< MPU region number 5 */
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) /*!< MPU region number 6 */
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) /*!< MPU region number 7 */
#define MPU_REGION_NUMBER8 ((uint8_t)0x08U) /*!< MPU region number 8 */
#define MPU_REGION_NUMBER9 ((uint8_t)0x09U) /*!< MPU region number 9 */
#define MPU_REGION_NUMBER10 ((uint8_t)0x0AU) /*!< MPU region number 10 */
#define MPU_REGION_NUMBER11 ((uint8_t)0x0BU) /*!< MPU region number 11 */
#define MPU_REGION_NUMBER12 ((uint8_t)0x0CU) /*!< MPU region number 12 */
#define MPU_REGION_NUMBER13 ((uint8_t)0x0DU) /*!< MPU region number 13 */
#define MPU_REGION_NUMBER14 ((uint8_t)0x0EU) /*!< MPU region number 14 */
#define MPU_REGION_NUMBER15 ((uint8_t)0x0FU) /*!< MPU region number 15 */
#define MPU_REGION_SIZE_32B ARM_MPU_REGION_SIZE_32B /*!< MPU region size is 32 bytes, the smallest supported region size is 32 bytes */
#define MPU_REGION_SIZE_64B ARM_MPU_REGION_SIZE_64B /*!< MPU region size is 64 bytes */
#define MPU_REGION_SIZE_128B ARM_MPU_REGION_SIZE_128B /*!< MPU region size is 128 bytes */
#define MPU_REGION_SIZE_256B ARM_MPU_REGION_SIZE_256B /*!< MPU region size is 256 bytes */
#define MPU_REGION_SIZE_512B ARM_MPU_REGION_SIZE_512B /*!< MPU region size is 512 bytes */
#define MPU_REGION_SIZE_1KB ARM_MPU_REGION_SIZE_1KB /*!< MPU region size is 1K bytes */
#define MPU_REGION_SIZE_2KB ARM_MPU_REGION_SIZE_2KB /*!< MPU region size is 2K bytes */
#define MPU_REGION_SIZE_4KB ARM_MPU_REGION_SIZE_4KB /*!< MPU region size is 4K bytes */
#define MPU_REGION_SIZE_8KB ARM_MPU_REGION_SIZE_8KB /*!< MPU region size is 8K bytes */
#define MPU_REGION_SIZE_16KB ARM_MPU_REGION_SIZE_16KB /*!< MPU region size is 16K bytes */
#define MPU_REGION_SIZE_32KB ARM_MPU_REGION_SIZE_32KB /*!< MPU region size is 32K bytes */
#define MPU_REGION_SIZE_64KB ARM_MPU_REGION_SIZE_64KB /*!< MPU region size is 64K bytes */
#define MPU_REGION_SIZE_128KB ARM_MPU_REGION_SIZE_128KB /*!< MPU region size is 128K bytes */
#define MPU_REGION_SIZE_256KB ARM_MPU_REGION_SIZE_256KB /*!< MPU region size is 256K bytes */
#define MPU_REGION_SIZE_512KB ARM_MPU_REGION_SIZE_512KB /*!< MPU region size is 512K bytes */
#define MPU_REGION_SIZE_1MB ARM_MPU_REGION_SIZE_1MB /*!< MPU region size is 1M bytes */
#define MPU_REGION_SIZE_2MB ARM_MPU_REGION_SIZE_2MB /*!< MPU region size is 2M bytes */
#define MPU_REGION_SIZE_4MB ARM_MPU_REGION_SIZE_4MB /*!< MPU region size is 4M bytes */
#define MPU_REGION_SIZE_8MB ARM_MPU_REGION_SIZE_8MB /*!< MPU region size is 8M bytes */
#define MPU_REGION_SIZE_16MB ARM_MPU_REGION_SIZE_16MB /*!< MPU region size is 16M bytes */
#define MPU_REGION_SIZE_32MB ARM_MPU_REGION_SIZE_32MB /*!< MPU region size is 32M bytes */
#define MPU_REGION_SIZE_64MB ARM_MPU_REGION_SIZE_64MB /*!< MPU region size is 64M bytes */
#define MPU_REGION_SIZE_128MB ARM_MPU_REGION_SIZE_128MB /*!< MPU region size is 128M bytes */
#define MPU_REGION_SIZE_256MB ARM_MPU_REGION_SIZE_256MB /*!< MPU region size is 256M bytes */
#define MPU_REGION_SIZE_512MB ARM_MPU_REGION_SIZE_512MB /*!< MPU region size is 512M bytes */
#define MPU_REGION_SIZE_1GB ARM_MPU_REGION_SIZE_1GB /*!< MPU region size is 1G bytes */
#define MPU_REGION_SIZE_2GB ARM_MPU_REGION_SIZE_2GB /*!< MPU region size is 2G bytes */
#define MPU_REGION_SIZE_4GB ARM_MPU_REGION_SIZE_4GB /*!< MPU region size is 4G bytes */
#define MPU_SUBREGION_ENABLE ((uint8_t)0x00U) /*!< Subregion enable */
#define MPU_SUBREGION_DISABLE ((uint8_t)0x01U) /*!< Subregion disable */
#define MPU_TEX_TYPE0 ((uint8_t)0x00U) /*!< MPU TEX type 0 */
#define MPU_TEX_TYPE1 ((uint8_t)0x01U) /*!< MPU TEX type 1 */
#define MPU_TEX_TYPE2 ((uint8_t)0x02U) /*!< MPU TEX type 2 */
#define MPU_AP_NO_ACCESS ARM_MPU_AP_NONE /*!< MPU access permission no access */
#define MPU_AP_PRIV_RW ARM_MPU_AP_PRIV /*!< MPU access permission privileged access only */
#define MPU_AP_PRIV_RW_UNPRIV_RO ARM_MPU_AP_URO /*!< MPU access permission unprivileged access read-only */
#define MPU_AP_FULL_ACCESS ARM_MPU_AP_FULL /*!< MPU access permission full access */
#define MPU_AP_PRIV_RO ARM_MPU_AP_PRO /*!< MPU access permission privileged access read-only */
#define MPU_AP_PRIV_UNPRIV_RO ARM_MPU_AP_RO /*!< MPU access permission privileged and unprivileged read-only access */
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) /*!< MPU access shareable */
#define MPU_ACCESS_NON_SHAREABLE ((uint8_t)0x00U) /*!< MPU access non-shareable */
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) /*!< MPU access cacheable */
#define MPU_ACCESS_NON_CACHEABLE ((uint8_t)0x00U) /*!< MPU access non-cacheable */
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) /*!< MPU access bufferable */
#define MPU_ACCESS_NON_BUFFERABLE ((uint8_t)0x00U) /*!< MPU access non-bufferable */
#define MPU_INSTRUCTION_EXEC_PERMIT ((uint8_t)0x00U) /*!< execution of an instruction fetched from this region permitted */
#define MPU_INSTRUCTION_EXEC_NOT_PERMIT ((uint8_t)0x01U) /*!< execution of an instruction fetched from this region not permitted */
#define MPU_MODE_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< HFNMIENA and PRIVDEFENA are 0 */
#define MPU_MODE_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< use the MPU for memory accesses by HardFault and NMI handlers only */
#define MPU_MODE_PRIV_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< enables the default memory map as a background region for privileged access only */
#define MPU_MODE_HFNMI_PRIVDEF ((uint32_t)MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< HFNMIENA and PRIVDEFENA are 1 */
#endif /* __MPU_PRESENT */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check the NVIC priority group */
#define NOT_NVIC_PRIORITY_GROUP(nvic_prigroup) (((nvic_prigroup) != NVIC_PRIGROUP_PRE0_SUB4) && \
((nvic_prigroup) != NVIC_PRIGROUP_PRE1_SUB3) && \
((nvic_prigroup) != NVIC_PRIGROUP_PRE2_SUB2) && \
((nvic_prigroup) != NVIC_PRIGROUP_PRE3_SUB1) && \
((nvic_prigroup) != NVIC_PRIGROUP_PRE4_SUB0))
/* check the priority parameter */
#define NVIC_IRQ_PRIORITY_HIGH ((uint8_t)0x0FU)
#define NOT_NVIC_IRQ_PRIORITY(priority) ((priority) > NVIC_IRQ_PRIORITY_HIGH)
/* check the low power mode state */
#define NOT_SYS_LOW_POWER_MODE(mode) (((mode) != SCB_LPM_SLEEP_EXIT_ISR) && \
((mode) != SCB_LPM_DEEPSLEEP) && \
((mode) != SCB_LPM_WAKE_BY_ALL_INT))
/* check the systick clock source */
#define NOT_SYSTICK_CLK_SRC(clk_source) (((clk_source) != SYSTICK_CLKSOURCE_CKSYS_DIV8) && \
((clk_source) != SYSTICK_CLKSOURCE_CKSYS))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* set the priority group */
void nvic_priority_group_set(uint32_t nvic_prigroup);
/* enable NVIC interrupt request */
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
/* disable NVIC interrupt request */
void nvic_irq_disable(IRQn_Type nvic_irq);
/* set the NVIC vector table base address */
void nvic_vector_table_set(uint32_t nvic_vect_tab, uint32_t offset);
/* set the state of the low power mode */
void system_lowpower_set(uint8_t lowpower_mode);
/* reset the state of the low power mode */
void system_lowpower_reset(uint8_t lowpower_mode);
/* set the systick clock source */
void systick_clksource_set(uint32_t systick_clksource);
#if (__MPU_PRESENT == 1)
/* initialize mpu_region_init_struct with the default values */
void mpu_region_struct_para_init(mpu_region_init_struct *mpu_init_struct);
/* configure the MPU region */
void mpu_region_config(mpu_region_init_struct *mpu_init_struct);
/* enable the MPU region */
void mpu_region_enable(void);
#endif /* __MPU_PRESENT */
#endif /* GD32H75E_MISC_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_ospi.h
+955
View File
@@ -0,0 +1,955 @@
/*!
\file gd32h75e_ospi.h
\brief definitions for the OSPI
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_OSPI_H
#define GD32H75E_OSPI_H
#include "gd32h75e.h"
/* OSPI definitions */
#define OSPI0 OSPI_BASE
#define OSPI1 (OSPI_BASE + 0x00005000U)
/* registers definitions */
#define OSPI_CTL(ospix) REG32((ospix) + 0x00000000U) /*!< OSPI control register */
#define OSPI_DCFG0(ospix) REG32((ospix) + 0x00000008U) /*!< OSPI device configuration register */
#define OSPI_DCFG1(ospix) REG32((ospix) + 0x0000000CU) /*!< OSPI device configuration register */
#define OSPI_STAT(ospix) REG32((ospix) + 0x00000020U) /*!< OSPI status register */
#define OSPI_STATC(ospix) REG32((ospix) + 0x00000024U) /*!< OSPI status clear register */
#define OSPI_DTLEN(ospix) REG32((ospix) + 0x00000040U) /*!< OSPI data length register */
#define OSPI_ADDR(ospix) REG32((ospix) + 0x00000048U) /*!< OSPI address register */
#define OSPI_DATA(ospix) REG32((ospix) + 0x00000050U) /*!< OSPI data register */
#define OSPI_STATMK(ospix) REG32((ospix) + 0x00000080U) /*!< OSPI status mask register */
#define OSPI_STATMATCH(ospix) REG32((ospix) + 0x00000088U) /*!< OSPI status match register */
#define OSPI_INTERVAL(ospix) REG32((ospix) + 0x00000090U) /*!< OSPI interval register */
#define OSPI_TCFG(ospix) REG32((ospix) + 0x00000100U) /*!< OSPI transfer configuration register */
#define OSPI_TIMCFG(ospix) REG32((ospix) + 0x00000108U) /*!< OSPI timing configuration register */
#define OSPI_INS(ospix) REG32((ospix) + 0x00000110U) /*!< OSPI instruction register */
#define OSPI_ALTE(ospix) REG32((ospix) + 0x00000120U) /*!< OSPI alternate bytes register */
#define OSPI_WPTCFG(ospix) REG32((ospix) + 0x00000140U) /*!< OSPI wrap transfer configuration register */
#define OSPI_WPTIMCFG(ospix) REG32((ospix) + 0x00000148U) /*!< OSPI wrap timing configuration register */
#define OSPI_WPINS(ospix) REG32((ospix) + 0x00000150U) /*!< OSPI wrap instruction register */
#define OSPI_WPALTE(ospix) REG32((ospix) + 0x00000160U) /*!< OSPI wrap alternate bytes register */
#define OSPI_WTCFG(ospix) REG32((ospix) + 0x00000180U) /*!< OSPI write transfer configuration register */
#define OSPI_WTIMCFG(ospix) REG32((ospix) + 0x00000188U) /*!< OSPI write timing configuration register */
#define OSPI_WINS(ospix) REG32((ospix) + 0x00000190U) /*!< OSPI write instruction register */
#define OSPI_WALTE(ospix) REG32((ospix) + 0x000001A0U) /*!< OSPI write alternate bytes register */
/* bits definitions */
/* OSPI_CTL */
#define OSPI_CTL_OSPIEN BIT(0) /*!< enable the quadspi */
#define OSPI_CTL_DMAEN BIT(2) /*!< dma enable */
#define OSPI_CTL_FTL BITS(8,12) /*!< fifo threshold level */
#define OSPI_CTL_TERRIE BIT(16) /*!< transfer error interrupt enable */
#define OSPI_CTL_TCIE BIT(17) /*!< transfer complete interrupt enable */
#define OSPI_CTL_FTIE BIT(18) /*!< fifo threshold interrupt enable */
#define OSPI_CTL_SMIE BIT(19) /*!< status match interrupt enable */
#define OSPI_CTL_SPS BIT(22) /*!< status polling mode stop */
#define OSPI_CTL_SPMOD BIT(23) /*!< status polling match mode */
#define OSPI_CTL_FMOD BITS(28,29) /*!< functional mode select */
/* OSPI_DCFG0 */
#define OSPI_DCFG0_CSHC BITS(8,13) /*!< chip select high cycle */
#define OSPI_DCFG0_MESZ BITS(16,20) /*!< memory size */
#define OSPI_DCFG0_DTYSEL BITS(24,26) /*!< select device type */
/* OSPI_DCFG1 */
#define OSPI_DCFG1_PSC BITS(0,7) /*!< prescaler set */
#define OSPI_DCFG1_WPSZ BITS(16,18) /*!< wrap size */
/* OSPI_STAT */
#define OSPI_STAT_TERR BIT(0) /*!< transfer error flag */
#define OSPI_STAT_TC BIT(1) /*!< transfer complete flag */
#define OSPI_STAT_FT BIT(2) /*!< fifo threshold flag */
#define OSPI_STAT_SM BIT(3) /*!< status match flag */
#define OSPI_STAT_BUSY BIT(5) /*!< busy flag */
#define OSPI_STAT_FL BITS(8,13) /*!< fifo level */
/* OSPI_STATC */
#define OSPI_STATC_TERRC BIT(0) /*!< clear transfer error flag */
#define OSPI_STATC_TCC BIT(1) /*!< clear transfer complete flag */
#define OSPI_STATC_SMC BIT(3) /*!< clear status match flag */
/* OSPI_DTLEN */
#define OSPI_DTLEN_DTLEN BITS(0,31) /*!< data length */
/* OSPI_ADDR */
#define OSPI_ADDR_ADDR BITS(0,31) /*!< address to be send to the external flash memory */
/* OSPI_DATA */
#define OSPI_DATA_DATA BITS(0,31) /*!< data to be transferred through the flash memory */
/* OSPI_STATMK */
#define OSPI_STATMK_MASK BITS(0,31) /*!< status mask */
/* OSPI_STATMATCH */
#define OSPI_STATMATCH_MATCH BITS(0,31) /*!< status match */
/* OSPI_INTERVAL */
#define OSPI_INTERVAL_INTERVAL BITS(0,15) /*!< interval cycle */
/* OSPI_TCFG */
#define OSPI_TCFG_IMOD BITS(0,2) /*!< instruction mode */
#define OSPI_TCFG_INSSZ BITS(4,5) /*!< instruction size */
#define OSPI_TCFG_ADDRMOD BITS(8,10) /*!< address mode */
#define OSPI_TCFG_ADDRDTR BIT(11) /*!< address double transfer rate */
#define OSPI_TCFG_ADDRSZ BITS(12,13) /*!< address size */
#define OSPI_TCFG_ALTEMOD BITS(16,18) /*!< alternate bytes mode */
#define OSPI_TCFG_ABDTR BIT(19) /*!< alternate bytes double transfer rate */
#define OSPI_TCFG_ALTESZ BITS(20,21) /*!< alternate bytes size */
#define OSPI_TCFG_DATAMOD BITS(24,26) /*!< data mode */
#define OSPI_TCFG_DADTR BIT(27) /*!< data double transfer rate */
/* OSPI_TIMCFG */
#define OSPI_TIMCFG_DUMYC BITS(0,4) /*!< number of dummy cycles */
#define OSPI_TIMCFG_DEHQC BIT(27) /*!< delay hold quarter cycle */
#define OSPI_TIMCFG_SSAMPLE BIT(30) /*!< sample shift */
/* OSPI_INS */
#define OSPI_INS_INSTRUCTION BITS(0,31) /*!< command information to be send to the flash memory */
/* OSPI_ALTE */
#define OSPI_ALTE_ALTE BITS(0,31) /*!< alternate bytes to be send to the flash memory */
/* OSPI_WPTCFG */
#define OSPI_WPTCFG_IMOD BITS(0,2) /*!< instruction mode */
#define OSPI_WPTCFG_INSSZ BITS(4,5) /*!< instruction size */
#define OSPI_WPTCFG_ADDRMOD BITS(8,10) /*!< address mode */
#define OSPI_WPTCFG_ADDRDTR BIT(11) /*!< address double transfer rate */
#define OSPI_WPTCFG_ADDRSZ BITS(12,13) /*!< address size */
#define OSPI_WPTCFG_ALTEMOD BITS(16,18) /*!< alternate bytes mode */
#define OSPI_WPTCFG_ABDTR BIT(19) /*!< alternate bytes double transfer rate */
#define OSPI_WPTCFG_ALTESZ BITS(20,21) /*!< alternate bytes size */
#define OSPI_WPTCFG_DATAMOD BITS(24,26) /*!< data mode */
#define OSPI_WPTCFG_DADTR BIT(27) /*!< data double transfer rate */
/* OSPI_WPTIMCFG */
#define OSPI_WPTIMCFG_DUMYC BITS(0,4) /*!< number of dummy cycles */
#define OSPI_WPTIMCFG_DEHQC BIT(28) /*!< delay hold quarter cycle */
#define OSPI_WPTIMCFG_SSAMPLE BIT(30) /*!< sample shift */
/* OSPI_WPINS */
#define OSPI_WPINS_INSTRUCTION BITS(0,31) /*!< command information to be send to the flash memory */
/* OSPI_WPALTE */
#define OSPI_WPALTE_ALTE BITS(0,31) /*!< optional data to be send to the flash memory */
/* OSPI_WTCFG */
#define OSPI_WTCFG_IMOD BITS(0,2) /*!< instruction mode */
#define OSPI_WTCFG_INSSZ BITS(4,5) /*!< instruction size */
#define OSPI_WTCFG_ADDRMOD BITS(8,10) /*!< address mode */
#define OSPI_WTCFG_ADDRDTR BIT(11) /*!< address double transfer rate */
#define OSPI_WTCFG_ADDRSZ BITS(12,13) /*!< address size */
#define OSPI_WTCFG_ALTEMOD BITS(16,18) /*!< alternate bytes mode */
#define OSPI_WTCFG_ABDTR BIT(19) /*!< alternate bytes double transfer rate */
#define OSPI_WTCFG_ALTESZ BITS(20,21) /*!< alternate bytes size */
#define OSPI_WTCFG_DATAMOD BITS(24,26) /*!< data mode */
#define OSPI_WTCFG_DADTR BIT(27) /*!< data double transfer rate */
/* OSPI_WTIMCFG */
#define OSPI_WTIMCFG_DUMYC BITS(0,4) /*!< number of dummy cycles */
/* OSPI_WINS */
#define OSPI_WINS_INSTRUCTION BITS(0,31) /*!< command information to be send to the flash memory */
/* OSPI_WALTE */
#define OSPI_WALTE_ALTE BITS(0,31) /*!< optional data to be send to the flash memory */
/* OSPI_HBLCFG */
#define OSPI_HBLCFG_LMOD BIT(0) /*!< latency mode */
#define OSPI_HBLCFG_WZLAT BIT(1) /*!< write zero latency */
#define OSPI_HBLCFG_ACCTM BITS(8,15) /*!< access time */
#define OSPI_HBLCFG_RWRTM BITS(16,23) /*!< read write recovery time */
/* constants definitions */
/* ospi init struct definitions */
typedef struct {
uint32_t prescaler; /*! specifies the prescaler factor for generating clock based on the kernel clock.
this parameter can be a number between 0 and 255 */
uint32_t fifo_threshold; /*! specifies the threshold number of bytes in the FIFO (used only in indirect mode)
this parameter can be a value between 1 and 31 */
uint32_t sample_shift; /*! specifies the sample shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (it should be OSPI_SAMPLE_SHIFTING_NONE in DTR mode) */
uint32_t device_size; /*! specifies the device size. FlashSize+1 is effectively the number of address bits
required to address the flash memory. The flash capacity can be up to 4GB
(addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
this parameter can be a number between 0 and 31 */
uint32_t cs_hightime; /*! specifies the chip select high time. chipselecthightime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands. */
uint32_t memory_type; /*! it indicates the external device type connected to the OSPI. */
uint32_t wrap_size; /*! it indicates the wrap-size corresponding the external device configuration. */
uint32_t delay_hold_cycle; /*! it allows to hold to 1/4 cycle the data. */
} ospi_parameter_struct;
/* ospi regular command struct definitions */
typedef struct {
uint32_t operation_type; /*! it indicates if the configuration applies to the common regsiters or
to the registers for the write operation (these registers are only
used for memory-mapped mode). */
uint32_t instruction; /*! it contains the instruction to be sent to the device.
this parameter can be a value between 0 and 0xFFFFFFFF */
uint32_t ins_mode; /*! it indicates the mode of the instruction */
uint32_t ins_size; /*! it indicates the size of the instruction */
uint32_t address; /*! it contains the address to be sent to the device.
this parameter can be a value between 0 and 0xFFFFFFFF */
uint32_t addr_mode; /*! it indicates the mode of the address */
uint32_t addr_size; /*! it indicates the size of the address */
uint32_t addr_dtr_mode; /*! it enables or not the DTR mode for the address phase */
uint32_t alter_bytes; /*! it contains the alternate bytes to be sent to the device.
this parameter can be a value between 0 and 0xFFFFFFFF */
uint32_t alter_bytes_mode; /*! it indicates the mode of the alternate bytes */
uint32_t alter_bytes_size; /*! it indicates the size of the alternate bytes */
uint32_t alter_bytes_dtr_mode; /*! it enables or not the DTR mode for the alternate bytes phase */
uint32_t data_mode; /*! it indicates the mode of the data */
uint32_t nbdata; /*! it indicates the number of data transferred with this command.
this field is only used for indirect mode.
this parameter can be a value between 1 and 0xFFFFFFFF */
uint32_t data_dtr_mode; /*! it enables or not the DTR mode for the data phase */
uint32_t dummy_cycles; /*! it indicates the number of dummy cycles inserted before data phase.
this parameter can be a value between 0 and 31 */
} ospi_regular_cmd_struct;
/* ospi autopolling struct definitions */
typedef struct {
uint32_t match; /*! specifies the value to be compared with the masked status register to get a match.
this parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t mask; /*! specifies the mask to be applied to the status bytes received.
this parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t interval; /*! specifies the number of clock cycles between two read during automatic polling phases.
this parameter can be any value between 0 and 0xFFFF */
uint32_t match_mode; /*! specifies the method used for determining a match */
uint32_t automatic_stop; /*! specifies if automatic polling is stopped after a match */
} ospi_autopolling_struct;
/* OSPI configuration */
/* OSPI automatic stop */
#define OSPI_AUTOMATIC_STOP_MATCH OSPI_CTL_SPS /*!< status polling mode stop in match */
/* OSPI match mode */
#define OSPI_MATCH_MODE_AND 0x00000000U /*!< OSPI status polling match mode and */
#define OSPI_MATCH_MODE_OR OSPI_CTL_SPMOD /*!< OSPI status polling match mode or */
/* OSPI functional mode */
#define OSPI_FMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28U))
#define OSPI_INDIRECT_WRITE OSPI_FMOD(0) /*!< OSPI indirect write mode */
#define OSPI_INDIRECT_READ OSPI_FMOD(1) /*!< OSPI indirect read mode */
#define OSPI_STATUS_POLLING OSPI_FMOD(2) /*!< OSPI status polling mode */
#define OSPI_MEMORY_MAPPED OSPI_FMOD(3) /*!< OSPI memory mapped mode */
/* OSPI FIFO threshold level set */
#define OSPI_FTL(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U))
#define OSPI_FIFO_THRESHOLD_1 OSPI_FTL(0) /*!< in indirect write mode, there are 1 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 1 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_2 OSPI_FTL(1) /*!< in indirect write mode, there are 2 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 2 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_3 OSPI_FTL(2) /*!< in indirect write mode, there are 3 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 3 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_4 OSPI_FTL(3) /*!< in indirect write mode, there are 4 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 4 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_5 OSPI_FTL(4) /*!< in indirect write mode, there are 5 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 5 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_6 OSPI_FTL(5) /*!< in indirect write mode, there are 6 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 6 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_7 OSPI_FTL(6) /*!< in indirect write mode, there are 7 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 7 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_8 OSPI_FTL(7) /*!< in indirect write mode, there are 8 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 8 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_9 OSPI_FTL(8) /*!< in indirect write mode, there are 9 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 9 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_10 OSPI_FTL(9) /*!< in indirect write mode, there are 10 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 10 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_11 OSPI_FTL(10) /*!< in indirect write mode, there are 11 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 11 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_12 OSPI_FTL(11) /*!< in indirect write mode, there are 12 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 12 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_13 OSPI_FTL(12) /*!< in indirect write mode, there are 13 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 13 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_14 OSPI_FTL(13) /*!< in indirect write mode, there are 14 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 14 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_15 OSPI_FTL(14) /*!< in indirect write mode, there are 15 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 15 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_16 OSPI_FTL(15) /*!< in indirect write mode, there are 16 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 16 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_17 OSPI_FTL(16) /*!< in indirect write mode, there are 17 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 17 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_18 OSPI_FTL(17) /*!< in indirect write mode, there are 18 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 18 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_19 OSPI_FTL(18) /*!< in indirect write mode, there are 19 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 19 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_20 OSPI_FTL(19) /*!< in indirect write mode, there are 20 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 20 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_21 OSPI_FTL(20) /*!< in indirect write mode, there are 21 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 21 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_22 OSPI_FTL(21) /*!< in indirect write mode, there are 22 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 22 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_23 OSPI_FTL(22) /*!< in indirect write mode, there are 23 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 23 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_24 OSPI_FTL(23) /*!< in indirect write mode, there are 24 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 24 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_25 OSPI_FTL(24) /*!< in indirect write mode, there are 25 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 25 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_26 OSPI_FTL(25) /*!< in indirect write mode, there are 26 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 26 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_27 OSPI_FTL(26) /*!< in indirect write mode, there are 27 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 27 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_28 OSPI_FTL(27) /*!< in indirect write mode, there are 28 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 28 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_29 OSPI_FTL(28) /*!< in indirect write mode, there are 29 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 29 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_30 OSPI_FTL(29) /*!< in indirect write mode, there are 30 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 30 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_31 OSPI_FTL(30) /*!< in indirect write mode, there are 31 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 31 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_32 OSPI_FTL(31) /*!< in indirect write mode, there are 32 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 32 or more free bytes available to be read from the FIFO */
/* OSPI chip select high cycle */
#define OSPI_CSHC(regval) (BITS(8,13) & ((uint32_t)(regval) << 8U))
#define OSPI_CS_HIGH_TIME_1_CYCLE OSPI_CSHC(0) /*!< OSPI csn stays high for at least 1 cycle */
#define OSPI_CS_HIGH_TIME_2_CYCLE OSPI_CSHC(1) /*!< OSPI csn stays high for at least 2 cycle */
#define OSPI_CS_HIGH_TIME_3_CYCLE OSPI_CSHC(2) /*!< OSPI csn stays high for at least 3 cycle */
#define OSPI_CS_HIGH_TIME_4_CYCLE OSPI_CSHC(3) /*!< OSPI csn stays high for at least 4 cycle */
#define OSPI_CS_HIGH_TIME_5_CYCLE OSPI_CSHC(4) /*!< OSPI csn stays high for at least 5 cycle */
#define OSPI_CS_HIGH_TIME_6_CYCLE OSPI_CSHC(5) /*!< OSPI csn stays high for at least 6 cycle */
#define OSPI_CS_HIGH_TIME_7_CYCLE OSPI_CSHC(6) /*!< OSPI csn stays high for at least 7 cycle */
#define OSPI_CS_HIGH_TIME_8_CYCLE OSPI_CSHC(7) /*!< OSPI csn stays high for at least 8 cycle */
#define OSPI_CS_HIGH_TIME_9_CYCLE OSPI_CSHC(8) /*!< OSPI csn stays high for at least 9 cycle */
#define OSPI_CS_HIGH_TIME_10_CYCLE OSPI_CSHC(9) /*!< OSPI csn stays high for at least 10 cycle */
#define OSPI_CS_HIGH_TIME_11_CYCLE OSPI_CSHC(10) /*!< OSPI csn stays high for at least 11 cycle */
#define OSPI_CS_HIGH_TIME_12_CYCLE OSPI_CSHC(11) /*!< OSPI csn stays high for at least 12 cycle */
#define OSPI_CS_HIGH_TIME_13_CYCLE OSPI_CSHC(12) /*!< OSPI csn stays high for at least 13 cycle */
#define OSPI_CS_HIGH_TIME_14_CYCLE OSPI_CSHC(13) /*!< OSPI csn stays high for at least 14 cycle */
#define OSPI_CS_HIGH_TIME_15_CYCLE OSPI_CSHC(14) /*!< OSPI csn stays high for at least 15 cycle */
#define OSPI_CS_HIGH_TIME_16_CYCLE OSPI_CSHC(15) /*!< OSPI csn stays high for at least 16 cycle */
#define OSPI_CS_HIGH_TIME_17_CYCLE OSPI_CSHC(16) /*!< OSPI csn stays high for at least 17 cycle */
#define OSPI_CS_HIGH_TIME_18_CYCLE OSPI_CSHC(17) /*!< OSPI csn stays high for at least 18 cycle */
#define OSPI_CS_HIGH_TIME_19_CYCLE OSPI_CSHC(18) /*!< OSPI csn stays high for at least 19 cycle */
#define OSPI_CS_HIGH_TIME_20_CYCLE OSPI_CSHC(19) /*!< OSPI csn stays high for at least 20 cycle */
#define OSPI_CS_HIGH_TIME_21_CYCLE OSPI_CSHC(20) /*!< OSPI csn stays high for at least 21 cycle */
#define OSPI_CS_HIGH_TIME_22_CYCLE OSPI_CSHC(21) /*!< OSPI csn stays high for at least 22 cycle */
#define OSPI_CS_HIGH_TIME_23_CYCLE OSPI_CSHC(22) /*!< OSPI csn stays high for at least 23 cycle */
#define OSPI_CS_HIGH_TIME_24_CYCLE OSPI_CSHC(23) /*!< OSPI csn stays high for at least 24 cycle */
#define OSPI_CS_HIGH_TIME_25_CYCLE OSPI_CSHC(24) /*!< OSPI csn stays high for at least 25 cycle */
#define OSPI_CS_HIGH_TIME_26_CYCLE OSPI_CSHC(25) /*!< OSPI csn stays high for at least 26 cycle */
#define OSPI_CS_HIGH_TIME_27_CYCLE OSPI_CSHC(26) /*!< OSPI csn stays high for at least 27 cycle */
#define OSPI_CS_HIGH_TIME_28_CYCLE OSPI_CSHC(27) /*!< OSPI csn stays high for at least 28 cycle */
#define OSPI_CS_HIGH_TIME_29_CYCLE OSPI_CSHC(28) /*!< OSPI csn stays high for at least 29 cycle */
#define OSPI_CS_HIGH_TIME_30_CYCLE OSPI_CSHC(29) /*!< OSPI csn stays high for at least 30 cycle */
#define OSPI_CS_HIGH_TIME_31_CYCLE OSPI_CSHC(30) /*!< OSPI csn stays high for at least 31 cycle */
#define OSPI_CS_HIGH_TIME_32_CYCLE OSPI_CSHC(31) /*!< OSPI csn stays high for at least 32 cycle */
#define OSPI_CS_HIGH_TIME_33_CYCLE OSPI_CSHC(32) /*!< OSPI csn stays high for at least 33 cycle */
#define OSPI_CS_HIGH_TIME_34_CYCLE OSPI_CSHC(33) /*!< OSPI csn stays high for at least 34 cycle */
#define OSPI_CS_HIGH_TIME_35_CYCLE OSPI_CSHC(34) /*!< OSPI csn stays high for at least 35 cycle */
#define OSPI_CS_HIGH_TIME_36_CYCLE OSPI_CSHC(35) /*!< OSPI csn stays high for at least 36 cycle */
#define OSPI_CS_HIGH_TIME_37_CYCLE OSPI_CSHC(36) /*!< OSPI csn stays high for at least 37 cycle */
#define OSPI_CS_HIGH_TIME_38_CYCLE OSPI_CSHC(37) /*!< OSPI csn stays high for at least 38 cycle */
#define OSPI_CS_HIGH_TIME_39_CYCLE OSPI_CSHC(38) /*!< OSPI csn stays high for at least 39 cycle */
#define OSPI_CS_HIGH_TIME_40_CYCLE OSPI_CSHC(39) /*!< OSPI csn stays high for at least 40 cycle */
#define OSPI_CS_HIGH_TIME_41_CYCLE OSPI_CSHC(40) /*!< OSPI csn stays high for at least 41 cycle */
#define OSPI_CS_HIGH_TIME_42_CYCLE OSPI_CSHC(41) /*!< OSPI csn stays high for at least 42 cycle */
#define OSPI_CS_HIGH_TIME_43_CYCLE OSPI_CSHC(42) /*!< OSPI csn stays high for at least 43 cycle */
#define OSPI_CS_HIGH_TIME_44_CYCLE OSPI_CSHC(43) /*!< OSPI csn stays high for at least 44 cycle */
#define OSPI_CS_HIGH_TIME_45_CYCLE OSPI_CSHC(44) /*!< OSPI csn stays high for at least 45 cycle */
#define OSPI_CS_HIGH_TIME_46_CYCLE OSPI_CSHC(45) /*!< OSPI csn stays high for at least 46 cycle */
#define OSPI_CS_HIGH_TIME_47_CYCLE OSPI_CSHC(46) /*!< OSPI csn stays high for at least 47 cycle */
#define OSPI_CS_HIGH_TIME_48_CYCLE OSPI_CSHC(47) /*!< OSPI csn stays high for at least 48 cycle */
#define OSPI_CS_HIGH_TIME_49_CYCLE OSPI_CSHC(48) /*!< OSPI csn stays high for at least 49 cycle */
#define OSPI_CS_HIGH_TIME_50_CYCLE OSPI_CSHC(49) /*!< OSPI csn stays high for at least 50 cycle */
#define OSPI_CS_HIGH_TIME_51_CYCLE OSPI_CSHC(50) /*!< OSPI csn stays high for at least 51 cycle */
#define OSPI_CS_HIGH_TIME_52_CYCLE OSPI_CSHC(51) /*!< OSPI csn stays high for at least 52 cycle */
#define OSPI_CS_HIGH_TIME_53_CYCLE OSPI_CSHC(52) /*!< OSPI csn stays high for at least 53 cycle */
#define OSPI_CS_HIGH_TIME_54_CYCLE OSPI_CSHC(53) /*!< OSPI csn stays high for at least 54 cycle */
#define OSPI_CS_HIGH_TIME_55_CYCLE OSPI_CSHC(54) /*!< OSPI csn stays high for at least 55 cycle */
#define OSPI_CS_HIGH_TIME_56_CYCLE OSPI_CSHC(55) /*!< OSPI csn stays high for at least 56 cycle */
#define OSPI_CS_HIGH_TIME_57_CYCLE OSPI_CSHC(56) /*!< OSPI csn stays high for at least 57 cycle */
#define OSPI_CS_HIGH_TIME_58_CYCLE OSPI_CSHC(57) /*!< OSPI csn stays high for at least 58 cycle */
#define OSPI_CS_HIGH_TIME_59_CYCLE OSPI_CSHC(58) /*!< OSPI csn stays high for at least 59 cycle */
#define OSPI_CS_HIGH_TIME_60_CYCLE OSPI_CSHC(59) /*!< OSPI csn stays high for at least 60 cycle */
#define OSPI_CS_HIGH_TIME_61_CYCLE OSPI_CSHC(60) /*!< OSPI csn stays high for at least 61 cycle */
#define OSPI_CS_HIGH_TIME_62_CYCLE OSPI_CSHC(61) /*!< OSPI csn stays high for at least 62 cycle */
#define OSPI_CS_HIGH_TIME_63_CYCLE OSPI_CSHC(62) /*!< OSPI csn stays high for at least 63 cycle */
#define OSPI_CS_HIGH_TIME_64_CYCLE OSPI_CSHC(63) /*!< OSPI csn stays high for at least 64 cycle */
/* OSPI flash memory size */
#define OSPI_MESZ(regval) (BITS(16,20) & ((uint32_t)(regval) << 16U))
#define OSPI_MESZ_2_BYTES OSPI_MESZ(0) /*!< the size of external memory is 2 bytes */
#define OSPI_MESZ_4_BYTES OSPI_MESZ(1) /*!< the size of external memory is 4 bytes */
#define OSPI_MESZ_8_BYTES OSPI_MESZ(2) /*!< the size of external memory is 8 bytes */
#define OSPI_MESZ_16_BYTES OSPI_MESZ(3) /*!< the size of external memory is 16 bytes */
#define OSPI_MESZ_32_BYTES OSPI_MESZ(4) /*!< the size of external memory is 32 bytes */
#define OSPI_MESZ_64_BYTES OSPI_MESZ(5) /*!< the size of external memory is 64 bytes */
#define OSPI_MESZ_128_BYTES OSPI_MESZ(6) /*!< the size of external memory is 128 bytes */
#define OSPI_MESZ_256_BYTES OSPI_MESZ(7) /*!< the size of external memory is 256 bytes */
#define OSPI_MESZ_512_BYTES OSPI_MESZ(8) /*!< the size of external memory is 512 bytes */
#define OSPI_MESZ_1024_BYTES OSPI_MESZ(9) /*!< the size of external memory is 1024 bytes */
#define OSPI_MESZ_2_KBS OSPI_MESZ(10) /*!< the size of external memory is 2 KB */
#define OSPI_MESZ_4_KBS OSPI_MESZ(11) /*!< the size of external memory is 4 KB */
#define OSPI_MESZ_8_KBS OSPI_MESZ(12) /*!< the size of external memory is 8 KB */
#define OSPI_MESZ_16_KBS OSPI_MESZ(13) /*!< the size of external memory is 16 KB */
#define OSPI_MESZ_32_KBS OSPI_MESZ(14) /*!< the size of external memory is 32 KB */
#define OSPI_MESZ_64_KBS OSPI_MESZ(15) /*!< the size of external memory is 64 KB */
#define OSPI_MESZ_128_KBS OSPI_MESZ(16) /*!< the size of external memory is 128 KB */
#define OSPI_MESZ_256_KBS OSPI_MESZ(17) /*!< the size of external memory is 256 KB */
#define OSPI_MESZ_512_KBS OSPI_MESZ(18) /*!< the size of external memory is 512 KB */
#define OSPI_MESZ_1024_KBS OSPI_MESZ(19) /*!< the size of external memory is 1024 KBS */
#define OSPI_MESZ_2_MBS OSPI_MESZ(20) /*!< the size of external memory is 2 MB */
#define OSPI_MESZ_4_MBS OSPI_MESZ(21) /*!< the size of external memory is 4 MB */
#define OSPI_MESZ_8_MBS OSPI_MESZ(22) /*!< the size of external memory is 8 MB */
#define OSPI_MESZ_16_MBS OSPI_MESZ(23) /*!< the size of external memory is 16 MB */
#define OSPI_MESZ_32_MBS OSPI_MESZ(24) /*!< the size of external memory is 32 MB */
#define OSPI_MESZ_64_MBS OSPI_MESZ(25) /*!< the size of external memory is 64 MB */
#define OSPI_MESZ_128_MBS OSPI_MESZ(26) /*!< the size of external memory is 128 MB */
#define OSPI_MESZ_256_MBS OSPI_MESZ(27) /*!< the size of external memory is 256 MB */
#define OSPI_MESZ_512_MBS OSPI_MESZ(28) /*!< the size of external memory is 512 MB */
#define OSPI_MESZ_1024_MBS OSPI_MESZ(29) /*!< the size of external memory is 1024 MB */
#define OSPI_MESZ_2048_MBS OSPI_MESZ(30) /*!< the size of external memory is 2048 MB */
#define OSPI_MESZ_4096_MBS OSPI_MESZ(31) /*!< the size of external memory is 4096 MB */
/* OSPI device type select */
#define OSPI_DTYSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24U))
#define OSPI_MICRON_MODE OSPI_DTYSEL(0) /*!< device type select micron mode */
#define OSPI_MACRONIX_MODE OSPI_DTYSEL(1) /*!< device type select micronix mode */
#define OSPI_STANDARD_MODE OSPI_DTYSEL(2) /*!< device type select standard mode */
#define OSPI_MACRONIX_RAM_MODE OSPI_DTYSEL(3) /*!< device type select micronix ram mode */
#define OSPI_RESERVE_MODE OSPI_DTYSEL(7) /*!< reserve mode, not use */
/* OSPI prescaler set */
#define OSPI_PSC(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U))
/* OSPI wrap size set */
#define OSPI_WPSZ(regval) (BITS(16,18) & ((uint32_t)(regval) << 16U))
#define OSPI_DIRECT OSPI_WPSZ(0) /*!< external memory indirect device does not support wrap read */
#define OSPI_WRAP_16BYTES OSPI_WPSZ(2) /*!< external memory device supports wrap size of 16 bytes */
#define OSPI_WRAP_32BYTES OSPI_WPSZ(3) /*!< external memory device supports wrap size of 32 bytes */
#define OSPI_WRAP_64BYTES OSPI_WPSZ(4) /*!< external memory device supports wrap size of 64 bytes */
#define OSPI_WRAP_128BYTES OSPI_WPSZ(5) /*!< external memory device supports wrap size of 128 bytes */
/* OSPI transmit configuration */
/* OSPI operation type */
#define OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< common configuration (indirect or auto-polling mode) */
#define OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< read configuration (memory-mapped mode) */
#define OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< write configuration (memory-mapped mode) */
#define OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U) /*!< wrap configuration (memory-mapped mode) */
/* OSPI instruction mode */
#define OSPI_IMOD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
#define OSPI_INSTRUCTION_NONE OSPI_IMOD(0) /*!< no instruction mode */
#define OSPI_INSTRUCTION_1_LINE OSPI_IMOD(1) /*!< instruction mode on a single line */
#define OSPI_INSTRUCTION_2_LINES OSPI_IMOD(2) /*!< instruction mode on two lines */
#define OSPI_INSTRUCTION_4_LINES OSPI_IMOD(3) /*!< instruction mode on four lines */
#define OSPI_INSTRUCTION_8_LINES OSPI_IMOD(4) /*!< instruction mode on eight lines */
/* OSPI instruction size */
#define OSPI_INSSZ(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U))
#define OSPI_INSTRUCTION_8_BITS OSPI_INSSZ(0) /*!< instruction size on 8-bit address */
#define OSPI_INSTRUCTION_16_BITS OSPI_INSSZ(1) /*!< instruction size on 16-bit address */
#define OSPI_INSTRUCTION_24_BITS OSPI_INSSZ(2) /*!< instruction size on 24-bit address */
#define OSPI_INSTRUCTION_32_BITS OSPI_INSSZ(3) /*!< instruction size on 32-bit address */
/* OSPI address mode */
#define OSPI_ADDRMOD(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U))
#define OSPI_ADDRESS_NONE OSPI_ADDRMOD(0) /*!< no address mode */
#define OSPI_ADDRESS_1_LINE OSPI_ADDRMOD(1) /*!< address mode on a single line */
#define OSPI_ADDRESS_2_LINES OSPI_ADDRMOD(2) /*!< address mode on two lines */
#define OSPI_ADDRESS_4_LINES OSPI_ADDRMOD(3) /*!< address mode on four lines */
#define OSPI_ADDRESS_8_LINES OSPI_ADDRMOD(4) /*!< address mode on eight lines */
/* OSPI address size */
#define OSPI_ADDRSZ(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U))
#define OSPI_ADDRESS_8_BITS OSPI_ADDRSZ(0) /*!< address size on 8-bit address */
#define OSPI_ADDRESS_16_BITS OSPI_ADDRSZ(1) /*!< address size on 16-bit address */
#define OSPI_ADDRESS_24_BITS OSPI_ADDRSZ(2) /*!< address size on 24-bit address */
#define OSPI_ADDRESS_32_BITS OSPI_ADDRSZ(3) /*!< address size on 32-bit address */
/* OSPI address double transfer rate */
#define OSPI_ADDRDTR_MODE_DISABLE 0x00000000U /*!< address double transfer rate mode disable */
#define OSPI_ADDRDTR_MODE_ENABLE OSPI_TCFG_ADDRDTR /*!< address double transfer rate mode disable */
/* OSPI alternate bytes mode */
#define OSPI_ALTEMOD(regval) (BITS(16,18) & ((uint32_t)(regval) << 16U))
#define OSPI_ALTERNATE_BYTES_NONE OSPI_ALTEMOD(0) /*!< no alternate bytes mode */
#define OSPI_ALTERNATE_BYTES_1_LINE OSPI_ALTEMOD(1) /*!< alternate bytes mode on a single line */
#define OSPI_ALTERNATE_BYTES_2_LINES OSPI_ALTEMOD(2) /*!< alternate bytes mode on two lines */
#define OSPI_ALTERNATE_BYTES_4_LINES OSPI_ALTEMOD(3) /*!< alternate bytes mode on four lines */
#define OSPI_ALTERNATE_BYTES_8_LINES OSPI_ALTEMOD(4) /*!< alternate bytes mode on eight lines */
/* OSPI alternate bytes size */
#define OSPI_ALTESZ(regval) (BITS(20,21) & ((uint32_t)(regval) << 20U))
#define OSPI_ALTERNATE_BYTES_8_BITS OSPI_ALTESZ(0) /*!< alternate bytes size on 8-bit address */
#define OSPI_ALTERNATE_BYTES_16_BITS OSPI_ALTESZ(1) /*!< alternate bytes size on 16-bit address */
#define OSPI_ALTERNATE_BYTES_24_BITS OSPI_ALTESZ(2) /*!< alternate bytes size on 24-bit address */
#define OSPI_ALTERNATE_BYTES_32_BITS OSPI_ALTESZ(3) /*!< alternate bytes size on 32-bit address */
/* OSPI alternate bytes double transfer rate */
#define OSPI_ABDTR_MODE_DISABLE 0x00000000U /*!< alternate bytes double transfer rate mode disable */
#define OSPI_ABDTR_MODE_ENABLE OSPI_TCFG_ABDTR /*!< alternate bytes double transfer rate mode enable */
/* OSPI data mode */
#define OSPI_DATAMOD(regval) (BITS(24,26) & ((uint32_t)(regval) << 24U))
#define OSPI_DATA_NONE OSPI_DATAMOD(0) /*!< no data mode */
#define OSPI_DATA_1_LINE OSPI_DATAMOD(1) /*!< data mode on a single line */
#define OSPI_DATA_2_LINES OSPI_DATAMOD(2) /*!< data mode on two lines */
#define OSPI_DATA_4_LINES OSPI_DATAMOD(3) /*!< data mode on four lines */
#define OSPI_DATA_8_LINES OSPI_DATAMOD(4) /*!< data mode on eight lines */
/* OSPI data double transfer rate */
#define OSPI_DADTR_MODE_DISABLE 0x00000000U /*!< data double transfer rate mode disable */
#define OSPI_DADTR_MODE_ENABLE OSPI_TCFG_DADTR /*!< data double transfer rate mode enable */
/* OSPI dummy cycles */
#define OSPI_DUMYC(regval) (BITS(0,4) & ((uint32_t)(regval) << 0U))
#define OSPI_DUMYC_CYCLES_0 OSPI_DUMYC(0) /*!< duration of the dummy instruction phase is 0 cycle */
#define OSPI_DUMYC_CYCLES_1 OSPI_DUMYC(1) /*!< duration of the dummy instruction phase is 1 cycle */
#define OSPI_DUMYC_CYCLES_2 OSPI_DUMYC(2) /*!< duration of the dummy instruction phase is 2 cycle */
#define OSPI_DUMYC_CYCLES_3 OSPI_DUMYC(3) /*!< duration of the dummy instruction phase is 3 cycle */
#define OSPI_DUMYC_CYCLES_4 OSPI_DUMYC(4) /*!< duration of the dummy instruction phase is 4 cycle */
#define OSPI_DUMYC_CYCLES_5 OSPI_DUMYC(5) /*!< duration of the dummy instruction phase is 5 cycle */
#define OSPI_DUMYC_CYCLES_6 OSPI_DUMYC(6) /*!< duration of the dummy instruction phase is 6 cycle */
#define OSPI_DUMYC_CYCLES_7 OSPI_DUMYC(7) /*!< duration of the dummy instruction phase is 7 cycle */
#define OSPI_DUMYC_CYCLES_8 OSPI_DUMYC(8) /*!< duration of the dummy instruction phase is 8 cycle */
#define OSPI_DUMYC_CYCLES_9 OSPI_DUMYC(9) /*!< duration of the dummy instruction phase is 9 cycle */
#define OSPI_DUMYC_CYCLES_10 OSPI_DUMYC(10) /*!< duration of the dummy instruction phase is 10 cycle */
#define OSPI_DUMYC_CYCLES_11 OSPI_DUMYC(11) /*!< duration of the dummy instruction phase is 11 cycle */
#define OSPI_DUMYC_CYCLES_12 OSPI_DUMYC(12) /*!< duration of the dummy instruction phase is 12 cycle */
#define OSPI_DUMYC_CYCLES_13 OSPI_DUMYC(13) /*!< duration of the dummy instruction phase is 13 cycle */
#define OSPI_DUMYC_CYCLES_14 OSPI_DUMYC(14) /*!< duration of the dummy instruction phase is 14 cycle */
#define OSPI_DUMYC_CYCLES_15 OSPI_DUMYC(15) /*!< duration of the dummy instruction phase is 15 cycle */
#define OSPI_DUMYC_CYCLES_16 OSPI_DUMYC(16) /*!< duration of the dummy instruction phase is 16 cycle */
#define OSPI_DUMYC_CYCLES_17 OSPI_DUMYC(17) /*!< duration of the dummy instruction phase is 17 cycle */
#define OSPI_DUMYC_CYCLES_18 OSPI_DUMYC(18) /*!< duration of the dummy instruction phase is 18 cycle */
#define OSPI_DUMYC_CYCLES_19 OSPI_DUMYC(19) /*!< duration of the dummy instruction phase is 19 cycle */
#define OSPI_DUMYC_CYCLES_20 OSPI_DUMYC(20) /*!< duration of the dummy instruction phase is 20 cycle */
#define OSPI_DUMYC_CYCLES_21 OSPI_DUMYC(21) /*!< duration of the dummy instruction phase is 21 cycle */
#define OSPI_DUMYC_CYCLES_22 OSPI_DUMYC(22) /*!< duration of the dummy instruction phase is 22 cycle */
#define OSPI_DUMYC_CYCLES_23 OSPI_DUMYC(23) /*!< duration of the dummy instruction phase is 23 cycle */
#define OSPI_DUMYC_CYCLES_24 OSPI_DUMYC(24) /*!< duration of the dummy instruction phase is 24 cycle */
#define OSPI_DUMYC_CYCLES_25 OSPI_DUMYC(25) /*!< duration of the dummy instruction phase is 25 cycle */
#define OSPI_DUMYC_CYCLES_26 OSPI_DUMYC(26) /*!< duration of the dummy instruction phase is 26 cycle */
#define OSPI_DUMYC_CYCLES_27 OSPI_DUMYC(27) /*!< duration of the dummy instruction phase is 27 cycle */
#define OSPI_DUMYC_CYCLES_28 OSPI_DUMYC(28) /*!< duration of the dummy instruction phase is 28 cycle */
#define OSPI_DUMYC_CYCLES_29 OSPI_DUMYC(29) /*!< duration of the dummy instruction phase is 29 cycle */
#define OSPI_DUMYC_CYCLES_30 OSPI_DUMYC(30) /*!< duration of the dummy instruction phase is 30 cycle */
#define OSPI_DUMYC_CYCLES_31 OSPI_DUMYC(31) /*!< duration of the dummy instruction phase is 31 cycle */
/* OSPI delay hold quarter cycle */
#define OSPI_DELAY_HOLD_NONE 0x00000000U /*!< OSPI no delay hold cycle */
#define OSPI_DELAY_HOLD_QUARTER_CYCLE OSPI_TIMCFG_DEHQC /*!< OSPI delay hold 1/4 cycle */
/* OSPI sample shift */
#define OSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!< OSPI no sample shift */
#define OSPI_SAMPLE_SHIFTING_HALF_CYCLE OSPI_TIMCFG_SSAMPLE /*!< OSPI have 1/2 cycle sample shift */
/* OSPI interrupt constants definitions */
#define OSPI_INT_TERR OSPI_CTL_TERRIE /*!< transfer error interrupt enable */
#define OSPI_INT_TC OSPI_CTL_TCIE /*!< transfer complete interrupt enable */
#define OSPI_INT_FT OSPI_CTL_FTIE /*!< fifo threshold interrupt enable */
#define OSPI_INT_SM OSPI_CTL_SMIE /*!< status match interrupt enable */
/* OSPI flag definitions */
#define OSPI_FLAG_TERR OSPI_STAT_TERR /*!< transfer error flag */
#define OSPI_FLAG_TC OSPI_STAT_TC /*!< transfer complete flag */
#define OSPI_FLAG_FT OSPI_STAT_FT /*!< fifo threshold flag */
#define OSPI_FLAG_SM OSPI_STAT_SM /*!< status match flag */
#define OSPI_FLAG_BUSY OSPI_STAT_BUSY /*!< busy flag */
/* define the OSPI bit position and its register index offset */
#define OSPI_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define OSPI_REG_VAL(ospix, offset) (REG32((ospix) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
#define OSPI_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
#define OSPI_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define OSPI_REG_VAL2(ospix, offset) (REG32((ospix) + ((uint32_t)(offset) >> 22)))
#define OSPI_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
/* register offset */
#define OSPI_CTL_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL register offset */
#define OSPI_STAT_REG_OFFSET ((uint32_t)0x00000020U) /*!< STAT register offset */
/* OSPI interrupt flags */
typedef enum {
OSPI_INT_FLAG_TERR = OSPI_REGIDX_BIT2(OSPI_CTL_REG_OFFSET, 16U, OSPI_STAT_REG_OFFSET, 0U), /*!< transfer error interrupt flag */
OSPI_INT_FLAG_TC = OSPI_REGIDX_BIT2(OSPI_CTL_REG_OFFSET, 17U, OSPI_STAT_REG_OFFSET, 1U), /*!< transfer complete interrupt enable */
OSPI_INT_FLAG_FT = OSPI_REGIDX_BIT2(OSPI_CTL_REG_OFFSET, 18U, OSPI_STAT_REG_OFFSET, 2U), /*!< fifo threshold interrupt flag */
OSPI_INT_FLAG_SM = OSPI_REGIDX_BIT2(OSPI_CTL_REG_OFFSET, 19U, OSPI_STAT_REG_OFFSET, 3U), /*!< status match interrupt flag */
} ospi_interrupt_flag_enum;
#ifdef FW_DEBUG_ERR_REPORT
/* check peripherals */
#define NOT_OSPI_PERIPH(ospi_periph) (((ospi_periph) != OSPI0) && ((ospi_periph) != OSPI1))
/* check OSPI prescaler */
#define NOT_OSPI_PSC(psc) ((psc) > 255U)
/* check OSPI FIFO threshold */
#define NOT_OSPI_FIFO_THRESHOLD(fifo_threshold) (((fifo_threshold) != OSPI_FIFO_THRESHOLD_1) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_2) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_3) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_4) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_5) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_6) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_7) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_8) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_9) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_10) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_11) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_12) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_13) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_14) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_15) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_16) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_17) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_18) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_19) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_20) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_21) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_22) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_23) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_24) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_25) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_26) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_27) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_28) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_29) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_30) && \
((fifo_threshold) != OSPI_FIFO_THRESHOLD_31) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_32))
/* check OSPI sample shift */
#define NOT_OSPI_SAMPLE_SHIFTING(sample_shift) (((sample_shift) != OSPI_SAMPLE_SHIFTING_NONE) && ((sample_shift) != OSPI_SAMPLE_SHIFTING_HALF_CYCLE))
/* check OPSI memory size */
#define NOT_OSPI_MESZ(device_size) (((device_size) != OSPI_MESZ_2_BYTES) && ((device_size) != OSPI_MESZ_4_BYTES) && \
((device_size) != OSPI_MESZ_8_BYTES) && ((device_size) != OSPI_MESZ_16_BYTES) && \
((device_size) != OSPI_MESZ_32_BYTES) && ((device_size) != OSPI_MESZ_64_BYTES) && \
((device_size) != OSPI_MESZ_128_BYTES) && ((device_size) != OSPI_MESZ_256_BYTES) && \
((device_size) != OSPI_MESZ_512_BYTES) && ((device_size) != OSPI_MESZ_1024_BYTES) && \
((device_size) != OSPI_MESZ_2_KBS) && ((device_size) != OSPI_MESZ_4_KBS) && \
((device_size) != OSPI_MESZ_8_KBS) && ((device_size) != OSPI_MESZ_16_KBS) && \
((device_size) != OSPI_MESZ_32_KBS) && ((device_size) != OSPI_MESZ_64_KBS) && \
((device_size) != OSPI_MESZ_128_KBS) && ((device_size) != OSPI_MESZ_256_KBS) && \
((device_size) != OSPI_MESZ_512_KBS) && ((device_size) != OSPI_MESZ_1024_KBS) && \
((device_size) != OSPI_MESZ_2_MBS) && ((device_size) != OSPI_MESZ_4_MBS) && \
((device_size) != OSPI_MESZ_8_MBS) && ((device_size) != OSPI_MESZ_16_MBS) && \
((device_size) != OSPI_MESZ_32_MBS) && ((device_size) != OSPI_MESZ_64_MBS) && \
((device_size) != OSPI_MESZ_128_MBS) && ((device_size) != OSPI_MESZ_256_MBS) && \
((device_size) != OSPI_MESZ_512_MBS) && ((device_size) != OSPI_MESZ_1024_MBS) && \
((device_size) != OSPI_MESZ_2048_MBS) && ((device_size) != OSPI_MESZ_4096_MBS))
/* check OSPI CS high time */
#define NOT_OSPI_CS_HIGH_TIME(cs_hightime) (((cs_hightime) != OSPI_CS_HIGH_TIME_1_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_2_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_3_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_4_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_5_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_6_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_7_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_8_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_9_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_10_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_11_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_12_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_13_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_14_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_15_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_16_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_17_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_18_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_19_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_20_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_21_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_22_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_23_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_24_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_25_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_26_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_27_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_28_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_29_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_30_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_31_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_32_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_33_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_34_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_35_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_36_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_37_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_38_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_39_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_40_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_41_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_42_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_43_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_44_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_45_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_46_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_47_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_48_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_49_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_50_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_51_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_52_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_53_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_54_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_55_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_56_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_57_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_58_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_59_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_60_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_61_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_62_CYCLE) && \
((cs_hightime) != OSPI_CS_HIGH_TIME_63_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_64_CYCLE))
/* check OSPI memory type */
#define NOT_OSPI_MEMORY_TYPE(memory_type) (((memory_type) != OSPI_MICRON_MODE) && ((memory_type) != OSPI_MACRONIX_MODE) && \
((memory_type) != OSPI_STANDARD_MODE) && ((memory_type) != OSPI_MACRONIX_RAM_MODE))
/* check wrap size */
#define NOT_OSPI_WRAP_SIZE(wrap_size) (((wrap_size) != OSPI_DIRECT) && ((wrap_size) != OSPI_WRAP_16BYTES) && \
((wrap_size) != OSPI_WRAP_32BYTES) && ((wrap_size) != OSPI_WRAP_64BYTES) && \
((wrap_size) != OSPI_WRAP_128BYTES))
/* check delay hold cycle */
#define NOT_OSPI_DELAY_HOLD_CYCLE(delay_hold_cycle) (((delay_hold_cycle) != OSPI_DELAY_HOLD_NONE) && ((delay_hold_cycle) != OSPI_DELAY_HOLD_QUARTER_CYCLE))
/* check OSPI function mode */
#define NOT_OSPI_MODE(fmod) (((fmod) != OSPI_INDIRECT_WRITE) && ((fmod) != OSPI_INDIRECT_READ) && \
((fmod) != OSPI_STATUS_POLLING) && ((fmod) != OSPI_MEMORY_MAPPED))
/* check status polling mode stop */
#define NOT_OSPI_AUTOMATIC_STOP_MATCH(stop) (((stop) != OSPI_AUTOMATIC_STOP_MATCH))
/* check OSPI status polling match mode */
#define NOT_OSPI_MATCH_MODE(mode) (((mode) != OSPI_MATCH_MODE_AND) && ((mode) != OSPI_MATCH_MODE_OR))
/* check OSPI dumyc cycles */
#define NOT_OSPI_DUMYC_CYCLES(dumyc) (((dumyc) != OSPI_DUMYC_CYCLES_0) && ((dumyc) != OSPI_DUMYC_CYCLES_1) && \
((dumyc) != OSPI_DUMYC_CYCLES_2) && ((dumyc) != OSPI_DUMYC_CYCLES_3) && \
((dumyc) != OSPI_DUMYC_CYCLES_4) && ((dumyc) != OSPI_DUMYC_CYCLES_5) && \
((dumyc) != OSPI_DUMYC_CYCLES_6) && ((dumyc) != OSPI_DUMYC_CYCLES_7) && \
((dumyc) != OSPI_DUMYC_CYCLES_8) && ((dumyc) != OSPI_DUMYC_CYCLES_9) && \
((dumyc) != OSPI_DUMYC_CYCLES_10) && ((dumyc) != OSPI_DUMYC_CYCLES_11) && \
((dumyc) != OSPI_DUMYC_CYCLES_12) && ((dumyc) != OSPI_DUMYC_CYCLES_13) && \
((dumyc) != OSPI_DUMYC_CYCLES_14) && ((dumyc) != OSPI_DUMYC_CYCLES_15) && \
((dumyc) != OSPI_DUMYC_CYCLES_16) && ((dumyc) != OSPI_DUMYC_CYCLES_17) && \
((dumyc) != OSPI_DUMYC_CYCLES_18) && ((dumyc) != OSPI_DUMYC_CYCLES_19) && \
((dumyc) != OSPI_DUMYC_CYCLES_20) && ((dumyc) != OSPI_DUMYC_CYCLES_21) && \
((dumyc) != OSPI_DUMYC_CYCLES_22) && ((dumyc) != OSPI_DUMYC_CYCLES_23) && \
((dumyc) != OSPI_DUMYC_CYCLES_24) && ((dumyc) != OSPI_DUMYC_CYCLES_25) && \
((dumyc) != OSPI_DUMYC_CYCLES_26) && ((dumyc) != OSPI_DUMYC_CYCLES_27) && \
((dumyc) != OSPI_DUMYC_CYCLES_28) && ((dumyc) != OSPI_DUMYC_CYCLES_29) && \
((dumyc) != OSPI_DUMYC_CYCLES_30) && ((dumyc) != OSPI_DUMYC_CYCLES_31))
/* check OSPI instruction mode */
#define NOT_OSPI_INSTRUCTION_MODE(imod) (((imod) != OSPI_INSTRUCTION_NONE) && ((imod) != OSPI_INSTRUCTION_1_LINE) && \
((imod) != OSPI_INSTRUCTION_2_LINES) && ((imod) != OSPI_INSTRUCTION_4_LINES) && \
((imod) != OSPI_INSTRUCTION_8_LINES))
/* check OSPI instruction size */
#define NOT_OSPI_INSTRUCTION_SIZE(inssz) (((inssz) != OSPI_INSTRUCTION_8_BITS) && ((inssz) != OSPI_INSTRUCTION_16_BITS) && \
((inssz) != OSPI_INSTRUCTION_24_BITS) && ((inssz) != OSPI_INSTRUCTION_32_BITS))
/* check OSPI address mode */
#define NOT_OSPI_ADDRESS_MODE(addrmod) (((addrmod) != OSPI_ADDRESS_NONE) && ((addrmod) != OSPI_ADDRESS_1_LINE) && \
((addrmod) != OSPI_ADDRESS_2_LINES) && ((addrmod) != OSPI_ADDRESS_4_LINES) && \
((addrmod) != OSPI_ADDRESS_8_LINES))
/* check OSPI address DTR mode */
#define NOT_OSPI_ADDRDTR_MODE(addrdtr) (((addrdtr) != OSPI_ADDRDTR_MODE_DISABLE) && ((addrdtr) != OSPI_ADDRDTR_MODE_ENABLE))
/* check OSPI address size */
#define NOT_OSPI_ADDRESS_SIZE(addrsz) (((addrsz) != OSPI_ADDRESS_8_BITS) && ((addrsz) != OSPI_ADDRESS_16_BITS) && \
((addrsz) != OSPI_ADDRESS_24_BITS) && ((addrsz) != OSPI_ADDRESS_32_BITS))
/* check OSPI alternate bytes mode */
#define NOT_OSPI_ALTERNATE_BYTES_MODE(atlemod) (((atlemod) != OSPI_ALTERNATE_BYTES_NONE) && ((atlemod) != OSPI_ALTERNATE_BYTES_1_LINE) && \
((atlemod) != OSPI_ALTERNATE_BYTES_2_LINES) && ((atlemod) != OSPI_ALTERNATE_BYTES_4_LINES) && \
((atlemod) != OSPI_ALTERNATE_BYTES_8_LINES))
/* check OSPI alternate bytes DTR mode */
#define NOT_OSPI_ABDTR_MODE(abdtr) (((abdtr) != OSPI_ABDTR_MODE_DISABLE) && ((abdtr) != OSPI_ABDTR_MODE_ENABLE))
/* check OSPI alternate bytes size */
#define NOT_OSPI_ALTERNATE_BYTES_SIZE(altesz) (((altesz) != OSPI_ALTERNATE_BYTES_8_BITS) && ((altesz) != OSPI_ALTERNATE_BYTES_16_BITS) && \
((altesz) != OSPI_ALTERNATE_BYTES_24_BITS) && ((altesz) != OSPI_ALTERNATE_BYTES_32_BITS))
#define NOT_OSPI_DATA_MODE(datamod) (((datamod) != OSPI_DATA_NONE) && ((datamod) != OSPI_DATA_1_LINE) && \
((datamod) != OSPI_DATA_2_LINES) && ((datamod) != OSPI_DATA_4_LINES) && \
((datamod) != OSPI_DATA_8_LINES))
/* check OSPI data DTR mode */
#define NOT_OSPI_DADTR_MODE(dadtr) (((dadtr) != OSPI_DADTR_MODE_DISABLE) && ((dadtr) != OSPI_DADTR_MODE_ENABLE))
/* check OSPI operation type */
#define NOT_OSPI_OPTYPE(operation_type) (((operation_type) != OSPI_OPTYPE_COMMON_CFG) && ((operation_type) != OSPI_OPTYPE_READ_CFG) && \
((operation_type) != OSPI_OPTYPE_WRITE_CFG) && ((operation_type) != OSPI_OPTYPE_WRAP_CFG))
/* check the number of clock cycles between two read during automatic polling phases */
#define NOT_INTERVAL_NUM(interval) (((interval) > 0xFFFFU))
/* check OSPI interrupt */
#define NOT_OSPI_INTERRUPT(interrupt) (((interrupt) != OSPI_INT_TERR) && ((interrupt) != OSPI_INT_TC) && \
((interrupt) != OSPI_INT_FT) && ((interrupt) != OSPI_INT_SM))
/* check OSPI flag */
#define NOT_OSPI_FLAG(flag) (((flag) != OSPI_FLAG_TERR) && ((flag) != OSPI_FLAG_TC) && \
((flag) != OSPI_FLAG_SM) && ((flag) != OSPI_FLAG_BUSY))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* deinitialization initialization functions */
/* reset OSPI */
void ospi_deinit(uint32_t ospi_periph);
/* initialize the parameters of OSPI struct with the default values */
void ospi_struct_init(ospi_parameter_struct *ospi_struct);
/* initialize OSPI parameter */
void ospi_init(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct);
/* enable OSPI */
void ospi_enable(uint32_t ospi_periph);
/* disable OSPI */
void ospi_disable(uint32_t ospi_periph);
/* device configuration functions */
/* configure device memory type */
void ospi_device_memory_type_config(uint32_t ospi_periph, uint32_t dtysel);
/* configure device memory size */
void ospi_device_memory_size_config(uint32_t ospi_periph, uint32_t mesz);
/* functional mode functions */
/* select functional mode */
void ospi_functional_mode_config(uint32_t ospi_periph, uint32_t fmod);
/* configure status polling mode */
void ospi_status_polling_config(uint32_t ospi_periph, uint32_t stop, uint32_t mode);
/* configure status mask */
void ospi_status_mask_config(uint32_t ospi_periph, uint32_t mask);
/* configure status match */
void ospi_status_match_config(uint32_t ospi_periph, uint32_t match);
/* configure interval cycle */
void ospi_interval_cycle_config(uint32_t ospi_periph, uint16_t interval);
/* OSPI mode functions */
/* configure OSPI fifo threshold level */
void ospi_fifo_level_config(uint32_t ospi_periph, uint32_t ftl);
/* configure chip select high cycle */
void ospi_chip_select_high_cycle_config(uint32_t ospi_periph, uint32_t cshc);
/* configure OSPI prescaler */
void ospi_prescaler_config(uint32_t ospi_periph, uint32_t psc);
/* configure send instruction only once mode */
void ospi_send_instruction_mode_config(uint32_t ospi_periph, uint32_t sioo);
/* configure dummy cycles number */
void ospi_dummy_cycles_config(uint32_t ospi_periph, uint32_t dumyc);
/* configure delay hold 1/4 cycle */
void ospi_delay_hold_cycle_config(uint32_t ospi_periph, uint32_t dehqc);
/* configure sample shift */
void ospi_sample_shift_config(uint32_t ospi_periph, uint32_t ssample);
/* OSPI tansfer configuration functions */
/* configure data length */
void ospi_data_length_config(uint32_t ospi_periph, uint32_t dtlen);
/* configure OSPI instruction */
void ospi_instruction_config(uint32_t ospi_periph, uint32_t instruction);
/* configure OSPI instruction mode */
void ospi_instruction_mode_config(uint32_t ospi_periph, uint32_t imod);
/* configure OSPI instruction size */
void ospi_instruction_size_config(uint32_t ospi_periph, uint32_t inssz);
/* configure OSPI address */
void ospi_address_config(uint32_t ospi_periph, uint32_t addr);
/* configure OSPI address mode */
void ospi_address_mode_config(uint32_t ospi_periph, uint32_t addrmod);
/* configure OSPI address dtr */
void ospi_address_dtr_config(uint32_t ospi_periph, uint32_t addrdtr);
/* configure OSPI address size */
void ospi_address_size_config(uint32_t ospi_periph, uint32_t addrsz);
/* configure alternate byte */
void ospi_alternate_byte_config(uint32_t ospi_periph, uint32_t alte);
/* configure OSPI alternate byte mode */
void ospi_alternate_byte_mode_config(uint32_t ospi_periph, uint32_t atlemod);
/* configure OSPI alternate byte dtr */
void ospi_alternate_byte_dtr_config(uint32_t ospi_periph, uint32_t abdtr);
/* configure OSPI alternate byte size */
void ospi_alternate_byte_size_config(uint32_t ospi_periph, uint32_t altesz);
/* configure data mode */
void ospi_data_mode_config(uint32_t ospi_periph, uint32_t datamod);
/* configure data size */
void ospi_data_dtr_config(uint32_t ospi_periph, uint32_t dadtr);
/* OSPI transmit data */
void ospi_data_transmit(uint32_t ospi_periph, uint32_t data);
/* OSPI receive data */
uint32_t ospi_data_receive(uint32_t ospi_periph);
/* OSPI DMA functions */
/* enable OSPI DMA */
void ospi_dma_enable(uint32_t ospi_periph);
/* disable OSPI DMA */
void ospi_dma_disable(uint32_t ospi_periph);
/* OSPI wrap configuration functions */
/* configure wrap size */
void ospi_wrap_size_config(uint32_t ospi_periph, uint32_t wpsz);
/* configure wrap instruction */
void ospi_wrap_instruction_config(uint32_t ospi_periph, uint32_t instruction);
/* configure wrap instruction mode */
void ospi_wrap_instruction_mode_config(uint32_t ospi_periph, uint32_t imod);
/* configure wrap instruction size */
void ospi_wrap_instruction_size_config(uint32_t ospi_periph, uint32_t inssz);
/* configure wrap address */
void ospi_wrap_address_config(uint32_t ospi_periph, uint32_t addr);
/* configure wrap address mode */
void ospi_wrap_address_mode_config(uint32_t ospi_periph, uint32_t addrmod);
/* configure wrap address dtr */
void ospi_wrap_address_dtr_config(uint32_t ospi_periph, uint32_t addrdtr);
/* configure wrap address size */
void ospi_wrap_address_size_config(uint32_t ospi_periph, uint32_t addrsz);
/* configure wrap alternate byte */
void ospi_wrap_alternate_byte_config(uint32_t ospi_periph, uint32_t alte);
/* configure wrap alternate bytes mode */
void ospi_wrap_alternate_byte_mode_config(uint32_t ospi_periph, uint32_t atlemod);
/* configure wrap alternate bytes dtr */
void ospi_wrap_alternate_byte_dtr_config(uint32_t ospi_periph, uint32_t abdtr);
/* configure wrap alternate bytes mode */
void ospi_wrap_alternate_byte_size_config(uint32_t ospi_periph, uint32_t altesz);
/* configure wrap data mode */
void ospi_wrap_data_mode_config(uint32_t ospi_periph, uint32_t datamod);
/* configure wrap data mode */
void ospi_wrap_data_dtr_config(uint32_t ospi_periph, uint32_t dadtr);
/* configure wrap dummy cycles number */
void ospi_wrap_dummy_cycles_config(uint32_t ospi_periph, uint32_t dumyc);
/* delay hold 1/4 cycle in wrap */
void ospi_wrap_delay_hold_cycle_config(uint32_t ospi_periph, uint32_t dehqc);
/* configure sample shift in wrap */
void ospi_wrap_sample_shift_config(uint32_t ospi_periph, uint32_t ssample);
/* OSPI write configure functions */
/* configure write instruction */
void ospi_write_instruction_config(uint32_t ospi_periph, uint32_t instruction);
/* configure write instruction mode */
void ospi_write_instruction_mode_config(uint32_t ospi_periph, uint32_t imod);
/* configure write instruction size */
void ospi_write_instruction_size_config(uint32_t ospi_periph, uint32_t inssz);
/* configure write address */
void ospi_write_address_config(uint32_t ospi_periph, uint32_t addr);
/* configure write address mode */
void ospi_write_address_mode_config(uint32_t ospi_periph, uint32_t addrmod);
/* configure write address dtr */
void ospi_write_address_dtr_config(uint32_t ospi_periph, uint32_t addrdtr);
/* configure write address size */
void ospi_write_address_size_config(uint32_t ospi_periph, uint32_t addrsz);
/* configure write alternate bytes mode */
void ospi_write_alternate_byte_config(uint32_t ospi_periph, uint32_t alte);
/* configure write alternate byte mode */
void ospi_write_alternate_byte_mode_config(uint32_t ospi_periph, uint32_t atlemod);
/* configure write alternate byte dtr */
void ospi_write_alternate_byte_dtr_config(uint32_t ospi_periph, uint32_t abdtr);
/* configure write alternate byte size */
void ospi_write_alternate_byte_size_config(uint32_t ospi_periph, uint32_t altesz);
/* configure write data mode */
void ospi_write_data_mode_config(uint32_t ospi_periph, uint32_t datamod);
/* configure write data dtr */
void ospi_write_data_dtr_config(uint32_t ospi_periph, uint32_t dadtr);
/* configure write dummy cycles number */
void ospi_write_dummy_cycles_config(uint32_t ospi_periph, uint32_t dumyc);
/* configure OSPI regular command parameter */
void ospi_command_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct, ospi_regular_cmd_struct *cmd_struct);
/* transmit data */
void ospi_transmit(uint32_t ospi_periph, uint8_t *pdata);
/* receive data */
void ospi_receive(uint32_t ospi_periph, uint8_t *pdata);
/* configure the OSPI automatic polling mode */
void ospi_autopolling_mode(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct, ospi_autopolling_struct *autopl_cfg_struct);
/* flag & interrupt functions */
/* enable OSPI interrupt */
void ospi_interrupt_enable(uint32_t ospi_periph, uint32_t interrupt);
/* disable OSPI interrupt */
void ospi_interrupt_disable(uint32_t ospi_periph, uint32_t interrupt);
/* get OSPI fifo level */
uint32_t ospi_fifo_level_get(uint32_t ospi_periph);
/* get OSPI flag status */
FlagStatus ospi_flag_get(uint32_t ospi_periph, uint32_t flag);
/* clear OSPI flag status */
void ospi_flag_clear(uint32_t ospi_periph, uint32_t flag);
/* get OSPI interrupt status */
FlagStatus ospi_interrupt_flag_get(uint32_t ospi_periph, ospi_interrupt_flag_enum int_flag);
/* clear OSPI interrupt flag status */
void ospi_interrupt_flag_clear(uint32_t ospi_periph, ospi_interrupt_flag_enum int_flag);
#endif /* GD32H75E_OSPI_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_ospim.h
+147
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/*!
\file gd32h75e_ospim.h
\brief definitions for the OSPIM
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_OSPIM_H
#define GD32H75E_OSPIM_H
#include "gd32h75e.h"
/* OSPIM definitions */
#define OSPIM OSPM_BASE
#define OSPIM_PCFG0 REG32(OSPIM + 0x00000004U) /*!< OSPI I/O manager port configuration register 0 */
#define OSPIM_PCFG1 REG32(OSPIM + 0x00000008U) /*!< OSPI I/O manager port configuration register 1 */
/* OSPIM_PCFG */
#define OSPIM_PCFG_SCKEN BIT(0) /*!< enable for sck of port 0 */
#define OSPIM_PCFG_SRCPCK BIT(1) /*!< source selection for sck of port n */
#define OSPIM_PCFG_NCSEN BIT(8) /*!< enable for csn of port 0 */
#define OSPIM_PCFG_SRCPCS BIT(9) /*!< source selection for csn of port n */
#define OSPIM_PCFG_POLEN BIT(16) /*!< enable for IO[3:0] of port 0 */
#define OSPIM_PCFG_SRCPLIO BITS(17,18) /*!< source selection for IO[3:0] of port 0 */
#define OSPIM_PCFG_POHEN BIT(24) /*!< enable for IO[7:4] of port 0 */
#define OSPIM_PCFG_SRCPHIO BITS(25,26) /*!< source selection for IO[7:4] of port 0 */
/* constants definitions */
/* ospi io manager configuration struct definitions */
/* ospim register address */
#define OSPIM_PCFG(regval) REG32(OSPIM + 0x4U * ((regval) + 1U)) /*!< the address of OSPI manager port configuration register */
/* ospim register address */
#define OSPIM_PORT0 0x00U /*!< OSPI manager port 0 */
#define OSPIM_PORT1 0x01U /*!< OSPI manager port 1 */
/* SCK of port */
#define OSPIM_PORT_SCK_DISABLE 0x00000000U /*!< disable SCK of port */
#define OSPIM_PORT_SCK_ENABLE OSPIM_PCFG_SCKEN /*!< disable SCK of port */
/* source selection for SCK of port */
#define OSPIM_SCK_SOURCE_OSPI0_SCK 0x00000000U /*!< the source of SCK is OSPI0_SCK */
#define OSPIM_SCK_SOURCE_OSPI1_SCK OSPIM_PCFG_SRCPCK /*!< the source of SCK is OSPI1_SCK */
/* CSN of port */
#define OSPIM_PORT_CSN_DISABLE 0x00000000U /*!< disable CSN of port */
#define OSPIM_PORT_CSN_ENABLE OSPIM_PCFG_NCSEN /*!< enable CSN of port */
/* source selection for CSN of port */
#define OSPIM_CSN_SOURCE_OSPI0_CSN 0x00000000U /*!< the source of CSN is OSPI0_CSN */
#define OSPIM_CSN_SOURCE_OSPI1_CSN OSPIM_PCFG_SRCPCS /*!< the source of CSN is OSPI1_CSN */
/* IO[3:0] of port */
#define OSPIM_IO_LOW_DISABLE 0x00000000U /*!< disable IO[3:0] of port */
#define OSPIM_IO_LOW_ENABLE OSPIM_PCFG_POLEN /*!< enable IO[3:0] of port */
/* source selection for IO[3:0] of port 0 */
#define OSPIM_SRCPLIO(regval) (BITS(17,18) & ((uint32_t)(regval) << 17U))
#define OSPIM_SRCPLIO_OSPI0_IO_LOW OSPIM_SRCPLIO(0) /*!< select OSPI0_IO[3:0] in non-multiplexed mode, and select multiplexed IO[3:0] in multiplex mode */
#define OSPIM_SRCPLIO_OSPI0_IO_HIGH OSPIM_SRCPLIO(1) /*!< select OSPI0_IO[7:4] in non-multiplexed mode, and select multiplexed IO[7:4] in multiplex mode */
#define OSPIM_SRCPLIO_OSPI1_IO_LOW OSPIM_SRCPLIO(2) /*!< select OSPI1_IO[3:0], only valied in non-multiplexed mode */
#define OSPIM_SRCPLIO_OSPI1_IO_HIGH OSPIM_SRCPLIO(3) /*!< select OSPI1_IO[7:4], only valied in non-multiplexed mode */
/* IO[7:4] of port */
#define OSPIM_IO_HIGH_DISABLE 0x00000000U /*!< disable IO[7:4] of port */
#define OSPIM_IO_HIGH_ENABLE OSPIM_PCFG_POHEN /*!< enable IO[7:4] of port */
/* source selection for IO[7:4] of port n */
#define OSPIM_SRCPHIO(regval) (BITS(25,26) & ((uint32_t)(regval) << 25U))
#define OSPIM_SRCPHIO_OSPI0_IO_LOW OSPIM_SRCPHIO(0) /*!< select OSPI0_IO[3:0] in non-multiplexed mode, and select multiplexed IO[3:0] in multiplex mode */
#define OSPIM_SRCPHIO_OSPI0_IO_HIGH OSPIM_SRCPHIO(1) /*!< select OSPI0_IO[7:4] in non-multiplexed mode, and select multiplexed IO[7:4] in multiplex mode */
#define OSPIM_SRCPHIO_OSPI1_IO_LOW OSPIM_SRCPHIO(2) /*!< select OSPI1_IO[3:0], only valied in non-multiplexed mode */
#define OSPIM_SRCPHIO_OSPI1_IO_HIGH OSPIM_SRCPHIO(3) /*!< select OSPI1_IO[7:4], only valied in non-multiplexed mode */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check OSPIM port */
#define NOT_OSPIM_PORT(port) (((port) != OSPIM_PORT0) && ((port) != OSPIM_PORT1))
/* check OSPIM port sck configuration */
#define NOT_OSPIM_PORT_SCK(sckconfg) (((sckconfg) != OSPIM_PORT_SCK_DISABLE) && ((sckconfg) != OSPIM_PORT_SCK_ENABLE))
/* check OSPIM port sck source */
#define NOT_OSPIM_PORT_SCK_SOURCE(sck_source) (((sck_source) != OSPIM_SCK_SOURCE_OSPI0_SCK) && ((sck_source) != OSPIM_SCK_SOURCE_OSPI1_SCK))
/* check OSPIM port CSN configuration */
#define NOT_OSPIM_PORT_CSN(csnconfig) (((csnconfig) != OSPIM_PORT_CSN_DISABLE) && ((csnconfig) != OSPIM_PORT_CSN_ENABLE))
/* check OSPIM port CSN source */
#define NOT_OSPIM_PORT_CSN_SOURCE(csn_source) (((csn_source) != OSPIM_CSN_SOURCE_OSPI0_CSN) && ((csn_source) != OSPIM_CSN_SOURCE_OSPI1_CSN))
/* check OSPIM IO[3:0] configuration */
#define NOT_OSPIM_IO_LOW(ioconfig) (((ioconfig) != OSPIM_IO_LOW_DISABLE) && ((ioconfig) != OSPIM_IO_LOW_ENABLE))
/* check the source of OSPIM IO[3:0] */
#define NOT_OSPIM_SRC_LOW(io_source) (((io_source) != OSPIM_SRCPLIO_OSPI0_IO_LOW) && ((io_source) != OSPIM_SRCPLIO_OSPI0_IO_HIGH) && ((io_source) != OSPIM_SRCPLIO_OSPI1_IO_LOW) && ((io_source) != OSPIM_SRCPLIO_OSPI1_IO_HIGH))
/* check OSPIM IO[7:4] configuration */
#define NOT_OSPIM_IO_HIGH(ioconfig) (((ioconfig) != OSPIM_IO_HIGH_DISABLE) && ((ioconfig) != OSPIM_IO_HIGH_ENABLE))
/* check the source of OSPIM IO[7:4] */
#define NOT_OSPIM_SRC_HIGH(io_source) (((io_source) != OSPIM_SRCPHIO_OSPI0_IO_LOW) && ((io_source) != OSPIM_SRCPHIO_OSPI0_IO_HIGH) && ((io_source) != OSPIM_SRCPHIO_OSPI1_IO_LOW) && ((io_source) != OSPIM_SRCPHIO_OSPI1_IO_HIGH))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* reset the OSPIM peripheral */
void ospim_deinit(void);
/* ospim port configuration functions */
/* configurate SCK for port */
void ospim_port_sck_config(uint8_t port, uint32_t sckconfg);
/* select source of SCK for port */
void ospim_port_sck_source_select(uint8_t port, uint32_t sck_source);
/* configurate CSN for port */
void ospim_port_csn_config(uint8_t port, uint32_t csnconfig);
/* select source of CSN for port */
void ospim_port_csn_source_select(uint8_t port, uint32_t csn_source);
/* configurate IO[3:0] for port */
void ospim_port_io3_0_config(uint8_t port, uint32_t ioconfig);
/* select source of IO[3:0] for port */
void ospim_port_io3_0_source_select(uint8_t port, uint32_t io_source);
/* configurate IO[7:4] for port */
void ospim_port_io7_4_config(uint8_t port, uint32_t ioconfig);
/* select source of IO[7:4] for port */
void ospim_port_io7_4_source_select(uint8_t port, uint32_t io_source);
#endif /* GD32H75E_OSPIM_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_pmu.h
+325
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/*!
\file gd32h75e_pmu.h
\brief definitions for the PMU
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_PMU_H
#define GD32H75E_PMU_H
#include "gd32h75e.h"
/* PMU definitions */
#define PMU PMU_BASE /*!< PMU base address */
/* registers definitions */
#define PMU_CTL0 REG32((PMU) + 0x00000000U) /*!< PMU control register 0 */
#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */
#define PMU_CTL1 REG32((PMU) + 0x00000008U) /*!< PMU control register 1 */
#define PMU_CTL2 REG32((PMU) + 0x00000010U) /*!< PMU control register 2 */
#define PMU_CTL3 REG32((PMU) + 0x00000014U) /*!< PMU control register 3 */
#define PMU_PAR REG32((PMU) + 0x00000018U) /*!< PMU parameter register */
/* bits definitions */
/* PMU_CTL0 */
#define PMU_CTL0_STBMOD BIT(1) /*!< standby mode */
#define PMU_CTL0_WURST BIT(2) /*!< wakeup flag reset */
#define PMU_CTL0_STBRST BIT(3) /*!< standby flag reset */
#define PMU_CTL0_LVDEN BIT(4) /*!< low voltage detector enable */
#define PMU_CTL0_LVDT BITS(5,7) /*!< low voltage detector threshold */
#define PMU_CTL0_BKPWEN BIT(8) /*!< backup domain write enable */
#define PMU_CTL0_SLDOVS BITS(14,15) /*!< deep sleep mode mode LDO output voltage select */
#define PMU_CTL0_VAVDEN BIT(16) /*!< VDDA analog voltage detector enable */
#define PMU_CTL0_VAVDVC BITS(17,18) /*!< VDDA analog voltage detector level configure bits */
#define PMU_CTL0_VOVDEN BIT(19) /*!< peripheral voltage on V0.9V detector enable bit */
/* PMU_CS */
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
#define PMU_CS_STBF BIT(1) /*!< standby flag */
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin0(PA0) enable */
#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin1(PA2) enable */
#define PMU_CS_WUPEN3 BIT(11) /*!< wakeup pin3(PC13) enable */
#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin5(PC1) enable */
#define PMU_CS_VAVDF BIT(16) /*!< VDDA analog voltage detector voltage output on VDDA flag */
#define PMU_CS_VOVDF BIT(20) /*!< peripheral voltage on V0.9V detector flag bit */
/* PMU_CTL1 */
#define PMU_CTL1_BKPVSEN BIT(0) /*!< backup voltage stabilizer enable */
#define PMU_CTL1_VBTMEN BIT(4) /*!< VBAT and temperature monitoring enable */
#define PMU_CTL1_BKPVSRF BIT(16) /*!< backup regulator ready */
#define PMU_CTL1_VBATLF BIT(20) /*!< VBAT level monitoring versus low threshold */
#define PMU_CTL1_VBATHF BIT(21) /*!< VBAT level monitoring versus high threshold */
#define PMU_CTL1_TEMPLF BIT(22) /*!< temperature level monitoring versus low threshold */
#define PMU_CTL1_TEMPHF BIT(23) /*!< temperature level monitoring versus high threshold */
/* PMU_CTL2 */
#define PMU_CTL2_BYPASS BIT(0) /*!< power management unit bypass control bit */
#define PMU_CTL2_LDOEN BIT(1) /*!< Low drop-out voltage stabilizer enable bit */
#define PMU_CTL2_DVSEN BIT(2) /*!< step-down voltage stabilizer enable bit */
#define PMU_CTL2_VCRSEL BIT(8) /*!< VBAT battery charging resistor selection */
#define PMU_CTL2_VCEN BIT(9) /*!< VBAT battery charging enable */
#define PMU_CTL2_DVSRF BIT(16) /*!< step-down voltage stabilizer ready flag bit */
#define PMU_CTL2_VUSB33DEN BIT(24) /*!< VDD33USB voltage level detector enable bit */
#define PMU_CTL2_USBSEN BIT(25) /*!< USB voltage stabilizer enable */
#define PMU_CTL2_USB33RF BIT(26) /*!< USB supply ready flag */
/* PMU_CTL3 */
#define PMU_CTL3_LDOVS BITS(12,14) /*!< voltage scaling selection according to performance */
#define PMU_CTL3_VOVRF BIT(16) /*!< V0.9V voltage ready bit */
/* PMU_PAR */
#define PMU_PAR_CNT BITS(0,11) /*!< exit deep-sleep mode wait time count configure bits */
#define PMU_PAR_TSW_IRCCNT BITS(16,20) /*!< when enter deep-sleep, switch to IRC wait clock */
/* constants definitions */
/* PMU low voltage detector threshold definitions */
#define CTL0_LVDT(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U))
#define PMU_LVDT_0 CTL0_LVDT(0) /*!< voltage threshold is 1.90V */
#define PMU_LVDT_1 CTL0_LVDT(1) /*!< voltage threshold is 2.05V */
#define PMU_LVDT_2 CTL0_LVDT(2) /*!< voltage threshold is 2.20V */
#define PMU_LVDT_3 CTL0_LVDT(3) /*!< voltage threshold is 2.35V */
#define PMU_LVDT_4 CTL0_LVDT(4) /*!< voltage threshold is 2.50V */
#define PMU_LVDT_5 CTL0_LVDT(5) /*!< voltage threshold is 2.65V */
#define PMU_LVDT_6 CTL0_LVDT(6) /*!< voltage threshold is 2.80V */
#define PMU_LVDT_7 CTL0_LVDT(7) /*!< input analog voltage on PB7 (compared with 0.8V) */
/* PMU deep-sleep mode voltage scaling selection */
#define CTL0_SLDOVS(regval) (BITS(14,15) & ((uint32_t)(regval) << 14U))
#define PMU_SLDOVS_0 CTL0_SLDOVS(0) /*!< SLDOVS scale 0.6V */
#define PMU_SLDOVS_1 CTL0_SLDOVS(1) /*!< SLDOVS scale 0.7V */
#define PMU_SLDOVS_2 CTL0_SLDOVS(2) /*!< SLDOVS scale 0.8V (default) */
#define PMU_SLDOVS_3 CTL0_SLDOVS(3) /*!< SLDOVS scale 0.9V */
/* PMU analog voltage detector threshold definitions */
#define CTL0_VAVDVC(regval) (BITS(17,18) & ((uint32_t)(regval) << 17U))
#define PMU_VAVDVC_0 CTL0_VAVDVC(0) /*!< voltage threshold is 1.7V */
#define PMU_VAVDVC_1 CTL0_VAVDVC(1) /*!< voltage threshold is 2.1V */
#define PMU_VAVDVC_2 CTL0_VAVDVC(2) /*!< voltage threshold is 2.5V */
#define PMU_VAVDVC_3 CTL0_VAVDVC(3) /*!< voltage threshold is 2.8V */
/* PMU VBAT battery charging resistor selection */
#define CTL2_VCRSEL(regval) (BIT(9) & ((uint32_t)(regval) << 9U))
#define PMU_VCRSEL_5K CTL2_VCRSEL(0) /*!< 5 kOhms resistor is selected for charing VBAT battery */
#define PMU_VCRSEL_1P5K CTL2_VCRSEL(1) /*!< 1.5 kOhms resistor is selected for charing VBAT battery */
/* PMU LDO output voltage select definitions */
#define CTL3_LDOVS(regval) (BITS(12,14) & ((uint32_t)(regval) << 12U))
#define PMU_LDOVS_0 CTL3_LDOVS(0) /*!< LDO output voltage 0.8V mode */
#define PMU_LDOVS_1 CTL3_LDOVS(1) /*!< LDO output voltage 0.85V mode */
#define PMU_LDOVS_2 CTL3_LDOVS(2) /*!< LDO output voltage 0.9V mode */
#define PMU_LDOVS_3 CTL3_LDOVS(3) /*!< LDO output voltage 0.95V mode */
#define PMU_LDOVS_4 CTL3_LDOVS(4) /*!< LDO output voltage 0.975V mode */
#define PMU_LDOVS_5 CTL3_LDOVS(5) /*!< LDO output voltage 1V mode */
/* PMU flag definitions */
#define PMU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define PMU_REG_VAL(periph) (REG32(PMU + ((uint32_t)(periph) >> 6U)))
#define PMU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define PMU_CTL0_OFFSET (0x00000000U) /*!< PMU control register 0 offset */
#define PMU_CS_OFFSET (0x00000004U) /*!< PMU control and status register offset */
#define PMU_CTL1_OFFSET (0x00000008U) /*!< PMU control register 1 offset */
#define PMU_CTL2_OFFSET (0x00000010U) /*!< PMU control register 2 offset */
#define PMU_CTL3_OFFSET (0x00000014U) /*!< PMU control register 3 offset */
#define PMU_PAR_OFFSET (0x00000018U) /*!< PMU parameter register offset */
#define PMU_FLAG_WAKEUP PMU_REGIDX_BIT(PMU_CS_OFFSET, 0) /*!< wakeup flag */
#define PMU_FLAG_STANDBY PMU_REGIDX_BIT(PMU_CS_OFFSET, 1) /*!< standby flag */
#define PMU_FLAG_LVDF PMU_REGIDX_BIT(PMU_CS_OFFSET, 2) /*!< low voltage detector status flag */
#define PMU_FLAG_VAVDF PMU_REGIDX_BIT(PMU_CS_OFFSET, 16) /*!< VDDA analog voltage detector voltage output on VDDA flag */
#define PMU_FLAG_VOVDF PMU_REGIDX_BIT(PMU_CS_OFFSET, 20) /*!< peripheral voltage on VDDA detector flag */
#define PMU_FLAG_BKPVSRF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 16) /*!< backup voltage stabilizer ready flag */
#define PMU_FLAG_VBATLF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 20) /*!< VBAT level monitoring versus low threshold */
#define PMU_FLAG_VBATHF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 21) /*!< VBAT level monitoring versus high threshold */
#define PMU_FLAG_TEMPLF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 22) /*!< temperature level monitoring versus low threshold */
#define PMU_FLAG_TEMPHF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 23) /*!< temperature level monitoring versus high threshold */
#define PMU_FLAG_DVSRF PMU_REGIDX_BIT(PMU_CTL2_OFFSET, 16) /*!< step-down voltage stabilizer ready flag bit */
#define PMU_FLAG_USB33RF PMU_REGIDX_BIT(PMU_CTL2_OFFSET, 26) /*!< USB supply ready flag bit */
#define PMU_FLAG_PWRRF PMU_REGIDX_BIT(PMU_CTL3_OFFSET, 16) /*!< Power Ready flag bit */
/* PMU wakeup pin definitions */
#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< wakeup pin 0 */
#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< wakeup pin 1 */
#define PMU_WAKEUP_PIN3 PMU_CS_WUPEN3 /*!< wakeup pin 3 */
#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< wakeup pin 5 */
/* PMU SMPS LDO supply mode definitions */
#define PMU_LDO_SUPPLY PMU_CTL2_LDOEN /*!< V0.9V domains are suppplied from the LDO */
#define PMU_DIRECT_SMPS_SUPPLY PMU_CTL2_DVSEN /*!< V0.9V domains are suppplied from the SMPS only */
#define PMU_BYPASS PMU_CTL2_BYPASS /*!< The SMPS disabled and the LDO Bypass. The V0.9V domains are supplied from an external source */
/* PMU command constants definitions */
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check PMU low voltage detector threshold */
#define NOT_PMU_LVD(lvdt_n) (((lvdt_n) != PMU_LVDT_0) && ((lvdt_n) != PMU_LVDT_1) && \
((lvdt_n) != PMU_LVDT_2) && ((lvdt_n) != PMU_LVDT_3) && \
((lvdt_n) != PMU_LVDT_4) && ((lvdt_n) != PMU_LVDT_5) && \
((lvdt_n) != PMU_LVDT_6) && ((lvdt_n) != PMU_LVDT_7))
/* check PMU analog voltage detector threshold */
#define NOT_PMU_VAVD(vavdt_n) (((vavdt_n) != PMU_VAVDVC_0) && ((vavdt_n) != PMU_VAVDVC_1) && \
((vavdt_n) != PMU_VAVDVC_2) && ((vavdt_n) != PMU_VAVDVC_3))
/* check PMU V0.9V core voltage level */
#define NOT_PMU_LDO(ldo_n) (((ldo_n) != PMU_LDOVS_0) && ((ldo_n) != PMU_LDOVS_1) && \
((ldo_n) != PMU_LDOVS_2) && ((ldo_n) != PMU_LDOVS_3) && \
((ldo_n) != PMU_LDOVS_4) && ((ldo_n) != PMU_LDOVS_5))
/* check PMU Deep-sleep mode V0.9V core voltage select */
#define NOT_PMU_SLDO(sldo_n) (((sldo_n) != PMU_SLDOVS_0) && ((sldo_n) != PMU_SLDOVS_1) && \
((sldo_n) != PMU_SLDOVS_2) && ((sldo_n) != PMU_SLDOVS_3))
/* check PMU VBAT battery charging resistor selection */
#define NOT_PMU_VBAT(resistor) (((resistor) != PMU_VCRSEL_5K) && ((resistor) != PMU_VCRSEL_1P5K))
/* check PMU power supply */
#define NOT_PMU_SMPS_LDO_SUPPLY(smpsmode) (((smpsmode) != PMU_LDO_SUPPLY) && ((smpsmode) != PMU_DIRECT_SMPS_SUPPLY) && \
((smpsmode) != PMU_BYPASS))
/* check PMU sleep mode */
#define NOT_PMU_SLEEPMODE(sleepmodecmd) (((sleepmodecmd) != WFI_CMD) && ((sleepmodecmd) != WFE_CMD))
/* check PMU deepsleep mode */
#define NOT_PMU_DEEPSLEEPMODE(deepsleepmodecmd) (((deepsleepmodecmd) != WFI_CMD) && ((deepsleepmodecmd) != WFE_CMD))
/* check PMU wakeup pin */
#define NOT_PMU_WAKEUP_PIN(wakeup_pin) (((wakeup_pin) != PMU_WAKEUP_PIN0) && ((wakeup_pin) != PMU_WAKEUP_PIN1) && \
((wakeup_pin) != PMU_WAKEUP_PIN3) && ((wakeup_pin) != PMU_WAKEUP_PIN5))
/* check PMU IRC counter before enter Deep-sleep mode */
#define NOT_PMU_ENTER_DEEPSLEEP_WAIT_TIME(wait_time) (((wait_time) > 0x1F) || ((wait_time) < 0x0))
/* check PMU IRC counter before exit Deep-sleep mode */
#define NOT_PMU_EXIT_DEEPSLEEP_WAIT_TIME(wait_time) (((wait_time) > 0xFFF) || ((wait_time) < 0x0))
/* check PMU flag state */
#define NOT_PMU_FLAG(flag) (((flag) != PMU_FLAG_WAKEUP) && ((flag) != PMU_FLAG_STANDBY) && \
((flag) != PMU_FLAG_LVDF) && ((flag) != PMU_FLAG_VAVDF) && \
((flag) != PMU_FLAG_VOVDF) && ((flag) != PMU_FLAG_VBATLF) && \
((flag) != PMU_FLAG_VBATHF) && ((flag) != PMU_FLAG_TEMPLF) && \
((flag) != PMU_FLAG_TEMPHF) && ((flag) != PMU_FLAG_DVSRF) && \
((flag) != PMU_FLAG_USB33RF) && ((flag) != PMU_FLAG_PWRRF))
/* check PMU reset flag state */
#define NOT_PMU_FLAG_RESET(flag_reset) (((flag_reset) != PMU_FLAG_WAKEUP) && ((flag_reset) != PMU_FLAG_STANDBY))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* reset PMU registers */
void pmu_deinit(void);
/* select low voltage detector threshold */
void pmu_lvd_select(uint32_t lvdt_n);
/* enable PMU lvd */
void pmu_lvd_enable(void);
/* disable PMU lvd */
void pmu_lvd_disable(void);
/* select analog voltage detector threshold */
void pmu_vavd_select(uint32_t vavdt_n);
/* enable PMU analog voltage detector */
void pmu_vavd_enable(void);
/* disable PMU analog voltage detector */
void pmu_vavd_disable(void);
/* enable PMU core voltage detector */
void pmu_vovd_enable(void);
/* disable PMU V0.9V core voltage detector */
void pmu_vovd_disable(void);
/* control the V0.9V core voltage level */
void pmu_ldo_output_select(uint32_t ldo_n);
/* Deep-sleep mode V0.9V core voltage select */
void pmu_sldo_output_select(uint32_t sldo_n);
/* PMU VBAT battery charging resistor selection */
void pmu_vbat_charging_select(uint32_t resistor);
/* enable VBAT battery charging */
void pmu_vbat_charging_enable(void);
/* disable VBAT battery charging */
void pmu_vbat_charging_disable(void);
/* enable VBAT and temperature monitoring */
void pmu_vbat_temp_moniter_enable(void);
/* disable VBAT and temperature monitoring */
void pmu_vbat_temp_moniter_disable(void);
/* USB regulator */
/* enable USB regulator */
void pmu_usb_regulator_enable(void);
/* disable USB regulator */
void pmu_usb_regulator_disable(void);
/* enable VDD33USB voltage level detector */
void pmu_usb_voltage_detector_enable(void);
/* disable VDD33USB voltage level detector */
void pmu_usb_voltage_detector_disable(void);
/* power supply configurations */
void pmu_smps_ldo_supply_config(uint32_t smpsmode);
/* set PMU mode */
/* enter sleep mode */
void pmu_to_sleepmode(uint8_t sleepmodecmd);
/* enter deepsleep mode */
void pmu_to_deepsleepmode(uint8_t deepsleepmodecmd);
/* enter standby mode */
void pmu_to_standbymode(void);
/* enable PMU wakeup pin */
void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
/* disable PMU wakeup pin */
void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
/* backup related functions */
/* enable backup domain write */
void pmu_backup_write_enable(void);
/* disable backup domain write */
void pmu_backup_write_disable(void);
/* enable backup voltage stabilizer */
void pmu_backup_voltage_stabilizer_enable(void);
/* disable backup voltage stabilizer */
void pmu_backup_voltage_stabilizer_disable(void);
/* configure IRC counter before enter Deep-sleep mode */
void pmu_enter_deepsleep_wait_time_config(int32_t wait_time);
/* configure IRC counter before exit Deep-sleep mode */
void pmu_exit_deepsleep_wait_time_config(int32_t wait_time);
/* flag functions */
/* get flag state */
FlagStatus pmu_flag_get(uint32_t flag);
/* clear flag bit */
void pmu_flag_clear(uint32_t flag_reset);
#endif /* GD32H75E_PMU_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_rameccmu.h
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/*!
\file gd32h75e_rameccmu.h
\brief definitions for the RAMECCMU
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_RAMECCMU_H
#define GD32H75E_RAMECCMU_H
#include "gd32h75e.h"
/* RAMECCMU definitions */
#define RAMECCMU0 (RAMECCMU_BASE + 0x09FE6000U) /*!< RAMECCMU for Region 0 */
#define RAMECCMU1 RAMECCMU_BASE /*!< RAMECCMU for Region 1 */
/* registers definitions */
#define RAMECCMU_INT(rameccmux) REG32((rameccmux) + 0x00000000U) /*!< RAMECCMU global interruput register */
#define RAMECCMU_M0CTL(rameccmux) REG32((rameccmux) + 0x00000020U) /*!< RAMECCMU monitor 0 control register */
#define RAMECCMU_M0STAT(rameccmux) REG32((rameccmux) + 0x00000024U) /*!< RAMECCMU monitor 0 status register */
#define RAMECCMU_M0FADDR(rameccmux) REG32((rameccmux) + 0x00000028U) /*!< RAMECCMU monitor 0 ECC failing address register */
#define RAMECCMU_M0FDL(rameccmux) REG32((rameccmux) + 0x0000002CU) /*!< RAMECCMU monitor 0 ECC failing data low register */
#define RAMECCMU_M0FDH(rameccmux) REG32((rameccmux) + 0x00000030U) /*!< RAMECCMU monitor 0 ECC failing data high register */
#define RAMECCMU_M0FECODE(rameccmux) REG32((rameccmux) + 0x00000034U) /*!< RAMECCMU monitor 0 failing ECC error code register */
#define RAMECCMU_M1CTL(rameccmux) REG32((rameccmux) + 0x00000040U) /*!< RAMECCMU monitor 1 control register */
#define RAMECCMU_M1STAT(rameccmux) REG32((rameccmux) + 0x00000044U) /*!< RAMECCMU monitor 1 status register */
#define RAMECCMU_M1FADDR(rameccmux) REG32((rameccmux) + 0x00000048U) /*!< RAMECCMU monitor 1 ECC failing address register */
#define RAMECCMU_M1FDL(rameccmux) REG32((rameccmux) + 0x0000004CU) /*!< RAMECCMU monitor 1 ECC failing data low register */
#define RAMECCMU_M1FDH(rameccmux) REG32((rameccmux) + 0x00000050U) /*!< RAMECCMU monitor 1 ECC failing data high register */
#define RAMECCMU_M1FECODE(rameccmux) REG32((rameccmux) + 0x00000054U) /*!< RAMECCMU monitor 1 failing ECC error code register */
#define RAMECCMU_M2CTL(rameccmux) REG32((rameccmux) + 0x00000060U) /*!< RAMECCMU monitor 2 control register */
#define RAMECCMU_M2STAT(rameccmux) REG32((rameccmux) + 0x00000064U) /*!< RAMECCMU monitor 2 status register */
#define RAMECCMU_M2FADDR(rameccmux) REG32((rameccmux) + 0x00000068U) /*!< RAMECCMU monitor 2 ECC failing address register */
#define RAMECCMU_M2FDL(rameccmux) REG32((rameccmux) + 0x0000006CU) /*!< RAMECCMU monitor 2 ECC failing data low register */
#define RAMECCMU_M2FDH(rameccmux) REG32((rameccmux) + 0x00000070U) /*!< RAMECCMU monitor 2 ECC failing data high register */
#define RAMECCMU_M2FECODE(rameccmux) REG32((rameccmux) + 0x00000074U) /*!< RAMECCMU monitor 2 failing ECC error code register */
#define RAMECCMU_M3CTL(rameccmux) REG32((rameccmux) + 0x00000080U) /*!< RAMECCMU monitor 3 control register */
#define RAMECCMU_M3STAT(rameccmux) REG32((rameccmux) + 0x00000084U) /*!< RAMECCMU monitor 3 status register */
#define RAMECCMU_M3FADDR(rameccmux) REG32((rameccmux) + 0x00000088U) /*!< RAMECCMU monitor 3 ECC failing address register */
#define RAMECCMU_M3FDL(rameccmux) REG32((rameccmux) + 0x0000008CU) /*!< RAMECCMU monitor 3 ECC failing data low register */
#define RAMECCMU_M3FDH(rameccmux) REG32((rameccmux) + 0x00000090U) /*!< RAMECCMU monitor 3 ECC failing data high register */
#define RAMECCMU_M3FECODE(rameccmux) REG32((rameccmux) + 0x00000094U) /*!< RAMECCMU monitor 3 failing ECC error code register */
#define RAMECCMU_M4CTL(rameccmux) REG32((rameccmux) + 0x000000A0U) /*!< RAMECCMU monitor 4 control register */
#define RAMECCMU_M4STAT(rameccmux) REG32((rameccmux) + 0x000000A4U) /*!< RAMECCMU monitor 4 status register */
#define RAMECCMU_M4FADDR(rameccmux) REG32((rameccmux) + 0x000000A8U) /*!< RAMECCMU monitor 4 ECC failing address register */
#define RAMECCMU_M4FDL(rameccmux) REG32((rameccmux) + 0x000000ACU) /*!< RAMECCMU monitor 4 ECC failing data low register */
#define RAMECCMU_M4FDH(rameccmux) REG32((rameccmux) + 0x000000B0U) /*!< RAMECCMU monitor 4 ECC failing data high register */
#define RAMECCMU_M4FECODE(rameccmux) REG32((rameccmux) + 0x000000B4U) /*!< RAMECCMU monitor 4 failing ECC error code register */
/* bits definitions */
/* RAMECCMU_INT */
#define RAMECCMU_INT_GEIE BIT(0) /*!< global ECC interrupt enable */
#define RAMECCMU_INT_GESERRIE BIT(1) /*!< global ECC single error interrupt enable */
#define RAMECCMU_INT_GEDERRIE BIT(2) /*!< global ECC double error interrupt enable */
#define RAMECCMU_INT_GEDERRBWIE BIT(3) /*!< global ECC double error on byte write interrupt enable */
/* RAMECCMU_MxCTL */
#define RAMECCMU_MXCTL_ECCSERRIE BIT(2) /*!< ECC single error interrupt enable */
#define RAMECCMU_MXCTL_ECCDERRIE BIT(3) /*!< ECC double error interrupt enable */
#define RAMECCMU_MXCTL_ECCDERRBWIE BIT(4) /*!< ECC double error on byte write interrupt enable */
#define RAMECCMU_MXCTL_ECCERRLATEN BIT(5) /*!< ECC error latching enable */
/* RAMECCMU_MxSTAT */
#define RAMECCMU_MXSTAT_ECCSERRDCF BIT(0) /*!< ECC single error detected and corrected flag */
#define RAMECCMU_MXSTAT_ECCDERRDF BIT(1) /*!< ECC double error detected flag */
#define RAMECCMU_MXSTAT_ECCDERRBWDF BIT(2) /*!< ECC double error on byte write detected flag */
/* RAMECCMU_MxFADDR */
#define RAMECCMU_MXFADDR_ECCFADDR BITS(0,31) /*!< ECC error failing address */
/* RAMECCMU_MxFDL */
#define RAMECCMU_MXFDL_ECCFDL BITS(0,31) /*!< ECC failing data low bits */
/* RAMECCMU_MxFDH */
#define RAMECCMU_MXFDH_ECCFDH BITS(0,31) /*!< ECC failing data high bits */
/* RAMECCMU_MxFECODE */
#define RAMECCMU_MXFECODE_ECCFECODE BITS(0,31) /*!< ECC failing error code */
/* constants definitions */
/* RAMECCMU monitor select */
typedef enum
{
RAMECCMU0_MONITOR0 = 0x00U, /*!< RAMECCMU0 monitor 0 */
RAMECCMU0_MONITOR1 = 0x01U, /*!< RAMECCMU0 monitor 1 */
RAMECCMU0_MONITOR2 = 0x02U, /*!< RAMECCMU0 monitor 2 */
RAMECCMU0_MONITOR3 = 0x03U, /*!< RAMECCMU0 monitor 3 */
RAMECCMU0_MONITOR4 = 0x04U, /*!< RAMECCMU0 monitor 4 */
RAMECCMU1_MONITOR0 = 0x10U, /*!< RAMECCMU1 monitor 0 */
RAMECCMU1_MONITOR1 = 0x11U, /*!< RAMECCMU1 monitor 1 */
RAMECCMU1_MONITOR2 = 0x12U /*!< RAMECCMU1 monitor 2 */
} rameccmu_monitor_enum;
/* RAMECCMUx monitor register address */
#define RAMECCMU_MXCTL(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x20U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor control register */
#define RAMECCMU_MXSTAT(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x24U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor status register */
#define RAMECCMU_MXFADDR(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x28U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing address register */
#define RAMECCMU_MXFDL(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x2CU + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing data low register */
#define RAMECCMU_MXFDH(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x30U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor ECC failing data high register */
#define RAMECCMU_MXFECODE(rameccmu_monitor) REG32(RAMECCMU0 - ((uint32_t)(rameccmu_monitor) >> 4U)*0x09FE6000U + 0x34U + ((rameccmu_monitor) & 0x0FU) * 0x20U) /*!< RAMECCMU monitor failing ECC error code register */
#define RAMECCMU_INT_ECC_GLOBAL_ERROR BIT(0) /*!< ECC global error interrupt */
#define RAMECCMU_INT_ECC_SINGLE_ERROR BIT(1) /*!< ECC single error interrupt */
#define RAMECCMU_INT_ECC_DOUBLE_ERROR BIT(2) /*!< ECC double error interrupt */
#define RAMECCMU_INT_ECC_DOUBLE_ERROR_BYTE_WRITE BIT(3) /*!< ECC double error on byte write interrupt */
#define RAMECCMU_INT_ECC_ERROR_LATCHING BIT(4) /*!< ECC error latching */
#define RAMECCMU_FLAG_ECC_SINGLE_ERROR RAMECCMU_MXSTAT_ECCSERRDCF /*!< ECC single error detected and corrected flag */
#define RAMECCMU_FLAG_ECC_DOUBLE_ERROR RAMECCMU_MXSTAT_ECCDERRDF /*!< ECC double error detected flag */
#define RAMECCMU_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE RAMECCMU_MXSTAT_ECCDERRBWDF /*!< ECC double error on byte write detected flag */
#define RAMECCMU_INT_FLAG_ECC_SINGLE_ERROR RAMECCMU_MXSTAT_ECCSERRDCF /*!< ECC single error detected and corrected flag */
#define RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR RAMECCMU_MXSTAT_ECCDERRDF /*!< ECC double error detected flag */
#define RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE RAMECCMU_MXSTAT_ECCDERRBWDF /*!< ECC double error on byte write detected flag */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
#define NOT_RAMECCMU_PERIPH(xxx) (((xxx) != RAMECCMU0) && ((xxx) != RAMECCMU1))
#define NOT_RAMECCMU_MONITOR(xxx) (((xxx) != RAMECCMU0_MONITOR0) && ((xxx) != RAMECCMU0_MONITOR1) && \
((xxx) != RAMECCMU0_MONITOR2) && ((xxx) != RAMECCMU0_MONITOR3) && \
((xxx) != RAMECCMU0_MONITOR4) && ((xxx) != RAMECCMU1_MONITOR0) && \
((xxx) != RAMECCMU1_MONITOR1) && ((xxx) != RAMECCMU1_MONITOR2))
#define NOT_RAMECCMU_INT_ERROR(xxx) (((xxx) != RAMECCMU_INT_ECC_GLOBAL_ERROR) && ((xxx) != RAMECCMU_INT_ECC_SINGLE_ERROR) && \
((xxx) != RAMECCMU_INT_ECC_DOUBLE_ERROR) && ((xxx) != RAMECCMU_INT_ECC_DOUBLE_ERROR_BYTE_WRITE))
#define NOT_RAMECCMU_MONITOR_INT_ERROR(xxx) (((xxx) != RAMECCMU_INT_ECC_SINGLE_ERROR) && ((xxx) != RAMECCMU_INT_ECC_DOUBLE_ERROR) && \
((xxx) != RAMECCMU_INT_ECC_DOUBLE_ERROR_BYTE_WRITE) && ((xxx) != RAMECCMU_INT_ECC_ERROR_LATCHING))
#define NOT_RAMECCMU_FLAG_ECC_ERROR(xxx) (((xxx) != RAMECCMU_FLAG_ECC_SINGLE_ERROR) && ((xxx) != RAMECCMU_FLAG_ECC_DOUBLE_ERROR) && \
((xxx) != RAMECCMU_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE))
#define NOT_RAMECCMU_INT_FLAG_ECC_ERROR(xxx) (((xxx) != RAMECCMU_INT_FLAG_ECC_SINGLE_ERROR) && ((xxx) != RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR) && \
((xxx) != RAMECCMU_INT_FLAG_ECC_DOUBLE_ERROR_BYTE_WRITE))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* deinit RAMECCMU unit */
void rameccmu_deinit(uint32_t rameccmu_periph);
/* RAMECCMU monitor ECC functions */
/* get RAMECCMU monitor ECC failing address */
uint32_t rameccmu_monitor_failing_address_get(rameccmu_monitor_enum rameccmu_monitor);
/* get RAMECCMU monitor ECC failing data low 32 bits */
uint32_t rameccmu_monitor_failing_data_low_bits_get(rameccmu_monitor_enum rameccmu_monitor);
/* get RAMECCMU monitor ECC failing data high 32 bits */
uint32_t rameccmu_monitor_failing_data_high_bits_get(rameccmu_monitor_enum rameccmu_monitor);
/* get RAMECCMU monitor failing ECC error code */
uint32_t rameccmu_monitor_failing_ecc_error_code_get(rameccmu_monitor_enum rameccmu_monitor);
/* interrupt & flag functions */
/* enable RAMECCMU global ECC interruput */
void rameccmu_global_interrupt_enable(uint32_t rameccmu_periph, uint32_t interrupt);
/* disable RAMECCMU global ECC interruput */
void rameccmu_global_interrupt_disable(uint32_t rameccmu_periph, uint32_t interrupt);
/* enable RAMECCMU monitor ECC error interruput */
void rameccmu_monitor_interrupt_enable(rameccmu_monitor_enum rameccmu_monitor, uint32_t monitor_interrupt);
/* disable RAMECCMU monitor ECC error interruput */
void rameccmu_monitor_interrupt_disable(rameccmu_monitor_enum rameccmu_monitor, uint32_t monitor_interrupt);
/* get RAMECCMU monitor ECC error flag */
FlagStatus rameccmu_monitor_flag_get(rameccmu_monitor_enum rameccmu_monitor, uint32_t flag);
/* clear RAMECCMU monitor ECC error flag */
void rameccmu_monitor_flag_clear(rameccmu_monitor_enum rameccmu_monitor, uint32_t flag);
/* get RAMECCMU monitor ECC interrupt error flag */
FlagStatus rameccmu_monitor_interrupt_flag_get(rameccmu_monitor_enum rameccmu_monitor, uint32_t int_flag);
/* clear RAMECCMU monitor interrupt ECC error flag */
void rameccmu_monitor_interrupt_flag_clear(rameccmu_monitor_enum rameccmu_monitor, uint32_t int_flag);
#endif /* GD32H75E_RAMECCMU_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_rcu.h
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828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_rtc.h
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/*!
\file gd32h75e_rtc.h
\brief definitions for the RTC
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_RTC_H
#define GD32H75E_RTC_H
#include "gd32h75e.h"
/* RTC definitions */
#define RTC RTC_BASE /* RTC base address */
/* registers definitions */
#define RTC_TIME REG32((RTC) + 0x00000000U) /*!< RTC time of day register */
#define RTC_DATE REG32((RTC) + 0x00000004U) /*!< RTC date register */
#define RTC_CTL REG32((RTC) + 0x00000008U) /*!< RTC control register */
#define RTC_STAT REG32((RTC) + 0x0000000CU) /*!< RTC status register */
#define RTC_PSC REG32((RTC) + 0x00000010U) /*!< RTC time prescaler register */
#define RTC_WUT REG32((RTC) + 0x00000014U) /*!< RTC wakeup timer regiser */
#define RTC_ALRM0TD REG32((RTC) + 0x0000001CU) /*!< RTC alarm 0 time and date register */
#define RTC_ALRM1TD REG32((RTC) + 0x00000020U) /*!< RTC alarm 1 time and date register */
#define RTC_WPK REG32((RTC) + 0x00000024U) /*!< RTC write protection key register */
#define RTC_SS REG32((RTC) + 0x00000028U) /*!< RTC sub second register */
#define RTC_SHIFTCTL REG32((RTC) + 0x0000002CU) /*!< RTC shift function control register */
#define RTC_TTS REG32((RTC) + 0x00000030U) /*!< RTC time of timestamp register */
#define RTC_DTS REG32((RTC) + 0x00000034U) /*!< RTC date of timestamp register */
#define RTC_SSTS REG32((RTC) + 0x00000038U) /*!< RTC sub second of timestamp register */
#define RTC_HRFC REG32((RTC) + 0x0000003CU) /*!< RTC high resolution frequency compensation register */
#define RTC_TAMP REG32((RTC) + 0x00000040U) /*!< RTC tamper register */
#define RTC_ALRM0SS REG32((RTC) + 0x00000044U) /*!< RTC alarm 0 sub second register */
#define RTC_ALRM1SS REG32((RTC) + 0x00000048U) /*!< RTC alarm 1 sub second register */
#define RTC_CFG REG32((RTC) + 0x0000004CU) /*!< RTC configure register */
#define RTC_BKP0 REG32((RTC) + 0x00000050U) /*!< RTC backup 0 register */
#define RTC_BKP1 REG32((RTC) + 0x00000054U) /*!< RTC backup 1 register */
#define RTC_BKP2 REG32((RTC) + 0x00000058U) /*!< RTC backup 2 register */
#define RTC_BKP3 REG32((RTC) + 0x0000005CU) /*!< RTC backup 3 register */
#define RTC_BKP4 REG32((RTC) + 0x00000060U) /*!< RTC backup 4 register */
#define RTC_BKP5 REG32((RTC) + 0x00000064U) /*!< RTC backup 5 register */
#define RTC_BKP6 REG32((RTC) + 0x00000068U) /*!< RTC backup 6 register */
#define RTC_BKP7 REG32((RTC) + 0x0000006CU) /*!< RTC backup 7 register */
#define RTC_BKP8 REG32((RTC) + 0x00000070U) /*!< RTC backup 8 register */
#define RTC_BKP9 REG32((RTC) + 0x00000074U) /*!< RTC backup 9 register */
#define RTC_BKP10 REG32((RTC) + 0x00000078U) /*!< RTC backup 10 register */
#define RTC_BKP11 REG32((RTC) + 0x0000007CU) /*!< RTC backup 11 register */
#define RTC_BKP12 REG32((RTC) + 0x00000080U) /*!< RTC backup 12 register */
#define RTC_BKP13 REG32((RTC) + 0x00000084U) /*!< RTC backup 13 register */
#define RTC_BKP14 REG32((RTC) + 0x00000088U) /*!< RTC backup 14 register */
#define RTC_BKP15 REG32((RTC) + 0x0000008CU) /*!< RTC backup 15 register */
#define RTC_BKP16 REG32((RTC) + 0x00000090U) /*!< RTC backup 16 register */
#define RTC_BKP17 REG32((RTC) + 0x00000094U) /*!< RTC backup 17 register */
#define RTC_BKP18 REG32((RTC) + 0x00000098U) /*!< RTC backup 18 register */
#define RTC_BKP19 REG32((RTC) + 0x0000009CU) /*!< RTC backup 19 register */
#define RTC_BKP20 REG32((RTC) + 0x000000A0U) /*!< RTC backup 20 register */
#define RTC_BKP21 REG32((RTC) + 0x000000A4U) /*!< RTC backup 21 register */
#define RTC_BKP22 REG32((RTC) + 0x000000A8U) /*!< RTC backup 22 register */
#define RTC_BKP23 REG32((RTC) + 0x000000ACU) /*!< RTC backup 23 register */
#define RTC_BKP24 REG32((RTC) + 0x000000B0U) /*!< RTC backup 24 register */
#define RTC_BKP25 REG32((RTC) + 0x000000B4U) /*!< RTC backup 25 register */
#define RTC_BKP26 REG32((RTC) + 0x000000B8U) /*!< RTC backup 26 register */
#define RTC_BKP27 REG32((RTC) + 0x000000BCU) /*!< RTC backup 27 register */
#define RTC_BKP28 REG32((RTC) + 0x000000C0U) /*!< RTC backup 28 register */
#define RTC_BKP29 REG32((RTC) + 0x000000C4U) /*!< RTC backup 29 register */
#define RTC_BKP30 REG32((RTC) + 0x000000C8U) /*!< RTC backup 30 register */
#define RTC_BKP31 REG32((RTC) + 0x000000CCU) /*!< RTC backup 31 register */
/* bits definitions */
/* RTC_TIME */
#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */
#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */
#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */
#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */
#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */
#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */
#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */
/* RTC_DATE */
#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */
#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */
#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */
#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */
#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */
#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */
#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */
/* RTC_CTL */
#define RTC_CTL_WTCS BITS(0,2) /*!< auto wakeup timer clock selection */
#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */
#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */
#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */
#define RTC_CTL_CS BIT(6) /*!< display format of clock system */
#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm0 function enable */
#define RTC_CTL_ALRM1EN BIT(9) /*!< alarm1 function enable */
#define RTC_CTL_WTEN BIT(10) /*!< auto wakeup timer function enable */
#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */
#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm0 interrupt enable */
#define RTC_CTL_ALRM1IE BIT(13) /*!< RTC alarm1 interrupt enable */
#define RTC_CTL_WTIE BIT(14) /*!< auto wakeup timer interrupt enable */
#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */
#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */
#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */
#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */
#define RTC_CTL_COS BIT(19) /*!< calibration output selection */
#define RTC_CTL_OPOL BIT(20) /*!< output polarity */
#define RTC_CTL_OS BITS(21,22) /*!< output selection */
#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */
#define RTC_CTL_ITSEN BIT(24) /*!< internal timestamp event enable */
/* RTC_STAT */
#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm0 configuration can be write flag */
#define RTC_STAT_ALRM1WF BIT(1) /*!< alarm1 configuration can be write flag */
#define RTC_STAT_WTWF BIT(2) /*!< wakeup timer can be write flag */
#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */
#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */
#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */
#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */
#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */
#define RTC_STAT_ALRM0F BIT(8) /*!< alarm0 occurs flag */
#define RTC_STAT_ALRM1F BIT(9) /*!< alarm1 occurs flag */
#define RTC_STAT_WTF BIT(10) /*!< wakeup timer flag */
#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */
#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */
#define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */
#define RTC_STAT_TP1F BIT(15) /*!< RTC tamp 1 detected flag */
#define RTC_STAT_SCPF BIT(16) /*!< Smooth calibration pending flag */
#define RTC_STAT_ITSF BIT(17) /*!< Internal timestamp flag */
/* RTC_PSC */
#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */
#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */
/* RTC_WUT */
#define RTC_WUT_WTRV BITS(0,15) /*!< auto wakeup timer reloads value */
/* RTC_ALRMxTD */
#define RTC_ALRMXTD_SCU BITS(0,3) /*!< second units in BCD code */
#define RTC_ALRMXTD_SCT BITS(4,6) /*!< second tens in BCD code */
#define RTC_ALRMXTD_MSKS BIT(7) /*!< alarm second mask bit */
#define RTC_ALRMXTD_MNU BITS(8,11) /*!< minutes units in BCD code */
#define RTC_ALRMXTD_MNT BITS(12,14) /*!< minutes tens in BCD code */
#define RTC_ALRMXTD_MSKM BIT(15) /*!< alarm minutes mask bit */
#define RTC_ALRMXTD_HRU BITS(16,19) /*!< hour units in BCD code */
#define RTC_ALRMXTD_HRT BITS(20,21) /*!< hour tens in BCD code */
#define RTC_ALRMXTD_PM BIT(22) /*!< AM/PM flag */
#define RTC_ALRMXTD_MSKH BIT(23) /*!< alarm hour mask bit */
#define RTC_ALRMXTD_DAYU BITS(24,27) /*!< date units or week day in BCD code */
#define RTC_ALRMXTD_DAYT BITS(28,29) /*!< date tens in BCD code */
#define RTC_ALRMXTD_DOWS BIT(30) /*!< day of week selection */
#define RTC_ALRMXTD_MSKD BIT(31) /*!< alarm date mask bit */
/* RTC_WPK */
#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */
/* RTC_SS */
#define RTC_SS_SSC BITS(0,15) /*!< sub second value */
/* RTC_SHIFTCTL */
#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */
#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */
/* RTC_TTS */
#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */
#define RTC_TTS_SCT BITS(4,6) /*!< second tens in BCD code */
#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */
#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */
#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */
#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */
#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */
/* RTC_DTS */
#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */
#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */
#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */
#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */
#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */
/* RTC_SSTS */
#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */
/* RTC_HRFC */
#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */
#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */
#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 8 seconds */
#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */
/* RTC_TAMP */
#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */
#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */
#define RTC_TAMP_TPIE BIT(2) /*!< enable tamper interrupt */
#define RTC_TAMP_TP1EN BIT(5) /*!< tamper 1 detection enable */
#define RTC_TAMP_TP1EG BIT(6) /*!< tamper 1 event trigger edge for RTC tamp 1 input */
#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */
#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */
#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */
#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */
#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */
/* RTC_ALRM0SS */
#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm0 sub second value */
#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */
/* RTC_ALRM1SS */
#define RTC_ALRM1SS_SSC BITS(0,14) /*!< alarm1 sub second value */
#define RTC_ALRM1SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */
/* RTC_CFG */
#define RTC_CFG_OUT2EN BIT(1) /*!< RTC_OUT is output on PB2 or PC13 */
#define RTC_CFG_ALRMOUTTYPE BIT(0) /*!< RTC_ALARM output is Push-pull output type */
/* RTC_BKP0 */
#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP1 */
#define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP2 */
#define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP3 */
#define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP4 */
#define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP5 */
#define RTC_BKP5_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP6 */
#define RTC_BKP6_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP7 */
#define RTC_BKP7_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP8 */
#define RTC_BKP8_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP9 */
#define RTC_BKP9_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP10 */
#define RTC_BKP10_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP11 */
#define RTC_BKP11_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP12 */
#define RTC_BKP12_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP13 */
#define RTC_BKP13_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP14 */
#define RTC_BKP14_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP15 */
#define RTC_BKP15_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP16 */
#define RTC_BKP16_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP17 */
#define RTC_BKP17_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP18 */
#define RTC_BKP18_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP19 */
#define RTC_BKP19_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP20 */
#define RTC_BKP20_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP21 */
#define RTC_BKP21_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP22 */
#define RTC_BKP22_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP23 */
#define RTC_BKP23_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP24 */
#define RTC_BKP24_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP25 */
#define RTC_BKP25_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP26 */
#define RTC_BKP26_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP27 */
#define RTC_BKP27_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP28 */
#define RTC_BKP28_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP29 */
#define RTC_BKP29_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP30 */
#define RTC_BKP30_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP31 */
#define RTC_BKP31_DATA BITS(0,31) /*!< backup domain registers */
/* constants definitions */
/* structure for initialization of the RTC */
typedef struct {
uint8_t year; /*!< RTC year value: 0x0 - 0x99(BCD format) */
uint8_t month; /*!< RTC month value */
uint8_t date; /*!< RTC date value: 0x1 - 0x31(BCD format) */
uint8_t day_of_week; /*!< RTC weekday value */
uint8_t hour; /*!< RTC hour value */
uint8_t minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */
uint8_t second; /*!< RTC second value: 0x0 - 0x59(BCD format) */
uint16_t factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */
uint16_t factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */
uint32_t am_pm; /*!< RTC AM/PM value */
uint32_t display_format; /*!< RTC time notation */
} rtc_parameter_struct;
/* structure for RTC alarm configuration */
typedef struct {
uint32_t alarm_mask; /*!< RTC alarm mask */
uint32_t weekday_or_date; /*!< specify RTC alarm is on date or weekday */
uint8_t alarm_day; /*!< RTC alarm date or weekday value*/
uint8_t alarm_hour; /*!< RTC alarm hour value */
uint8_t alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */
uint8_t alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */
uint32_t am_pm; /*!< RTC alarm AM/PM value */
} rtc_alarm_struct;
/* structure for RTC time-stamp configuration */
typedef struct {
uint8_t timestamp_month; /*!< RTC time-stamp month value */
uint8_t timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */
uint8_t timestamp_day; /*!< RTC time-stamp weekday value */
uint8_t timestamp_hour; /*!< RTC time-stamp hour value */
uint8_t timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */
uint8_t timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */
uint32_t am_pm; /*!< RTC time-stamp AM/PM value */
} rtc_timestamp_struct;
/* structure for RTC tamper configuration */
typedef struct {
uint32_t tamper_source; /*!< RTC tamper source */
uint32_t tamper_trigger; /*!< RTC tamper trigger */
uint32_t tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */
uint32_t tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */
ControlStatus tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */
uint32_t tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */
ControlStatus tamper_with_timestamp; /*!< RTC tamper time-stamp feature */
} rtc_tamper_struct;
/* time register value */
#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TIME_SC bit field */
#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */
#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TIME_MN bit field */
#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */
#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TIME_HR bit field */
#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */
#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */
#define RTC_PM RTC_TIME_PM /*!< PM format */
/* date register value */
#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DATE_DAY bit field */
#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */
#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DATE_MON bit field */
#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */
#define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */
#define RTC_FEB ((uint8_t)0x02U) /*!< February */
#define RTC_MAR ((uint8_t)0x03U) /*!< March */
#define RTC_APR ((uint8_t)0x04U) /*!< April */
#define RTC_MAY ((uint8_t)0x05U) /*!< May */
#define RTC_JUN ((uint8_t)0x06U) /*!< June */
#define RTC_JUL ((uint8_t)0x07U) /*!< July */
#define RTC_AUG ((uint8_t)0x08U) /*!< August */
#define RTC_SEP ((uint8_t)0x09U) /*!< September */
#define RTC_OCT ((uint8_t)0x10U) /*!< October */
#define RTC_NOV ((uint8_t)0x11U) /*!< November */
#define RTC_DEC ((uint8_t)0x12U) /*!< December */
#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DATE_DOW bit field */
#define GET_DATE_DOW(regval) GET_BITS((uint32_t)(regval),13,15) /*!< get value of RTC_DATE_DOW bit field */
#define RTC_MONDAY ((uint8_t)0x01) /*!< monday */
#define RTC_TUESDAY ((uint8_t)0x02) /*!< tuesday */
#define RTC_WEDNESDAY ((uint8_t)0x03) /*!< wednesday */
#define RTC_THURSDAY ((uint8_t)0x04) /*!< thursday */
#define RTC_FRIDAY ((uint8_t)0x05) /*!< friday */
#define RTC_SATURDAY ((uint8_t)0x06) /*!< saturday */
#define RTC_SUNDAY ((uint8_t)0x07) /*!< sunday */
#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_DATE_YR bit field */
#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */
#define RTC_OUT_PC13 ((uint32_t)0x00000000U) /*!< RTC_OUT is connected to PC13 */
#define RTC_OUT_PB2 RTC_CTL_OUT2EN /*!< RTC_OUT is connected to PB2 */
#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) /*!< write value to RTC_CTL_OS bit field */
#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */
#define RTC_OS_ALARM0 CTL_OS(1) /*!< enable alarm0 flag output */
#define RTC_OS_ALARM1 CTL_OS(2) /*!< enable alarm1 flag output */
#define RTC_OS_WAKEUP CTL_OS(3) /*!< enable wakeup flag output */
#define RTC_ITSEN_DISABLE ((uint32_t)0x00000000U) /*!< disable output RTC_ALARM */
#define RTC_ITSEN_ENABLE RTC_CTL_ITSEN /*!< enable alarm0 flag output */
#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */
#define RTC_CALIBRATION_1HZ (RTC_CTL_COEN | RTC_CTL_COS) /*!< calibration output of 1Hz is enable */
#define RTC_ALARM0_HIGH RTC_OS_ALARM0 /*!< enable alarm0 flag output with high level */
#define RTC_ALARM0_LOW (RTC_OS_ALARM0 | RTC_CTL_OPOL) /*!< enable alarm0 flag output with low level*/
#define RTC_ALARM1_HIGH RTC_OS_ALARM1 /*!< enable alarm1 flag output with high level */
#define RTC_ALARM1_LOW (RTC_OS_ALARM1 | RTC_CTL_OPOL) /*!< enable alarm1 flag output with low level*/
#define RTC_WAKEUP_HIGH RTC_OS_WAKEUP /*!< enable wakeup flag output with high level */
#define RTC_WAKEUP_LOW (RTC_OS_WAKEUP | RTC_CTL_OPOL) /*!< enable wakeup flag output with low level*/
#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */
#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */
#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */
#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */
#define CTL_WTCS(regval) (BITS(0,2) & ((uint32_t)(regval)<< 0))
#define WAKEUP_RTCCK_DIV16 CTL_WTCS(0) /*!< wakeup timer clock is RTC clock divided by 16 */
#define WAKEUP_RTCCK_DIV8 CTL_WTCS(1) /*!< wakeup timer clock is RTC clock divided by 8 */
#define WAKEUP_RTCCK_DIV4 CTL_WTCS(2) /*!< wakeup timer clock is RTC clock divided by 4 */
#define WAKEUP_RTCCK_DIV2 CTL_WTCS(3) /*!< wakeup timer clock is RTC clock divided by 2 */
#define WAKEUP_CKSPRE CTL_WTCS(4) /*!< wakeup timer clock is ckapre */
#define WAKEUP_CKSPRE_2EXP16 CTL_WTCS(6) /*!< wakeup timer clock is ckapre and wakeup timer add 2exp16 */
/* psc register value */
#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_PSC_FACTOR_S bit field */
#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */
#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_PSC_FACTOR_A bit field */
#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */
/* alrmtd register value */
#define ALRMTD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMTD_SC bit field */
#define GET_ALRMTD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRMTD_SC bit field */
#define ALRMTD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_ALRMTD_MN bit field */
#define GET_ALRMTD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRMTD_MN bit field */
#define ALRMTD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_ALRMTD_HR bit field */
#define GET_ALRMTD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRMTD_HR bit field */
#define ALRMTD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMTD_DAY bit field */
#define GET_ALRMTD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRMTD_DAY bit field */
#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */
#define RTC_ALARM_DATE_MASK RTC_ALRMXTD_MSKD /*!< alarm date mask */
#define RTC_ALARM_HOUR_MASK RTC_ALRMXTD_MSKH /*!< alarm hour mask */
#define RTC_ALARM_MINUTE_MASK RTC_ALRMXTD_MSKM /*!< alarm minute mask */
#define RTC_ALARM_SECOND_MASK RTC_ALRMXTD_MSKS /*!< alarm second mask */
#define RTC_ALARM_ALL_MASK (RTC_ALRMXTD_MSKD|RTC_ALRMXTD_MSKH|RTC_ALRMXTD_MSKM|RTC_ALRMXTD_MSKS) /*!< alarm all mask */
#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */
#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRMXTD_DOWS /*!< alarm weekday format selected */
/* wpk register value */
#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_WPK_WPK bit field */
/* ss register value */
#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SS_SSC bit field */
/* shiftctl register value */
#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SHIFTCTL_SFS bit field */
#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */
#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */
/* tts register value */
#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TTS_SC bit field */
#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */
#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TTS_MN bit field */
#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */
#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TTS_HR bit field */
#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */
/* dts register value */
#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DTS_DAY bit field */
#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */
#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DTS_MON bit field */
#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */
#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DTS_DOW bit field */
#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */
/* ssts register value */
#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SSTS_SSC bit field */
/* hrfc register value */
#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_HRFC_CMSK bit field */
#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */
#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */
#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */
#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */
#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */
#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_TAMP_PRCH bit field */
#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */
#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */
#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */
#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */
#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< write value to RTC_TAMP_FLT bit field */
#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */
#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */
#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */
#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */
#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TAMP_FREQ bit field */
#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */
#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */
#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */
#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */
#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */
#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */
#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */
#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */
#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */
#define RTC_ALARM_OUTPUT_PP RTC_CTL_ALRMOUTTYPE /*!< RTC alarm output push-pull mode */
/* alrm0ss register value */
#define ALRMXSS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMXSS_SSC bit field */
#define ALRMXSS_MSKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMXSS_MSKSSC bit field */
#define RTC_MSKSSC_0_14 ALRMXSS_MSKSSC(0) /*!< mask alarm subsecond configuration */
#define RTC_MSKSSC_1_14 ALRMXSS_MSKSSC(1) /*!< mask RTC_ALRMXSS_SSC[14:1], and RTC_ALRMXSS_SSC[0] is to be compared */
#define RTC_MSKSSC_2_14 ALRMXSS_MSKSSC(2) /*!< mask RTC_ALRMXSS_SSC[14:2], and RTC_ALRMXSS_SSC[1:0] is to be compared */
#define RTC_MSKSSC_3_14 ALRMXSS_MSKSSC(3) /*!< mask RTC_ALRMXSS_SSC[14:3], and RTC_ALRMXSS_SSC[2:0] is to be compared */
#define RTC_MSKSSC_4_14 ALRMXSS_MSKSSC(4) /*!< mask RTC_ALRMXSS_SSC[14:4]], and RTC_ALRMXSS_SSC[3:0] is to be compared */
#define RTC_MSKSSC_5_14 ALRMXSS_MSKSSC(5) /*!< mask RTC_ALRMXSS_SSC[14:5], and RTC_ALRMXSS_SSC[4:0] is to be compared */
#define RTC_MSKSSC_6_14 ALRMXSS_MSKSSC(6) /*!< mask RTC_ALRMXSS_SSC[14:6], and RTC_ALRMXSS_SSC[5:0] is to be compared */
#define RTC_MSKSSC_7_14 ALRMXSS_MSKSSC(7) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */
#define RTC_MSKSSC_8_14 ALRMXSS_MSKSSC(8) /*!< mask RTC_ALRMXSS_SSC[14:8], and RTC_ALRMXSS_SSC[7:0] is to be compared */
#define RTC_MSKSSC_9_14 ALRMXSS_MSKSSC(9) /*!< mask RTC_ALRMXSS_SSC[14:9], and RTC_ALRMXSS_SSC[8:0] is to be compared */
#define RTC_MSKSSC_10_14 ALRMXSS_MSKSSC(10) /*!< mask RTC_ALRMXSS_SSC[14:10], and RTC_ALRMXSS_SSC[9:0] is to be compared */
#define RTC_MSKSSC_11_14 ALRMXSS_MSKSSC(11) /*!< mask RTC_ALRMXSS_SSC[14:11], and RTC_ALRMXSS_SSC[10:0] is to be compared */
#define RTC_MSKSSC_12_14 ALRMXSS_MSKSSC(12) /*!< mask RTC_ALRMXSS_SSC[14:12], and RTC_ALRMXSS_SSC[11:0] is to be compared */
#define RTC_MSKSSC_13_14 ALRMXSS_MSKSSC(13) /*!< mask RTC_ALRMXSS_SSC[14:13], and RTC_ALRMXSS_SSC[12:0] is to be compared */
#define RTC_MSKSSC_14 ALRMXSS_MSKSSC(14) /*!< mask RTC_ALRMXSS_SSC[14], and RTC_ALRMXSS_SSC[13:0] is to be compared */
#define RTC_MSKSSC_NONE ALRMXSS_MSKSSC(15) /*!< mask none, and RTC_ALRMXSS_SSC[14:0] is to be compared */
/* RTC interrupt source */
#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */
#define RTC_INT_ALARM0 RTC_CTL_ALRM0IE /*!< RTC alarm0 interrupt enable */
#define RTC_INT_ALARM1 RTC_CTL_ALRM1IE /*!< RTC alarm1 interrupt enable */
#define RTC_INT_TAMP_ALL RTC_TAMP_TPIE /*!< tamper detection interrupt enable */
#define RTC_INT_WAKEUP RTC_CTL_WTIE /*!< RTC wakeup timer interrupt enable */
/* write protect key */
#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */
#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */
#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */
/* registers reset value */
#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */
#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */
#define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */
#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */
#define RTC_WUT_RESET ((uint32_t)0x0000FFFFU) /*!< RTC_WUT register reset value */
/* RTC alarm */
#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */
#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */
/* RTC flag */
#define RTC_FLAG_ALARM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */
#define RTC_FLAG_ALARM1W RTC_STAT_ALRM1WF /*!< alarm1 configuration can be write flag */
#define RTC_FLAG_WTW RTC_STAT_WTWF /*!< wakeup timer can be write flag */
#define RTC_FLAG_SOP RTC_STAT_SOPF /*!< shift function operation pending flag */
#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */
#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */
#define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */
#define RTC_FLAG_SCP RTC_STAT_SOPF /*!< smooth calibration pending flag */
#define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */
#define RTC_FLAG_ALARM1 RTC_STAT_ALRM1F /*!< alarm1 occurs flag */
#define RTC_FLAG_WT RTC_STAT_WTF /*!< wakeup timer occurs flag */
#define RTC_FLAG_TS RTC_STAT_TSF /*!< time-stamp flag */
#define RTC_FLAG_TSOVR RTC_STAT_TSOVRF /*!< time-stamp overflow flag */
#define RTC_FLAG_TP0 RTC_STAT_TP0F /*!< RTC tamper 0 detected flag */
#define RTC_FLAG_TP2 RTC_STAT_TP2F /*!< RTC tamper 2 detected flag */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
#define NOT_RTC_ALARM_VALID(rtc_alarm) (((rtc_alarm) != RTC_ALARM0) && ((rtc_alarm) != RTC_ALARM1))
#define NOT_RTC_ALARM_MASK(mask) (((mask) != RTC_ALARM_NONE_MASK) && ((mask) != RTC_ALARM_DATE_MASK) && \
((mask) != RTC_ALARM_HOUR_MASK) && ((mask) != RTC_ALARM_MINUTE_MASK) && \
((mask) != RTC_ALARM_SECOND_MASK) && ((mask) != RTC_ALARM_ALL_MASK))
#define NOT_RTC_WEEKDAY_OR_DATE(weekday) (((weekday) != RTC_ALARM_DATE_SELECTED) && ((weekday) != RTC_ALARM_WEEKDAY_SELECTED))
#define NOT_RTC_ALARM_DAY(day) (((day) != RTC_MONDAY) && ((day) != RTC_TUESDAY) && \
((day) != RTC_WEDNESDAY) && ((day) != RTC_THURSDAY) && \
((day) != RTC_FRIDAY) && ((day) != RTC_SATURDAY) && \
((day) != RTC_SUNDAY) && (((day) > 0x31U) || ((day) == 0x00U)))
#define NOT_RTC_ALARM_HOUR(hour) ((hour) > 0x23U)
#define NOT_RTC_ALARM_MINUTE(minute) ((minute) > 0x59U)
#define NOT_RTC_ALARM_SECOND(second) ((second) > 0x59U)
#define NOT_RTC_AM_PM(ampm) (((ampm) != RTC_AM) && ((ampm) != RTC_PM))
#define NOT_RTC_YEAR(year) ((year) > 0x99U)
#define NOT_RTC_MONTH(mouth) (((mouth) != RTC_JAN) && ((mouth) != RTC_FEB) && \
((mouth) != RTC_MAR) && ((mouth) != RTC_APR) && \
((mouth) != RTC_MAY) && ((mouth) != RTC_JUN) && \
((mouth) != RTC_JUL) && ((mouth) != RTC_AUG) && \
((mouth) != RTC_SEP) && ((mouth) != RTC_OCT) && \
((mouth) != RTC_NOV) && ((mouth) != RTC_DEC))
#define NOT_RTC_DATE(date) (((date) > 0x31U) || ((date) == 0x00U))
#define NOT_RTC_EDGE(edge) (((edge) != RTC_TIMESTAMP_RISING_EDGE) && ((edge) != RTC_TIMESTAMP_FALLING_EDGE))
#define NOT_RTC_ITSEN_MODE_VALID(mode) (((mode) != RTC_ITSEN_DISABLE )&& ((mode) != RTC_ITSEN_ENABLE))
#define NOT_RTC_TAMPER_SOURCE(source) (((source) != RTC_TAMPER0) && ((source) != RTC_TAMPER1))
#define NOT_RTC_TAMPER_TRIGGER_VALID(trigger) (((trigger) != RTC_TAMPER_TRIGGER_EDGE_RISING) && ((trigger) != RTC_TAMPER_TRIGGER_EDGE_FALLING )&& \
((trigger) != RTC_TAMPER_TRIGGER_LEVEL_LOW) && ((trigger) != RTC_TAMPER_TRIGGER_LEVEL_HIGH))
#define NOT_RTC_TAMPER_FILTER_VALID(filter) (((filter) != RTC_FLT_EDGE) &&((filter) != RTC_FLT_2S)&& \
((filter) != RTC_FLT_4S) &&((filter) != RTC_FLT_8S))
#define NOT_RTC_SAMPLE_FREQ_VALID(freq) (((freq) != RTC_FREQ_DIV32768 )&& ((freq) != RTC_FREQ_DIV16384) && \
((freq) != RTC_FREQ_DIV8192 )&& ((freq) != RTC_FREQ_DIV4096) && \
((freq) != RTC_FREQ_DIV2048) && ((freq) != RTC_FREQ_DIV1024)&& \
((freq) != RTC_FREQ_DIV512) && ((freq) != RTC_FREQ_DIV256))
#define NOT_RTC_ALARM_OUTPUT_MODE_VALID(mode) (((mode) != RTC_ALARM_OUTPUT_OD) && ((mode) != RTC_ALARM_OUTPUT_PP))
#define NOT_RTC_TAMPER_PRECHARGE_TIME(time) (((time) != RTC_PRCH_1C )&& ((time) && RTC_PRCH_2C) && \
((time) != RTC_PRCH_4C) && ((time) != RTC_PRCH_8C))
#define NOT_RTC_ALARM_OUTPUT_SOURCE_VALID(source) (((source) != RTC_ALARM0_HIGH) && ((source) != RTC_ALARM0_LOW) && \
((source) != RTC_ALARM1_HIGH)&&((source) != RTC_ALARM1_LOW) && \
((source) != RTC_WAKEUP_HIGH)&&((source) != RTC_WAKEUP_LOW))
#define NOT_RTC_WAKEUP_CLOCK_VALID(wakeup_clock) (((wakeup_clock) != WAKEUP_RTCCK_DIV16) &&((wakeup_clock) != WAKEUP_RTCCK_DIV8) && \
((wakeup_clock) != WAKEUP_RTCCK_DIV4)&&((wakeup_clock) != WAKEUP_RTCCK_DIV2) && \
((wakeup_clock) != WAKEUP_CKSPRE)&& ((wakeup_clock) != WAKEUP_CKSPRE_2EXP16))
#define NOT_RTC_WAKEUP_TIMER_VALID(wakeup_timer) ((wakeup_timer) == 0x0000U)
#define NOT_RTC_SOURCE(source) (((source) != RTC_CALIBRATION_512HZ) && ((source) != RTC_CALIBRATION_1HZ))
#define NOT_RTC_MODE(mode) (((mode) != RTC_ALARM_OUTPUT_OD) && ((mode) != RTC_CTL_ALRMOUTTYPE))
#define NOT_RTC_MASK_SUBSECOND(mask) (((mask) != RTC_MSKSSC_0_14) && ((mask) != RTC_MSKSSC_1_14) && \
((mask) != RTC_MSKSSC_2_14) && ((mask) != RTC_MSKSSC_3_14) && \
((mask) != RTC_MSKSSC_4_14) && ((mask) != RTC_MSKSSC_5_14) && \
((mask) != RTC_MSKSSC_6_14) && ((mask) != RTC_MSKSSC_7_14) && \
((mask) != RTC_MSKSSC_8_14) && ((mask) != RTC_MSKSSC_9_14) && \
((mask) != RTC_MSKSSC_10_14) && ((mask) != RTC_MSKSSC_11_14) && \
((mask) != RTC_MSKSSC_12_14) && ((mask) != RTC_MSKSSC_13_14) && \
((mask) != RTC_MSKSSC_14) && ((mask) != RTC_MSKSSC_NONE))
#define NOT_RTC_SUBSECOND(subsecond) ((subsecond) > 0x7FFFU)
#define NOT_RTC_DAY_OF_WEEK(week) (((week) != RTC_MONDAY) && ((week) != RTC_TUESDAY) && \
((week) != RTC_WEDNESDAY) && ((week) != RTC_THURSDAY) && \
((week) != RTC_FRIDAY) && ((week) != RTC_SATURDAY) && \
((week) != RTC_SUNDAY))
#define NOT_RTC_HOUR(hour) ((hour) > 0x23U)
#define NOT_RTC_MINUTE(minute) ((minute) > 0x59U)
#define NOT_RTC_SECOND(second) ((second) > 0x59U)
#define NOT_RTC_FACTOR_ASYN(asyn) ((asyn) > 0x7FU)
#define NOT_RTC_FACTOR_SYN(syn) ((syn) > 0x7FFFU)
#define NOT_RTC_DISPLAY_FORMAT(format) (((format) != RTC_24HOUR) && ((format) != RTC_12HOUR))
#define NOT_RTC_OPERATION(operation) (((operation) != RTC_CTL_A1H) && ((operation) != RTC_CTL_S1H))
#define NOT_RTC_ADD(add) (((add) != RTC_SHIFT_ADD1S_RESET) && ((add) != RTC_SHIFT_ADD1S_SET))
#define NOT_RTC_MINUS(minus) ((minus) > 0x7FFFU)
#define NOT_RTC_WINDOW(window) (((window) != RTC_CALIBRATION_WINDOW_32S) && ((window) != RTC_CALIBRATION_WINDOW_16S) && \
((window) != RTC_CALIBRATION_WINDOW_8S))
#define NOT_RTC_PLUS(plus) (((plus) != RTC_CALIBRATION_PLUS_SET) && ((plus) != RTC_CALIBRATION_PLUS_RESET))
#define NOT_RTC_SMOOTH_MINUS(smooth_minus) ((smooth_minus) > 0x1FFU)
#define NOT_RTC_OUTPUTPIN(outputpin) (((outputpin) != RTC_OUT_PC13) && ((outputpin) != RTC_CFG_OUT2EN))
#define NOT_RTC_FLAG(flag) (((flag) != RTC_FLAG_SCP) && ((flag) != RTC_FLAG_TSOVR) && \
((flag) != RTC_FLAG_TS) && ((flag) != RTC_FLAG_ALARM0) && \
((flag) != RTC_FLAG_INIT) && ((flag) != RTC_FLAG_RSYN) && \
((flag) != RTC_FLAG_YCM) && ((flag) != RTC_FLAG_SOP) && \
((flag) != RTC_FLAG_ALARM0W))
#define NOT_RTC_INTERRUPT(interrupt) (((interrupt) != RTC_INT_TIMESTAMP) && ((interrupt) != RTC_INT_ALARM0))
/* check the RTC pointer*/
#define NOT_RTC_VALID_POINTER(pointer) ((void *) 0 == (pointer)) /*!< check the invalid pointer */
#endif
/* function declarations */
/* initialization and configuration functions */
/* reset most of the RTC registers */
ErrStatus rtc_deinit(void);
/* initialize RTC registers */
ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct);
/* enter RTC init mode */
ErrStatus rtc_init_mode_enter(void);
/* exit RTC init mode */
void rtc_init_mode_exit(void);
/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */
ErrStatus rtc_register_sync_wait(void);
/* get current time and date */
void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct);
/* get current subsecond value */
uint32_t rtc_subsecond_get(void);
/* alarm configuration functions */
/* configure RTC alarm */
void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time);
/* configure subsecond of RTC alarm */
void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond);
/* get RTC alarm */
void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time);
/* get RTC alarm subsecond */
uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm);
/* enable RTC alarm */
void rtc_alarm_enable(uint8_t rtc_alarm);
/* disable RTC alarm */
ErrStatus rtc_alarm_disable(uint8_t rtc_alarm);
/* timestamp and tamper configuration functions */
/* enable RTC time-stamp */
void rtc_timestamp_enable(uint32_t edge);
/* disable RTC time-stamp */
void rtc_timestamp_disable(void);
/* get RTC timestamp time and date */
void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp);
/* configure RTC time-stamp internal event */
void rtc_timestamp_internalevent_config(uint32_t mode);
/* get RTC time-stamp subsecond */
uint32_t rtc_timestamp_subsecond_get(void);
/* enable RTC tamper */
void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper);
/* disable RTC tamper */
void rtc_tamper_disable(uint32_t source);
/* select the RTC output pin */
void rtc_output_pin_select(uint32_t outputpin);
/* configure RTC alarm output source */
void rtc_alarm_output_config(uint32_t source, uint32_t mode);
/* configure RTC calibration output source */
void rtc_calibration_output_config(uint32_t source);
/* adjust the daylight saving time by adding or substracting one hour from the current time */
void rtc_hour_adjust(uint32_t operation);
/* adjust RTC second or subsecond value of current time */
ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus);
/* enable RTC bypass shadow registers function */
void rtc_bypass_shadow_enable(void);
/* disable RTC bypass shadow registers function */
void rtc_bypass_shadow_disable(void);
/* enable RTC reference clock detection function */
ErrStatus rtc_refclock_detection_enable(void);
/* disable RTC reference clock detection function */
ErrStatus rtc_refclock_detection_disable(void);
/* enable RTC wakeup timer */
void rtc_wakeup_enable(void);
/* disable RTC wakeup timer */
ErrStatus rtc_wakeup_disable(void);
/* set auto wakeup timer clock */
ErrStatus rtc_wakeup_clock_set(uint32_t wakeup_clock);
/* set auto wakeup timer value */
ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer);
/* get auto wakeup timer value */
uint16_t rtc_wakeup_timer_get(void);
/* configure RTC smooth calibration */
ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t minus);
/* enable specified RTC interrupt */
void rtc_interrupt_enable(uint32_t interrupt);
/* disable specified RTC interrupt */
void rtc_interrupt_disable(uint32_t interrupt);
/* check specified flag */
FlagStatus rtc_flag_get(uint32_t flag);
/* clear specified flag */
void rtc_flag_clear(uint32_t flag);
#endif /* GD32H75E_RTC_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_spi.h
+863
View File
@@ -0,0 +1,863 @@
/*!
\file gd32h75e_spi.h
\brief definitions for the SPI
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_SPI_H
#define GD32H75E_SPI_H
#include "gd32h75e.h"
/* SPIx(x=0,1,2,3,4,5) definitions */
#define SPI0 (SPI_BASE + 0x0000F800U)
#define SPI1 SPI_BASE
#define SPI2 (SPI_BASE + 0x00000400U)
#define SPI3 (SPI_BASE + 0x0000FC00U)
#define SPI4 (SPI_BASE + 0x00011800U)
#define SPI5 (SPI_BASE + 0x00010000U)
/* SPI registers definitions */
#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */
#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/
#define SPI_CFG0(spix) REG32((spix) + 0x08U) /*!< SPI configuration register 0 */
#define SPI_CFG1(spix) REG32((spix) + 0x0CU) /*!< SPI configuration register 1 */
#define SPI_INT(spix) REG32((spix) + 0x10U) /*!< SPI interrupt register */
#define SPI_STAT(spix) REG32((spix) + 0x14U) /*!< SPI status register */
#define SPI_STATC(spix) REG32((spix) + 0x18U) /*!< SPI interrupt/status flags clear register */
#define SPI_TDATA(spix) REG32((spix) + 0x20U) /*!< SPI data transfer register */
#define SPI_RDATA(spix) REG32((spix) + 0x30U) /*!< SPI data receive register */
#define SPI_CRCPOLY(spix) REG32((spix) + 0x40U) /*!< SPI CRC polynomial register */
#define SPI_TCRC(spix) REG32((spix) + 0x44U) /*!< SPI TX CRC register */
#define SPI_RCRC(spix) REG32((spix) + 0x48U) /*!< SPI RX CRC register */
#define SPI_URDATA(spix) REG32((spix) + 0x4CU) /*!< SPI underrun data register */
#define SPI_I2SCTL(spix) REG32((spix) + 0x50U) /*!< I2S control register */
#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< quad_SPI mode control register(for SPI3/4) */
#define SPI_RXDLYCK(spix) REG32((spix) + 0xFCU) /*!< SPI receive clock delay register */
/* bits definitions */
/* SPI_CTL0 */
#define SPI_CTL0_SPIEN BIT(0) /*!< SPI enable */
#define SPI_CTL0_MASP BIT(8) /*!< the master is suspended automatically in receive mode */
#define SPI_CTL0_MSTART BIT(9) /*!< master start transfer */
#define SPI_CTL0_MSPDR BIT(10) /*!< suspend request in SPI master mode */
#define SPI_CTL0_NSSI BIT(12) /*!< the input level to internal NSS signal */
#define SPI_CTL0_CRCFS BIT(13) /*!< full scale CRC polynomial configuration */
#define SPI_CTL0_RXCRCI BIT(14) /*!< the receiver CRC initialization configuration */
#define SPI_CTL0_TXCRCI BIT(15) /*!< the transmitter CRC initialization configuration */
#define SPI_CTL0_IOAFEN BIT(16) /*!< related IOs AF configuration enable */
/* SPI_CFG0 */
#define SPI_CFG0_DZ BITS(0,4) /*!< data size */
#define SPI_CFG0_FIFOLVL BITS(5,8) /*!< FIFO threshold level */
#define SPI_CFG0_TXUROP BITS(9,10) /*!< operation of slave transmitter when underrun detected */
#define SPI_CFG0_TXURDT BITS(11,12) /*!< detection of underrun error at slave transmitter */
#define SPI_CFG0_DMAREN BIT(14) /*!< receive buffer DMA enable */
#define SPI_CFG0_DMATEN BIT(15) /*!< transmit buffer DMA enable */
#define SPI_CFG0_CRCSZ BITS(16,20) /*!< CRC size */
#define SPI_CFG0_CRCEN BIT(22) /*!< CRC calculation enable */
#define SPI_CFG0_BYTEN BIT(23) /*!< byte access enable */
#define SPI_CFG0_WORDEN BIT(24) /*!< word access enable */
#define SPI_CFG0_PSC BITS(28,30) /*!< master clock prescaler selection */
/* SPI_CFG1 */
#define SPI_CFG1_MSSD BITS(0,3) /*!< delay between active edge of NSS and start transfer or receive data in SPI master mode */
#define SPI_CFG1_MDFD BITS(4,7) /*!< delay between the data frames in SPI master mode */
#define SPI_CFG1_SWPMIO BIT(15) /*!< MOSI and MISO pin swap */
#define SPI_CFG1_RO BIT(16) /*!< receive only */
#define SPI_CFG1_BDOEN BIT(17) /*!< bidirectional transmit output enable */
#define SPI_CFG1_BDEN BIT(18) /*!< bidirectional enable */
#define SPI_CFG1_TMOD BIT(21) /*!< SPI TI mode enable */
#define SPI_CFG1_MSTMOD BIT(22) /*!< Master mode enable */
#define SPI_CFG1_LF BIT(23) /*!< LSB first mode */
#define SPI_CFG1_CKPH BIT(24) /*!< clock phase selection */
#define SPI_CFG1_CKPL BIT(25) /*!< clock polarity selection */
#define SPI_CFG1_NSSIM BIT(26) /*!< NSS input signal manage mode */
#define SPI_CFG1_NSSIOPL BIT(28) /*!< NSS pin input/output polarity selection */
#define SPI_CFG1_NSSDRV BIT(29) /*!< NSS pin output enable in master mode */
#define SPI_CFG1_NSSCTL BIT(30) /*!< NSS pin output control in master mode */
#define SPI_CFG1_AFCTL BIT(31) /*!< AF GPIOs control */
/* SPI_INT */
#define SPI_INT_RPIE BIT(0) /*!< RP interrupt enable */
#define SPI_INT_TPIE BIT(1) /*!< TP interrupt enable */
#define SPI_INT_DPIE BIT(2) /*!< DP interrupt enable */
#define SPI_INT_ESTCIE BIT(3) /*!< end of transfer or suspend or TXFIFO clear interrupt enable */
#define SPI_INT_TXFIE BIT(4) /*!< transmission filled interrupt enable */
#define SPI_INT_TXUREIE BIT(5) /*!< underrun error interrupt enable */
#define SPI_INT_RXOREIE BIT(6) /*!< overrun error interrupt enable */
#define SPI_INT_CRCERIE BIT(7) /*!< CRC error interrupt enable */
#define SPI_INT_FEIE BIT(8) /*!< TI frame error interrupt enable */
#define SPI_INT_CONFEIE BIT(9) /*!< SPI configuration error interrupt enable */
#define SPI_INT_TXSERFIE BIT(10) /*!< TXSER reload interrupt enable */
/* SPI_STAT */
#define SPI_STAT_RP BIT(0) /*!< RxFIFO packet space available flag */
#define SPI_STAT_TP BIT(1) /*!< TxFIFO packet space available flag */
#define SPI_STAT_DP BIT(2) /*!< duplex packet */
#define SPI_STAT_ET BIT(3) /*!< End of transmission/reception flag */
#define SPI_STAT_TXF BIT(4) /*!< TxFIFO transmission has been filled */
#define SPI_STAT_TXURERR BIT(5) /*!< transmission underrun error */
#define SPI_STAT_RXORERR BIT(6) /*!< reception overrun error */
#define SPI_STAT_CRCERR BIT(7) /*!< SPI CRC error */
#define SPI_STAT_FERR BIT(8) /*!< SPI TI format error */
#define SPI_STAT_CONFERR BIT(9) /*!< SPI configuration error */
#define SPI_STAT_TXSERF BIT(10) /*!< The additional SPI data has been reloaded */
#define SPI_STAT_SPD BIT(11) /*!< suspend flsg */
#define SPI_STAT_TC BIT(12) /*!< TxFIFO transmission complete flag */
#define SPI_STAT_RPLVL BITS(13,14) /*!< RxFIFO packing level */
#define SPI_STAT_RWNE BIT(15) /*!< the word of RXFIFO is not empty */
#define SPI_STAT_CTXSIZE BITS(16,31) /*!< the number of data frames remaining in the TXSIZE session */
/* SPI_STATC */
#define SPI_STATC_ETC BIT(3) /*!< Clear the end of transmission/reception flag */
#define SPI_STATC_TXFC BIT(4) /*!< Clear the TxFIFO transmission filled flag */
#define SPI_STATC_TXURERRC BIT(5) /*!< clear the transmission underrun error flag */
#define SPI_STATC_RXORERRC BIT(6) /*!< clear the reception overrun error flag */
#define SPI_STATC_CRCERRC BIT(7) /*!< clear the CRC error flag */
#define SPI_STATC_FERRC BIT(8) /*!< clear the SPI TI format error flag */
#define SPI_STATC_CONFERRC BIT(9) /*!< clear the configuration error flag */
#define SPI_STATC_TXSERFC BIT(10) /*!< clear the TXSERF flag */
#define SPI_STATC_SPDC BIT(11) /*!< clear the suspend flag */
/* SPI_TDATA */
#define SPI_TDATA_TDATA BITS(0,31) /*!< data transfer register */
/* SPI_RDATA */
#define SPI_RDATA_RDATA BITS(0,31) /*!< data receive register */
/* SPI_CRCPOLY */
#define SPI_CRCPOLY_CRCPOLY BITS(0,31) /*!< CRC polynomial register */
/* SPI_TCRC */
#define SPI_TCRC_TCRC BITS(0,31) /*!< Tx CRC register */
/* SPI_RCRC */
#define SPI_RCRC_RCRC BITS(0,31) /*!< Rx CRC register */
/* SPI_URDATA */
#define SPI_URDATA_URDATA BITS(0,31) /*!< transmission underrun data at slave mode */
/* SPI_I2SCTL */
#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
#define SPI_I2SCTL_DIV BITS(16,23) /*!< dividing factor for the prescaler */
#define SPI_I2SCTL_OF BIT(24) /*!< odd factor for the prescaler */
#define SPI_I2SCTL_MCKOEN BIT(25) /*!< I2S_MCK output enable */
#define SPI_I2SCTL_I2SCH BIT(31) /*!< I2S Channel side */
/* SPI_QCTL(only for SPI3/4) */
#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */
#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */
#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */
/* SPI_RXDLYCK */
#define SPI_RXDLYCK_SRXD BITS(0,4) /*!< slave mode receive clock delay units*/
#define SPI_RXDLYCK_SRXDEN BIT(5) /*!< slave mode receive clock delay enable*/
#define SPI_RXDLYCK_MRXD BITS(6,10) /*!< master mode receive clock delay units*/
#define SPI_RXDLYCK_MRXDEN BIT(11) /*!< master mode receive clock delay enable*/
/* constants definitions */
/* SPI and I2S parameter struct definitions */
typedef struct
{
uint32_t device_mode; /*!< SPI master or slave */
uint32_t trans_mode; /*!< SPI transtype */
uint32_t data_size; /*!< SPI data frame size */
uint32_t nss; /*!< SPI NSS control by handware or software */
uint32_t endian; /*!< SPI big endian or little endian */
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
uint32_t prescale; /*!< SPI prescale factor */
}spi_parameter_struct;
/* SPI suspend in receive mode */
#define SPI_AUTO_SUSPEND SPI_CTL0_MASP /*!< until the overrun condition is reached, the SPI stream is suspended in the full RxFIFO state */
#define SPI_CONTINUOUS ((uint32_t)0x00000000U) /*!< SPI stream/clock generation is continuous whether or not an overrun occurs */
/* SPI master start transfer */
#define SPI_TRANS_START SPI_CTL0_MSTART /*!< the master transmission is occurring, or has been temporarily suspended by automatic suspend */
#define SPI_TRANS_IDLE ((uint32_t)0x00000000U) /*!< the master transfer is idle status */
/* SPI NSS input level */
#define SPI_NSS_LEVEL_HIGH SPI_CTL0_NSSI /*!< NSS pin is pulled high */
#define SPI_NSS_LEVEL_LOW ((uint32_t)0x00000000U) /*!< NSS pin is pulled low */
/* SPI TCRC init pattern */
#define SPI_TCRC_INIT_1 SPI_CTL0_TXCRCI /*!< use all 1 pattern */
#define SPI_TCRC_INIT_0 ((uint32_t)0x00000000U) /*!< use all 0 pattern */
/* SPI RCRC init pattern */
#define SPI_RCRC_INIT_1 SPI_CTL0_RXCRCI /*!< use all 1 pattern */
#define SPI_RCRC_INIT_0 ((uint32_t)0x00000000U) /*!< use all 0 pattern */
/* SPI data frame size */
#define CFG0_DZ(regval) (BITS(0,4) & ((uint32_t)(regval) << 0))
#define SPI_DATASIZE_4BIT CFG0_DZ(3) /*!< SPI data frame size is 4-bit */
#define SPI_DATASIZE_5BIT CFG0_DZ(4) /*!< SPI data frame size is 5-bit */
#define SPI_DATASIZE_6BIT CFG0_DZ(5) /*!< SPI data frame size is 6-bit */
#define SPI_DATASIZE_7BIT CFG0_DZ(6) /*!< SPI data frame size is 7-bit */
#define SPI_DATASIZE_8BIT CFG0_DZ(7) /*!< SPI data frame size is 8-bit */
#define SPI_DATASIZE_9BIT CFG0_DZ(8) /*!< SPI data frame size is 9-bit */
#define SPI_DATASIZE_10BIT CFG0_DZ(9) /*!< SPI data frame size is 10-bit */
#define SPI_DATASIZE_11BIT CFG0_DZ(10) /*!< SPI data frame size is 11-bit */
#define SPI_DATASIZE_12BIT CFG0_DZ(11) /*!< SPI data frame size is 12-bit */
#define SPI_DATASIZE_13BIT CFG0_DZ(12) /*!< SPI data frame size is 13-bit */
#define SPI_DATASIZE_14BIT CFG0_DZ(13) /*!< SPI data frame size is 14-bit */
#define SPI_DATASIZE_15BIT CFG0_DZ(14) /*!< SPI data frame size is 15-bit */
#define SPI_DATASIZE_16BIT CFG0_DZ(15) /*!< SPI data frame size is 16-bit */
#define SPI_DATASIZE_17BIT CFG0_DZ(16) /*!< SPI data frame size is 17-bit */
#define SPI_DATASIZE_18BIT CFG0_DZ(17) /*!< SPI data frame size is 18-bit */
#define SPI_DATASIZE_19BIT CFG0_DZ(18) /*!< SPI data frame size is 19-bit */
#define SPI_DATASIZE_20BIT CFG0_DZ(19) /*!< SPI data frame size is 20-bit */
#define SPI_DATASIZE_21BIT CFG0_DZ(20) /*!< SPI data frame size is 21-bit */
#define SPI_DATASIZE_22BIT CFG0_DZ(21) /*!< SPI data frame size is 22-bit */
#define SPI_DATASIZE_23BIT CFG0_DZ(22) /*!< SPI data frame size is 23-bit */
#define SPI_DATASIZE_24BIT CFG0_DZ(23) /*!< SPI data frame size is 24-bit */
#define SPI_DATASIZE_25BIT CFG0_DZ(24) /*!< SPI data frame size is 25-bit */
#define SPI_DATASIZE_26BIT CFG0_DZ(25) /*!< SPI data frame size is 26-bit */
#define SPI_DATASIZE_27BIT CFG0_DZ(26) /*!< SPI data frame size is 27-bit */
#define SPI_DATASIZE_28BIT CFG0_DZ(27) /*!< SPI data frame size is 28-bit */
#define SPI_DATASIZE_29BIT CFG0_DZ(28) /*!< SPI data frame size is 29-bit */
#define SPI_DATASIZE_30BIT CFG0_DZ(29) /*!< SPI data frame size is 30-bit */
#define SPI_DATASIZE_31BIT CFG0_DZ(30) /*!< SPI data frame size is 31-bit */
#define SPI_DATASIZE_32BIT CFG0_DZ(31) /*!< SPI data frame size is 32-bit */
/* SPI FIFO threshold level */
#define CFG0_FIFOLVL(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
#define SPI_FIFO_TH_01DATA CFG0_FIFOLVL(0) /*!< set FIFO threshold level = 1-data frame */
#define SPI_FIFO_TH_02DATA CFG0_FIFOLVL(1) /*!< set FIFO threshold level = 2-data frame */
#define SPI_FIFO_TH_03DATA CFG0_FIFOLVL(2) /*!< set FIFO threshold level = 3-data frame */
#define SPI_FIFO_TH_04DATA CFG0_FIFOLVL(3) /*!< set FIFO threshold level = 4-data frame */
#define SPI_FIFO_TH_05DATA CFG0_FIFOLVL(4) /*!< set FIFO threshold level = 5-data frame */
#define SPI_FIFO_TH_06DATA CFG0_FIFOLVL(5) /*!< set FIFO threshold level = 6-data frame */
#define SPI_FIFO_TH_07DATA CFG0_FIFOLVL(6) /*!< set FIFO threshold level = 7-data frame */
#define SPI_FIFO_TH_08DATA CFG0_FIFOLVL(7) /*!< set FIFO threshold level = 8-data frame */
#define SPI_FIFO_TH_09DATA CFG0_FIFOLVL(8) /*!< set FIFO threshold level = 9-data frame */
#define SPI_FIFO_TH_10DATA CFG0_FIFOLVL(9) /*!< set FIFO threshold level = 10-data frame */
#define SPI_FIFO_TH_11DATA CFG0_FIFOLVL(10) /*!< set FIFO threshold level = 11-data frame */
#define SPI_FIFO_TH_12DATA CFG0_FIFOLVL(11) /*!< set FIFO threshold level = 12-data frame */
#define SPI_FIFO_TH_13DATA CFG0_FIFOLVL(12) /*!< set FIFO threshold level = 13-data frame */
#define SPI_FIFO_TH_14DATA CFG0_FIFOLVL(13) /*!< set FIFO threshold level = 14-data frame */
#define SPI_FIFO_TH_15DATA CFG0_FIFOLVL(14) /*!< set FIFO threshold level = 15-data frame */
#define SPI_FIFO_TH_16DATA CFG0_FIFOLVL(15) /*!< set FIFO threshold level = 16-data frame */
/* SPI slave transmitter underrun detected operation */
#define CFG0_TXUROP(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
#define SPI_CONFIG_REGISTER_PATTERN CFG0_TXUROP(0) /*!< slave send a constant value defined by the SPI_URDATA register */
#define SPI_CONFIG_LAST_RECEIVED CFG0_TXUROP(1) /*!< slave send the data frame received from master lastly */
#define SPI_CONFIG_LAST_TRANSMITTED CFG0_TXUROP(2) /*!< Slave send the data frame which is lastly transmitted by itself */
/* SPI slave transmitter underrun detected config */
#define CFG0_TXURDT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
#define SPI_DETECT_BEGIN_DATA_FRAME CFG0_TXURDT(0) /*!< underrun detected at start of data frame (no bit 1 protection) */
#define SPI_DETECT_END_DATA_FRAME CFG0_TXURDT(1) /*!< underrun detected at end of last data frame */
#define SPI_DETECT_BEGIN_ACTIVE_NSS CFG0_TXURDT(2) /*!< underrun detected at start of NSS signal */
/* SPI CRC size */
#define CFG0_CRCSZ(regval) (BITS(16,20) & ((uint32_t)(regval) << 16))
#define SPI_CRCSIZE_4BIT CFG0_CRCSZ(3) /*!< SPI crc size is 4-bit */
#define SPI_CRCSIZE_5BIT CFG0_CRCSZ(4) /*!< SPI crc size is 5-bit */
#define SPI_CRCSIZE_6BIT CFG0_CRCSZ(5) /*!< SPI crc size is 6-bit */
#define SPI_CRCSIZE_7BIT CFG0_CRCSZ(6) /*!< SPI crc size is 7-bit */
#define SPI_CRCSIZE_8BIT CFG0_CRCSZ(7) /*!< SPI crc size is 8-bit */
#define SPI_CRCSIZE_9BIT CFG0_CRCSZ(8) /*!< SPI crc size is 9-bit */
#define SPI_CRCSIZE_10BIT CFG0_CRCSZ(9) /*!< SPI crc size is 10-bit */
#define SPI_CRCSIZE_11BIT CFG0_CRCSZ(10) /*!< SPI crc size is 11-bit */
#define SPI_CRCSIZE_12BIT CFG0_CRCSZ(11) /*!< SPI crc size is 12-bit */
#define SPI_CRCSIZE_13BIT CFG0_CRCSZ(12) /*!< SPI crc size is 13-bit */
#define SPI_CRCSIZE_14BIT CFG0_CRCSZ(13) /*!< SPI crc size is 14-bit */
#define SPI_CRCSIZE_15BIT CFG0_CRCSZ(14) /*!< SPI crc size is 15-bit */
#define SPI_CRCSIZE_16BIT CFG0_CRCSZ(15) /*!< SPI crc size is 16-bit */
#define SPI_CRCSIZE_17BIT CFG0_CRCSZ(16) /*!< SPI crc size is 17-bit */
#define SPI_CRCSIZE_18BIT CFG0_CRCSZ(17) /*!< SPI crc size is 18-bit */
#define SPI_CRCSIZE_19BIT CFG0_CRCSZ(18) /*!< SPI crc size is 19-bit */
#define SPI_CRCSIZE_20BIT CFG0_CRCSZ(19) /*!< SPI crc size is 20-bit */
#define SPI_CRCSIZE_21BIT CFG0_CRCSZ(20) /*!< SPI crc size is 21-bit */
#define SPI_CRCSIZE_22BIT CFG0_CRCSZ(21) /*!< SPI crc size is 22-bit */
#define SPI_CRCSIZE_23BIT CFG0_CRCSZ(22) /*!< SPI crc size is 23-bit */
#define SPI_CRCSIZE_24BIT CFG0_CRCSZ(23) /*!< SPI crc size is 24-bit */
#define SPI_CRCSIZE_25BIT CFG0_CRCSZ(24) /*!< SPI crc size is 25-bit */
#define SPI_CRCSIZE_26BIT CFG0_CRCSZ(25) /*!< SPI crc size is 26-bit */
#define SPI_CRCSIZE_27BIT CFG0_CRCSZ(26) /*!< SPI crc size is 27-bit */
#define SPI_CRCSIZE_28BIT CFG0_CRCSZ(27) /*!< SPI crc size is 28-bit */
#define SPI_CRCSIZE_29BIT CFG0_CRCSZ(28) /*!< SPI crc size is 29-bit */
#define SPI_CRCSIZE_30BIT CFG0_CRCSZ(29) /*!< SPI crc size is 30-bit */
#define SPI_CRCSIZE_31BIT CFG0_CRCSZ(30) /*!< SPI crc size is 31-bit */
#define SPI_CRCSIZE_32BIT CFG0_CRCSZ(31) /*!< SPI crc size is 32-bit */
/* SPI clock prescale factor */
#define CFG0_PSC(regval) (BITS(28,30) & ((uint32_t)(regval) << 28))
#define SPI_PSC_2 CFG0_PSC(0) /*!< SPI clock prescale factor is 2 */
#define SPI_PSC_4 CFG0_PSC(1) /*!< SPI clock prescale factor is 4 */
#define SPI_PSC_8 CFG0_PSC(2) /*!< SPI clock prescale factor is 8 */
#define SPI_PSC_16 CFG0_PSC(3) /*!< SPI clock prescale factor is 16 */
#define SPI_PSC_32 CFG0_PSC(4) /*!< SPI clock prescale factor is 32 */
#define SPI_PSC_64 CFG0_PSC(5) /*!< SPI clock prescale factor is 64 */
#define SPI_PSC_128 CFG0_PSC(6) /*!< SPI clock prescale factor is 128 */
#define SPI_PSC_256 CFG0_PSC(7) /*!< SPI clock prescale factor is 256 */
/* SPI NSS idleness delay */
#define CFG1_MSSD(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define SPI_NSS_IDLENESS_00CYCLE CFG1_MSSD(0) /*!< no delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_01CYCLE CFG1_MSSD(1) /*!< 1 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_02CYCLE CFG1_MSSD(2) /*!< 2 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_03CYCLE CFG1_MSSD(3) /*!< 3 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_04CYCLE CFG1_MSSD(4) /*!< 4 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_05CYCLE CFG1_MSSD(5) /*!< 5 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_06CYCLE CFG1_MSSD(6) /*!< 6 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_07CYCLE CFG1_MSSD(7) /*!< 7 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_08CYCLE CFG1_MSSD(8) /*!< 8 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_09CYCLE CFG1_MSSD(9) /*!< 9 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_10CYCLE CFG1_MSSD(10) /*!< 10 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_11CYCLE CFG1_MSSD(11) /*!< 11 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_12CYCLE CFG1_MSSD(12) /*!< 12 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_13CYCLE CFG1_MSSD(13) /*!< 13 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_14CYCLE CFG1_MSSD(14) /*!< 14 clock cycle delay between active edge of NSS and transmittion */
#define SPI_NSS_IDLENESS_15CYCLE CFG1_MSSD(15) /*!< 15 clock cycle delay between active edge of NSS and transmittion */
/* SPI master data frame delay */
#define CFG1_MDFD(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
#define SPI_DATA_IDLENESS_00CYCLE CFG1_MDFD(0) /*!< no delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_01CYCLE CFG1_MDFD(1) /*!< 1 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_02CYCLE CFG1_MDFD(2) /*!< 2 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_03CYCLE CFG1_MDFD(3) /*!< 3 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_04CYCLE CFG1_MDFD(4) /*!< 4 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_05CYCLE CFG1_MDFD(5) /*!< 5 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_06CYCLE CFG1_MDFD(6) /*!< 6 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_07CYCLE CFG1_MDFD(7) /*!< 7 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_08CYCLE CFG1_MDFD(8) /*!< 8 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_09CYCLE CFG1_MDFD(9) /*!< 9 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_10CYCLE CFG1_MDFD(10) /*!< 10 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_11CYCLE CFG1_MDFD(11) /*!< 11 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_12CYCLE CFG1_MDFD(12) /*!< 12 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_13CYCLE CFG1_MDFD(13) /*!< 13 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_14CYCLE CFG1_MDFD(14) /*!< 14 clock cycle delay between data frames in SPI master mode */
#define SPI_DATA_IDLENESS_15CYCLE CFG1_MDFD(15) /*!< 15 clock cycle delay between data frames in SPI master mode */
/* SPI IO swap */
#define SPI_IO_SWAP SPI_CFG1_SWPMIO /*!< SPI MOSI and MISO swap */
#define SPI_IO_NORMAL (~SPI_CFG1_SWPMIO) /*!< SPI MOSI and MISO no swap */
/* SPI bidirectional transfer direction */
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CFG1_BDOEN /*!< SPI work in transmit-only mode */
#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CFG1_BDOEN) /*!< SPI work in receive-only mode */
/* SPI transmit type */
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
#define SPI_TRANSMODE_RECEIVEONLY SPI_CFG1_RO /*!< SPI only receive data */
#define SPI_TRANSMODE_BDRECEIVE SPI_CFG1_BDEN /*!< bidirectional receive data */
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CFG1_BDEN | SPI_CFG1_BDOEN) /*!< bidirectional transmit data*/
/* SPI mode definitions */
#define SPI_MASTER SPI_CFG1_MSTMOD /*!< SPI as master */
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
/* SPI transmit way */
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
#define SPI_ENDIAN_LSB SPI_CFG1_LF /*!< SPI transmit way is little endian: transmit LSB first */
/* SPI clock phase and polarity */
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CFG1_CKPL /*!< SPI clock polarity is high level and phase is first edge */
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CFG1_CKPH /*!< SPI clock polarity is low level and phase is second edge */
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CFG1_CKPL | SPI_CFG1_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
/* SPI NSS control mode */
#define SPI_NSS_SOFT SPI_CFG1_NSSIM /*!< SPI NSS control by sofrware */
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */
/* SPI NSS polarity */
#define SPI_NSS_POLARITY_HIGH SPI_CFG1_NSSIOPL /*!< SPI NSS high level is active */
#define SPI_NSS_POLARITY_LOW ((uint32_t)0x00000000U) /*!< SPI NSS low level is active */
/* SPI NSS output control */
#define SPI_NSS_INVALID_PULSE SPI_CFG1_NSSCTL /*!< SPI data frames are interleaved with NSS invalid pulses */
#define SPI_NSS_HOLD_UNTIL_TRANS_END ((uint32_t)0x00000000U) /*!< SPI NSS remains active level until data transfer complete */
/* SPI af gpio control */
#define SPI_GPIO_CONTROL SPI_CFG1_AFCTL /*!< SPI always control all associated GPIO */
#define SPI_GPIO_FREE ((uint32_t)0x00000000U) /*!< SPI do not control GPIO when disabled */
/* SPI RxFIFO packing level */
#define STAT_RPLVL(regval) (BITS(13,14) & ((uint32_t)(regval) << 13))
#define SPI_RX_FIFO_0PACKET STAT_RPLVL(0) /*!< no frame or 4 frames stored in RxFIFO */
#define SPI_RX_FIFO_1PACKET STAT_RPLVL(1) /*!< 1 frame stored in RxFIFO */
#define SPI_RX_FIFO_2PACKET STAT_RPLVL(2) /*!< 2 frames stored in RxFIFO */
#define SPI_RX_FIFO_3PACKET STAT_RPLVL(3) /*!< 3 frames stored in RxFIFO */
/* I2S audio sample rate */
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
/* I2S frame format */
#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
/* I2S master clock output */
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
#define I2S_MCKOUT_ENABLE SPI_I2SCTL_MCKOEN /*!< I2S master clock output enable */
/* I2S operation mode */
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
/* I2S standard */
#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define I2S_STD_PHILIPS I2SCTL_I2SSTD(0) /*!< I2S philips standard */
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
/* I2S clock polarity */
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
/* SPI DMA constants definitions */
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
/* SPI CRC constants definitions */
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
/* SPI/I2S interrupt enable/disable constants definitions */
#define SPI_I2S_INT_RP ((uint8_t)0x00U) /*!< RP interrupt */
#define SPI_I2S_INT_TP ((uint8_t)0x01U) /*!< TP interrupt */
#define SPI_I2S_INT_DP ((uint8_t)0x02U) /*!< DP interrupt */
#define SPI_I2S_INT_ESTC ((uint8_t)0x03U) /*!< end of transfer or suspend or TXFIFO clear interrupt */
#define SPI_I2S_INT_TXF ((uint8_t)0x04U) /*!< transmission filled interrupt */
#define SPI_I2S_INT_TXURE ((uint8_t)0x05U) /*!< underrun error interrupt */
#define SPI_I2S_INT_RXORE ((uint8_t)0x06U) /*!< overrun error interrupt */
#define SPI_I2S_INT_CRCER ((uint8_t)0x07U) /*!< CRC error interrupt */
#define SPI_I2S_INT_FE ((uint8_t)0x08U) /*!< TI frame error interrupt */
#define SPI_I2S_INT_CONFE ((uint8_t)0x09U) /*!< mode error interrupt */
#define SPI_I2S_INT_TXSERF ((uint8_t)0x0AU) /*!< TXSER reload interrupt */
/* SPI/I2S interrupt flag constants definitions */
#define SPI_I2S_INT_FLAG_RP ((uint8_t)0x00U) /*!< RP interrupt flag */
#define SPI_I2S_INT_FLAG_TP ((uint8_t)0x01U) /*!< TP interrupt flag */
#define SPI_I2S_INT_FLAG_DP ((uint8_t)0x02U) /*!< DP interrupt flag */
#define SPI_I2S_INT_FLAG_ET ((uint8_t)0x03U) /*!< end of transfer or receive interrupt flag */
#define SPI_I2S_INT_FLAG_TXF ((uint8_t)0x04U) /*!< transmission filled interrupt flag */
#define SPI_I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x06U) /*!< overrun error interrupt flag */
#define SPI_I2S_INT_FLAG_CRCERR ((uint8_t)0x07U) /*!< CRC error interrupt flag */
#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x08U) /*!< TI frame error interrupt flag */
#define SPI_I2S_INT_FLAG_CONFERR ((uint8_t)0x09U) /*!< mode error interrupt flag */
#define SPI_I2S_INT_FLAG_TXSERF ((uint8_t)0x0AU) /*!< TXSER reload interrupt flag */
#define SPI_I2S_INT_FLAG_SPD ((uint8_t)0x0BU) /*!< suspend interrupt flag */
#define SPI_I2S_INT_FLAG_TC ((uint8_t)0x0CU) /*!< TXFIFO clear interrupt flag */
/* SPI/I2S flag definitions */
#define SPI_FLAG_RP SPI_STAT_RP /*!< RP flag */
#define SPI_FLAG_TP SPI_STAT_TP /*!< TP flag */
#define SPI_FLAG_DP SPI_STAT_DP /*!< DP flag */
#define SPI_FLAG_ET SPI_STAT_ET /*!< end of transfer or receive flag */
#define SPI_FLAG_TXF SPI_STAT_TXF /*!< transmission filled flag */
#define SPI_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
#define SPI_FLAG_FERR SPI_STAT_FERR /*!< TI frame error flag */
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode error flag */
#define SPI_FLAG_TXSERF SPI_STAT_TXSERF /*!< TXSER reload flag */
#define SPI_FLAG_SPD SPI_STAT_SPD /*!< suspend flag */
#define SPI_FLAG_TC SPI_STAT_TC /*!< TXFIFO clear flag */
#define SPI_FLAG_RPLVL SPI_STAT_RPLVL /*!< RxFIFO packing level flag */
#define SPI_FLAG_RWNE SPI_STAT_RWNE /*!< the word of RXFIFO is not empty flag */
#define SPI_FLAG_CTXSIZE SPI_STAT_CTXSIZE /*!< the number of data frames remaining in the TXSIZE session flag */
#define I2S_FLAG_RP SPI_STAT_RP /*!< RP flag */
#define I2S_FLAG_TP SPI_STAT_TP /*!< TP flag */
#define I2S_FLAG_DP SPI_STAT_DP /*!< DP flag */
#define I2S_FLAG_ET SPI_STAT_ET /*!< end of transfer or suspend or TXFIFO clear flag */
#define I2S_FLAG_TXF SPI_STAT_TXF /*!< transmission filled flag */
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check SPI peripherals */
#define NOT_SPI_PERIPH(periph) (((periph) != SPI0) && ((periph) != SPI1) && ((periph) != SPI2) && \
((periph) != SPI3) && ((periph) != SPI4) && ((periph) != SPI5))
#define NOT_I2S_PERIPH(periph) (((periph) != SPI0) && ((periph) != SPI1)&& ((periph) != SPI2)&& ((periph) != SPI5))
/* check SPI device mode */
#define NOT_SPI_DEVICE_MODE(device_mode) (((device_mode) != SPI_MASTER) && ((device_mode) != SPI_SLAVE))
/* check SPI trans mode */
#define NOT_SPI_TRANS_MODE(trans_mode) (((trans_mode) != SPI_TRANSMODE_FULLDUPLEX) && ((trans_mode) != SPI_TRANSMODE_RECEIVEONLY) && \
((trans_mode) != SPI_TRANSMODE_BDRECEIVE) && ((trans_mode) != SPI_TRANSMODE_BDTRANSMIT))
/* check SPI nss */
#define NOT_SPI_NSS(nss) (((nss) != SPI_NSS_SOFT) && ((nss) != SPI_NSS_HARD))
/* check SPI nss active polarity*/
#define NOT_SPI_NSS_POLARITY(polarity) (((polarity) != SPI_NSS_POLARITY_HIGH) && ((polarity) != SPI_NSS_POLARITY_LOW))
/* check SPI endian */
#define NOT_SPI_ENDIAN(endian) (((endian) != SPI_ENDIAN_MSB) && ((endian) != SPI_ENDIAN_LSB))
/* check SPI clock polarity phase */
#define NOT_SPI_CLOCK_PLORITY_PHRASE(clock_polarity_phase) (((clock_polarity_phase) != SPI_CK_PL_LOW_PH_1EDGE) && ((clock_polarity_phase) != SPI_CK_PL_HIGH_PH_1EDGE) && \
((clock_polarity_phase) != SPI_CK_PL_LOW_PH_2EDGE) && ((clock_polarity_phase) != SPI_CK_PL_HIGH_PH_2EDGE))
/* check SPI clock polarity phase */
#define NOT_SPI_PRESCALE(prescale) (((prescale) != SPI_PSC_2) && ((prescale) != SPI_PSC_4) && \
((prescale) != SPI_PSC_8) && ((prescale) != SPI_PSC_16) && \
((prescale) != SPI_PSC_32) && ((prescale) != SPI_PSC_64) && \
((prescale) != SPI_PSC_128) && ((prescale) != SPI_PSC_256))
/* check SPI pin swap mode */
#define NOT_SPI_SWAP_MODE(io_cfg) (((io_cfg) != SPI_IO_SWAP) && ((io_cfg) != SPI_IO_NORMAL))
/* check SPI i2s mode */
#define NOT_SPI_I2S_MODE(i2s_mode) (((i2s_mode) != I2S_MODE_SLAVETX) && ((i2s_mode) != I2S_MODE_SLAVERX) && \
((i2s_mode) != I2S_MODE_MASTERTX) && ((i2s_mode) != I2S_MODE_MASTERRX))
/* check SPI i2s standard */
#define NOT_SPI_I2S_STANDARD(i2s_standard) (((i2s_standard) != I2S_STD_PHILIPS) && ((i2s_standard) != I2S_STD_MSB) && \
((i2s_standard) != I2S_STD_LSB) && ((i2s_standard) != I2S_STD_PCMSHORT) && \
((i2s_standard) != I2S_STD_PCMLONG))
/* check SPI i2s ckpl */
#define NOT_SPI_I2S_CKPL(i2s_ckpl) (((i2s_ckpl) != I2S_CKPL_LOW) && ((i2s_ckpl) != I2S_CKPL_HIGH))
/* check SPI i2s audiosample */
#define NOT_SPI_I2S_AUDIOSAMPLE(i2s_audiosample) (((i2s_audiosample) != I2S_AUDIOSAMPLE_8K) && ((i2s_audiosample) != I2S_AUDIOSAMPLE_11K) && \
((i2s_audiosample) != I2S_AUDIOSAMPLE_16K) && ((i2s_audiosample) != I2S_AUDIOSAMPLE_22K) && \
((i2s_audiosample) != I2S_AUDIOSAMPLE_32K)&& ((i2s_audiosample) != I2S_AUDIOSAMPLE_44K) && \
((i2s_audiosample) != I2S_AUDIOSAMPLE_48K)&& ((i2s_audiosample) != I2S_AUDIOSAMPLE_96K) && \
((i2s_audiosample) != I2S_AUDIOSAMPLE_192K))
/* check SPI i2s frameformat */
#define NOT_SPI_I2S_FRAMEFORMAT(i2s_frameformat) (((i2s_frameformat) != I2S_FRAMEFORMAT_DT16B_CH16B) && ((i2s_frameformat) != I2S_FRAMEFORMAT_DT16B_CH32B) && \
((i2s_frameformat) != I2S_FRAMEFORMAT_DT24B_CH32B) && ((i2s_frameformat) != I2S_FRAMEFORMAT_DT32B_CH32B))
/* check SPI i2s mckout */
#define NOT_SPI_I2S_MCKOUT(i2s_mckout) (((i2s_mckout) != I2S_MCKOUT_ENABLE) && ((i2s_mckout) != I2S_MCKOUT_DISABLE))
/* check SPI dma mode */
#define NOT_SPI_DMA_MODE(spi_dma) (((spi_dma) != SPI_DMA_TRANSMIT) && ((spi_dma) != SPI_DMA_RECEIVE))
/* check SPI transfer direction */
#define NOT_SPI_TRANS_DIR(transfer_direction) (((transfer_direction) != SPI_BIDIRECTIONAL_TRANSMIT) && ((transfer_direction) != SPI_BIDIRECTIONAL_RECEIVE))
/* check SPI transfer direction */
#define NOT_SPI_NSS_OUT_MODE(nss_mode) (((nss_mode) != SPI_NSS_HOLD_UNTIL_TRANS_END) && ((nss_mode) != SPI_NSS_INVALID_PULSE))
/* check SPI/I2S master start transfer */
#define NOT_SPI_START_TRANS_MODE(trans_mode) (((trans_mode) != SPI_TRANS_START) && ((trans_mode) != SPI_TRANS_IDLE))
/* check SPI data size */
#define NOT_SPI_DATA_SIZE(size) (((size) != SPI_DATASIZE_4BIT)&& ((size) != SPI_DATASIZE_5BIT)&& ((size) != SPI_DATASIZE_6BIT) && \
((size) != SPI_DATASIZE_7BIT)&& ((size) != SPI_DATASIZE_8BIT) && \
((size) != SPI_DATASIZE_9BIT)&& ((size) != SPI_DATASIZE_10BIT) && \
((size) != SPI_DATASIZE_11BIT) && ((size) != SPI_DATASIZE_12BIT) && \
((size) != SPI_DATASIZE_13BIT)&& ((size) != SPI_DATASIZE_14BIT) && \
((size) != SPI_DATASIZE_15BIT)&& ((size) != SPI_DATASIZE_16BIT) && \
((size) != SPI_DATASIZE_17BIT)&& ((size) != SPI_DATASIZE_18BIT) && \
((size) != SPI_DATASIZE_19BIT) && ((size) != SPI_DATASIZE_20BIT) && \
((size) != SPI_DATASIZE_21BIT)&& ((size) != SPI_DATASIZE_22BIT) && \
((size) != SPI_DATASIZE_23BIT)&& ((size) != SPI_DATASIZE_24BIT) && \
((size) != SPI_DATASIZE_25BIT)&& ((size) != SPI_DATASIZE_26BIT) && \
((size) != SPI_DATASIZE_27BIT) && ((size) != SPI_DATASIZE_28BIT) && \
((size) != SPI_DATASIZE_29BIT)&& ((size) != SPI_DATASIZE_30BIT) && \
((size) != SPI_DATASIZE_31BIT)&& ((size) != SPI_DATASIZE_32BIT))
/* check NSS idleness size */
#define NOT_SPI_NSS_IDLE_SIZE(size) (((size) != SPI_NSS_IDLENESS_00CYCLE)&& ((size) != SPI_NSS_IDLENESS_01CYCLE)&& ((size) != SPI_NSS_IDLENESS_02CYCLE) && \
((size) != SPI_NSS_IDLENESS_03CYCLE)&& ((size) != SPI_NSS_IDLENESS_04CYCLE) && \
((size) != SPI_NSS_IDLENESS_05CYCLE)&& ((size) != SPI_NSS_IDLENESS_06CYCLE) && \
((size) != SPI_NSS_IDLENESS_07CYCLE) && ((size) != SPI_NSS_IDLENESS_08CYCLE) && \
((size) != SPI_NSS_IDLENESS_09CYCLE)&& ((size) != SPI_NSS_IDLENESS_10CYCLE) && \
((size) != SPI_NSS_IDLENESS_11CYCLE)&& ((size) != SPI_NSS_IDLENESS_12CYCLE) && \
((size) != SPI_NSS_IDLENESS_13CYCLE)&& ((size) != SPI_NSS_IDLENESS_14CYCLE) && \
((size) != SPI_NSS_IDLENESS_15CYCLE))
/* check DATA idleness size */
#define NOT_SPI_DATA_IDLE_SIZE(size) (((size) != SPI_DATA_IDLENESS_00CYCLE)&& ((size) != SPI_DATA_IDLENESS_01CYCLE)&& ((size) != SPI_DATA_IDLENESS_02CYCLE) && \
((size) != SPI_DATA_IDLENESS_03CYCLE)&& ((size) != SPI_DATA_IDLENESS_04CYCLE) && \
((size) != SPI_DATA_IDLENESS_05CYCLE)&& ((size) != SPI_DATA_IDLENESS_06CYCLE) && \
((size) != SPI_DATA_IDLENESS_07CYCLE) && ((size) != SPI_DATA_IDLENESS_08CYCLE) && \
((size) != SPI_DATA_IDLENESS_09CYCLE)&& ((size) != SPI_DATA_IDLENESS_10CYCLE) && \
((size) != SPI_DATA_IDLENESS_11CYCLE)&& ((size) != SPI_DATA_IDLENESS_12CYCLE) && \
((size) != SPI_DATA_IDLENESS_13CYCLE)&& ((size) != SPI_DATA_IDLENESS_14CYCLE) && \
((size) != SPI_DATA_IDLENESS_15CYCLE))
/* check SPI crc value */
#define NOT_SPI_CRC_VALUE(crc) (((crc) != SPI_CRC_TX) && ((crc) != SPI_CRC_RX))
/* check SPI tcrc value */
#define NOT_SPI_TCRC_VALUE(tcrc) (((tcrc) != SPI_TCRC_INIT_0) && ((tcrc) != SPI_TCRC_INIT_1))
/* check SPI rcrc value */
#define NOT_SPI_RCRC_VALUE(rcrc) (((rcrc) != SPI_RCRC_INIT_0) && ((rcrc) != SPI_RCRC_INIT_1))
/* check SPI transmitter underrun detected operation */
#define NOT_SPI_UNDERRUN_OPERAT(opreat) (((opreat) != SPI_CONFIG_REGISTER_PATTERN) && ((opreat) != SPI_CONFIG_LAST_RECEIVED) && ((opreat) != SPI_CONFIG_LAST_TRANSMITTED))
/* check SPI transmitter underrun detected */
#define NOT_SPI_UNDERRUN_DETECT(detect) (((detect) != SPI_DETECT_BEGIN_DATA_FRAME) && ((detect) != SPI_DETECT_END_DATA_FRAME) && ((detect) != SPI_DETECT_BEGIN_ACTIVE_NSS))
/* check SPI suspend in receive mode */
#define NOT_SPI_SUSPEND_CONFIG(susp_mode) (((susp_mode) != SPI_AUTO_SUSPEND) && ((susp_mode) != SPI_CONTINUOUS))
/* check SPI af gpio control */
#define NOT_SPI_AF_CONFIG(af_mode) (((af_mode) != SPI_GPIO_CONTROL) && ((af_mode) != SPI_GPIO_FREE))
/* check CRC length */
#define NOT_SPI_CRC_LENGTH(length) (((length) != SPI_CRCSIZE_4BIT) && ((length) != SPI_CRCSIZE_5BIT)&& ((length) != SPI_CRCSIZE_6BIT) && \
((length) != SPI_CRCSIZE_7BIT) && ((length) != SPI_CRCSIZE_8BIT) && \
((length) != SPI_CRCSIZE_9BIT) && ((length) != SPI_CRCSIZE_10BIT) && \
((length) != SPI_CRCSIZE_11BIT) && ((length) != SPI_CRCSIZE_12BIT) && \
((length) != SPI_CRCSIZE_13BIT) && ((length) != SPI_CRCSIZE_14BIT) && \
((length) != SPI_CRCSIZE_15BIT) && ((length) != SPI_CRCSIZE_16BIT) && \
((length) != SPI_CRCSIZE_17BIT) && ((length) != SPI_CRCSIZE_18BIT) && \
((length) != SPI_CRCSIZE_19BIT) && ((length) != SPI_CRCSIZE_20BIT) && \
((length) != SPI_CRCSIZE_21BIT) && ((length) != SPI_CRCSIZE_22BIT) && \
((length) != SPI_CRCSIZE_23BIT) && ((length) != SPI_CRCSIZE_24BIT) && \
((length) != SPI_CRCSIZE_25BIT) && ((length) != SPI_CRCSIZE_26BIT) && \
((length) != SPI_CRCSIZE_27BIT) && ((length) != SPI_CRCSIZE_28BIT) && \
((length) != SPI_CRCSIZE_29BIT) && ((length) != SPI_CRCSIZE_30BIT) && \
((length) != SPI_CRCSIZE_31BIT) && ((length) != SPI_CRCSIZE_32BIT))
/* check SPI/I2S flag status */
#define NOT_SPI_I2S_FLAG_STATUS(flag) (((flag) != SPI_FLAG_RP) && ((flag) != SPI_FLAG_TP) && \
((flag) != SPI_FLAG_DP) && ((flag) != SPI_FLAG_ET) && \
((flag) != SPI_FLAG_TXF) && ((flag) != SPI_FLAG_TXURERR) && \
((flag) != SPI_FLAG_RXORERR) && ((flag) != SPI_FLAG_CRCERR) && \
((flag) != SPI_FLAG_FERR) && ((flag) != SPI_FLAG_CONFERR) && \
((flag) != SPI_FLAG_TXSERF) && ((flag) != SPI_FLAG_SPD) && \
((flag) != SPI_FLAG_TC) && ((flag) != SPI_FLAG_RPLVL) && \
((flag) != SPI_FLAG_RWNE) && ((flag) != SPI_FLAG_CTXSIZE) && \
((flag) != I2S_FLAG_RP) && ((flag) != I2S_FLAG_TP) && \
((flag) != I2S_FLAG_DP) && ((flag) != I2S_FLAG_ET) && \
((flag) != I2S_FLAG_TXF) && ((flag) != I2S_FLAG_TXURERR) && ((flag) != I2S_FLAG_RXORERR))
/* check SPI/I2S clear flag */
#define NOT_SPI_I2S_CLEAR_FLAG(flag) (((flag) != SPI_STATC_ETC) && ((flag) != SPI_STATC_TXFC) && \
((flag) != SPI_STATC_TXURERRC) && ((flag) != SPI_STATC_RXORERRC) && \
((flag) != SPI_STATC_CRCERRC) && ((flag) != SPI_STATC_FERRC) && \
((flag) != SPI_STATC_CONFERRC) && ((flag) != SPI_STATC_TXSERFC) && \
((flag) != SPI_STATC_SPDC))
/* check SPI/I2S FIFO number */
#define NOT_SPI_I2S_FIFO_LEVEL(level) (((level) != SPI_FIFO_TH_01DATA) && ((level) != SPI_FIFO_TH_02DATA) && \
((level) != SPI_FIFO_TH_03DATA) && ((level) != SPI_FIFO_TH_04DATA) && \
((level) != SPI_FIFO_TH_05DATA) && ((level) != SPI_FIFO_TH_06DATA) && \
((level) != SPI_FIFO_TH_07DATA) && ((level) != SPI_FIFO_TH_08DATA) && \
((level) != SPI_FIFO_TH_09DATA) && ((level) != SPI_FIFO_TH_10DATA) && \
((level) != SPI_FIFO_TH_11DATA) && ((level) != SPI_FIFO_TH_12DATA) && \
((level) != SPI_FIFO_TH_13DATA) && ((level) != SPI_FIFO_TH_14DATA) && \
((level) != SPI_FIFO_TH_15DATA) && ((level) != SPI_FIFO_TH_16DATA))
/* check SPI/I2S interrupt */
#define NOT_SPI_I2S_INTERRUPT(interrupt) (((interrupt) != SPI_I2S_INT_RP) && ((interrupt) != SPI_I2S_INT_TP) && \
((interrupt) != SPI_I2S_INT_DP) && ((interrupt) != SPI_I2S_INT_ESTC) && \
((interrupt) != SPI_I2S_INT_TXF) && ((interrupt) != SPI_I2S_INT_TXURE) && \
((interrupt) != SPI_I2S_INT_RXORE) && ((interrupt) != SPI_I2S_INT_CRCER) && \
((interrupt) != SPI_I2S_INT_FE) && ((interrupt) != SPI_I2S_INT_CONFE) && \
((interrupt) != SPI_I2S_INT_TXSERF))
/* check SPI/I2S interrupt flag status */
#define NOT_SPI_I2S_INTERRUPT_FLAG_STATUS(flag) (((flag) != SPI_I2S_INT_FLAG_RP) && ((flag) != SPI_I2S_INT_FLAG_TP) && \
((flag) != SPI_I2S_INT_FLAG_DP) && ((flag) != SPI_I2S_INT_FLAG_ET) && \
((flag) != SPI_I2S_INT_FLAG_TXF) && ((flag) != SPI_I2S_INT_FLAG_TXURERR) && \
((flag) != SPI_I2S_INT_FLAG_RXORERR) && ((flag) != SPI_I2S_INT_FLAG_CRCERR) && \
((flag) != SPI_I2S_INT_FLAG_FERR) && ((flag) != SPI_I2S_INT_FLAG_CONFERR) && \
((flag) != SPI_I2S_INT_FLAG_TXSERF) && ((flag) != SPI_I2S_INT_FLAG_SPD) && \
((flag) != SPI_I2S_INT_FLAG_TC))
/* check SPI master mode rx clock delay */
#define NOT_SPI_RX_CLK_NUM(clk_num) (((clk_num) > 0x1FU))
/* check SPI transfer current data number */
#define NOT_SPI_TRANS_NUM(num) (((num) > 0xFFFFU))
/* check SPI reload data number */
#define NOT_SPI_RELOAD_NUM(num) (((num) > 0xFFFFU))
#endif
/* function declarations */
/* initialization functions */
/* reset SPI and I2S */
void spi_i2s_deinit(uint32_t spi_periph);
/* initialize the parameters of SPI struct with the default values */
void spi_struct_para_init(spi_parameter_struct* spi_struct);
/* initialize SPI parameter */
void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
/* enable SPI */
void spi_enable(uint32_t spi_periph);
/* disable SPI */
void spi_disable(uint32_t spi_periph);
/* initialize I2S parameter */
void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl);
/* configure I2S prescaler */
void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout);
/* enable I2S */
void i2s_enable(uint32_t spi_periph);
/* disable I2S */
void i2s_disable(uint32_t spi_periph);
/* IO swap functions */
/* SPI MOSI and MISO pin swap */
void spi_io_config(uint32_t spi_periph, uint32_t io_cfg);
/* SPI delay config functions */
/* set delay between active edge of NSS and start transfer or receive data in SPI master mode */
void spi_nss_idleness_delay_set(uint32_t spi_periph, uint32_t delay_cycle);
/* set SPI master data frame delay */
void spi_data_frame_delay_set(uint32_t spi_periph, uint32_t delay_cycle);
/* set SPI master mode rx clock delay */
void spi_master_receive_clock_delay_set(uint32_t spi_periph, uint32_t delay_unit);
/* set SPI slave mode rx clock delay */
void spi_slave_receive_clock_delay_set(uint32_t spi_periph, uint32_t delay_unit);
/* clear SPI master mode rx clock delay */
void spi_master_receive_clock_delay_clear(uint32_t spi_periph);
/* clear SPI slave mode rx clock delay */
void spi_slave_receive_clock_delay_clear(uint32_t spi_periph);
/* NSS functions */
/* NSS output control */
void spi_nss_output_control(uint32_t spi_periph, uint32_t nss_ctl);
/* set SPI NSS active polarity */
void spi_nss_polarity_set(uint32_t spi_periph, uint32_t polarity);
/* enable SPI NSS output */
void spi_nss_output_enable(uint32_t spi_periph);
/* disable SPI NSS output */
void spi_nss_output_disable(uint32_t spi_periph);
/* SPI NSS pin high level in software mode */
void spi_nss_internal_high(uint32_t spi_periph);
/* SPI NSS pin low level in software mode */
void spi_nss_internal_low(uint32_t spi_periph);
/* SPI DMA functions */
/* enable SPI DMA */
void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma);
/* disable SPI DMA */
void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma);
/* SPI/I2S transfer configure functions */
/* configure SPI/I2S data frame size */
void spi_i2s_data_frame_size_config(uint32_t spi_periph, uint32_t frame_size);
/* SPI/I2S transmit data */
void spi_i2s_data_transmit(uint32_t spi_periph, uint32_t data);
/* SPI/I2S receive data */
uint32_t spi_i2s_data_receive(uint32_t spi_periph);
/* configure SPI bidirectional transfer direction */
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
/* SPI/I2S master start transfer */
void spi_master_transfer_start(uint32_t spi_periph, uint32_t transfer_start);
/* configure SPI current data number */
void spi_current_data_num_config(uint32_t spi_periph, uint32_t current_num);
/* configure SPI reload data number */
void spi_reload_data_num_config(uint32_t spi_periph, uint32_t reload_num);
/* SPI CRC functions */
/* set SPI CRC polynomial */
void spi_crc_polynomial_set(uint32_t spi_periph, uint32_t crc_poly);
/* get SPI CRC polynomial */
uint32_t spi_crc_polynomial_get(uint32_t spi_periph);
/* configure SPI CRC length */
void spi_crc_length_config(uint32_t spi_periph, uint32_t crc_size);
/* turn on SPI CRC function */
void spi_crc_on(uint32_t spi_periph);
/* turn off SPI CRC function */
void spi_crc_off(uint32_t spi_periph);
/* get SPI CRC send value or receive value */
uint32_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
/* enable SPI CRC full size(33 bit or 17 bit) polynomial */
void spi_crc_full_size_enable(uint32_t spi_periph);
/* disable SPI CRC full size(33 bit or 17 bit) polynomial */
void spi_crc_full_size_disable(uint32_t spi_periph);
/* configure SPI TCRC init pattern */
void spi_tcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern);
/* configure SPI RCRC init pattern */
void spi_rcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern);
/* SPI TI mode functions */
/* enable SPI TI mode */
void spi_ti_mode_enable(uint32_t spi_periph);
/* disable SPI TI mode */
void spi_ti_mode_disable(uint32_t spi_periph);
/* quad wire SPI functions */
/* enable quad wire SPI */
void spi_quad_enable(uint32_t spi_periph);
/* disable quad wire SPI */
void spi_quad_disable(uint32_t spi_periph);
/* enable quad wire SPI write */
void spi_quad_write_enable(uint32_t spi_periph);
/* enable quad wire SPI read */
void spi_quad_read_enable(uint32_t spi_periph);
/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
void spi_quad_io23_output_enable(uint32_t spi_periph);
/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
void spi_quad_io23_output_disable(uint32_t spi_periph);
/* SPI underrun functions */
/* slave transmitter underrun detected operation */
void spi_underrun_operation(uint32_t spi_periph, uint32_t ur_ope);
/* configure slave transmitter underrun detected */
void spi_underrun_config(uint32_t spi_periph, uint32_t ur_cfg);
/* configure underrun data at slave mode */
void spi_underrun_data_config(uint32_t spi_periph, uint32_t udata);
/* SPI suspend functions */
/* configure SPI suspend in receive mode */
void spi_suspend_mode_config(uint32_t spi_periph, uint32_t sus_mode);
/* SPI master mode suspend request */
void spi_suspend_request(uint32_t spi_periph);
/* SPI Related IOS AF functions */
/* enable SPI related IOs AF */
void spi_related_ios_af_enable(uint32_t spi_periph);
/* disable SPI related IOs AF */
void spi_related_ios_af_disable(uint32_t spi_periph);
/* SPI af gpio control */
void spi_af_gpio_control(uint32_t spi_periph, uint32_t ctl);
/* flag and interrupt functions */
/* enable SPI and I2S interrupt */
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
/* disable SPI and I2S interrupt */
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
/* get SPI and I2S interrupt flag status */
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
/* get SPI and I2S flag status */
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
/* clear SPI and I2S flag status */
void spi_i2s_flag_clear(uint32_t spi_periph, uint32_t flag);
/* get SPI and I2S RXFIFO packing level */
uint32_t spi_i2s_rxfifo_plevel_get(uint32_t spi_periph);
/* get SPI and I2S remaining data frames number in the TXSIZE session */
uint32_t spi_i2s_remain_data_num_get(uint32_t spi_periph);
/* SPI FIFO configure */
/* set SPI FIFO threshold level */
void spi_fifo_threshold_level_set(uint32_t spi_periph, uint32_t fifo_thl);
/* enable SPI word access */
void spi_word_access_enable(uint32_t spi_periph);
/* disable SPI word access */
void spi_word_access_disable(uint32_t spi_periph);
/* enable SPI byte access */
void spi_byte_access_enable(uint32_t spi_periph);
/* disable SPI byte access */
void spi_byte_access_disable(uint32_t spi_periph);
#endif /* GD32H75E_SPI_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_syscfg.h
+695
View File
@@ -0,0 +1,695 @@
/*!
\file gd32h75e_syscfg.h
\brief definitions for the SYSCFG
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_SYSCFG_H
#define GD32H75E_SYSCFG_H
#include "gd32h75e.h"
/* SYSCFG definitions */
#define SYSCFG SYSCFG_BASE /*!< SYSCFG base address */
/* registers definitions */
#define SYSCFG_PMCFG REG32(SYSCFG + 0x00000004U) /*!< SYSCFG peripheral mode configuration register */
#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x00000008U) /*!< EXTI sources selection register 0 */
#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0000000CU) /*!< EXTI sources selection register 1 */
#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x00000010U) /*!< EXTI sources selection register 2 */
#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x00000014U) /*!< EXTI sources selection register 3 */
#define SYSCFG_LKCTL REG32(SYSCFG + 0x00000018U) /*!< SYSCFG lock control register */
#define SYSCFG_CPSCTL REG32(SYSCFG + 0x00000020U) /*!< SYSCFG I/O compensation control register */
#define SYSCFG_CPSCCCFG REG32(SYSCFG + 0x00000028U) /*!< SYSCFG I/O compensation cell code configuration */
#define SYSCFG_TIMERCISEL0 REG32(SYSCFG + 0x00000034U) /*!< SYSCFG timer input selection register 0 */
#define SYSCFG_TIMERCISEL1 REG32(SYSCFG + 0x00000038U) /*!< SYSCFG timer input selection register 1 */
#define SYSCFG_TIMERCISEL2 REG32(SYSCFG + 0x0000003CU) /*!< SYSCFG timer input selection register 2 */
#define SYSCFG_TIMERCISEL3 REG32(SYSCFG + 0x00000040U) /*!< SYSCFG timer input selection register 3 */
#define SYSCFG_TIMERCISEL5 REG32(SYSCFG + 0x00000048U) /*!< SYSCFG timer input selection register 5 */
#define SYSCFG_TIMERCISEL6 REG32(SYSCFG + 0x0000004CU) /*!< SYSCFG timer input selection register 6 */
#define SYSCFG_CPUICAC REG32(SYSCFG + 0x00000054U) /*!< SYSCFG CPU icache error status register */
#define SYSCFG_CPUDCAC REG32(SYSCFG + 0x00000058U) /*!< SYSCFG CPU dcache error status register */
#define SYSCFG_FPUINTEN REG32(SYSCFG + 0x0000005CU) /*!< SYSCFG FPU interrupt enable register */
#define SYSCFG_SRAMCFG0 REG32(SYSCFG + 0x00000064U) /*!< SYSCFG SRAM configuration register 0*/
#define SYSCFG_SRAMCFG1 REG32(SYSCFG + 0x00000068U) /*!< SYSCFG SRAM configuration register 1*/
#define SYSCFG_USERCFG REG32(SYSCFG + 0x00000300U) /*!< SYSCFG user configuration register */
/* SYSCFG_PMCFG bits definitions */
#define SYSCFG_PMCFG_I2C0FMPEN BIT(0) /*!< I2C0 fast mode plus enable */
#define SYSCFG_PMCFG_I2C1FMPEN BIT(1) /*!< I2C1 fast mode plus enable */
#define SYSCFG_PMCFG_I2C2FMPEN BIT(2) /*!< I2C2 fast mode plus enable */
#define SYSCFG_PMCFG_I2C3FMPEN BIT(3) /*!< I2C3 fast mode plus enable */
#define SYSCFG_PMCFG_PB6FMPEN BIT(4) /*!< I2C fast mode plus on PB6 pin enable */
#define SYSCFG_PMCFG_PB7FMPEN BIT(5) /*!< I2C fast mode plus on PB7 pin enable */
#define SYSCFG_PMCFG_PB8FMPEN BIT(6) /*!< I2C fast mode plus on PB8 pin enable */
#define SYSCFG_PMCFG_PB9FMPEN BIT(7) /*!< I2C fast mode plus on PB9 pin enable */
#define SYSCFG_PMCFG_PA0SWON BIT(24) /*!< PA0 switch open */
#define SYSCFG_PMCFG_PA1SWON BIT(25) /*!< PA1 switch open */
#define SYSCFG_PMCFG_PC2SWON BIT(26) /*!< PC2 switch open */
#define SYSCFG_PMCFG_PC3SWON BIT(27) /*!< PC3 switch open */
/* SYSCFG_EXTISS0 bits definitions */
#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */
#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */
#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */
#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */
/* SYSCFG_EXTISS1 bits definitions */
#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */
#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */
#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */
#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */
/* SYSCFG_EXTISS2 bits definitions */
#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */
#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */
#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */
#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */
/* SYSCFG_EXTISS3 bits definitions */
#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */
#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */
#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */
#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */
/* SYSCFG_LKCTL bits definitions */
#define SYSCFG_LKCTL_LVD_LOCK BIT(2) /*!< programmable voltage detector lockup */
#define SYSCFG_LKCTL_CPU_LOCK BIT(6) /*!< CPU lockup */
#define SYSCFG_LKCTL_BKPRAM_LOCK BIT(7) /*!< Region 2 backup SRAM ECC double error lockup */
#define SYSCFG_LKCTL_SRAM1_LOCK BIT(11) /*!< Region 1 SRAM1 ECC double error lockup */
#define SYSCFG_LKCTL_SRAM0_LOCK BIT(12) /*!< Region 1 SRAM0 ECC double error lockup */
#define SYSCFG_LKCTL_DTCM_LOCK BIT(13) /*!< Region 0 DTCM ECC double error lock */
#define SYSCFG_LKCTL_ITCM_LOCK BIT(14) /*!< Region 0 ITCM-RAM ECC double error lock */
#define SYSCFG_LKCTL_AXIRAM_LOCK BIT(15) /*!< Region 0 AXI-SRAM ECC double error lock */
/* SYSCFG_CPSCTL bits definitions */
#define SYSCFG_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */
#define SYSCFG_CPSCTL_CPS_RDY BIT(8) /*!< Compensation cell ready flag */
#define SYSCFG_CPSCTL_IOSPDOP BIT(16) /*!< I/O speed optimization, high-speed at low-voltage */
#define SYSCFG_CPSCTL_IOLV BIT(23) /*!< I/O in low voltage state */
/* SYSCFG_CPSCCCFG bits definitions */
#define SYSCFG_CPSCCCFG_NCPSCC BITS(0,3) /*!< NMOS compensation cell code */
#define SYSCFG_CPSCCCFG_PCPSCC BITS(4,7) /*!< PMOS compensation cell code */
/* SYSCFG_TIMERCISEL0 bits definitions */
#define SYSCFG_TIMER7_CI0_SEL BITS(0,3) /*!< selects TIMER7_CI0 input */
#define SYSCFG_TIMER7_CI1_SEL BITS(4,7) /*!< selects TIMER7_CI1 input */
#define SYSCFG_TIMER7_CI2_SEL BITS(8,11) /*!< selects TIMER7_CI2 input */
#define SYSCFG_TIMER7_CI3_SEL BITS(12,15) /*!< selects TIMER7_CI3 input */
#define SYSCFG_TIMER0_CI0_SEL BITS(16,19) /*!< selects TIMER0_CI0 input */
#define SYSCFG_TIMER0_CI1_SEL BITS(20,23) /*!< selects TIMER0_CI1 input */
#define SYSCFG_TIMER0_CI2_SEL BITS(24,27) /*!< selects TIMER0_CI2 input */
#define SYSCFG_TIMER0_CI3_SEL BITS(28,31) /*!< selects TIMER0_CI3 input */
/* SYSCFG_TIMERCISEL1 bits definitions */
#define SYSCFG_TIMER2_CI0_SEL BITS(0,3) /*!< selects TIMER2_CI0 input */
#define SYSCFG_TIMER2_CI1_SEL BITS(4,7) /*!< selects TIMER2_CI1 input */
#define SYSCFG_TIMER2_CI2_SEL BITS(8,11) /*!< selects TIMER2_CI2 input */
#define SYSCFG_TIMER2_CI3_SEL BITS(12,15) /*!< selects TIMER2_CI3 input */
#define SYSCFG_TIMER1_CI0_SEL BITS(16,19) /*!< selects TIMER1_CI0 input */
#define SYSCFG_TIMER1_CI1_SEL BITS(20,23) /*!< selects TIMER1_CI1 input */
#define SYSCFG_TIMER1_CI2_SEL BITS(24,27) /*!< selects TIMER1_CI2 input */
#define SYSCFG_TIMER1_CI3_SEL BITS(28,31) /*!< selects TIMER1_CI3 input */
/* SYSCFG_TIMERCISEL2 bits definitions */
#define SYSCFG_TIMER4_CI0_SEL BITS(0,3) /*!< selects TIMER4_CI0 input */
#define SYSCFG_TIMER4_CI1_SEL BITS(4,7) /*!< selects TIMER4_CI1 input */
#define SYSCFG_TIMER4_CI2_SEL BITS(8,11) /*!< selects TIMER4_CI2 input */
#define SYSCFG_TIMER4_CI3_SEL BITS(12,15) /*!< selects TIMER4_CI3 input */
#define SYSCFG_TIMER3_CI0_SEL BITS(16,19) /*!< selects TIMER3_CI0 input */
#define SYSCFG_TIMER3_CI1_SEL BITS(20,23) /*!< selects TIMER3_CI1 input */
#define SYSCFG_TIMER3_CI2_SEL BITS(24,27) /*!< selects TIMER3_CI2 input */
#define SYSCFG_TIMER3_CI3_SEL BITS(28,31) /*!< selects TIMER3_CI3 input */
/* SYSCFG_TIMERCISEL3 bits definitions */
#define SYSCFG_TIMER23_CI0_SEL BITS(0,3) /*!< selects TIMER23_CI0 input */
#define SYSCFG_TIMER23_CI1_SEL BITS(4,7) /*!< selects TIMER23_CI1 input */
#define SYSCFG_TIMER23_CI2_SEL BITS(8,11) /*!< selects TIMER23_CI2 input */
#define SYSCFG_TIMER23_CI3_SEL BITS(12,15) /*!< selects TIMER23_CI3 input */
#define SYSCFG_TIMER22_CI0_SEL BITS(16,19) /*!< selects TIMER22_CI0 input */
#define SYSCFG_TIMER22_CI1_SEL BITS(20,23) /*!< selects TIMER22_CI1 input */
#define SYSCFG_TIMER22_CI2_SEL BITS(24,27) /*!< selects TIMER22_CI2 input */
#define SYSCFG_TIMER22_CI3_SEL BITS(28,31) /*!< selects TIMER22_CI3 input */
/* SYSCFG_TIMERCISEL5 bits definitions */
#define SYSCFG_TIMER14_CI0_SEL BITS(0,3) /*!< selects TIMER14_CI0 input */
#define SYSCFG_TIMER14_CI1_SEL BITS(4,7) /*!< selects TIMER14_CI1 input */
#define SYSCFG_TIMER40_CI0_SEL BITS(8,11) /*!< selects TIMER40_CI0 input */
#define SYSCFG_TIMER40_CI1_SEL BITS(12,15) /*!< selects TIMER40_CI1 input */
#define SYSCFG_TIMER41_CI0_SEL BITS(16,19) /*!< selects TIMER41_CI0 input */
#define SYSCFG_TIMER41_CI1_SEL BITS(20,23) /*!< selects TIMER41_CI1 input */
#define SYSCFG_TIMER42_CI0_SEL BITS(24,27) /*!< selects TIMER42_CI0 input */
#define SYSCFG_TIMER42_CI1_SEL BITS(28,31) /*!< selects TIMER42_CI1 input */
/* SYSCFG_TIMERCISEL6 bits definitions */
#define SYSCFG_TIMER15_CI0_SEL BITS(0,3) /*!< selects TIMER15_CI0 input */
#define SYSCFG_TIMER16_CI0_SEL BITS(4,7) /*!< selects TIMER16_CI0 input */
#define SYSCFG_TIMER43_CI0_SEL BITS(8,11) /*!< selects TIMER43_CI0 input */
#define SYSCFG_TIMER43_CI1_SEL BITS(12,15) /*!< selects TIMER43_CI1 input */
#define SYSCFG_TIMER44_CI0_SEL BITS(16,19) /*!< selects TIMER44_CI0 input */
#define SYSCFG_TIMER44_CI1_SEL BITS(20,23) /*!< selects TIMER44_CI1 input */
/* CPU ICACHE error status bits definitions */
#define SYSCFG_CPUICAC_CPU_ICERR BITS(6,27) /*!< CPU ICACHE error bank information */
#define SYSCFG_CPUICAC_CPU_ICDET BITS(28,31) /*!< CPU ICACHE error detection information */
/* CPU DCACHE error status bits definitions */
#define SYSCFG_CPUDCAC_CPU_DCERR BITS(6,27) /*!< CPU DCACHE error bank information */
#define SYSCFG_CPUDCAC_CPU_DCDET BITS(28,31) /*!< CPU DCACHE error detection information */
/* floating point unit interrupt enable bits definitions */
#define SYSCFG_FPUINTEN_IOPIE BIT(0) /*!< invalid operation interrupt enable */
#define SYSCFG_FPUINTEN_DZIE BIT(1) /*!< divide-by-zero interrupt enable */
#define SYSCFG_FPUINTEN_UFIE BIT(2) /*!< underflow interrupt enable */
#define SYSCFG_FPUINTEN_OVFIE BIT(3) /*!< overflow interrupt enable */
#define SYSCFG_FPUINTEN_IDIE BIT(4) /*!< input abnormal interrupt enable */
#define SYSCFG_FPUINTEN_IXIE BIT(5) /*!< inexact interrupt enable */
/* SRAM configuration register 0 */
#define SYSCFG_SRAMCFG0_SECURE_SRAM_SIZE BITS(0,1) /*!< size of secure sram */
/* SRAM configuration register 1 */
#define SYSCFG_SRAMCFG1_TCM_WAITSTATE BIT(0) /*!< TCM wait state configuration */
/* TIMER trigger selection register */
#define SYSCFG_TIMERCFG_TSCFG0 BITS(0,4) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG1 BITS(5,9) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG2 BITS(10,14) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG3 BITS(16,20) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG4 BITS(21,25) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG5 BITS(26,30) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG6 BITS(0,4) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG7 BITS(5,9) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG8 BITS(10,14) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG9 BITS(16,20) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG10 BITS(21,25) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG11 BITS(26,30) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG12 BITS(0,4) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG13 BITS(5,9) /*!< TIMER trigger selection */
#define SYSCFG_TIMERCFG_TSCFG14 BITS(10,14) /*!< TIMER trigger selection */
/* SYSCFG_USERCFG bits definitions */
#define SYSCFG_USERCFG_BOR_TH BITS(0,1) /*!< BOR threshold status bits */
#define SYSCFG_USERCFG_BOOT_MODE BITS(4,6) /*!< BOOT mode */
/* constants definitions */
/* I2Cx fast mode plus enable definitions */
#define SYSCFG_I2C0_FMP SYSCFG_PMCFG_I2C0FMPEN /*!< I2C0 fast mode plus */
#define SYSCFG_I2C1_FMP SYSCFG_PMCFG_I2C1FMPEN /*!< I2C1 fast mode plus */
#define SYSCFG_I2C2_FMP SYSCFG_PMCFG_I2C2FMPEN /*!< I2C2 fast mode plus */
#define SYSCFG_I2C3_FMP SYSCFG_PMCFG_I2C3FMPEN /*!< I2C3 fast mode plus */
#define SYSCFG_I2C_FMP_PB6 SYSCFG_PMCFG_PB6FMPEN /*!< I2C fast mode plus on PB6 pin */
#define SYSCFG_I2C_FMP_PB7 SYSCFG_PMCFG_PB7FMPEN /*!< I2C fast mode plus on PB7 pin */
#define SYSCFG_I2C_FMP_PB8 SYSCFG_PMCFG_PB8FMPEN /*!< I2C fast mode plus on PB8 pin */
#define SYSCFG_I2C_FMP_PB9 SYSCFG_PMCFG_PB9FMPEN /*!< I2C fast mode plus on PB9 pin */
/* pin analog switch definitions */
#define SYSCFG_PA0_ANALOG_SWITCH SYSCFG_PMCFG_PA0SWON /*!< PA0 analog switch */
#define SYSCFG_PA1_ANALOG_SWITCH SYSCFG_PMCFG_PA1SWON /*!< PA1 analog switch */
#define SYSCFG_PC2_ANALOG_SWITCH SYSCFG_PMCFG_PC2SWON /*!< PC2 analog switch */
#define SYSCFG_PC3_ANALOG_SWITCH SYSCFG_PMCFG_PC3SWON /*!< PC3 analog switch */
/* EXTI source select definitions */
#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */
#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */
#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */
#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */
/* EXTI source select mask bits definition */
#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */
/* EXTI source select jumping step definition */
#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */
/* EXTI source select moving step definition */
#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */
/* EXTI source port definitions */
#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */
#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */
#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */
#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */
#define EXTI_SOURCE_GPIOE ((uint8_t)0x04U) /*!< EXTI GPIOE configuration */
#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */
#define EXTI_SOURCE_GPIOG ((uint8_t)0x06U) /*!< EXTI GPIOG configuration */
#define EXTI_SOURCE_GPIOH ((uint8_t)0x07U) /*!< EXTI GPIOH configuration */
#define EXTI_SOURCE_GPIOJ ((uint8_t)0x09U) /*!< EXTI GPIOJ configuration */
#define EXTI_SOURCE_GPIOK ((uint8_t)0x0AU) /*!< EXTI GPIOK configuration */
/* EXTI source pin definitions */
#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */
#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */
#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */
#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */
#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */
#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */
#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */
#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */
#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */
#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */
#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */
#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */
#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */
#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */
#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */
#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */
/* MOS mode definitions */
#define PMOS_COMPENSATION ((uint8_t)0x00U) /*!< PMOS compensation */
#define NMOS_COMPENSATION ((uint8_t)0x01U) /*!< NMOS compensation */
/* timer input select definition */
#define TIMERCISEL0 ((uint8_t)0x00U) /*!< TIMER input select register 0 */
#define TIMERCISEL1 ((uint8_t)0x01U) /*!< TIMER input select register 1 */
#define TIMERCISEL2 ((uint8_t)0x02U) /*!< TIMER input select register 2 */
#define TIMERCISEL3 ((uint8_t)0x03U) /*!< TIMER input select register 3 */
#define TIMERCISEL5 ((uint8_t)0x05U) /*!< TIMER input select register 5 */
#define TIMERCISEL6 ((uint8_t)0x06U) /*!< TIMER input select register 6 */
/* define the timer bit position and its register index offset */
#define TIMER_REGIDX_BIT(regidx, bitpos, value) (((uint32_t)(regidx) << 24U) | (uint32_t)((bitpos) << 16U)\
| ((uint32_t)(value)))
#define TIMER_REG_INDEX(val) (((uint32_t)(val) & 0xFF000000U) >> 24U)
#define TIMER_BIT_POS(val) (((uint32_t)(val) & 0x00FF0000U) >> 16U)
#define TIMER_SEL_VAL(val) ((uint32_t)(val) & 0x000000FFU)
/* TIMERx channel input select definitions */
typedef enum {
TIMER7_CI0_INPUT_TIMER7_CH0 = TIMER_REGIDX_BIT(TIMERCISEL0, 0U, 0U), /*!< select CMP1 output as TIMER7 CI0 */
TIMER7_CI0_INPUT_CMP1_OUT = TIMER_REGIDX_BIT(TIMERCISEL0, 0U, 1U), /*!< select TIMER7 CH0 as TIMER7 CI0 */
TIMER7_CI1_INPUT_TIMER7_CH1 = TIMER_REGIDX_BIT(TIMERCISEL0, 4U, 0U), /*!< select TIMER7 CH1 as TIMER7 CI1 */
TIMER7_CI2_INPUT_TIMER7_CH2 = TIMER_REGIDX_BIT(TIMERCISEL0, 8U, 0U), /*!< select TIMER7 CH2 as TIMER7 CI2 */
TIMER7_CI3_INPUT_TIMER7_CH3 = TIMER_REGIDX_BIT(TIMERCISEL0, 12U, 0U), /*!< select TIMER7 CH3 as TIMER7 CI3 */
TIMER0_CI0_INPUT_TIMER0_CH0 = TIMER_REGIDX_BIT(TIMERCISEL0, 16U, 0U), /*!< select CMP0 output as TIMER0 CI0 */
TIMER0_CI0_INPUT_CMP0_OUT = TIMER_REGIDX_BIT(TIMERCISEL0, 16U, 1U), /*!< select TIMER0 CH0 as TIMER0 CI0 */
TIMER0_CI1_INPUT_TIMER0_CH1 = TIMER_REGIDX_BIT(TIMERCISEL0, 20U, 0U), /*!< select TIMER0 CH1 as TIMER0 CI1 */
TIMER0_CI2_INPUT_TIMER0_CH2 = TIMER_REGIDX_BIT(TIMERCISEL0, 24U, 0U), /*!< select TIMER0 CH2 as TIMER0 CI2 */
TIMER0_CI3_INPUT_TIMER0_CH3 = TIMER_REGIDX_BIT(TIMERCISEL0, 28U, 0U), /*!< select TIMER0 CH3 as TIMER0 CI3 */
TIMER2_CI0_INPUT_TIMER2_CH0 = TIMER_REGIDX_BIT(TIMERCISEL1, 0U, 0U), /*!< select TIMER2 CH0 as TIMER2 CI0 */
TIMER2_CI0_INPUT_CMP0_OUT = TIMER_REGIDX_BIT(TIMERCISEL1, 0U, 1U), /*!< select CMP0 as TIMER2 CI0 */
TIMER2_CI0_INPUT_CMP1_OUT = TIMER_REGIDX_BIT(TIMERCISEL1, 0U, 2U), /*!< select CMP1 as TIMER2 CI0 */
TIMER2_CI0_INPUT_CMP0_OR_CMP1_OUT = TIMER_REGIDX_BIT(TIMERCISEL1, 0U, 3U), /*!< select CMP0 or CMP1 as TIMER2 CI0 */
TIMER2_CI1_INPUT_TIMER2_CH1 = TIMER_REGIDX_BIT(TIMERCISEL1, 4U, 0U), /*!< select TIMER2 CH1 as TIMER2 CI1 */
TIMER2_CI2_INPUT_TIMER2_CH2 = TIMER_REGIDX_BIT(TIMERCISEL1, 8U, 0U), /*!< select TIMER2 CH2 as TIMER2 CI2 */
TIMER2_CI3_INPUT_TIMER2_CH3 = TIMER_REGIDX_BIT(TIMERCISEL1, 12U, 0U), /*!< select TIMER2 CH3 as TIMER2 CI3 */
TIMER1_CI0_INPUT_TIMER1_CH0 = TIMER_REGIDX_BIT(TIMERCISEL1, 16U, 0U), /*!< select TIMER1 CH0 as TIMER1 CI0 */
TIMER1_CI1_INPUT_TIMER1_CH1 = TIMER_REGIDX_BIT(TIMERCISEL1, 20U, 0U), /*!< select TIMER1 CH1 as TIMER1 CI1 */
TIMER1_CI2_INPUT_TIMER1_CH2 = TIMER_REGIDX_BIT(TIMERCISEL1, 24U, 0U), /*!< select TIMER1 CH2 as TIMER1 CI2 */
TIMER1_CI3_INPUT_TIMER1_CH3 = TIMER_REGIDX_BIT(TIMERCISEL1, 28U, 0U), /*!< select TIMER1 CH3 as TIMER1 CI3 */
TIMER1_CI3_INPUT_CMP0_OUT = TIMER_REGIDX_BIT(TIMERCISEL1, 28U, 1U), /*!< select CMP0 output as TIMER1 CI3 */
TIMER1_CI3_INPUT_CMP1_OUT = TIMER_REGIDX_BIT(TIMERCISEL1, 28U, 2U), /*!< select CMP1 output as TIMER1 CI3 */
TIMER1_CI3_INPUT_CMP0_OR_CMP1_OUT = TIMER_REGIDX_BIT(TIMERCISEL1, 28U, 3U), /*!< select CMP0 or CMP1 output as TIMER1 CI3 */
TIMER4_CI0_INPUT_TIMER4_CH0 = TIMER_REGIDX_BIT(TIMERCISEL2, 0U, 0U), /*!< select TIMER4 CH0 as TIMER4 CI0 */
TIMER4_CI1_INPUT_TIMER4_CH1 = TIMER_REGIDX_BIT(TIMERCISEL2, 4U, 0U), /*!< select TIMER4 CH1 as TIMER4 CI1 */
TIMER4_CI2_INPUT_TIMER4_CH2 = TIMER_REGIDX_BIT(TIMERCISEL2, 8U, 0U), /*!< select TIMER4 CH2 as TIMER4 CI2 */
TIMER4_CI3_INPUT_TIMER4_CH3 = TIMER_REGIDX_BIT(TIMERCISEL2, 12U, 0U), /*!< select TIMER4 CH3 as TIMER4 CI3 */
TIMER3_CI0_INPUT_TIMER3_CH0 = TIMER_REGIDX_BIT(TIMERCISEL2, 16U, 0U), /*!< select TIMER3 CH0 as TIMER3 CI0 */
TIMER3_CI1_INPUT_TIMER3_CH1 = TIMER_REGIDX_BIT(TIMERCISEL2, 20U, 0U), /*!< select TIMER3 CH1 as TIMER3 CI1 */
TIMER3_CI2_INPUT_TIMER3_CH2 = TIMER_REGIDX_BIT(TIMERCISEL2, 24U, 0U), /*!< select TIMER3 CH2 as TIMER3 CI2 */
TIMER3_CI3_INPUT_TIMER3_CH3 = TIMER_REGIDX_BIT(TIMERCISEL2, 28U, 0U), /*!< select TIMER3 CH3 as TIMER3 CI3 */
TIMER23_CI0_INPUT_TIMER23_CH0 = TIMER_REGIDX_BIT(TIMERCISEL3, 0U, 0U), /*!< select TIMER23 CH0 as TIMER23 CI0 */
TIMER23_CI1_INPUT_TIMER23_CH1 = TIMER_REGIDX_BIT(TIMERCISEL3, 4U, 0U), /*!< select TIMER23 CH1 as TIMER23 CI1 */
TIMER23_CI2_INPUT_TIMER23_CH2 = TIMER_REGIDX_BIT(TIMERCISEL3, 8U, 0U), /*!< select TIMER23 CH2 as TIMER23 CI2 */
TIMER23_CI3_INPUT_TIMER23_CH3 = TIMER_REGIDX_BIT(TIMERCISEL3, 12U, 0U), /*!< select TIMER23 CH3 as TIMER23 CI3 */
TIMER22_CI0_INPUT_TIMER22_CH0 = TIMER_REGIDX_BIT(TIMERCISEL3, 16U, 0U), /*!< select TIMER22 CH0 as TIMER22 CI0 */
TIMER22_CI1_INPUT_TIMER22_CH1 = TIMER_REGIDX_BIT(TIMERCISEL3, 20U, 0U), /*!< select TIMER22 CH1 as TIMER22 CI1 */
TIMER22_CI2_INPUT_TIMER22_CH2 = TIMER_REGIDX_BIT(TIMERCISEL3, 24U, 0U), /*!< select TIMER22 CH2 as TIMER22 CI2 */
TIMER22_CI3_INPUT_TIMER22_CH3 = TIMER_REGIDX_BIT(TIMERCISEL3, 28U, 0U), /*!< select TIMER22 CH3 as TIMER22 CI3 */
TIMER22_CI3_INPUT_CMP0_OUT = TIMER_REGIDX_BIT(TIMERCISEL3, 28U, 1U), /*!< select CMP0 output as TIMER22 CI3 */
TIMER22_CI3_INPUT_CMP1_OUT = TIMER_REGIDX_BIT(TIMERCISEL3, 28U, 2U), /*!< select CMP1 output as TIMER22 CI3 */
TIMER22_CI3_INPUT_CMP0_OR_CMP1_OUT = TIMER_REGIDX_BIT(TIMERCISEL3, 28U, 3U), /*!< select CMP0 or CMP1 output as TIMER22 CI3 */
TIMER14_CI0_INPUT_TIMER14_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 0U, 0U), /*!< select TIMER14 CH0 as TIMER14 CI0 */
TIMER14_CI0_INPUT_TIMER1_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 0U, 1U), /*!< select TIMER1 CH0 as TIMER14 CI0 */
TIMER14_CI0_INPUT_TIMER2_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 0U, 2U), /*!< select TIMER2 CH0 as TIMER14 CI0 */
TIMER14_CI0_INPUT_TIMER3_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 0U, 3U), /*!< select TIMER3 CH0 as TIMER14 CI0 */
TIMER14_CI0_INPUT_LXTAL = TIMER_REGIDX_BIT(TIMERCISEL5, 0U, 4U), /*!< select LXTAL as TIMER14 CI0 */
TIMER14_CI0_INPUT_LPIRC4M = TIMER_REGIDX_BIT(TIMERCISEL5, 0U, 5U), /*!< select LPIRC4M as TIMER14 CI0 */
TIMER14_CI0_INPUT_CKOUT1 = TIMER_REGIDX_BIT(TIMERCISEL5, 0U, 6U), /*!< select CKOUT1 as TIMER14 CI0 */
TIMER14_CI1_INPUT_TIMER14_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 4U, 0U), /*!< select TIMER14 CH1 as TIMER14 CI1 */
TIMER14_CI1_INPUT_TIMER1_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 4U, 1U), /*!< select TIMER1 CH1 as TIMER14 CI1 */
TIMER14_CI1_INPUT_TIMER2_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 4U, 2U), /*!< select TIMER2 CH1 as TIMER14 CI1 */
TIMER14_CI1_INPUT_TIMER3_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 4U, 3U), /*!< select TIMER3 CH1 as TIMER14 CI1 */
TIMER40_CI0_INPUT_TIMER40_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 8U, 0U), /*!< select TIMER40 CH0 as TIMER40 CI0 */
TIMER40_CI0_INPUT_TIMER2_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 8U, 1U), /*!< select TIMER2 CH0 as TIMER40 CI0 */
TIMER40_CI0_INPUT_TIMER3_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 8U, 2U), /*!< select TIMER3 CH0 as TIMER40 CI0 */
TIMER40_CI0_INPUT_TIMER4_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 8U, 3U), /*!< select TIMER4 CH0 as TIMER40 CI0 */
TIMER40_CI0_INPUT_LXTAL = TIMER_REGIDX_BIT(TIMERCISEL5, 8U, 4U), /*!< select LXTAL as TIMER40 CI0 */
TIMER40_CI0_INPUT_LPIRC4M = TIMER_REGIDX_BIT(TIMERCISEL5, 8U, 5U), /*!< select LPIRC4M as TIMER40 CI0 */
TIMER40_CI0_INPUT_CKOUT1 = TIMER_REGIDX_BIT(TIMERCISEL5, 8U, 6U), /*!< select CKOUT1 as TIMER40 CI0 */
TIMER40_CI1_INPUT_TIMER40_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 12U, 0U), /*!< select TIMER40 CH1 as TIMER40 CI0 */
TIMER40_CI1_INPUT_TIMER2_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 12U, 1U), /*!< select TIMER2 CH1 as TIMER40 CI0 */
TIMER40_CI1_INPUT_TIMER3_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 12U, 2U), /*!< select TIMER3 CH1 as TIMER40 CI0 */
TIMER40_CI1_INPUT_TIMER4_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 12U, 3U), /*!< select TIMER4 CH1 as TIMER40 CI0 */
TIMER41_CI0_INPUT_TIMER41_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 16U, 0U), /*!< select TIMER41 CH0 as TIMER41 CI0 */
TIMER41_CI0_INPUT_TIMER3_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 16U, 1U), /*!< select TIMER3 CH0 as TIMER41 CI0 */
TIMER41_CI0_INPUT_TIMER4_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 16U, 2U), /*!< select TIMER4 CH0 as TIMER41 CI0 */
TIMER41_CI0_INPUT_TIMER22_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 16U, 3U), /*!< select TIMER22 CH0 as TIMER41 CI0 */
TIMER41_CI0_INPUT_LXTAL = TIMER_REGIDX_BIT(TIMERCISEL5, 16U, 4U), /*!< select LXTAL as TIMER41 CI0 */
TIMER41_CI0_INPUT_LPIRC4M = TIMER_REGIDX_BIT(TIMERCISEL5, 16U, 5U), /*!< select LPIRC4M as TIMER41 CI0 */
TIMER41_CI0_INPUT_CKOUT1 = TIMER_REGIDX_BIT(TIMERCISEL5, 16U, 6U), /*!< select CKOUT1 as TIMER41 CI0 */
TIMER41_CI1_INPUT_TIMER41_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 20U, 0U), /*!< select TIMER41 CH1 as TIMER41 CI1 */
TIMER41_CI1_INPUT_TIMER3_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 20U, 1U), /*!< select TIMER3 CH1 as TIMER41 CI1 */
TIMER41_CI1_INPUT_TIMER4_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 20U, 2U), /*!< select TIMER4 CH1 as TIMER41 CI1 */
TIMER41_CI1_INPUT_TIMER22_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 20U, 3U), /*!< select TIMER22 CH1 as TIMER41 CI1 */
TIMER42_CI0_INPUT_TIMER42_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 24U, 0U), /*!< select TIMER42 CH0 as TIMER42 CI0 */
TIMER42_CI0_INPUT_TIMER4_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 24U, 1U), /*!< select TIMER4 CH0 as TIMER42 CI0 */
TIMER42_CI0_INPUT_TIMER22_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 24U, 2U), /*!< select TIMER22 CH0 as TIMER42 CI0 */
TIMER42_CI0_INPUT_TIMER23_CH0 = TIMER_REGIDX_BIT(TIMERCISEL5, 24U, 3U), /*!< select TIMER23 CH0 as TIMER42 CI0 */
TIMER42_CI0_INPUT_LXTAL = TIMER_REGIDX_BIT(TIMERCISEL5, 24U, 4U), /*!< select LXTAL as TIMER42 CI0 */
TIMER42_CI0_INPUT_LPIRC4M = TIMER_REGIDX_BIT(TIMERCISEL5, 24U, 5U), /*!< select LPIRC4M as TIMER42 CI0 */
TIMER42_CI0_INPUT_CKOUT1 = TIMER_REGIDX_BIT(TIMERCISEL5, 24U, 6U), /*!< select CKOUT1 as TIMER42 CI0 */
TIMER42_CI1_INPUT_TIMER42_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 28U, 0U), /*!< select TIMER42 CH1 as TIMER42 CI1 */
TIMER42_CI1_INPUT_TIMER4_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 28U, 1U), /*!< select TIMER4 CH1 as TIMER42 CI1 */
TIMER42_CI1_INPUT_TIMER22_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 28U, 2U), /*!< select TIMER22 CH1 as TIMER42 CI1 */
TIMER42_CI1_INPUT_TIMER23_CH1 = TIMER_REGIDX_BIT(TIMERCISEL5, 28U, 3U), /*!< select TIMER23 CH1 as TIMER42 CI1 */
TIMER15_CI0_INPUT_TIMER15_CH0 = TIMER_REGIDX_BIT(TIMERCISEL6, 0U, 0U), /*!< select TIMER15 CH0 as TIMER15 CI0 */
TIMER15_CI0_INPUT_IRC32K = TIMER_REGIDX_BIT(TIMERCISEL6, 0U, 1U), /*!< select IRC32K as TIMER15 CI0 */
TIMER15_CI0_INPUT_LXTAL = TIMER_REGIDX_BIT(TIMERCISEL6, 0U, 2U), /*!< select LXTAL as TIMER15 CI0 */
TIMER15_CI0_INPUT_WKUP_IT = TIMER_REGIDX_BIT(TIMERCISEL6, 0U, 3U), /*!< select WKUP IT as TIMER15 CI0 */
TIMER16_CI0_INPUT_TIMER16_CH0 = TIMER_REGIDX_BIT(TIMERCISEL6, 4U, 0U), /*!< select TIMER16 CH0 as TIMER16 CI0 */
TIMER16_CI0_INPUT_RSPDIF = TIMER_REGIDX_BIT(TIMERCISEL6, 4U, 1U), /*!< select RSPDIF symbol ck as TIMER16 CI0 */
TIMER16_CI0_INPUT_HXTAL_RTCDIV = TIMER_REGIDX_BIT(TIMERCISEL6, 4U, 2U), /*!< select HXTAL/RTCDIV 1M as TIMER16 CI0 */
TIMER16_CI0_INPUT_CKOUT0 = TIMER_REGIDX_BIT(TIMERCISEL6, 4U, 3U), /*!< select CKOUT0 as TIMER16 CI0 */
TIMER43_CI0_INPUT_TIMER43_CH0 = TIMER_REGIDX_BIT(TIMERCISEL6, 8U, 0U), /*!< select TIMER43 CH0 as TIMER43 CI0 */
TIMER43_CI0_INPUT_TIMER22_CH0 = TIMER_REGIDX_BIT(TIMERCISEL6, 8U, 1U), /*!< select TIMER22 CH0 as TIMER43 CI0 */
TIMER43_CI0_INPUT_TIMER23_CH0 = TIMER_REGIDX_BIT(TIMERCISEL6, 8U, 2U), /*!< select TIMER23 CH0 as TIMER43 CI0 */
TIMER43_CI0_INPUT_LXTAL = TIMER_REGIDX_BIT(TIMERCISEL6, 8U, 4U), /*!< select LXTAL as TIMER43 CI0 */
TIMER43_CI0_INPUT_LPIRC4M = TIMER_REGIDX_BIT(TIMERCISEL6, 8U, 5U), /*!< select LPIRC4M as TIMER43 CI0 */
TIMER43_CI0_INPUT_CKOUT1 = TIMER_REGIDX_BIT(TIMERCISEL6, 8U, 6U), /*!< select CKOUT1 as TIMER43 CI0 */
TIMER43_CI1_INPUT_TIMER43_CH1 = TIMER_REGIDX_BIT(TIMERCISEL6, 12U, 0U), /*!< select TIMER43 CH1 as TIMER43 CI1 */
TIMER43_CI1_INPUT_TIMER22_CH1 = TIMER_REGIDX_BIT(TIMERCISEL6, 12U, 1U), /*!< select TIMER22 CH1 as TIMER43 CI1 */
TIMER43_CI1_INPUT_TIMER23_CH1 = TIMER_REGIDX_BIT(TIMERCISEL6, 12U, 2U), /*!< select TIMER23 CH1 as TIMER43 CI1 */
TIMER44_CI0_INPUT_TIMER44_CH0 = TIMER_REGIDX_BIT(TIMERCISEL6, 16U, 0U), /*!< select TIMER44 CH0 as TIMER44 CI0 */
TIMER44_CI0_INPUT_TIMER23_CH0 = TIMER_REGIDX_BIT(TIMERCISEL6, 16U, 1U), /*!< select TIMER23 CH0 as TIMER44 CI0 */
TIMER44_CI0_INPUT_LXTAL = TIMER_REGIDX_BIT(TIMERCISEL6, 16U, 4U), /*!< select LXTAL as TIMER44 CI0 */
TIMER44_CI0_INPUT_LPIRC4M = TIMER_REGIDX_BIT(TIMERCISEL6, 16U, 5U), /*!< select LPIRC4M as TIMER44 CI0 */
TIMER44_CI0_INPUT_CKOUT1 = TIMER_REGIDX_BIT(TIMERCISEL6, 16U, 6U), /*!< select CKOUT1 as TIMER44 CI0 */
TIMER44_CI1_INPUT_TIMER44_CH1 = TIMER_REGIDX_BIT(TIMERCISEL6, 20U, 0U), /*!< select TIMER44 CH1 as TIMER44 CI1 */
TIMER44_CI1_INPUT_TIMER23_CH1 = TIMER_REGIDX_BIT(TIMERCISEL6, 20U, 1U), /*!< select TIMER23 CH1 as TIMER44 CI1 */
} timer_channel_input_enum;
/* timer tigger source select definition */
#define TIMER_SMCFG_TRGSEL_NONE ((uint8_t)0x00U) /*!< trigger input is none */
#define TIMER_SMCFG_TRGSEL_ITI0 ((uint8_t)0x01U) /*!< internal trigger 0 */
#define TIMER_SMCFG_TRGSEL_ITI1 ((uint8_t)0x02U) /*!< internal trigger 1 */
#define TIMER_SMCFG_TRGSEL_ITI2 ((uint8_t)0x03U) /*!< internal trigger 2 */
#define TIMER_SMCFG_TRGSEL_ITI3 ((uint8_t)0x04U) /*!< internal trigger 3 */
#define TIMER_SMCFG_TRGSEL_CI0F_ED ((uint8_t)0x05U) /*!< TI0 edge detector */
#define TIMER_SMCFG_TRGSEL_CI0FE0 ((uint8_t)0x06U) /*!< filtered TIMER input 0 */
#define TIMER_SMCFG_TRGSEL_CI1FE1 ((uint8_t)0x07U) /*!< filtered TIMER input 1 */
#define TIMER_SMCFG_TRGSEL_ETIFP ((uint8_t)0x08U) /*!< external trigger */
#define TIMER_SMCFG_TRGSEL_CI2FE2 ((uint8_t)0x09U) /*!< filtered TIMER input 2 */
#define TIMER_SMCFG_TRGSEL_CI3FE3 ((uint8_t)0x0AU) /*!< filtered TIMER input 3 */
#define TIMER_SMCFG_TRGSEL_MCI0FEM0 ((uint8_t)0x0BU) /*!< filtered output of multi mode channel 0 */
#define TIMER_SMCFG_TRGSEL_MCI1FEM1 ((uint8_t)0x0CU) /*!< filtered output of multi mode channel 1 */
#define TIMER_SMCFG_TRGSEL_MCI2FEM2 ((uint8_t)0x0DU) /*!< filtered output of multi mode channel 2 */
#define TIMER_SMCFG_TRGSEL_MCI3FEM3 ((uint8_t)0x0EU) /*!< filtered output of multi mode channel 3 */
#define TIMER_SMCFG_TRGSEL_ITI12 ((uint8_t)0x11U) /*!< internal trigger input 12 */
#define TIMER_SMCFG_TRGSEL_ITI13 ((uint8_t)0x12U) /*!< internal trigger input 13 */
#define TIMER_SMCFG_TRGSEL_ITI14 ((uint8_t)0x13U) /*!< internal trigger input 14 */
#define TIMER_L0_SMCFG_TRGSEL_ITI4 ((uint8_t)0x09U) /*!< internal trigger 4 for General-L0 timer */
#define TIMER_L0_SMCFG_TRGSEL_ITI5 ((uint8_t)0x0AU) /*!< internal trigger 5 for General-L0 timer */
#define TIMER_L0_SMCFG_TRGSEL_ITI7 ((uint8_t)0x0CU) /*!< internal trigger 7 for General-L0 timer */
#define TIMER_L0_SMCFG_TRGSEL_ITI9 ((uint8_t)0x0EU) /*!< internal trigger 9 for General-L0 timer */
#define TIMER_L0_SMCFG_TRGSEL_ITI10 ((uint8_t)0x0FU) /*!< internal trigger 10 for General-L0 timer */
#define TIMER_L0_SMCFG_TRGSEL_ITI11 ((uint8_t)0x10U) /*!< internal trigger 11 for General-L0 timer */
/* timer tigger mode select definition */
#define TIMER_QUAD_DECODER_MODE0 ((uint8_t)0x00U) /*!< quadrature decoder mode 0 */
#define TIMER_QUAD_DECODER_MODE1 ((uint8_t)0x01U) /*!< quadrature decoder mode 1 */
#define TIMER_QUAD_DECODER_MODE2 ((uint8_t)0x02U) /*!< quadrature decoder mode 2 */
#define TIMER_SLAVE_MODE_RESTART ((uint8_t)0x03U) /*!< restart mode */
#define TIMER_SLAVE_MODE_PAUSE ((uint8_t)0x04U) /*!< pause mode */
#define TIMER_SLAVE_MODE_EVENT ((uint8_t)0x05U) /*!< event mode */
#define TIMER_SLAVE_MODE_EXTERNAL0 ((uint8_t)0x06U) /*!< external clock mode 0 */
#define TIMER_SLAVE_MODE_RESTART_EVENT ((uint8_t)0x07U) /*!< restart + event mode */
#define TIMER_NONQUAD_DECODER_MODE0 ((uint8_t)0x08U) /*!< non-quadrature decoder mode 0 */
#define TIMER_NONQUAD_DECODER_MODE1 ((uint8_t)0x09U) /*!< non-quadrature decoder mode 1 */
#define TIMER_SLAVE_MODE_DISABLE ((uint8_t)0x0FU) /*!< slave mode disable */
#define SYSCFG_TIMERCFG0(syscfg_timerx) REG32(SYSCFG + 0x100U + (syscfg_timerx) * 0x0CU)/*!< TIMERx configuration register */
#define SYSCFG_TIMERCFG1(syscfg_timerx) REG32(SYSCFG + 0x104U + (syscfg_timerx) * 0x0CU)/*!< TIMERx configuration register */
#define SYSCFG_TIMERCFG2(syscfg_timerx) REG32(SYSCFG + 0x108U + (syscfg_timerx) * 0x0CU)/*!< TIMERx configuration register */
#define SYSCFG_TIMER0 ((uint8_t)0x00U) /*!< SYSCFG TIMER0 */
#define SYSCFG_TIMER1 ((uint8_t)0x01U) /*!< SYSCFG TIMER1 */
#define SYSCFG_TIMER2 ((uint8_t)0x02U) /*!< SYSCFG TIMER2 */
#define SYSCFG_TIMER3 ((uint8_t)0x03U) /*!< SYSCFG TIMER3 */
#define SYSCFG_TIMER4 ((uint8_t)0x04U) /*!< SYSCFG TIMER4 */
#define SYSCFG_TIMER7 ((uint8_t)0x05U) /*!< SYSCFG TIMER7 */
#define SYSCFG_TIMER14 ((uint8_t)0x06U) /*!< SYSCFG TIMER14 */
#define SYSCFG_TIMER22 ((uint8_t)0x07U) /*!< SYSCFG TIMER22 */
#define SYSCFG_TIMER23 ((uint8_t)0x08U) /*!< SYSCFG TIMER23 */
#define SYSCFG_TIMER40 ((uint8_t)0x0BU) /*!< SYSCFG TIMER40 */
#define SYSCFG_TIMER41 ((uint8_t)0x0CU) /*!< SYSCFG TIMER41 */
#define SYSCFG_TIMER42 ((uint8_t)0x0DU) /*!< SYSCFG TIMER42 */
#define SYSCFG_TIMER43 ((uint8_t)0x0EU) /*!< SYSCFG TIMER43 */
#define SYSCFG_TIMER44 ((uint8_t)0x0FU) /*!< SYSCFG TIMER44 */
/* TIMER input select mask bits definition */
#define TIMER_IS_MASK BITS(0,3) /*!< TIMER source select mask */
/* CACHE mode definitions */
#define ICACHE_STATUS ((uint32_t)0x00000000U) /*!< select ICACHE */
#define DCACHE_STATUS ((uint32_t)0x00000001U) /*!< select DCACHE */
/* CACHE status definitions */
#define CPU_CACHE_ERROR_DETECTION ((uint32_t)0x00000000U) /*!< select detection information */
#define CPU_CACHE_ERROR_BANK ((uint32_t)0x00000001U) /*!< select error information */
/* Secure SRAM size definition */
#define SECURE_SRAM_SIZE_0KB ((uint32_t)0x00000000U) /*!< secure SRAM size is 0KB */
#define SECURE_SRAM_SIZE_32KB ((uint32_t)0x00000001U) /*!< secure SRAM size is 32KB */
#define SECURE_SRAM_SIZE_64KB ((uint32_t)0x00000002U) /*!< secure SRAM size is 64KB */
#define SECURE_SRAM_SIZE_128KB ((uint32_t)0x00000003U) /*!< secure SRAM size is 128KB */
/* I/O compensation cell enable/disable */
#define SYSCFG_IO_COMPENSATION_ENABLE ((uint32_t)0x00000001U) /*!< I/O compensation cell enable */
#define SYSCFG_IO_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell disable */
/* module lockup */
#define SYSCFG_LVD_LOCKUP SYSCFG_LKCTL_LVD_LOCK /*!< LVD signal connected */
#define SYSCFG_CPU_LOCKUP SYSCFG_LKCTL_CPU_LOCK /*!< CPU lockup signal connected */
#define SYSCFG_BKPRAM_LOCKUP SYSCFG_LKCTL_BKPRAM_LOCK /*!< Region 2 backup SRAM ECC double error signal connected */
#define SYSCFG_SRAM1_LOCKUP SYSCFG_LKCTL_SRAM1_LOCK /*!< Region 1 SRAM1 ECC double error signal connected */
#define SYSCFG_SRAM0_LOCKUP SYSCFG_LKCTL_SRAM0_LOCK /*!< Region 1 SRAM0 ECC double error signal connected */
#define SYSCFG_DTCM_LOCKUP SYSCFG_LKCTL_DTCM_LOCK /*!< Region 0 DTCM ECC double error signal connected */
#define SYSCFG_ITCM_LOCKUP SYSCFG_LKCTL_ITCM_LOCK /*!< Region 0 ITCM-RAM ECC double error signal connected */
#define SYSCFG_AXIRAM_LOCKUP SYSCFG_LKCTL_AXIRAM_LOCK /*!< Region 0 AXI-SRAM ECC double error signal connected */
/* SYSCFG compensation flag definitions */
#define SYSCFG_FLAG_IO_LOW_VOLTAGE SYSCFG_CPSCTL_IOLV /*!< I/O in low voltage state flag, product supply voltage is working below 2.5V */
#define SYSCFG_FLAG_COMPENSATION_READY SYSCFG_CPSCTL_CPS_RDY /*!< I/O compensation cell ready flag */
/* SYSCFG FPU interrupt definitions */
#define SYSCFG_FPUINT_INEXACT SYSCFG_FPUINTEN_IXIE /*!< inexact interrupt */
#define SYSCFG_FPUINT_INPUT_ABNORMAL SYSCFG_FPUINTEN_IDIE /*!< input abnormal interrupt */
#define SYSCFG_FPUINT_OVERFLOW SYSCFG_FPUINTEN_OVFIE /*!< overflow interrupt */
#define SYSCFG_FPUINT_UNDERFLOW SYSCFG_FPUINTEN_UFIE /*!< underflow interrupt */
#define SYSCFG_FPUINT_DIV0 SYSCFG_FPUINTEN_DZIE /*!< divide-by-zero interrupt */
#define SYSCFG_FPUINT_INVALID_OPERATION SYSCFG_FPUINTEN_IOPIE /*!< invalid operation interrupt */
/* BOOT modes definitions */
#define BOOT_SRAM ((uint32_t)0x00000000U) /*!< BOOT from SRAM (ITCM/DTCM/RAM shared/AXI SRAM) */
#define BOOT_SECURITY ((uint32_t)0x00000001U) /*!< BOOT from Security */
#define BOOT_SYSTEM ((uint32_t)0x00000002U) /*!< BOOT_SYS (BootLoader) */
#define BOOT_USER_FLASH ((uint32_t)0x00000003U) /*!< BOOT_USER (User flash OSPI0/1) */
/* BOR threshold level definitions */
#define BOR_OFF ((uint32_t)0x00000000U) /*!< no BOR function */
#define BOR_THRESHOLD_VAL1 ((uint32_t)0x00000001U) /*!< BOR threshold value 1 */
#define BOR_THRESHOLD_VAL2 ((uint32_t)0x00000002U) /*!< BOR threshold value 2 */
#define BOR_THRESHOLD_VAL3 ((uint32_t)0x00000003U) /*!< BOR threshold value 3 */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
#define NOT_SYSCFG_I2C_FMP(xxx) (((xxx) != SYSCFG_I2C0_FMP) && ((xxx) != SYSCFG_I2C1_FMP) && \
((xxx) != SYSCFG_I2C2_FMP) && ((xxx) != SYSCFG_I2C3_FMP) && \
((xxx) != SYSCFG_I2C_FMP_PB6) && ((xxx) != SYSCFG_I2C_FMP_PB7) && \
((xxx) != SYSCFG_I2C_FMP_PB8) && ((xxx) != SYSCFG_I2C_FMP_PB9))
#define NOT_SYSCFG_ANALOG_SWITCH(xxx) (((xxx) != SYSCFG_PA0_ANALOG_SWITCH) && ((xxx) != SYSCFG_PA1_ANALOG_SWITCH) && \
((xxx) != SYSCFG_PC2_ANALOG_SWITCH) && ((xxx) != SYSCFG_PC3_ANALOG_SWITCH))
#define NOT_EXTI_SOURCE_GPIO(xxx) (((xxx) != EXTI_SOURCE_GPIOA) && ((xxx) != EXTI_SOURCE_GPIOB) && \
((xxx) != EXTI_SOURCE_GPIOC) && ((xxx) != EXTI_SOURCE_GPIOD) && \
((xxx) != EXTI_SOURCE_GPIOE) && ((xxx) != EXTI_SOURCE_GPIOF) && \
((xxx) != EXTI_SOURCE_GPIOG) && ((xxx) != EXTI_SOURCE_GPIOH) && \
((xxx) != EXTI_SOURCE_GPIOJ) && ((xxx) != EXTI_SOURCE_GPIOK))
#define NOT_EXTI_SOURCE_PIN(xxx) (((xxx) != EXTI_SOURCE_PIN0) && ((xxx) != EXTI_SOURCE_PIN1) && \
((xxx) != EXTI_SOURCE_PIN2) && ((xxx) != EXTI_SOURCE_PIN3) && \
((xxx) != EXTI_SOURCE_PIN4) && ((xxx) != EXTI_SOURCE_PIN5) && \
((xxx) != EXTI_SOURCE_PIN6) && ((xxx) != EXTI_SOURCE_PIN7) && \
((xxx) != EXTI_SOURCE_PIN8) && ((xxx) != EXTI_SOURCE_PIN9) && \
((xxx) != EXTI_SOURCE_PIN10) && ((xxx) != EXTI_SOURCE_PIN11) && \
((xxx) != EXTI_SOURCE_PIN12) && ((xxx) != EXTI_SOURCE_PIN13) && \
((xxx) != EXTI_SOURCE_PIN14) && ((xxx) != EXTI_SOURCE_PIN15))
#define NOT_SYSCFG_LOCKUP(xxx) (((xxx) != SYSCFG_LVD_LOCKUP) && ((xxx) != SYSCFG_CPU_LOCKUP) && \
((xxx) != SYSCFG_BKPRAM_LOCKUP) && ((xxx) != SYSCFG_SRAM1_LOCKUP) && \
((xxx) != SYSCFG_SRAM0_LOCKUP) && ((xxx) != SYSCFG_DTCM_LOCKUP) && \
((xxx) != SYSCFG_ITCM_LOCKUP) && ((xxx) != SYSCFG_AXIRAM_LOCKUP))
#define NOT_SYSCFG_TIMERCI_INPUT(xxx) (((xxx) != TIMER7_CI0_INPUT_TIMER7_CH0) && ((xxx) != TIMER7_CI0_INPUT_CMP1_OUT) && \
((xxx) != TIMER7_CI1_INPUT_TIMER7_CH1) && ((xxx) != TIMER7_CI2_INPUT_TIMER7_CH2) && \
((xxx) != TIMER7_CI3_INPUT_TIMER7_CH3) && ((xxx) != TIMER0_CI0_INPUT_TIMER0_CH0) && \
((xxx) != TIMER0_CI0_INPUT_CMP0_OUT) && ((xxx) != TIMER0_CI1_INPUT_TIMER0_CH1) && \
((xxx) != TIMER0_CI2_INPUT_TIMER0_CH2) && ((xxx) != TIMER0_CI3_INPUT_TIMER0_CH3) && \
((xxx) != TIMER2_CI0_INPUT_TIMER2_CH0) && ((xxx) != TIMER2_CI0_INPUT_CMP0_OUT) && \
((xxx) != TIMER2_CI0_INPUT_CMP1_OUT) && ((xxx) != TIMER2_CI0_INPUT_CMP0_OR_CMP1_OUT) && \
((xxx) != TIMER2_CI1_INPUT_TIMER2_CH1) && ((xxx) != TIMER2_CI2_INPUT_TIMER2_CH2) && \
((xxx) != TIMER2_CI3_INPUT_TIMER2_CH3) && ((xxx) != TIMER1_CI0_INPUT_TIMER1_CH0) && \
((xxx) != TIMER1_CI1_INPUT_TIMER1_CH1) && ((xxx) != TIMER1_CI2_INPUT_TIMER1_CH2) && \
((xxx) != TIMER1_CI3_INPUT_TIMER1_CH3) && ((xxx) != TIMER1_CI3_INPUT_CMP0_OUT) && \
((xxx) != TIMER1_CI3_INPUT_CMP1_OUT) && ((xxx) != TIMER1_CI3_INPUT_CMP0_OR_CMP1_OUT) && \
((xxx) != TIMER4_CI0_INPUT_TIMER4_CH0) && ((xxx) != TIMER4_CI1_INPUT_TIMER4_CH1) && \
((xxx) != TIMER4_CI2_INPUT_TIMER4_CH2) && ((xxx) != TIMER4_CI3_INPUT_TIMER4_CH3) && \
((xxx) != TIMER3_CI0_INPUT_TIMER3_CH0) && ((xxx) != TIMER3_CI1_INPUT_TIMER3_CH1) && \
((xxx) != TIMER3_CI2_INPUT_TIMER3_CH2) && ((xxx) != TIMER3_CI3_INPUT_TIMER3_CH3) && \
((xxx) != TIMER23_CI0_INPUT_TIMER23_CH0) && ((xxx) != TIMER23_CI1_INPUT_TIMER23_CH1) && \
((xxx) != TIMER23_CI2_INPUT_TIMER23_CH2) && ((xxx) != TIMER23_CI3_INPUT_TIMER23_CH3) && \
((xxx) != TIMER22_CI0_INPUT_TIMER22_CH0) && ((xxx) != TIMER22_CI1_INPUT_TIMER22_CH1) && \
((xxx) != TIMER22_CI2_INPUT_TIMER22_CH2) && ((xxx) != TIMER22_CI3_INPUT_TIMER22_CH3) && \
((xxx) != TIMER22_CI3_INPUT_CMP0_OUT) && ((xxx) != TIMER22_CI3_INPUT_CMP1_OUT) && \
((xxx) != TIMER22_CI3_INPUT_CMP0_OR_CMP1_OUT) && ((xxx) != TIMER14_CI0_INPUT_TIMER14_CH0) && \
((xxx) != TIMER14_CI0_INPUT_TIMER1_CH0) && ((xxx) != TIMER14_CI0_INPUT_TIMER2_CH0) && \
((xxx) != TIMER14_CI0_INPUT_TIMER3_CH0) && ((xxx) != TIMER14_CI0_INPUT_LXTAL) && \
((xxx) != TIMER14_CI0_INPUT_LPIRC4M) && ((xxx) != TIMER14_CI0_INPUT_CKOUT1) && \
((xxx) != TIMER14_CI1_INPUT_TIMER14_CH1) && ((xxx) != TIMER14_CI1_INPUT_TIMER1_CH1) && \
((xxx) != TIMER14_CI1_INPUT_TIMER2_CH1) && ((xxx) != TIMER14_CI1_INPUT_TIMER3_CH1) && \
((xxx) != TIMER40_CI0_INPUT_TIMER40_CH0) && ((xxx) != TIMER40_CI0_INPUT_TIMER2_CH0) && \
((xxx) != TIMER40_CI0_INPUT_TIMER3_CH0) && ((xxx) != TIMER40_CI0_INPUT_TIMER4_CH0) && \
((xxx) != TIMER40_CI0_INPUT_LXTAL) && ((xxx) != TIMER40_CI0_INPUT_LPIRC4M) && \
((xxx) != TIMER40_CI0_INPUT_CKOUT1) && ((xxx) != TIMER40_CI1_INPUT_TIMER40_CH1) && \
((xxx) != TIMER40_CI1_INPUT_TIMER2_CH1) && ((xxx) != TIMER40_CI1_INPUT_TIMER3_CH1) && \
((xxx) != TIMER40_CI1_INPUT_TIMER4_CH1) && ((xxx) != TIMER41_CI0_INPUT_TIMER41_CH0) && \
((xxx) != TIMER41_CI0_INPUT_TIMER3_CH0) && ((xxx) != TIMER41_CI0_INPUT_TIMER4_CH0) && \
((xxx) != TIMER41_CI0_INPUT_TIMER22_CH0) && ((xxx) != TIMER41_CI0_INPUT_LXTAL) && \
((xxx) != TIMER41_CI0_INPUT_LPIRC4M) && ((xxx) != TIMER41_CI0_INPUT_CKOUT1) && \
((xxx) != TIMER41_CI1_INPUT_TIMER41_CH1) && ((xxx) != TIMER41_CI1_INPUT_TIMER3_CH1) && \
((xxx) != TIMER41_CI1_INPUT_TIMER4_CH1) && ((xxx) != TIMER41_CI1_INPUT_TIMER22_CH1) && \
((xxx) != TIMER42_CI0_INPUT_TIMER42_CH0) && ((xxx) != TIMER42_CI0_INPUT_TIMER4_CH0) && \
((xxx) != TIMER42_CI0_INPUT_TIMER22_CH0) && ((xxx) != TIMER42_CI0_INPUT_TIMER23_CH0) && \
((xxx) != TIMER42_CI0_INPUT_LXTAL) && ((xxx) != TIMER42_CI0_INPUT_LPIRC4M) && \
((xxx) != TIMER42_CI0_INPUT_CKOUT1) && ((xxx) != TIMER42_CI1_INPUT_TIMER42_CH1) && \
((xxx) != TIMER42_CI1_INPUT_TIMER4_CH1) && ((xxx) != TIMER42_CI1_INPUT_TIMER22_CH1) && \
((xxx) != TIMER42_CI1_INPUT_TIMER23_CH1) && ((xxx) != TIMER15_CI0_INPUT_TIMER15_CH0) && \
((xxx) != TIMER15_CI0_INPUT_IRC32K) && ((xxx) != TIMER15_CI0_INPUT_LXTAL) && \
((xxx) != TIMER15_CI0_INPUT_WKUP_IT) && ((xxx) != TIMER16_CI0_INPUT_TIMER16_CH0) && \
((xxx) != TIMER16_CI0_INPUT_RSPDIF) && ((xxx) != TIMER16_CI0_INPUT_HXTAL_RTCDIV) && \
((xxx) != TIMER16_CI0_INPUT_CKOUT0) && ((xxx) != TIMER43_CI0_INPUT_TIMER43_CH0) && \
((xxx) != TIMER43_CI0_INPUT_TIMER22_CH0) && ((xxx) != TIMER43_CI0_INPUT_TIMER23_CH0) && \
((xxx) != TIMER43_CI0_INPUT_LXTAL) && \
((xxx) != TIMER43_CI0_INPUT_LPIRC4M) && ((xxx) != TIMER43_CI0_INPUT_CKOUT1) && \
((xxx) != TIMER43_CI1_INPUT_TIMER43_CH1) && ((xxx) != TIMER43_CI1_INPUT_TIMER22_CH1) && \
((xxx) != TIMER43_CI1_INPUT_TIMER23_CH1) && \
((xxx) != TIMER44_CI0_INPUT_TIMER44_CH0) && ((xxx) != TIMER44_CI0_INPUT_TIMER23_CH0) && \
((xxx) != TIMER44_CI0_INPUT_LXTAL) && ((xxx) != TIMER44_CI0_INPUT_LPIRC4M) && \
((xxx) != TIMER44_CI0_INPUT_CKOUT1) && ((xxx) != TIMER44_CI1_INPUT_TIMER44_CH1) && \
((xxx) != TIMER44_CI1_INPUT_TIMER23_CH1))
#define NOT_SYSCFG_IO_COMPENSATION(xxx) (((xxx) != SYSCFG_IO_COMPENSATION_ENABLE) && ((xxx) != SYSCFG_IO_COMPENSATION_DISABLE))
#define NOT_SYSCFG_MOS_COMPENSATION(xxx) (((xxx) != NMOS_COMPENSATION) && ((xxx) != PMOS_COMPENSATION))
#define NOT_SYSCFG_SECURE_SRAM_SIZE(xxx) (((xxx) != SECURE_SRAM_SIZE_0KB) && ((xxx) != SECURE_SRAM_SIZE_32KB) && \
((xxx) != SECURE_SRAM_SIZE_64KB) && ((xxx) != SECURE_SRAM_SIZE_128KB))
#define NOT_SYSCFG_FPUINT(xxx) (((xxx) != SYSCFG_FPUINT_INEXACT) && ((xxx) != SYSCFG_FPUINT_INPUT_ABNORMAL) && \
((xxx) != SYSCFG_FPUINT_OVERFLOW) && ((xxx) != SYSCFG_FPUINT_UNDERFLOW) && \
((xxx) != SYSCFG_FPUINT_DIV0) && ((xxx) != SYSCFG_FPUINT_INVALID_OPERATION))
#define NOT_SYSCFG_FLAG(xxx) (((xxx) != SYSCFG_FLAG_IO_LOW_VOLTAGE) && ((xxx) != SYSCFG_FLAG_COMPENSATION_READY))
#define NOT_SYSCFG_CACHE_STATUS(xxx) (((xxx) != ICACHE_STATUS) && ((xxx) != DCACHE_STATUS))
#define NOT_CPU_CACHE_ERROR(xxx) (((xxx) != CPU_CACHE_ERROR_DETECTION) && ((xxx) != CPU_CACHE_ERROR_BANK))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* initialization functions */
/* reset the SYSCFG registers */
void syscfg_deinit(void);
/* peripheral SYSCFG configuration functions */
/* enable I2Cx(x=0,1,2,3) fast mode plus or I2C fast mode plus PBx(x=6,7,8,9) */
void syscfg_i2c_fast_mode_plus_enable(uint32_t i2c_fmp);
/* disable I2Cx(x=0,1,2,3) fast mode plus or I2C fast mode plus PBx(x=6,7,8,9) */
void syscfg_i2c_fast_mode_plus_disable(uint32_t i2c_fmp);
/* open analog switch (Pxy_C and Pxy are separated pads) */
void syscfg_analog_switch_enable(uint32_t gpio_answ);
/* close analog switch (Pxy_C and Pxy are connected through the analog switch) */
void syscfg_analog_switch_disable(uint32_t gpio_answ);
/* configure the GPIO pin as EXTI line */
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin);
/* enable module lockup function (function can be disabled by system reset) */
void syscfg_lockup_enable(uint32_t lockup);
/* select timer channel input source */
void syscfg_timer_input_source_select(timer_channel_input_enum timer_input);
/* I/O compensation cell functions */
/* configure the I/O compensation cell */
void syscfg_io_compensation_config(uint32_t syscfg_cps);
/* enable I/O speed optimization, high-speed at low-voltage */
void syscfg_io_low_voltage_speed_optimization_enable(void);
/* disable I/O speed optimization, high-speed at low-voltage */
void syscfg_io_low_voltage_speed_optimization_disable(void);
/* set P/N MOS compensation value */
void syscfg_pnmos_compensation_code_set(uint32_t mos, uint32_t code);
/* secure and boot functions */
/* set secure SRAM size */
void syscfg_secure_sram_size_set(uint32_t size);
/* get secure SRAM size */
uint32_t syscfg_secure_sram_size_get(void);
/* get BOOT mode */
uint32_t syscfg_bootmode_get(void);
/* enable TCM wait state */
void syscfg_tcm_wait_state_enable(void);
/* disable TCM wait state */
void syscfg_tcm_wait_state_disable(void);
/* flag and interrupt functions */
/* FPU interrupt enable */
void syscfg_fpu_interrupt_enable(uint32_t fpu_int);
/* FPU interrupt disable */
void syscfg_fpu_interrupt_disable(uint32_t fpu_int);
/* get compensation cell flags */
FlagStatus syscfg_compensation_flag_get(uint32_t cps_flag);
/* get ICACHE or DCACHE status */
uint32_t syscfg_cpu_cache_status_get(uint32_t cache, uint32_t status);
/* get brownout reset threshold level */
uint32_t syscfg_brownout_reset_threshold_level_get(void);
#endif /* GD32H75E_SYSCFG_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_timer.h
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828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_tmu.h
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/*!
\file gd32h75e_tmu.h
\brief definitions for the TMU
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_TMU_H
#define GD32H75E_TMU_H
#include "gd32h75e.h"
/* TMU definitions */
#define TMU TMU_BASE
/* registers definitions */
#define TMU_CS REG32(TMU + 0x00000000U) /*!< TMU control and status register */
#define TMU_IDATA REG32(TMU + 0x00000004U) /*!< TMU input data register */
#define TMU_ODATA REG32(TMU + 0x00000008U) /*!< TMU output data register */
/* bits definitions */
/* TMU_CS */
#define TMU_CS_MODE BITS(0,3) /*!< TMU operation mode selection */
#define TMU_CS_ITRTNUM BITS(4,7) /*!< number of iterations selection */
#define TMU_CS_FACTOR BITS(8,10) /*!< scaling factor */
#define TMU_CS_RIE BIT(16) /*!< read TMU_ODATA interrupt enable */
#define TMU_CS_RDEN BIT(17) /*!< read TMU_ODATA DMA request enable */
#define TMU_CS_WDEN BIT(18) /*!< write TMU_IDATA DMA request enable */
#define TMU_CS_ONUM BIT(19) /*!< times the TMU_ODATA needs to be read */
#define TMU_CS_INUM BIT(20) /*!< times the TMU_IDATA needs to be write */
#define TMU_CS_OWIDTH BIT(21) /*!< width of output data */
#define TMU_CS_IWIDTH BIT(22) /*!< width of input data */
#define TMU_CS_ENDF BIT(31) /*!< end of TMU operation flag */
/* TMU_IDATA */
#define TMU_IDATA_IDATA BITS(0,31) /*!< the input data of TMU operation */
/* TMU_ODATA */
#define TMU_ODATA_ODATA BITS(0,31) /*!< the output data of TMU operation */
/* constants definitions */
/* TMU init parameter struct definitions */
typedef struct
{
uint32_t mode; /*!< mode of TMU operation */
uint32_t iterations_number; /*!< number of iterations selection */
uint32_t scale; /*!< scaling factor */
uint32_t dma_read; /*!< DMA request to read TMU_ODATA */
uint32_t dma_write; /*!< DMA request to write TMU_IDATA */
uint32_t read_times; /*!< times the TMU_ODATA needs to be read */
uint32_t write_times; /*!< times the TMU_IDATA needs to be write */
uint32_t output_width; /*!< width of output data */
uint32_t input_width; /*!< width of input data */
}tmu_parameter_struct;
/* TMU mode definitions */
#define TMU_MODE(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define TMU_MODE_COS TMU_MODE(0) /*!< mode0: m*cos(��) */
#define TMU_MODE_SIN TMU_MODE(1) /*!< mode1: m*sin(��) */
#define TMU_MODE_ATAN2 TMU_MODE(2) /*!< mode2: atan2(y,x) */
#define TMU_MODE_MODULUS TMU_MODE(3) /*!< mode3: sqrt(x^2+y^2) */
#define TMU_MODE_ATAN TMU_MODE(4) /*!< mode4: atan(x) */
#define TMU_MODE_COSH TMU_MODE(5) /*!< mode5: cosh(x) */
#define TMU_MODE_SINH TMU_MODE(6) /*!< mode6: sinh(x) */
#define TMU_MODE_ATANH TMU_MODE(7) /*!< mode7: atanh(x) */
#define TMU_MODE_LN TMU_MODE(8) /*!< mode8: ln(x) */
#define TMU_MODE_SQRT TMU_MODE(9) /*!< mode9: sqrt(x) */
/* TMU number of iterations definitions */
#define ITERATIONS(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
#define TMU_ITERATION_STEPS_4 ITERATIONS(1) /*!< 4 iteration steps */
#define TMU_ITERATION_STEPS_8 ITERATIONS(2) /*!< 8 iteration steps */
#define TMU_ITERATION_STEPS_12 ITERATIONS(3) /*!< 12 iteration steps */
#define TMU_ITERATION_STEPS_16 ITERATIONS(4) /*!< 16 iteration steps */
#define TMU_ITERATION_STEPS_20 ITERATIONS(5) /*!< 20 iteration steps */
#define TMU_ITERATION_STEPS_24 ITERATIONS(6) /*!< 24 iteration steps */
/* TMU scaling factor definitions */
#define SCALE(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
#define TMU_SCALING_FACTOR_1 SCALE(0) /*!< scaling factor = 1 */
#define TMU_SCALING_FACTOR_2 SCALE(1) /*!< scaling factor = 2 */
#define TMU_SCALING_FACTOR_4 SCALE(2) /*!< scaling factor = 4 */
#define TMU_SCALING_FACTOR_8 SCALE(3) /*!< scaling factor = 8 */
#define TMU_SCALING_FACTOR_16 SCALE(4) /*!< scaling factor = 16 */
#define TMU_SCALING_FACTOR_32 SCALE(5) /*!< scaling factor = 32 */
#define TMU_SCALING_FACTOR_64 SCALE(6) /*!< scaling factor = 64 */
#define TMU_SCALING_FACTOR_128 SCALE(7) /*!< scaling factor = 128 */
/* TMU DMA read enable definitions */
#define TMU_READ_DMA_DISABLE ((uint32_t)0x00000000U) /*!< disable DMA request to read TMU_ODATA */
#define TMU_READ_DMA_ENABLE TMU_CS_RDEN /*!< enable DMA request to read TMU_ODATA */
/* TMU DMA write enable definitions */
#define TMU_WRITE_DMA_DISABLE ((uint32_t)0x00000000U) /*!< disable DMA request to write TMU_IDATA */
#define TMU_WRITE_DMA_ENABLE TMU_CS_WDEN /*!< enable DMA request to write TMU_IDATA */
/* TMU_ODATA read times definitions */
#define TMU_READ_TIMES_1 ((uint32_t)0x00000000U) /*!< one 32-bit read operation */
#define TMU_READ_TIMES_2 TMU_CS_ONUM /*!< two 32-bit read operation */
/* TMU_IDATA write times definitions */
#define TMU_WRITE_TIMES_1 ((uint32_t)0x00000000U) /*!< one 32-bit write operation */
#define TMU_WRITE_TIMES_2 TMU_CS_INUM /*!< two 32-bit write operation */
/* TMU output data width definitions */
#define TMU_OUTPUT_WIDTH_32 ((uint32_t)0x00000000U) /*!< TMU_ODATA contains the output data in q1.31 format */
#define TMU_OUTPUT_WIDTH_16 TMU_CS_OWIDTH /*!< TMU_ODATA contains the output data in q1.15 format */
/* TMU input data width definitions */
#define TMU_INPUT_WIDTH_32 ((uint32_t)0x00000000U) /*!< TMU_IDATA contains the input data in q1.31 format */
#define TMU_INPUT_WIDTH_16 TMU_CS_IWIDTH /*!< TMU_IDATA contains the input data in q1.15 format */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check init parameter struct */
#define NOT_TMU_MODE(mode) (((mode) != (TMU_MODE_COS)) && ((mode) != (TMU_MODE_SIN))&& ((mode) != (TMU_MODE_ATAN2)) && \
((mode) != (TMU_MODE_MODULUS)) && ((mode) != (TMU_MODE_ATAN))&& ((mode) != (TMU_MODE_COSH)) && \
((mode) != (TMU_MODE_SINH)) && ((mode) != (TMU_MODE_ATANH))&& ((mode) != (TMU_MODE_LN)) && \
((mode) != (TMU_MODE_SQRT)))
#define NOT_TMU_ITERATIONS_NUM(num) (((num) != (TMU_ITERATION_STEPS_4)) && ((num) != (TMU_ITERATION_STEPS_8))&& ((num) != (TMU_ITERATION_STEPS_12)) && \
((num) != (TMU_ITERATION_STEPS_16)) && ((num) != (TMU_ITERATION_STEPS_20))&& ((num) != (TMU_ITERATION_STEPS_24)))
#define NOT_TMU_SCALE_FACTOR(scale) (((scale) != (TMU_SCALING_FACTOR_1)) && ((scale) != (TMU_SCALING_FACTOR_2))&& ((scale) != (TMU_SCALING_FACTOR_4)) && \
((scale) != (TMU_SCALING_FACTOR_8)) && ((scale) != (TMU_SCALING_FACTOR_16))&& ((scale) != (TMU_SCALING_FACTOR_32)) && \
((scale) != (TMU_SCALING_FACTOR_64)) && ((scale) != (TMU_SCALING_FACTOR_128)))
#define NOT_TMU_DMA_READ(dma_read) (((dma_read) != (TMU_READ_DMA_DISABLE)) && ((dma_read) != (TMU_READ_DMA_ENABLE)))
#define NOT_TMU_DMA_WRITE(dma_write) (((dma_write) != (TMU_WRITE_DMA_DISABLE)) && ((dma_write) != (TMU_WRITE_DMA_ENABLE)))
#define NOT_TMU_READ_TIMES(read_times) (((read_times) != (TMU_READ_TIMES_1)) && ((read_times) != (TMU_READ_TIMES_2)))
#define NOT_TMU_WRITE_TIMES(write_times) (((write_times) != (TMU_WRITE_TIMES_1)) && ((write_times) != (TMU_WRITE_TIMES_2)))
#define NOT_TMU_OUTPUT_WIDTH(output_width) (((output_width) != (TMU_OUTPUT_WIDTH_32)) && ((output_width) != (TMU_OUTPUT_WIDTH_16)))
#define NOT_TMU_INPUT_WIDTH(input_width) (((input_width) != (TMU_INPUT_WIDTH_32)) && ((input_width) != (TMU_INPUT_WIDTH_16)))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* initialization functions */
/* reset the TMU registers */
void tmu_deinit(void);
/* initialize the parameters of TMU struct with the default values */
void tmu_struct_para_init(tmu_parameter_struct* init_struct);
/* initialize TMU */
void tmu_init(tmu_parameter_struct* init_struct);
/* interrupt and dma configuration */
/* enable TMU read interrupt */
void tmu_read_interrupt_enable(void);
/* disable TMU read interrupt */
void tmu_read_interrupt_disable(void);
/* enable TMU DMA read request */
void tmu_dma_read_enable(void);
/* disable TMU DMA read request */
void tmu_dma_read_disable(void);
/* enable TMU DMA write request */
void tmu_dma_write_enable(void);
/* disable TMU DMA write request */
void tmu_dma_write_disable(void);
/* TMU data write and read */
/* write one data in q1.31 format */
void tmu_one_q31_write(uint32_t data);
/* write two data in q1.31 format */
void tmu_two_q31_write(uint32_t data1, uint32_t data2);
/* write two data in q1.15 format */
void tmu_two_q15_write(uint16_t data1, uint16_t data2);
/* read one data in q1.31 format */
void tmu_one_q31_read(uint32_t* p);
/* read two data in q1.31 format */
void tmu_two_q31_read(uint32_t* p1, uint32_t* p2);
/* read two data in q1.15 format */
void tmu_two_q15_read(uint16_t* p1, uint16_t* p2);
#endif /* GD32H75E_TMU_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_trigsel.h
+318
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/*!
\file gd32h75e_trigsel.h
\brief definitions for the TRIGSEL
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_TRIGSEL_H
#define GD32H75E_TRIGSEL_H
#include "gd32h75e.h"
/* TRIGSEL definitions */
#define TRIGSEL TRIGSEL_BASE /*!< TRIGSEL base address */
/* register definitions */
#define TRIGSEL_EXTOUT0 REG32((TRIGSEL) + 0x00000000U) /*!< TRIGSEL trigger selection for EXTOUT0 register */
#define TRIGSEL_EXTOUT1 REG32((TRIGSEL) + 0x00000004U) /*!< TRIGSEL trigger selection for EXTOUT1 register */
#define TRIGSEL_EXTOUT2 REG32((TRIGSEL) + 0x00000008U) /*!< TRIGSEL trigger selection for EXTOUT2 register */
#define TRIGSEL_EXTOUT3 REG32((TRIGSEL) + 0x0000000CU) /*!< TRIGSEL trigger selection for EXTOUT3 register */
#define TRIGSEL_ADC0 REG32((TRIGSEL) + 0x00000010U) /*!< TRIGSEL trigger selection for ADC0 register */
#define TRIGSEL_ADC1 REG32((TRIGSEL) + 0x00000014U) /*!< TRIGSEL trigger selection for ADC1 register */
#define TRIGSEL_ADC2 REG32((TRIGSEL) + 0x00000018U) /*!< TRIGSEL trigger selection for ADC2 register */
#define TRIGSEL_DAC0OUT0 REG32((TRIGSEL) + 0x0000001CU) /*!< TRIGSEL trigger selection for DAC0_OUT0 register */
#define TRIGSEL_DAC0OUT1 REG32((TRIGSEL) + 0x00000020U) /*!< TRIGSEL trigger selection for DAC0_OUT1 register */
#define TRIGSEL_TIMER0BRKIN REG32((TRIGSEL) + 0x00000024U) /*!< TRIGSEL trigger selection for TIMER0_BRKIN register */
#define TRIGSEL_TIMER7BRKIN REG32((TRIGSEL) + 0x00000028U) /*!< TRIGSEL trigger selection for TIMER7_BRKIN register */
#define TRIGSEL_TIMER14BRKIN REG32((TRIGSEL) + 0x0000002CU) /*!< TRIGSEL trigger selection for TIMER14_BRKIN register */
#define TRIGSEL_TIMER15BRKIN REG32((TRIGSEL) + 0x00000030U) /*!< TRIGSEL trigger selection for TIMER15_BRKIN register */
#define TRIGSEL_TIMER16BRKIN REG32((TRIGSEL) + 0x00000034U) /*!< TRIGSEL trigger selection for TIMER16_BRKIN register */
#define TRIGSEL_TIMER40BRKIN REG32((TRIGSEL) + 0x00000038U) /*!< TRIGSEL trigger selection for TIMER40_BRKIN register */
#define TRIGSEL_TIMER41BRKIN REG32((TRIGSEL) + 0x0000003CU) /*!< TRIGSEL trigger selection for TIMER41_BRKIN register */
#define TRIGSEL_TIMER42BRKIN REG32((TRIGSEL) + 0x00000040U) /*!< TRIGSEL trigger selection for TIMER42_BRKIN register */
#define TRIGSEL_TIMER43BRKIN REG32((TRIGSEL) + 0x00000044U) /*!< TRIGSEL trigger selection for TIMER43_BRKIN register */
#define TRIGSEL_TIMER44BRKIN REG32((TRIGSEL) + 0x00000048U) /*!< TRIGSEL trigger selection for TIMER44_BRKIN register */
#define TRIGSEL_CAN0 REG32((TRIGSEL) + 0x0000004CU) /*!< TRIGSEL trigger selection for CAN0 register */
#define TRIGSEL_CAN1 REG32((TRIGSEL) + 0x00000050U) /*!< TRIGSEL trigger selection for CAN1 register */
#define TRIGSEL_CAN2 REG32((TRIGSEL) + 0x00000054U) /*!< TRIGSEL trigger selection for CAN2 register */
#define TRIGSEL_LPDTS REG32((TRIGSEL) + 0x00000058U) /*!< TRIGSEL trigger selection for LPDTS register */
#define TRIGSEL_TIMER0ETI REG32((TRIGSEL) + 0x0000005CU) /*!< TRIGSEL trigger selection for TIMER0_ETI register */
#define TRIGSEL_TIMER1ETI REG32((TRIGSEL) + 0x00000060U) /*!< TRIGSEL trigger selection for TIMER1_ETI register */
#define TRIGSEL_TIMER2ETI REG32((TRIGSEL) + 0x00000064U) /*!< TRIGSEL trigger selection for TIMER2_ETI register */
#define TRIGSEL_TIMER3ETI REG32((TRIGSEL) + 0x00000068U) /*!< TRIGSEL trigger selection for TIMER3_ETI register */
#define TRIGSEL_TIMER4ETI REG32((TRIGSEL) + 0x0000006CU) /*!< TRIGSEL trigger selection for TIMER4_ETI register */
#define TRIGSEL_TIMER7ETI REG32((TRIGSEL) + 0x00000070U) /*!< TRIGSEL trigger selection for TIMER7_ETI register */
#define TRIGSEL_TIMER22ETI REG32((TRIGSEL) + 0x00000074U) /*!< TRIGSEL trigger selection for TIMER22_ETI register */
#define TRIGSEL_TIMER23ETI REG32((TRIGSEL) + 0x00000078U) /*!< TRIGSEL trigger selection for TIMER23_ETI register */
#define TRIGSEL_EDOUT REG32((TRIGSEL) + 0x00000084U) /*!< TRIGSEL trigger selection for EDOUT register */
#define TRIGSEL_HPDF REG32((TRIGSEL) + 0x00000088U) /*!< TRIGSEL trigger selection for HPDF register */
#define TRIGSEL_TIMER0ITI14 REG32((TRIGSEL) + 0x0000008CU) /*!< TRIGSEL trigger selection for TIMER0_ITI14 register */
#define TRIGSEL_TIMER1ITI14 REG32((TRIGSEL) + 0x00000090U) /*!< TRIGSEL trigger selection for TIMER1_ITI14 register */
#define TRIGSEL_TIMER2ITI14 REG32((TRIGSEL) + 0x00000094U) /*!< TRIGSEL trigger selection for TIMER2_ITI14 register */
#define TRIGSEL_TIMER3ITI14 REG32((TRIGSEL) + 0x00000098U) /*!< TRIGSEL trigger selection for TIMER3_ITI14 register */
#define TRIGSEL_TIMER4ITI14 REG32((TRIGSEL) + 0x0000009CU) /*!< TRIGSEL trigger selection for TIMER4_ITI14 register */
#define TRIGSEL_TIMER7ITI14 REG32((TRIGSEL) + 0x000000A0U) /*!< TRIGSEL trigger selection for TIMER7_ITI14 register */
#define TRIGSEL_TIMER14ITI14 REG32((TRIGSEL) + 0x000000A4U) /*!< TRIGSEL trigger selection for TIMER14_ITI14 register */
#define TRIGSEL_TIMER22ITI14 REG32((TRIGSEL) + 0x000000A8U) /*!< TRIGSEL trigger selection for TIMER22_ITI14 register */
#define TRIGSEL_TIMER23ITI14 REG32((TRIGSEL) + 0x000000ACU) /*!< TRIGSEL trigger selection for TIMER23_ITI14 register */
#define TRIGSEL_TIMER40ITI14 REG32((TRIGSEL) + 0x000000B8U) /*!< TRIGSEL trigger selection for TIMER40_ITI14 register */
#define TRIGSEL_TIMER41ITI14 REG32((TRIGSEL) + 0x000000BCU) /*!< TRIGSEL trigger selection for TIMER41_ITI14 register */
#define TRIGSEL_TIMER42ITI14 REG32((TRIGSEL) + 0x000000C0U) /*!< TRIGSEL trigger selection for TIMER42_ITI14 register */
#define TRIGSEL_TIMER43ITI14 REG32((TRIGSEL) + 0x000000C4U) /*!< TRIGSEL trigger selection for TIMER43_ITI14 register */
#define TRIGSEL_TIMER44ITI14 REG32((TRIGSEL) + 0x000000C8U) /*!< TRIGSEL trigger selection for TIMER44_ITI14 register */
/* bit definitions */
/* trigger input source selection */
#define TRIGSEL_TARGET_INSEL0 BITS(0,7) /*!< trigger input source selection for output0 */
#define TRIGSEL_TARGET_INSEL1 BITS(8,15) /*!< trigger input source selection for output1 */
#define TRIGSEL_TARGET_INSEL2 BITS(16,23) /*!< trigger input source selection for output2 */
#define TRIGSEL_TARGET_LK BIT(31) /*!< TRIGSEL register lock */
/* constants definitions */
/* trigger source definitions */
typedef enum
{
TRIGSEL_INPUT_0 = ((uint8_t)0x00U), /*!< trigger input source 0 */
TRIGSEL_INPUT_1 = ((uint8_t)0x01U), /*!< trigger input source 1 */
TRIGSEL_INPUT_TRIGSEL_IN0 = ((uint8_t)0x02U), /*!< trigger input source TRIGSEL_IN0 pin */
TRIGSEL_INPUT_TRIGSEL_IN1 = ((uint8_t)0x03U), /*!< trigger input source TRIGSEL_IN1 pin */
TRIGSEL_INPUT_TRIGSEL_IN2 = ((uint8_t)0x04U), /*!< trigger input source TRIGSEL_IN2 pin */
TRIGSEL_INPUT_TRIGSEL_IN3 = ((uint8_t)0x05U), /*!< trigger input source TRIGSEL_IN3 pin */
TRIGSEL_INPUT_TRIGSEL_IN4 = ((uint8_t)0x06U), /*!< trigger input source TRIGSEL_IN4 pin */
TRIGSEL_INPUT_TRIGSEL_IN5 = ((uint8_t)0x07U), /*!< trigger input source TRIGSEL_IN5 pin */
TRIGSEL_INPUT_TRIGSEL_IN6 = ((uint8_t)0x08U), /*!< trigger input source TRIGSEL_IN6 pin */
TRIGSEL_INPUT_TRIGSEL_IN7 = ((uint8_t)0x09U), /*!< trigger input source TRIGSEL_IN7 pin */
TRIGSEL_INPUT_TRIGSEL_IN8 = ((uint8_t)0x0AU), /*!< trigger input source TRIGSEL_IN8 pin */
TRIGSEL_INPUT_TRIGSEL_IN9 = ((uint8_t)0x0BU), /*!< trigger input source TRIGSEL_IN9 pin */
TRIGSEL_INPUT_TRIGSEL_IN10 = ((uint8_t)0x0CU), /*!< trigger input source TRIGSEL_IN10 pin */
TRIGSEL_INPUT_TRIGSEL_IN11 = ((uint8_t)0x0DU), /*!< trigger input source TRIGSEL_IN11 pin */
TRIGSEL_INPUT_TRIGSEL_IN12 = ((uint8_t)0x0EU), /*!< trigger input source TRIGSEL_IN12 pin */
TRIGSEL_INPUT_TRIGSEL_IN13 = ((uint8_t)0x0FU), /*!< trigger input source TRIGSEL_IN13 pin */
TRIGSEL_INPUT_LXTAL_TRG = ((uint8_t)0x10U), /*!< trigger input source LXTAL_TRG */
TRIGSEL_INPUT_TIMER0_TRGO0 = ((uint8_t)0x11U), /*!< trigger input source TIMER0 TRGO0 */
TRIGSEL_INPUT_TIMER0_TRGO1 = ((uint8_t)0x12U), /*!< trigger input source TIMER0 TRGO1 */
TRIGSEL_INPUT_TIMER0_CH0 = ((uint8_t)0x13U), /*!< trigger input source TIMER0 CH0 */
TRIGSEL_INPUT_TIMER0_CH1 = ((uint8_t)0x14U), /*!< trigger input source TIMER0 CH1 */
TRIGSEL_INPUT_TIMER0_CH2 = ((uint8_t)0x15U), /*!< trigger input source TIMER0 CH2 */
TRIGSEL_INPUT_TIMER0_CH3 = ((uint8_t)0x16U), /*!< trigger input source TIMER0 CH3 */
TRIGSEL_INPUT_TIMER0_MCH0 = ((uint8_t)0x17U), /*!< trigger input source TIMER0 MCH0 */
TRIGSEL_INPUT_TIMER0_MCH1 = ((uint8_t)0x18U), /*!< trigger input source TIMER0 MCH1 */
TRIGSEL_INPUT_TIMER0_MCH2 = ((uint8_t)0x19U), /*!< trigger input source TIMER0 MCH2 */
TRIGSEL_INPUT_TIMER0_MCH3 = ((uint8_t)0x1AU), /*!< trigger input source TIMER0 MCH3 */
TRIGSEL_INPUT_TIMER0_BRKIN0 = ((uint8_t)0x21U), /*!< trigger input source TIMER0 BRKIN0 */
TRIGSEL_INPUT_TIMER0_BRKIN1 = ((uint8_t)0x22U), /*!< trigger input source TIMER0 BRKIN1 */
TRIGSEL_INPUT_TIMER0_BRKIN2 = ((uint8_t)0x23U), /*!< trigger input source TIMER0 BRKIN2 */
TRIGSEL_INPUT_TIMER0_ETI = ((uint8_t)0x24U), /*!< trigger input source TIMER0 ETI */
TRIGSEL_INPUT_TIMER1_TRGO0 = ((uint8_t)0x25U), /*!< trigger input source TIMER1 TRGO0 */
TRIGSEL_INPUT_TIMER1_CH0 = ((uint8_t)0x26U), /*!< trigger input source TIMER1 CH0 */
TRIGSEL_INPUT_TIMER1_CH1 = ((uint8_t)0x27U), /*!< trigger input source TIMER1 CH1 */
TRIGSEL_INPUT_TIMER1_CH2 = ((uint8_t)0x28U), /*!< trigger input source TIMER1 CH2 */
TRIGSEL_INPUT_TIMER1_CH3 = ((uint8_t)0x29U), /*!< trigger input source TIMER1 CH3 */
TRIGSEL_INPUT_TIMER1_ETI = ((uint8_t)0x2AU), /*!< trigger input source TIMER1 ETI */
TRIGSEL_INPUT_TIMER2_TRGO0 = ((uint8_t)0x2BU), /*!< trigger input source TIMER2 TRGO0 */
TRIGSEL_INPUT_TIMER2_CH0 = ((uint8_t)0x2CU), /*!< trigger input source TIMER2 CH0 */
TRIGSEL_INPUT_TIMER2_CH1 = ((uint8_t)0x2DU), /*!< trigger input source TIMER2 CH1 */
TRIGSEL_INPUT_TIMER2_CH2 = ((uint8_t)0x2EU), /*!< trigger input source TIMER2 CH2 */
TRIGSEL_INPUT_TIMER2_CH3 = ((uint8_t)0x2FU), /*!< trigger input source TIMER2 CH3 */
TRIGSEL_INPUT_TIMER2_ETI = ((uint8_t)0x30U), /*!< trigger input source TIMER2 ETI */
TRIGSEL_INPUT_TIMER3_TRGO0 = ((uint8_t)0x31U), /*!< trigger input source TIMER3 TRGO0 */
TRIGSEL_INPUT_TIMER3_CH0 = ((uint8_t)0x32U), /*!< trigger input source TIMER3 CH0 */
TRIGSEL_INPUT_TIMER3_CH1 = ((uint8_t)0x33U), /*!< trigger input source TIMER3 CH1 */
TRIGSEL_INPUT_TIMER3_CH2 = ((uint8_t)0x34U), /*!< trigger input source TIMER3 CH2 */
TRIGSEL_INPUT_TIMER3_CH3 = ((uint8_t)0x35U), /*!< trigger input source TIMER3 CH3 */
TRIGSEL_INPUT_TIMER3_ETI = ((uint8_t)0x36U), /*!< trigger input source TIMER3 ETI */
TRIGSEL_INPUT_TIMER4_TRGO0 = ((uint8_t)0x37U), /*!< trigger input source TIMER4 TRGO0 */
TRIGSEL_INPUT_TIMER4_CH0 = ((uint8_t)0x38U), /*!< trigger input source TIMER4 CH0 */
TRIGSEL_INPUT_TIMER4_CH1 = ((uint8_t)0x39U), /*!< trigger input source TIMER4 CH1 */
TRIGSEL_INPUT_TIMER4_CH2 = ((uint8_t)0x3AU), /*!< trigger input source TIMER4 CH2 */
TRIGSEL_INPUT_TIMER4_CH3 = ((uint8_t)0x3BU), /*!< trigger input source TIMER4 CH3 */
TRIGSEL_INPUT_TIMER4_ETI = ((uint8_t)0x3CU), /*!< trigger input source TIMER4 ETI */
TRIGSEL_INPUT_TIMER5_TRGO0 = ((uint8_t)0x3DU), /*!< trigger input source TIMER5 TRGO0 */
TRIGSEL_INPUT_TIMER6_TRGO0 = ((uint8_t)0x3EU), /*!< trigger input source TIMER6 TRGO0 */
TRIGSEL_INPUT_TIMER7_TRGO0 = ((uint8_t)0x3FU), /*!< trigger input source TIMER7 TRGO0 */
TRIGSEL_INPUT_TIMER7_TRGO1 = ((uint8_t)0x40U), /*!< trigger input source TIMER7 TRGO1 */
TRIGSEL_INPUT_TIMER7_CH0 = ((uint8_t)0x41U), /*!< trigger input source TIMER7 CH0 */
TRIGSEL_INPUT_TIMER7_CH1 = ((uint8_t)0x42U), /*!< trigger input source TIMER7 CH1 */
TRIGSEL_INPUT_TIMER7_CH2 = ((uint8_t)0x43U), /*!< trigger input source TIMER7 CH2 */
TRIGSEL_INPUT_TIMER7_CH3 = ((uint8_t)0x44U), /*!< trigger input source TIMER7 CH3 */
TRIGSEL_INPUT_TIMER7_MCH0 = ((uint8_t)0x45U), /*!< trigger input source TIMER7 MCH0 */
TRIGSEL_INPUT_TIMER7_MCH1 = ((uint8_t)0x46U), /*!< trigger input source TIMER7 MCH1 */
TRIGSEL_INPUT_TIMER7_MCH2 = ((uint8_t)0x47U), /*!< trigger input source TIMER7 MCH2 */
TRIGSEL_INPUT_TIMER7_MCH3 = ((uint8_t)0x48U), /*!< trigger input source TIMER7 MCH3 */
TRIGSEL_INPUT_TIMER7_BRKIN0 = ((uint8_t)0x4FU), /*!< trigger input source TIMER7 BRKIN0 */
TRIGSEL_INPUT_TIMER7_BRKIN1 = ((uint8_t)0x50U), /*!< trigger input source TIMER7 BRKIN1 */
TRIGSEL_INPUT_TIMER7_BRKIN2 = ((uint8_t)0x51U), /*!< trigger input source TIMER7 BRKIN2 */
TRIGSEL_INPUT_TIMER7_ETI = ((uint8_t)0x52U), /*!< trigger input source TIMER7 ETI */
TRIGSEL_INPUT_TIMER14_TRGO0 = ((uint8_t)0x53U), /*!< trigger input source TIMER14 TRGO0 */
TRIGSEL_INPUT_TIMER14_CH0 = ((uint8_t)0x54U), /*!< trigger input source TIMER14 CH0 */
TRIGSEL_INPUT_TIMER14_CH1 = ((uint8_t)0x55U), /*!< trigger input source TIMER14 CH1 */
TRIGSEL_INPUT_TIMER14_MCH0 = ((uint8_t)0x56U), /*!< trigger input source TIMER14 MCH0 */
TRIGSEL_INPUT_TIMER14_BRKIN0 = ((uint8_t)0x59U), /*!< trigger input source TIMER14 BRKIN0 */
TRIGSEL_INPUT_TIMER15_CH0 = ((uint8_t)0x5AU), /*!< trigger input source TIMER15 CH0 */
TRIGSEL_INPUT_TIMER15_MCH0 = ((uint8_t)0x5BU), /*!< trigger input source TIMER15 MCH0 */
TRIGSEL_INPUT_TIMER15_BRKIN0 = ((uint8_t)0x5EU), /*!< trigger input source TIMER15 BRKIN0 */
TRIGSEL_INPUT_TIMER16_CH0 = ((uint8_t)0x5FU), /*!< trigger input source TIMER16 CH0 */
TRIGSEL_INPUT_TIMER16_MCH0 = ((uint8_t)0x60U), /*!< trigger input source TIMER16 MCH0 */
TRIGSEL_INPUT_TIMER16_BRKIN0 = ((uint8_t)0x63U), /*!< trigger input source TIMER16 BRKIN0 */
TRIGSEL_INPUT_TIMER22_TRGO0 = ((uint8_t)0x64U), /*!< trigger input source TIMER22 TRGO0 */
TRIGSEL_INPUT_TIMER22_CH0 = ((uint8_t)0x65U), /*!< trigger input source TIMER22 CH0 */
TRIGSEL_INPUT_TIMER22_CH1 = ((uint8_t)0x66U), /*!< trigger input source TIMER22 CH1 */
TRIGSEL_INPUT_TIMER22_CH2 = ((uint8_t)0x67U), /*!< trigger input source TIMER22 CH2 */
TRIGSEL_INPUT_TIMER22_CH3 = ((uint8_t)0x68U), /*!< trigger input source TIMER22 CH3 */
TRIGSEL_INPUT_TIMER22_ETI = ((uint8_t)0x69U), /*!< trigger input source TIMER22 ETI */
TRIGSEL_INPUT_TIMER23_TRGO0 = ((uint8_t)0x6AU), /*!< trigger input source TIMER23 TRGO0 */
TRIGSEL_INPUT_TIMER23_CH0 = ((uint8_t)0x6BU), /*!< trigger input source TIMER23 CH0 */
TRIGSEL_INPUT_TIMER23_CH1 = ((uint8_t)0x6CU), /*!< trigger input source TIMER23 CH1 */
TRIGSEL_INPUT_TIMER23_CH2 = ((uint8_t)0x6DU), /*!< trigger input source TIMER23 CH2 */
TRIGSEL_INPUT_TIMER23_CH3 = ((uint8_t)0x6EU), /*!< trigger input source TIMER23 CH3 */
TRIGSEL_INPUT_TIMER23_ETI = ((uint8_t)0x6FU), /*!< trigger input source TIMER23 ETI */
TRIGSEL_INPUT_TIMER40_TRGO0 = ((uint8_t)0x7CU), /*!< trigger input source TIMER40 TRGO0 */
TRIGSEL_INPUT_TIMER40_CH0 = ((uint8_t)0x7DU), /*!< trigger input source TIMER40 CH0 */
TRIGSEL_INPUT_TIMER40_CH1 = ((uint8_t)0x7EU), /*!< trigger input source TIMER40 CH1 */
TRIGSEL_INPUT_TIMER40_MCH0 = ((uint8_t)0x7FU), /*!< trigger input source TIMER40 MCH0 */
TRIGSEL_INPUT_TIMER40_BRKIN0 = ((uint8_t)0x82U), /*!< trigger input source TIMER40 BRKIN0 */
TRIGSEL_INPUT_TIMER41_TRGO0 = ((uint8_t)0x83U), /*!< trigger input source TIMER41 TRGO0 */
TRIGSEL_INPUT_TIMER41_CH0 = ((uint8_t)0x84U), /*!< trigger input source TIMER41 CH0 */
TRIGSEL_INPUT_TIMER41_CH1 = ((uint8_t)0x85U), /*!< trigger input source TIMER41 CH1 */
TRIGSEL_INPUT_TIMER41_MCH0 = ((uint8_t)0x86U), /*!< trigger input source TIMER41 MCH0 */
TRIGSEL_INPUT_TIMER41_BRKIN0 = ((uint8_t)0x89U), /*!< trigger input source TIMER41 BRKIN0 */
TRIGSEL_INPUT_TIMER42_TRGO0 = ((uint8_t)0x8AU), /*!< trigger input source TIMER42 TRGO0 */
TRIGSEL_INPUT_TIMER42_CH0 = ((uint8_t)0x8BU), /*!< trigger input source TIMER42 CH0 */
TRIGSEL_INPUT_TIMER42_CH1 = ((uint8_t)0x8CU), /*!< trigger input source TIMER42 CH1 */
TRIGSEL_INPUT_TIMER42_MCH0 = ((uint8_t)0x8DU), /*!< trigger input source TIMER42 MCH0 */
TRIGSEL_INPUT_TIMER42_BRKIN0 = ((uint8_t)0x90U), /*!< trigger input source TIMER42 BRKIN0 */
TRIGSEL_INPUT_TIMER43_TRGO0 = ((uint8_t)0x91U), /*!< trigger input source TIMER43 TRGO0 */
TRIGSEL_INPUT_TIMER43_CH0 = ((uint8_t)0x92U), /*!< trigger input source TIMER43 CH0 */
TRIGSEL_INPUT_TIMER43_CH1 = ((uint8_t)0x93U), /*!< trigger input source TIMER43 CH1 */
TRIGSEL_INPUT_TIMER43_MCH0 = ((uint8_t)0x94U), /*!< trigger input source TIMER43 MCH0 */
TRIGSEL_INPUT_TIMER43_BRKIN0 = ((uint8_t)0x97U), /*!< trigger input source TIMER43 BRKIN0 */
TRIGSEL_INPUT_TIMER44_TRGO0 = ((uint8_t)0x98U), /*!< trigger input source TIMER44 TRGO0 */
TRIGSEL_INPUT_TIMER44_CH0 = ((uint8_t)0x99U), /*!< trigger input source TIMER44 CH0 */
TRIGSEL_INPUT_TIMER44_CH1 = ((uint8_t)0x9AU), /*!< trigger input source TIMER44 CH1 */
TRIGSEL_INPUT_TIMER44_MCH0 = ((uint8_t)0x9BU), /*!< trigger input source TIMER44 MCH0 */
TRIGSEL_INPUT_TIMER44_BRKIN0 = ((uint8_t)0x9EU), /*!< trigger input source TIMER44 BRKIN0 */
TRIGSEL_INPUT_TIMER50_TRGO0 = ((uint8_t)0x9FU), /*!< trigger input source TIMER50 TRGO0 */
TRIGSEL_INPUT_TIMER51_TRGO0 = ((uint8_t)0xA0U), /*!< trigger input source TIMER51 TRGO0 */
TRIGSEL_INPUT_RTC_ALARM = ((uint8_t)0xA1U), /*!< trigger input source RTC alarm */
TRIGSEL_INPUT_RTC_TPTS = ((uint8_t)0xA2U), /*!< trigger input source RTC tamper and time-stamp */
TRIGSEL_INPUT_ADC0_WD0_OUT = ((uint8_t)0xA3U), /*!< trigger input source ADC0 watchdog0 output */
TRIGSEL_INPUT_ADC0_WD1_OUT = ((uint8_t)0xA4U), /*!< trigger input source ADC0 watchdog1 output */
TRIGSEL_INPUT_ADC0_WD2_OUT = ((uint8_t)0xA5U), /*!< trigger input source ADC0 watchdog2 output */
TRIGSEL_INPUT_ADC1_WD0_OUT = ((uint8_t)0xA6U), /*!< trigger input source ADC1 watchdog0 output */
TRIGSEL_INPUT_ADC1_WD1_OUT = ((uint8_t)0xA7U), /*!< trigger input source ADC1 watchdog1 output */
TRIGSEL_INPUT_ADC1_WD2_OUT = ((uint8_t)0xA8U), /*!< trigger input source ADC1 watchdog2 output */
TRIGSEL_INPUT_ADC2_WD0_OUT = ((uint8_t)0xA9U), /*!< trigger input source ADC2 watchdog0 output */
TRIGSEL_INPUT_ADC2_WD1_OUT = ((uint8_t)0xAAU), /*!< trigger input source ADC2 watchdog1 output */
TRIGSEL_INPUT_ADC2_WD2_OUT = ((uint8_t)0xABU), /*!< trigger input source ADC2 watchdog2 output */
TRIGSEL_INPUT_CMP0_OUT = ((uint8_t)0xACU), /*!< trigger input source CMP0_OUT */
TRIGSEL_INPUT_CMP1_OUT = ((uint8_t)0xADU), /*!< trigger input source CMP1_OUT */
TRIGSEL_INPUT_SAI0_FS0 = ((uint8_t)0xAEU), /*!< trigger input source SAI0_FS0 */
TRIGSEL_INPUT_SAI0_FS1 = ((uint8_t)0xAFU), /*!< trigger input source SAI0_FS1 */
TRIGSEL_INPUT_SAI2_FS0 = ((uint8_t)0xB0U), /*!< trigger input source SAI2_FS0 */
TRIGSEL_INPUT_SAI2_FS1 = ((uint8_t)0xB1U), /*!< trigger input source SAI2_FS1 */
}trigsel_source_enum;
/* target peripheral definitions */
typedef enum
{
TRIGSEL_OUTPUT_TRIGSEL_OUT0 = ((uint8_t)0x00U), /*!< output target peripheral TRIGSEL_OUT0 pin */
TRIGSEL_OUTPUT_TRIGSEL_OUT1 = ((uint8_t)0x01U), /*!< output target peripheral TRIGSEL_OUT1 pin */
TRIGSEL_OUTPUT_TRIGSEL_OUT2 = ((uint8_t)0x04U), /*!< output target peripheral TRIGSEL_OUT2 pin */
TRIGSEL_OUTPUT_TRIGSEL_OUT3 = ((uint8_t)0x05U), /*!< output target peripheral TRIGSEL_OUT3 pin */
TRIGSEL_OUTPUT_TRIGSEL_OUT4 = ((uint8_t)0x08U), /*!< output target peripheral TRIGSEL_OUT4 pin */
TRIGSEL_OUTPUT_TRIGSEL_OUT5 = ((uint8_t)0x09U), /*!< output target peripheral TRIGSEL_OUT5 pin */
TRIGSEL_OUTPUT_TRIGSEL_OUT6 = ((uint8_t)0x0CU), /*!< output target peripheral TRIGSEL_OUT6 pin */
TRIGSEL_OUTPUT_TRIGSEL_OUT7 = ((uint8_t)0x0DU), /*!< output target peripheral TRIGSEL_OUT7 pin */
TRIGSEL_OUTPUT_ADC0_REGTRG = ((uint8_t)0x10U), /*!< output target peripheral ADC0_REGTRG */
TRIGSEL_OUTPUT_ADC0_INSTRG = ((uint8_t)0x11U), /*!< output target peripheral ADC0_INSTRG */
TRIGSEL_OUTPUT_ADC1_REGTRG = ((uint8_t)0x14U), /*!< output target peripheral ADC1_REGTRG */
TRIGSEL_OUTPUT_ADC1_INSTRG = ((uint8_t)0x15U), /*!< output target peripheral ADC1_INSTRG */
TRIGSEL_OUTPUT_ADC2_REGTRG = ((uint8_t)0x18U), /*!< output target peripheral ADC2_REGTRG */
TRIGSEL_OUTPUT_ADC2_INSTRG = ((uint8_t)0x19U), /*!< output target peripheral ADC2_INSTRG */
TRIGSEL_OUTPUT_DAC0_OUT0_EXTRG = ((uint8_t)0x1CU), /*!< output target peripheral DAC0_OUT0_EXTRG */
TRIGSEL_OUTPUT_DAC0_OUT1_EXTRG = ((uint8_t)0x20U), /*!< output target peripheral DAC0_OUT1_EXTRG */
TRIGSEL_OUTPUT_TIMER0_BRKIN0 = ((uint8_t)0x24U), /*!< output target peripheral TIMER0_BRKIN0 */
TRIGSEL_OUTPUT_TIMER0_BRKIN1 = ((uint8_t)0x25U), /*!< output target peripheral TIMER0_BRKIN1 */
TRIGSEL_OUTPUT_TIMER0_BRKIN2 = ((uint8_t)0x26U), /*!< output target peripheral TIMER0_BRKIN2 */
TRIGSEL_OUTPUT_TIMER7_BRKIN0 = ((uint8_t)0x28U), /*!< output target peripheral TIMER7_BRKIN0 */
TRIGSEL_OUTPUT_TIMER7_BRKIN1 = ((uint8_t)0x29U), /*!< output target peripheral TIMER7_BRKIN1 */
TRIGSEL_OUTPUT_TIMER7_BRKIN2 = ((uint8_t)0x2AU), /*!< output target peripheral TIMER7_BRKIN2 */
TRIGSEL_OUTPUT_TIMER14_BRKIN0 = ((uint8_t)0x2CU), /*!< output target peripheral TIMER14_BRKIN0 */
TRIGSEL_OUTPUT_TIMER15_BRKIN0 = ((uint8_t)0x30U), /*!< output target peripheral TIMER15_BRKIN0 */
TRIGSEL_OUTPUT_TIMER16_BRKIN0 = ((uint8_t)0x34U), /*!< output target peripheral TIMER16_BRKIN0 */
TRIGSEL_OUTPUT_TIMER40_BRKIN0 = ((uint8_t)0x38U), /*!< output target peripheral TIMER40_BRKIN0 */
TRIGSEL_OUTPUT_TIMER41_BRKIN0 = ((uint8_t)0x3CU), /*!< output target peripheral TIMER41_BRKIN0 */
TRIGSEL_OUTPUT_TIMER42_BRKIN0 = ((uint8_t)0x40U), /*!< output target peripheral TIMER42_BRKIN0 */
TRIGSEL_OUTPUT_TIMER43_BRKIN0 = ((uint8_t)0x44U), /*!< output target peripheral TIMER43_BRKIN0 */
TRIGSEL_OUTPUT_TIMER44_BRKIN0 = ((uint8_t)0x48U), /*!< output target peripheral TIMER44_BRKIN0 */
TRIGSEL_OUTPUT_CAN0_EX_TIME_TICK = ((uint8_t)0x4CU), /*!< output target peripheral CAN0_EX_TIME_TICK */
TRIGSEL_OUTPUT_CAN1_EX_TIME_TICK = ((uint8_t)0x50U), /*!< output target peripheral CAN1_EX_TIME_TICK */
TRIGSEL_OUTPUT_CAN2_EX_TIME_TICK = ((uint8_t)0x54U), /*!< output target peripheral CAN2_EX_TIME_TICK */
TRIGSEL_OUTPUT_LPDTS_TRG = ((uint8_t)0x58U), /*!< output target peripheral LPDTS_TRG */
TRIGSEL_OUTPUT_TIMER0_ETI = ((uint8_t)0x5CU), /*!< output target peripheral TIMER0_ETI */
TRIGSEL_OUTPUT_TIMER1_ETI = ((uint8_t)0x60U), /*!< output target peripheral TIMER1_ETI */
TRIGSEL_OUTPUT_TIMER2_ETI = ((uint8_t)0x64U), /*!< output target peripheral TIMER2_ETI */
TRIGSEL_OUTPUT_TIMER3_ETI = ((uint8_t)0x68U), /*!< output target peripheral TIMER3_ETI */
TRIGSEL_OUTPUT_TIMER4_ETI = ((uint8_t)0x6CU), /*!< output target peripheral TIMER4_ETI */
TRIGSEL_OUTPUT_TIMER7_ETI = ((uint8_t)0x70U), /*!< output target peripheral TIMER7_ETI */
TRIGSEL_OUTPUT_TIMER22_ETI = ((uint8_t)0x74U), /*!< output target peripheral TIMER22_ETI */
TRIGSEL_OUTPUT_TIMER23_ETI = ((uint8_t)0x78U), /*!< output target peripheral TIMER23_ETI */
TRIGSEL_OUTPUT_EDOUT_TRG = ((uint8_t)0x84U), /*!< output target peripheral EDOUT_TRG */
TRIGSEL_OUTPUT_HPDF_ITR = ((uint8_t)0x88U), /*!< output target peripheral HPDF_ITR */
TRIGSEL_OUTPUT_TIMER0_ITI14 = ((uint8_t)0x8CU), /*!< output target peripheral TIMER0_ITI14 */
TRIGSEL_OUTPUT_TIMER1_ITI14 = ((uint8_t)0x90U), /*!< output target peripheral TIMER1_ITI14 */
TRIGSEL_OUTPUT_TIMER2_ITI14 = ((uint8_t)0x94U), /*!< output target peripheral TIMER2_ITI14 */
TRIGSEL_OUTPUT_TIMER3_ITI14 = ((uint8_t)0x98U), /*!< output target peripheral TIMER3_ITI14 */
TRIGSEL_OUTPUT_TIMER4_ITI14 = ((uint8_t)0x9CU), /*!< output target peripheral TIMER4_ITI14 */
TRIGSEL_OUTPUT_TIMER7_ITI14 = ((uint8_t)0xA0U), /*!< output target peripheral TIMER7_ITI14 */
TRIGSEL_OUTPUT_TIMER14_ITI14 = ((uint8_t)0xA4U), /*!< output target peripheral TIMER14_ITI14 */
TRIGSEL_OUTPUT_TIMER22_ITI14 = ((uint8_t)0xA8U), /*!< output target peripheral TIMER22_ITI14 */
TRIGSEL_OUTPUT_TIMER23_ITI14 = ((uint8_t)0xACU), /*!< output target peripheral TIMER23_ITI14 */
TRIGSEL_OUTPUT_TIMER40_ITI14 = ((uint8_t)0xB8U), /*!< output target peripheral TIMER40_ITI14 */
TRIGSEL_OUTPUT_TIMER41_ITI14 = ((uint8_t)0xBCU), /*!< output target peripheral TIMER41_ITI14 */
TRIGSEL_OUTPUT_TIMER42_ITI14 = ((uint8_t)0xC0U), /*!< output target peripheral TIMER42_ITI14 */
TRIGSEL_OUTPUT_TIMER43_ITI14 = ((uint8_t)0xC4U), /*!< output target peripheral TIMER43_ITI14 */
TRIGSEL_OUTPUT_TIMER44_ITI14 = ((uint8_t)0xC8U), /*!< output target peripheral TIMER44_ITI14 */
}trigsel_periph_enum;
/* function declarations */
/* deinitialize TRIGSEL */
void trigsel_deinit(void);
/* set the trigger input signal for target peripheral */
void trigsel_init(trigsel_periph_enum target_periph, trigsel_source_enum trigger_source);
/* get the trigger input signal for target peripheral */
trigsel_source_enum trigsel_trigger_source_get(trigsel_periph_enum target_periph);
/* lock the trigger register */
void trigsel_register_lock_set(trigsel_periph_enum target_periph);
/* get the trigger register lock status */
FlagStatus trigsel_register_lock_get(trigsel_periph_enum target_periph);
#endif /* GD32H75E_TRIGSEL_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_trng.h
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/*!
\file gd32h75e_trng.h
\brief definitions for the TRNG
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_TRNG_H
#define GD32H75E_TRNG_H
#include "gd32h75e.h"
/* TRNG definitions */
#define TRNG TRNG_BASE
/* registers definitions */
#define TRNG_CTL REG32(TRNG + 0x00000000U) /*!< control register */
#define TRNG_STAT REG32(TRNG + 0x00000004U) /*!< status register */
#define TRNG_DATA REG32(TRNG + 0x00000008U) /*!< data register */
#define TRNG_HTCFG REG32(TRNG + 0x00000010U) /*!< health tests configure register */
/* bits definitions */
/* TRNG_CTL */
#define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */
#define TRNG_CTL_IE BIT(3) /*!< interrupt enable bit */
#define TRNG_CTL_MODSEL BIT(4) /*!< TRNG working mode config bit */
#define TRNG_CTL_CED BIT(5) /*!< clock error detect enable bit */
#define TRNG_CTL_RTEN BIT(7) /*!< replace test enable */
#define TRNG_CTL_INIT BIT(8) /*!< HASH algorithm init */
#define TRNG_CTL_PPEN BIT(9) /*!< TRNG post-porcessing module enable */
#define TRNG_CTL_CONDEN BIT(10) /*!< TRNG conditioning module enable */
#define TRNG_CTL_ALGO BITS(12,13) /*!< TRNG conditioning module hash algo select */
#define TRNG_CTL_OUTMOD BIT(14) /*!< TRNG conditioning output width config bit */
#define TRNG_CTL_INMOD BIT(15) /*!< TRNG conditioning input width config bit */
#define TRNG_CTL_CLKDIV BITS(16,19) /*!< TRNG clock divider */
#define TRNG_CTL_NR BITS(24,25) /*!< TRNG analog power mode bits */
#define TRNG_CTL_CONDRST BIT(30) /*!< reset TRNG conditioning logic */
#define TRNG_CTL_LK BIT(31) /*!< TRNG_CTL register lock bit */
/* TRNG_STAT */
#define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */
#define TRNG_STAT_CECS BIT(1) /*!< clock error current status */
#define TRNG_STAT_SECS BIT(2) /*!< seed error current status */
#define TRNG_STAT_ERRSTA BIT(3) /*!< NIST mode error status */
#define TRNG_STAT_CEIF BIT(5) /*!< clock error interrupt flag */
#define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */
/* TRNG_DATA */
#define TRNG_DATA_TRNDATA BITS(0,31) /*!< 32-Bit Random data */
/* TRNG_HTCFG */
#define TRNG_HTCFG_RCTTH BITS(0,6) /*!< repetition (00/11) count test threshold */
#define TRNG_HTCFG_APTTH BITS(16,25) /*!< adaptive proportion test threshold */
/* TRNG clock division */
#define CTL_ALGO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U))
#define TRNG_ALGO_SHA1 CTL_ALGO(0) /*!< TRNG conditioning module hash SHA1 */
#define TRNG_ALGO_MD5 CTL_ALGO(1) /*!< TRNG conditioning module hash MD5 */
#define TRNG_ALGO_SHA224 CTL_ALGO(2) /*!< TRNG conditioning module hash SHA224 */
#define TRNG_ALGO_SHA256 CTL_ALGO(3) /*!< TRNG conditioning module hash SHA256 */
/* TRNG clock division */
#define CTL_CLKDIV(regval) (BITS(16,19) & ((uint32_t)(regval) << 16U))
#define TRNG_CLK_DIV1 CTL_CLKDIV(0) /*!< TRNG clock TRNG_CLK divider 1 */
#define TRNG_CLK_DIV2 CTL_CLKDIV(1) /*!< TRNG clock TRNG_CLK divider 2 */
#define TRNG_CLK_DIV4 CTL_CLKDIV(2) /*!< TRNG clock TRNG_CLK divider 4 */
#define TRNG_CLK_DIV8 CTL_CLKDIV(3) /*!< TRNG clock TRNG_CLK divider 8 */
#define TRNG_CLK_DIV16 CTL_CLKDIV(4) /*!< TRNG clock TRNG_CLK divider 16 */
#define TRNG_CLK_DIV32 CTL_CLKDIV(5) /*!< TRNG clock TRNG_CLK divider 32 */
#define TRNG_CLK_DIV64 CTL_CLKDIV(6) /*!< TRNG clock TRNG_CLK divider 64 */
#define TRNG_CLK_DIV128 CTL_CLKDIV(7) /*!< TRNG clock TRNG_CLK divider 128 */
#define TRNG_CLK_DIV256 CTL_CLKDIV(8) /*!< TRNG clock TRNG_CLK divider 256 */
#define TRNG_CLK_DIV512 CTL_CLKDIV(9) /*!< TRNG clock TRNG_CLK divider 512 */
#define TRNG_CLK_DIV1024 CTL_CLKDIV(10) /*!< TRNG clock TRNG_CLK divider 1024 */
#define TRNG_CLK_DIV2048 CTL_CLKDIV(11) /*!< TRNG clock TRNG_CLK divider 2048 */
#define TRNG_CLK_DIV4096 CTL_CLKDIV(12) /*!< TRNG clock TRNG_CLK divider 4096 */
#define TRNG_CLK_DIV8192 CTL_CLKDIV(13) /*!< TRNG clock TRNG_CLK divider 8192 */
#define TRNG_CLK_DIV16384 CTL_CLKDIV(14) /*!< TRNG clock TRNG_CLK divider 16384 */
#define TRNG_CLK_DIV32768 CTL_CLKDIV(15) /*!< TRNG clock TRNG_CLK divider 32768 */
/* TRNG power mode */
#define CTL_NR(regval) (BITS(24,25) & ((uint32_t)(regval) << 24U))
#define TRNG_NR_ULTRALOW CTL_NR(0) /*!< TRNG analog power mode ultralow */
#define TRNG_NR_LOW CTL_NR(1) /*!< TRNG analog power mode low */
#define TRNG_NR_MEDIUM CTL_NR(2) /*!< TRNG analog power mode medium */
#define TRNG_NR_HIGH CTL_NR(3) /*!< TRNG analog power mode high */
/* constants definitions */
/* trng input mode */
typedef enum {
TRNG_INMOD_256BIT = 0, /*!< conditioning module input bitwidth 256bits */
TRNG_INMOD_440BIT = TRNG_CTL_INMOD /*!< conditioning module input bitwidth 440bits */
} trng_inmod_enum;
/* trng output mode */
typedef enum {
TRNG_OUTMOD_128BIT = 0, /*!< conditioning module output bitwidth 128bits */
TRNG_OUTMOD_256BIT = TRNG_CTL_OUTMOD /*!< conditioning module output bitwidth 256bits */
} trng_outmod_enum;
/* trng working mode */
typedef enum {
TRNG_MODSEL_LFSR = 0, /*!< TRNG working in LFSR mode */
TRNG_MODSEL_NIST = TRNG_CTL_MODSEL /*!< TRNG working in NIST mode */
} trng_modsel_enum;
/* trng status flag */
typedef enum {
TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random data ready status */
TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */
TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */
} trng_flag_enum;
/* trng interrupt flag */
typedef enum {
TRNG_INT_FLAG_CEIF = TRNG_STAT_CEIF, /*!< clock error interrupt flag */
TRNG_INT_FLAG_SEIF = TRNG_STAT_SEIF /*!< seed error interrupt flag */
} trng_int_flag_enum;
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check TRNG power mode */
#define NOT_TRNG_POWER_MODE(powermode) (((powermode) != TRNG_NR_ULTRALOW) && \
((powermode) != TRNG_NR_LOW) && \
((powermode) != TRNG_NR_MEDIUM) && \
((powermode) != TRNG_NR_HIGH))
/* check TRNG clock divider */
#define NOT_TRNG_CLOCK_DIVIDER(clkdiv) (((clkdiv) != TRNG_CLK_DIV1) && \
((clkdiv) != TRNG_CLK_DIV2) && \
((clkdiv) != TRNG_CLK_DIV4) && \
((clkdiv) != TRNG_CLK_DIV8) && \
((clkdiv) != TRNG_CLK_DIV16) && \
((clkdiv) != TRNG_CLK_DIV32) && \
((clkdiv) != TRNG_CLK_DIV64) && \
((clkdiv) != TRNG_CLK_DIV128) && \
((clkdiv) != TRNG_CLK_DIV256) && \
((clkdiv) != TRNG_CLK_DIV512) && \
((clkdiv) != TRNG_CLK_DIV1024) && \
((clkdiv) != TRNG_CLK_DIV2048) && \
((clkdiv) != TRNG_CLK_DIV4096) && \
((clkdiv) != TRNG_CLK_DIV8192) && \
((clkdiv) != TRNG_CLK_DIV16384) && \
((clkdiv) != TRNG_CLK_DIV32768))
/* check TRNG module algorithm */
#define NOT_TRNG_MODULE_ALGORITHM(module_algo) (((module_algo) != TRNG_ALGO_SHA1) && \
((module_algo) != TRNG_ALGO_MD5) && \
((module_algo) != TRNG_ALGO_SHA224) && \
((module_algo) != TRNG_ALGO_SHA256))
/* check TRNG adaptive proportion threshold */
#define NOT_TRNG_ADPO_THRESHOLD(adpo_threshold) (((adpo_threshold) > 0x000003FFU))
/* check TRNG repetitive threshold */
#define NOT_TRNG_REP_THRESHOLD(rep_threshold) (((rep_threshold) > 0x7FU))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* initialization functions */
/* deinitialize the TRNG */
void trng_deinit(void);
/* enable the TRNG interface */
void trng_enable(void);
/* disable the TRNG interface */
void trng_disable(void);
/* lock the TRNG control bits */
void trng_lock(void);
/* configure TRNG working mode */
void trng_mode_config(trng_modsel_enum mode_select);
/* enable the TRNG post-processing module */
void trng_postprocessing_enable(void);
/* disable the TRNG post-processing module */
void trng_postprocessing_disable(void);
/* enable the TRNG conditioning module */
void trng_conditioning_enable(void);
/* disable the TRNG conditioning module */
void trng_conditioning_disable(void);
/* configure TRNG conditioning module input bitwidth */
void trng_conditioning_input_bitwidth(trng_inmod_enum input_bitwidth);
/* configure TRNG conditioning module output bitwidth */
void trng_conditioning_output_bitwidth(trng_outmod_enum output_bitwidth);
/* enable TRNG replace test */
void trng_replace_test_enable(void);
/* disable TRNG replace test */
void trng_replace_test_disable(void);
/* enable hash algorithm init when conditioning module enabled */
void trng_hash_init_enable(void);
/* disable hash algorithm init when conditioning module enabled */
void trng_hash_init_disable(void);
/* configure TRNG analog power mode */
void trng_powermode_config(uint32_t powermode);
/* configure TRNG clock divider */
void trng_clockdiv_config(uint32_t clkdiv);
/* enable the TRNG clock error detection */
void trng_clockerror_detection_enable(void);
/* disable the TRNG clock error detection */
void trng_clockerror_detection_disable(void);
/* get the true random data */
uint32_t trng_get_true_random_data(void);
/* conditioning configration */
/* enable the conditioning logic reset */
void trng_conditioning_reset_enable(void);
/* disable the conditioning logic reset */
void trng_conditioning_reset_disable(void);
/* configure the conditioning module hash algorithm */
void trng_conditioning_algo_config(uint32_t module_algo);
/* configure health tests default value */
void trng_health_tests_config(uint32_t adpo_threshold, uint8_t rep_threshold);
/* flag & interrupt functions */
/* get the TRNG status flags */
FlagStatus trng_flag_get(trng_flag_enum flag);
/* enable TRNG interrupt */
void trng_interrupt_enable(void);
/* disable TRNG interrupt */
void trng_interrupt_disable(void);
/* get the TRNG interrupt flags */
FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag);
/* clear the TRNG interrupt flags */
void trng_interrupt_flag_clear(trng_int_flag_enum int_flag);
#endif /* GD32H75E_TRNG_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_usart.h
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/*!
\file gd32h75e_usart.h
\brief definitions for the USART
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_USART_H
#define GD32H75E_USART_H
#include "gd32h75e.h"
/* USARTx(x=0,1,2,5), UARTx(x=3,4,6,7) definitions */
#define USART0 (USART_BASE + 0x0000CC00U) /*!< USART0 base address */
#define USART1 USART_BASE /*!< USART1 base address */
#define USART2 (USART_BASE + 0x00000400U) /*!< USART2 base address */
#define UART3 (USART_BASE + 0x00000800U) /*!< UART3 base address */
#define UART4 (USART_BASE + 0x00000C00U) /*!< UART4 base address */
#define USART5 (USART_BASE + 0x0000D000U) /*!< USART5 base address */
#define UART6 (USART_BASE + 0x00003400U) /*!< UART6 base address */
#define UART7 (USART_BASE + 0x00003800U) /*!< UART7 base address */
/* registers definitions */
#define USART_CTL0(usartx) REG32((usartx) + 0x00000000U) /*!< USART control register 0 */
#define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 */
#define USART_CTL2(usartx) REG32((usartx) + 0x00000008U) /*!< USART control register 2 */
#define USART_BAUD(usartx) REG32((usartx) + 0x0000000CU) /*!< USART baud rate generator register */
#define USART_GP(usartx) REG32((usartx) + 0x00000010U) /*!< USART prescaler and guard time configuration register */
#define USART_RT(usartx) REG32((usartx) + 0x00000014U) /*!< USART receiver timeout register */
#define USART_CMD(usartx) REG32((usartx) + 0x00000018U) /*!< USART command register */
#define USART_STAT(usartx) REG32((usartx) + 0x0000001CU) /*!< USART status register */
#define USART_INTC(usartx) REG32((usartx) + 0x00000020U) /*!< USART interrupt status clear register */
#define USART_RDATA(usartx) REG32((usartx) + 0x00000024U) /*!< USART receive data register */
#define USART_TDATA(usartx) REG32((usartx) + 0x00000028U) /*!< USART transmit data register */
#define USART_CHC(usartx) REG32((usartx) + 0x000000C0U) /*!< USART coherence control register */
#define USART_FCS(usartx) REG32((usartx) + 0x000000D0U) /*!< USART FIFO control and status register */
/* bits definitions */
/* USARTx_CTL0 */
#define USART_CTL0_UEN BIT(0) /*!< enable USART */
#define USART_CTL0_UESM BIT(1) /*!< enable USART in deep-sleep mode */
#define USART_CTL0_REN BIT(2) /*!< enable receiver */
#define USART_CTL0_TEN BIT(3) /*!< enable transmitter */
#define USART_CTL0_IDLEIE BIT(4) /*!< enable idle line detected interrupt */
#define USART_CTL0_RBNEIE BIT(5) /*!< enable read data buffer not empty interrupt and overrun error interrupt (when FIFO is disabled) */
#define USART_CTL0_RFNEIE BIT(5) /*!< enable receive FIFO not empty interrupt and overrun error interrupt (when FIFO is enabled) */
#define USART_CTL0_TCIE BIT(6) /*!< enable transmission complete interrupt */
#define USART_CTL0_TBEIE BIT(7) /*!< enable transmitter register empty interrupt (when FIFO is disabled) */
#define USART_CTL0_TFNFIE BIT(7) /*!< enable transmit FIFO not full interrupt (when FIFO is enabled) */
#define USART_CTL0_PERRIE BIT(8) /*!< enable parity error interrupt */
#define USART_CTL0_PM BIT(9) /*!< parity mode */
#define USART_CTL0_PCEN BIT(10) /*!< enable parity control */
#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
#define USART_CTL0_WL0 BIT(12) /*!< word length 0 */
#define USART_CTL0_MEN BIT(13) /*!< enable mute mode */
#define USART_CTL0_AMIE0 BIT(14) /*!< enable address 0 character match interrupt */
#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */
#define USART_CTL0_DED BITS(16,20) /*!< enable driver deassertion time */
#define USART_CTL0_DEA BITS(21,25) /*!< enable driver assertion time */
#define USART_CTL0_RTIE BIT(26) /*!< enable receiver timeout interrupt */
#define USART_CTL0_EBIE BIT(27) /*!< enable end of block interrupt */
#define USART_CTL0_WL1 BIT(28) /*!< word length 1 */
#define USART_CTL0_AMIE1 BIT(31) /*!< enable address 1 character match interrupt */
/* USARTx_CTL1 */
#define USART_CTL1_AMEN0 BIT(0) /*!< enable address 0 match mode */
#define USART_CTL1_ADDM0 BIT(4) /*!< address 0 detection mode */
#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
#define USART_CTL1_LBDIE BIT(6) /*!< enable LIN break detection interrupt */
#define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */
#define USART_CTL1_CPH BIT(9) /*!< clock phase */
#define USART_CTL1_CPL BIT(10) /*!< clock polarity */
#define USART_CTL1_CKEN BIT(11) /*!< enable ck pin */
#define USART_CTL1_STB BITS(12,13) /*!< stop bits length */
#define USART_CTL1_LMEN BIT(14) /*!< enable LIN mode */
#define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */
#define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */
#define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */
#define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */
#define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */
#define USART_CTL1_RTEN BIT(23) /*!< enable receiver timeout */
#define USART_CTL1_ADDR0 BITS(24,31) /*!< address 0 of the USART terminal */
/* USARTx_CTL2 */
#define USART_CTL2_ERRIE BIT(0) /*!< enable error interrupt in multibuffer communication */
#define USART_CTL2_IREN BIT(1) /*!< enable IrDA mode */
#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
#define USART_CTL2_HDEN BIT(3) /*!< enable half-duplex */
#define USART_CTL2_NKEN BIT(4) /*!< enable NACK in smartcard mode */
#define USART_CTL2_SCEN BIT(5) /*!< enable smartcard mode */
#define USART_CTL2_DENR BIT(6) /*!< enable DMA for reception */
#define USART_CTL2_DENT BIT(7) /*!< enable DMA for transmission */
#define USART_CTL2_RTSEN BIT(8) /*!< enable RTS */
#define USART_CTL2_CTSEN BIT(9) /*!< enable CTS */
#define USART_CTL2_CTSIE BIT(10) /*!< enable CTS interrupt */
#define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */
#define USART_CTL2_OVRD BIT(12) /*!< disable overrun */
#define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */
#define USART_CTL2_DEM BIT(14) /*!< enable driver mode */
#define USART_CTL2_DEP BIT(15) /*!< enable driver polarity mode */
#define USART_CTL2_AMEN1 BIT(16) /*!< enable address 1 match mode */
#define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */
#define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */
#define USART_CTL2_WUIE BIT(22) /*!< enable wakeup from deep-sleep mode interrupt */
#define USART_CTL2_ADDM1 BIT(23) /*!< address 1 detection mode */
#define USART_CTL2_ADDR1 BITS(24,31) /*!< address 1 of the USART terminal */
/* USARTx_BAUD */
#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */
#define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */
/* USARTx_GP */
#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */
#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
/* USARTx_RT */
#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */
#define USART_RT_BL BITS(24,31) /*!< block length */
/* USARTx_CMD */
#define USART_CMD_SBKCMD BIT(1) /*!< send break command */
#define USART_CMD_MMCMD BIT(2) /*!< mute mode command */
#define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */
#define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */
/* USARTx_STAT */
#define USART_STAT_PERR BIT(0) /*!< parity error flag */
#define USART_STAT_FERR BIT(1) /*!< frame error flag */
#define USART_STAT_NERR BIT(2) /*!< noise error flag */
#define USART_STAT_ORERR BIT(3) /*!< overrun error */
#define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */
#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty(when FIFO is disabled) */
#define USART_STAT_RFNE BIT(5) /*!< receive FIFO not empty(when FIFO is enabled) */
#define USART_STAT_TC BIT(6) /*!< transmission completed */
#define USART_STAT_TBE BIT(7) /*!< transmit data register empty(when FIFO is disabled) */
#define USART_STAT_TFNF BIT(7) /*!< transmit FIFO not full(when FIFO is enabled) */
#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */
#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */
#define USART_STAT_CTS BIT(10) /*!< CTS level */
#define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */
#define USART_STAT_EBF BIT(12) /*!< end of block flag */
#define USART_STAT_AMF1 BIT(13) /*!< address 1 character match flag */
#define USART_STAT_BSY BIT(16) /*!< busy flag */
#define USART_STAT_AMF0 BIT(17) /*!< address 0 character match flag */
#define USART_STAT_SBF BIT(18) /*!< send break flag */
#define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */
#define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */
#define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */
#define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */
/* USARTx_INTC */
#define USART_INTC_PEC BIT(0) /*!< clear parity error */
#define USART_INTC_FEC BIT(1) /*!< clear frame error flag */
#define USART_INTC_NEC BIT(2) /*!< clear noise detected */
#define USART_INTC_OREC BIT(3) /*!< clear overrun error */
#define USART_INTC_IDLEC BIT(4) /*!< clear idle line detected */
#define USART_INTC_TCC BIT(6) /*!< clear transmission complete */
#define USART_INTC_LBDC BIT(8) /*!< clear LIN break detected */
#define USART_INTC_CTSC BIT(9) /*!< clear CTS change */
#define USART_INTC_RTC BIT(11) /*!< clear receiver timeout */
#define USART_INTC_EBC BIT(12) /*!< clear end of timeout */
#define USART_INTC_AMC1 BIT(16) /*!< clear address 1 character match */
#define USART_INTC_AMC0 BIT(17) /*!< clear address 0 character match */
#define USART_INTC_WUC BIT(20) /*!< clear wakeup from deep-sleep mode */
/* USARTx_RDATA */
#define USART_RDATA_RDATA BITS(0,9) /*!< receive data value */
/* USARTx_TDATA */
#define USART_TDATA_TDATA BITS(0,9) /*!< transmit data value */
/* USARTx_CHC */
#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */
#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */
/* USARTx_FCS */
#define USART_FCS_ELNACK BIT(0) /*!< early NACK when smartcard mode is selected */
#define USART_FCS_RFCNT3_4 BITS(1,2) /*!< receive FIFO counter number RFCNT[4:3] */
#define USART_FCS_RFT BIT(4) /*!< receive FIFO threshold flag */
#define USART_FCS_TFT BIT(5) /*!< transmit FIFO threshold flag */
#define USART_FCS_TFE BIT(6) /*!< transmit FIFO empty flag */
#define USART_FCS_TFF BIT(7) /*!< transmit FIFO full flag */
#define USART_FCS_FEN BIT(8) /*!< enable FIFO */
#define USART_FCS_RFFIE BIT(9) /*!< enable receive FIFO full interrupt */
#define USART_FCS_RFE BIT(10) /*!< receive FIFO empty flag */
#define USART_FCS_RFF BIT(11) /*!< receive FIFO full flag */
#define USART_FCS_RFCNT0_2 BITS(12,14) /*!< receive FIFO counter number RFCNT[2:0] */
#define USART_FCS_RFFIF BIT(15) /*!< receive FIFO full interrupt flag */
#define USART_FCS_RFTCFG BITS(16,18) /*!< receive FIFO threshold configuration */
#define USART_FCS_TFTCFG BITS(19,21) /*!< transmit FIFO threshold configuration */
#define USART_FCS_RFTIF BIT(22) /*!< receive FIFO threshold interrupt flag */
#define USART_FCS_TFEIF BIT(24) /*!< transmit FIFO empty interrupt flag */
#define USART_FCS_TFTIF BIT(25) /*!< transmit FIFO threshold interrupt flag */
#define USART_FCS_TFEC BIT(26) /*!< clear transmit FIFO empty flag */
#define USART_FCS_RFTIE BIT(27) /*!< enable receive FIFO threshold interrupt */
#define USART_FCS_TFTIE BIT(29) /*!< enable transmit FIFO threshold interrupt */
#define USART_FCS_TFEIE BIT(31) /*!< enable transmit FIFO empty interrupt */
/* constants definitions */
/* define the USART bit position and its register index offset */
#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
#define USART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
/* register offset */
#define USART_CTL0_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */
#define USART_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */
#define USART_CTL2_REG_OFFSET ((uint32_t)0x00000008U) /*!< CTL2 register offset */
#define USART_STAT_REG_OFFSET ((uint32_t)0x0000001CU) /*!< STAT register offset */
#define USART_CHC_REG_OFFSET ((uint32_t)0x000000C0U) /*!< CHC register offset */
#define USART_FCS_REG_OFFSET ((uint32_t)0x000000D0U) /*!< FCS register offset */
/* USART flags */
typedef enum{
/* flags in STAT register */
USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */
USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */
USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from Deep-sleep mode flag */
USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */
USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */
USART_FLAG_AM0 = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR0 match flag */
USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */
USART_FLAG_AM1 = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 13U), /*!< ADDR1 match flag */
USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */
USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */
USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */
USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */
USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */
USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty(when FIFO is disabled) */
USART_FLAG_TFNF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit FIFO not full(when FIFO is enabled) */
USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */
USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty(when FIFO is disabled) */
USART_FLAG_RFNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< receive FIFO not empty(when FIFO is enabled) */
USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */
USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */
USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */
USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */
USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */
/* flags in CHC register */
USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */
/* flags in FCS register */
USART_FLAG_RFF = USART_REGIDX_BIT(USART_FCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */
USART_FLAG_RFE = USART_REGIDX_BIT(USART_FCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */
USART_FLAG_TFF = USART_REGIDX_BIT(USART_FCS_REG_OFFSET, 7U), /*!< transmit FIFO full flag */
USART_FLAG_TFE = USART_REGIDX_BIT(USART_FCS_REG_OFFSET, 6U), /*!< transmit FIFO empty flag */
USART_FLAG_TFT = USART_REGIDX_BIT(USART_FCS_REG_OFFSET, 5U), /*!< transmit FIFO threshold reach flag */
USART_FLAG_RFT = USART_REGIDX_BIT(USART_FCS_REG_OFFSET, 4U) /*!< receive FIFO threshold reach flag */
}usart_flag_enum;
/* USART interrupt flags */
typedef enum
{
/* interrupt flags in CTL0 register */
USART_INT_FLAG_AM1 = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 31U, USART_STAT_REG_OFFSET, 13U), /*!< address 1 match interrupt and flag */
USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt and flag */
USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt and flag */
USART_INT_FLAG_AM0 = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address 0 match interrupt and flag */
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag(when FIFO is disabled) */
USART_INT_FLAG_TFNF = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmit FIFO not full interrupt and flag(when FIFO is enabled) */
USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */
USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag(when FIFO is disabled) */
USART_INT_FLAG_RFNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< receive FIFO not empty interrupt and flag(when FIFO is enabled) */
USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag(when FIFO is disabled) */
USART_INT_FLAG_RFNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< receive FIFO not empty interrupt and overrun error flag(when FIFO is enabled) */
USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */
/* interrupt flags in CTL1 register */
USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */
/* interrupt flags in CTL2 register */
USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt and flag */
USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */
USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */
USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */
USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */
/* interrupt flags in FCS register */
USART_INT_FLAG_TFT = USART_REGIDX_BIT2(USART_FCS_REG_OFFSET, 29U, USART_FCS_REG_OFFSET, 25U), /*!< transmit FIFO threshold reach interrupt and flag */
USART_INT_FLAG_TFE = USART_REGIDX_BIT2(USART_FCS_REG_OFFSET, 31U, USART_FCS_REG_OFFSET, 24U), /*!< transmit FIFO empty interrupt and flag */
USART_INT_FLAG_RFT = USART_REGIDX_BIT2(USART_FCS_REG_OFFSET, 27U, USART_FCS_REG_OFFSET, 22U), /*!< receive FIFO threshold reach interrupt and flag */
USART_INT_FLAG_RFF = USART_REGIDX_BIT2(USART_FCS_REG_OFFSET, 9U, USART_FCS_REG_OFFSET, 15U) /*!< receive FIFO full interrupt and flag */
}usart_interrupt_flag_enum;
/* enable or disable USART interrupt */
typedef enum
{
/* interrupt in CTL0 register */
USART_INT_AM1 = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 31U), /*!< address 1 match interrupt */
USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */
USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */
USART_INT_AM0 = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address 0 match interrupt */
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt(when FIFO is disabled) */
USART_INT_TFNF = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmit FIFO not full interrupt(when FIFO is enabled) */
USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */
USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt(when FIFO is disabled) */
USART_INT_RFNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< receive FIFO not empty interrupt and overrun error interrupt(when FIFO is enabled) */
USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */
/* interrupt in CTL1 register */
USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */
/* interrupt in CTL2 register */
USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */
USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */
USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */
/* interrupt in FCS register */
USART_INT_TFE = USART_REGIDX_BIT(USART_FCS_REG_OFFSET, 31U), /*!< transmit FIFO empty interrupt */
USART_INT_TFT = USART_REGIDX_BIT(USART_FCS_REG_OFFSET, 29U), /*!< transmit FIFO threshold interrupt */
USART_INT_RFT = USART_REGIDX_BIT(USART_FCS_REG_OFFSET, 27U), /*!< receive FIFO threshold interrupt */
USART_INT_RFF = USART_REGIDX_BIT(USART_FCS_REG_OFFSET, 9U) /*!< receive FIFO full interrupt */
}usart_interrupt_enum;
/* configure USART invert */
typedef enum {
/* data bit level inversion */
USART_DINV_ENABLE, /*!< data bit level inversion */
USART_DINV_DISABLE, /*!< data bit level not inversion */
/* TX pin level inversion */
USART_TXPIN_ENABLE, /*!< TX pin level inversion */
USART_TXPIN_DISABLE, /*!< TX pin level not inversion */
/* RX pin level inversion */
USART_RXPIN_ENABLE, /*!< RX pin level inversion */
USART_RXPIN_DISABLE, /*!< RX pin level not inversion */
/* swap TX/RX pins */
USART_SWAP_ENABLE, /*!< swap TX/RX pins */
USART_SWAP_DISABLE /*!< not swap TX/RX pins */
}usart_invert_enum;
/* configure USART receiver */
#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
/* configure USART transmitter */
#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
/* USART parity bits definitions */
#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
#define USART_PM_NONE CTL0_PM(0) /*!< no parity */
#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */
#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */
/* USART wakeup method in mute mode */
#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */
#define USART_WM_ADDR CTL0_WM(1) /*!< address match */
/* USART word length definitions */
#define CTL0_WL(regval1, regval2) ((BIT(28) & ((uint32_t)(regval1) << 28)) | (BIT(12) & ((uint32_t)(regval2) << 12)))
#define USART_WL_8BIT CTL0_WL(0, 0) /*!< 8 bits */
#define USART_WL_9BIT CTL0_WL(0, 1) /*!< 9 bits */
#define USART_WL_7BIT CTL0_WL(1, 0) /*!< 7 bits */
#define USART_WL_10BIT CTL0_WL(1, 1) /*!< 10 bits */
/* USART oversample mode */
#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15))
#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */
#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */
/* USART LIN break frame length */
#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */
#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */
/* USART last bit clock pulse */
#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
#define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */
#define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */
/* USART clock phase */
#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */
#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */
/* USART clock polarity */
#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
/* USART stop bits definitions */
#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */
#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */
#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */
#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */
/* USART data is transmitted/received with the LSB/MSB first */
#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19))
#define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */
#define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */
/* enable USART IrDA low-power */
#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
/* USART DMA request for receive configure */
#define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
#define USART_RECEIVE_DMA_ENABLE CTL2_DENR(1) /*!< DMA request enable for reception */
#define USART_RECEIVE_DMA_DISABLE CTL2_DENR(0) /*!< DMA request disable for reception */
/* USART DMA request for transmission configure */
#define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
#define USART_TRANSMIT_DMA_ENABLE CTL2_DENT(1) /*!< DMA request enable for transmission */
#define USART_TRANSMIT_DMA_DISABLE CTL2_DENT(0) /*!< DMA request disable for transmission */
/* configure USART RTS hardware flow control */
#define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
#define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< RTS hardware flow control enabled */
#define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< RTS hardware flow control disabled */
/* configure USART CTS hardware flow control */
#define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
#define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< CTS hardware flow control enabled */
#define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< CTS hardware flow control disabled */
/* configure USART one sample bit method */
#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11))
#define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */
#define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */
/* USART driver enable polarity mode */
#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15))
#define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */
#define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */
/* USART wakeup mode from deep-sleep mode */
#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
#define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */
#define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */
#define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */
/* USART address 0 detection mode */
#define CTL1_ADDM0(regval) (BIT(4) & ((uint32_t)(regval) << 4))
#define USART_ADDM0_4BIT CTL1_ADDM0(0) /*!< 4-bit address detection */
#define USART_ADDM0_FULLBIT CTL1_ADDM0(1) /*!< full-bit address detection */
/* USART address 1 detection mode */
#define CTL2_ADDM1(regval) (BIT(23) & ((uint32_t)(regval) << 23))
#define USART_ADDM1_4BIT CTL2_ADDM1(0) /*!< 4-bit address detection */
#define USART_ADDM1_FULLBIT CTL2_ADDM1(1) /*!< full-bit address detection */
/* USART hardware flow control coherence mode */
#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0))
#define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */
#define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */
/* configure USART transmit FIFO threshold */
#define FCS_TFTCFG(regval) (BITS(19,21) & ((uint32_t)(regval) << 19))
#define USART_TFTCFG_THRESHOLD_1_8 FCS_TFTCFG(0) /*!< transmit FIFO reaches 1/8 of its depth */
#define USART_TFTCFG_THRESHOLD_1_4 FCS_TFTCFG(1) /*!< transmit FIFO reaches 1/4 of its depth */
#define USART_TFTCFG_THRESHOLD_1_2 FCS_TFTCFG(2) /*!< transmit FIFO reaches 1/2 of its depth */
#define USART_TFTCFG_THRESHOLD_3_4 FCS_TFTCFG(3) /*!< transmit FIFO reaches 3/4 of its depth */
#define USART_TFTCFG_THRESHOLD_7_8 FCS_TFTCFG(4) /*!< transmit FIFO reaches 7/8 of its depth */
#define USART_TFTCFG_THRESHOLD_EMPTY FCS_TFTCFG(5) /*!< transmit FIFO becomes empty */
/* configure USART receive FIFO threshold */
#define FCS_RFTCFG(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
#define USART_RFTCFG_THRESHOLD_1_8 FCS_RFTCFG(0) /*!< receive FIFO reaches 1/8 of its depth */
#define USART_RFTCFG_THRESHOLD_1_4 FCS_RFTCFG(1) /*!< receive FIFO reaches 1/4 of its depth */
#define USART_RFTCFG_THRESHOLD_1_2 FCS_RFTCFG(2) /*!< receive FIFO reaches 1/2 of its depth */
#define USART_RFTCFG_THRESHOLD_3_4 FCS_RFTCFG(3) /*!< receive FIFO reaches 3/4 of its depth */
#define USART_RFTCFG_THRESHOLD_7_8 FCS_RFTCFG(4) /*!< receive FIFO reaches 7/8 of its depth */
#define USART_RFTCFG_THRESHOLD_FULL FCS_RFTCFG(5) /*!< receive FIFO becomes full */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check USART/UART peripheral */
#define NOT_USART_PERIPH(periph) (((periph) != USART0) && ((periph) != USART1) && \
((periph) != USART2) && ((periph) != UART3) && \
((periph) != UART4) && ((periph) != USART5) && \
((periph) != UART6) && ((periph) != UART7))
/* check USART peripheral */
#define NOT_USART0125_PERIPH(periph) (((periph) != USART0) && ((periph) != USART1) && \
((periph) != USART2) && ((periph) != USART5))
/* check if the baudrate is not a USART baudrate */
#define NOT_USART_BAUDRATE(baudval) ((baudval) == 0U)
/* check if the parity mode is not a USART parity mode */
#define NOT_USART_PM(parity) (((parity) != USART_PM_NONE) && ((parity) != USART_PM_EVEN) && \
((parity) != USART_PM_ODD))
/* check if the word length is not a USART word length */
#define NOT_USART_WL(wlen) (((wlen) != USART_WL_8BIT) && ((wlen) != USART_WL_9BIT) && \
((wlen) != USART_WL_7BIT) && ((wlen) != USART_WL_10BIT))
/* check if the stop bit length is not a USART stop bit length */
#define NOT_USART_STB(stblen) (((stblen) != USART_STB_1BIT) && ((stblen) != USART_STB_0_5BIT) && \
((stblen) != USART_STB_2BIT) && ((stblen) != USART_STB_1_5BIT))
/* check if the transmit configuration is not a USART transmit configuration */
#define NOT_USART_TRANSMIT(txconfig) (((txconfig) != USART_TRANSMIT_ENABLE) && ((txconfig) != USART_TRANSMIT_DISABLE))
/* check if the receive configuration is not a USART receive configuration */
#define NOT_USART_RECEIVE(rxconfig) (((rxconfig) != USART_RECEIVE_ENABLE) && ((rxconfig) != USART_RECEIVE_DISABLE))
/* check if the MSB/LSB first configuration is not a USART configuration */
#define NOT_USART_MSBF(msbf) (((msbf) != USART_MSBF_LSB) && ((msbf) != USART_MSBF_MSB))
/* check if the oversampling mode is not a USART oversampling mode */
#define NOT_USART_OVSMOD(oversamp) (((oversamp) != USART_OVSMOD_8) && ((oversamp) != USART_OVSMOD_16))
/* check if the oversampling bit configuration is not a USART configuration */
#define NOT_USART_OSB(osb) (((osb) != USART_OSB_1BIT) && ((osb) != USART_OSB_3BIT))
/* check if the receive timeout is not within the USART receive timeout range */
#define USART_RECEIVE_TIMEOUT_HIGH ((uint32_t)0x00FFFFFFU)
#define NOT_USART_RECEIVE_TIMEOUT(rtimeout) (USART_RECEIVE_TIMEOUT_HIGH < (rtimeout))
/* check if the transmit data is not within the USART transmit data range */
#define USART_TRANSMIT_DATA_HIGH ((uint32_t)0x000003FFU)
#define NOT_USART_TRANSMIT_DATA(data) (USART_TRANSMIT_DATA_HIGH < (data))
/* check if the command type is not a USART command type */
#define NOT_USART_CMD(cmdtype) (((cmdtype) != USART_CMD_SBKCMD) && ((cmdtype) != USART_CMD_MMCMD) && \
((cmdtype) != USART_CMD_RXFCMD) && ((cmdtype) != USART_CMD_TXFCMD))
/* check if the address mode is not a USART address mode */
#define NOT_USART_ADDR_MODE(addrmod) (((addrmod) != USART_ADDM0_4BIT) && ((addrmod) != USART_ADDM0_FULLBIT))
/* check if the wakeup mode is not a USART wakeup mode */
#define NOT_USART_WM_METHOD(wmethod) (((wmethod) != USART_WM_IDLE) && ((wmethod) != USART_WM_ADDR))
/* check if the LIN break length is not a USART LIN break length */
#define NOT_USART_LBLEN_LENGTH(lblen) (((lblen) != USART_LBLEN_10B) && ((lblen) != USART_LBLEN_11B))
/* check if the clock length mode is not a USART clock length mode */
#define NOT_USART_CLEN_MODE(clen) (((clen) != USART_CLEN_NONE) && ((clen) != USART_CLEN_EN))
/* check if the clock phase mode is not a USART clock phase mode */
#define NOT_USART_CPH_MODE(cph) (((cph) != USART_CPH_1CK) && ((cph) != USART_CPH_2CK))
/* check if the clock polarity mode is not a USART clock polarity mode */
#define NOT_USART_CPL_MODE(cpl) (((cpl) != USART_CPL_LOW) && ((cpl) != USART_CPL_HIGH))
/* check if the guard time is not within the USART guard time range */
#define USART_GUARD_TIME_HIGH ((uint32_t)0x000000FFU)
#define NOT_USART_GUARD_TIME_RANGE(guat) (USART_GUARD_TIME_HIGH < (guat))
/* check if the smartcard auto-retry number is not within the USART smartcard auto-retry range */
#define USART_SMARTCARD_AUTORETRY_HIGH ((uint32_t)0x00000007U)
#define NOT_USART_SMARTCARD_AUTORETRY_RANGE(scrtnum) (USART_SMARTCARD_AUTORETRY_HIGH < (scrtnum))
/* check if the block length is not within the USART block length range */
#define USART_BLOCK_LEN_HIGH ((uint32_t)0x000000FFU)
#define NOT_USART_BLOCK_LEN_RANGE(bl) (USART_BLOCK_LEN_HIGH < (bl))
/* check if the IrDA smart pre-scaler is not within the USART IrDA smart pre-scaler range */
#define USART_IRDA_SMART_PRE_HIGH ((uint32_t)0x000000FFU)
#define NOT_USART_IRDA_SMART_PRE_RANGE(psc) (USART_IRDA_SMART_PRE_HIGH < (psc))
/* check if the IrDA mode is not a USART IrDA mode */
#define NOT_USART_IRDA_MODE(irlp) (((irlp) != USART_IRLP_LOW) && ((irlp) != USART_IRLP_NORMAL))
/* check if the RTS configuration is not a USART RTS configuration */
#define NOT_USART_RTS_CONFIG(rtsconfig) (((rtsconfig) != USART_RTS_ENABLE) && ((rtsconfig) != USART_RTS_DISABLE))
/* check if the CTS configuration is not a USART CTS configuration */
#define NOT_USART_CTS_CONFIG(ctsconfig) (((ctsconfig) != USART_CTS_ENABLE) && ((ctsconfig) != USART_CTS_DISABLE))
/* check if the hardware flow control mode is not a USART hardware flow control mode */
#define NOT_USART_HCM_CONFIG(hcm) (((hcm) != USART_HCM_NONE) && ((hcm) != USART_HCM_EN))
/* check if the asser time is not within the USART DE time range */
#define USART_ASSERTIME_HIGH ((uint32_t)0x0000001FU)
#define NOT_USART_ASSERTIME_RANGE(dedtime) (USART_ASSERTIME_HIGH < (dedtime))
/* check if the DE time is not within the USART DE time range */
#define USART_DE_ASSERTIME_HIGH ((uint32_t)0x0000001FU)
#define NOT_USART_DE_ASSERTIME_RANGE(dedtime) (USART_DE_ASSERTIME_HIGH < (dedtime))
/* check if the DE signal configuration is not a USART DE polarity configuration */
#define NOT_USART_DEP_CONFIG(dep) (((dep) != USART_DEP_HIGH) && ((dep) != USART_DEP_LOW))
/* check if the receive DMA configuration is not a USART receive DMA configuration */
#define NOT_USART_RECEIVE_DMA_CONFIG(dmacmd) (((dmacmd) != USART_RECEIVE_DMA_ENABLE) && ((dmacmd) != USART_RECEIVE_DMA_DISABLE))
/* check if the transmit DMA configuration is not a USART transmit DMA configuration */
#define NOT_USART_TRANSMIT_DMA_CONFIG(dmacmd) (((dmacmd) != USART_TRANSMIT_DMA_ENABLE) && ((dmacmd) != USART_TRANSMIT_DMA_DISABLE))
/* check the wakeup mode configuration */
#define NOT_USART_WAKEUP_MODE_CONFIG(wum) (((wum) != USART_WUM_ADDR) && ((wum) != USART_WUM_STARTB) && ((wum) != USART_WUM_RBNE))
/* check if the TX FIFO threshold configuration is not a USART TX FIFO threshold configuration */
#define NOT_USART_TFTCFG_THRESHOLD_CONFIG(txthreshold) (((txthreshold) != USART_TFTCFG_THRESHOLD_1_8) && ((txthreshold) != USART_TFTCFG_THRESHOLD_1_4) && \
((txthreshold) != USART_TFTCFG_THRESHOLD_1_2) && ((txthreshold) != USART_TFTCFG_THRESHOLD_3_4) && \
((txthreshold) != USART_TFTCFG_THRESHOLD_7_8) && ((txthreshold) != USART_TFTCFG_THRESHOLD_EMPTY))
/* check if the RX FIFO threshold configuration is not a USART RX FIFO threshold configuration */
#define NOT_USART_RFTCFG_THRESHOLD_CONFIG(rxthreshold) (((rxthreshold) != USART_RFTCFG_THRESHOLD_1_8) && ((rxthreshold) != USART_RFTCFG_THRESHOLD_1_4) && \
((rxthreshold) != USART_RFTCFG_THRESHOLD_1_2) && ((rxthreshold) != USART_RFTCFG_THRESHOLD_3_4) && \
((rxthreshold) != USART_RFTCFG_THRESHOLD_7_8) && ((rxthreshold) != USART_RFTCFG_THRESHOLD_FULL))
#endif
/* function declarations */
/* initialization functions */
/* reset USART */
void usart_deinit(uint32_t usart_periph);
/* configure USART baud rate value */
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
/* configure USART parity function */
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
/* configure USART word length */
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
/* configure USART stop bit length */
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
/* enable USART */
void usart_enable(uint32_t usart_periph);
/* disable USART */
void usart_disable(uint32_t usart_periph);
/* configure USART transmitter */
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
/* configure USART receiver */
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
/* USART normal mode communication */
/* data is transmitted/received with the LSB/MSB first */
void usart_data_first_config(uint32_t usart_periph, uint32_t msbf);
/* USART inverted configure */
void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara);
/* enable the USART overrun function */
void usart_overrun_enable(uint32_t usart_periph);
/* disable the USART overrun function */
void usart_overrun_disable(uint32_t usart_periph);
/* configure the USART oversample mode */
void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp);
/* configure sample bit method */
void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb);
/* enable receiver timeout */
void usart_receiver_timeout_enable(uint32_t usart_periph);
/* disable receiver timeout */
void usart_receiver_timeout_disable(uint32_t usart_periph);
/* configure receiver timeout threshold */
void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout);
/* USART transmit data function */
void usart_data_transmit(uint32_t usart_periph, uint16_t data);
/* USART receive data function */
uint16_t usart_data_receive(uint32_t usart_periph);
/* enable USART command */
void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype);
/* multi-processor communication */
/* enable address 0 match mode */
void usart_address_0_match_mode_enable(uint32_t usart_periph);
/* disable address 0 match mode */
void usart_address_0_match_mode_disable(uint32_t usart_periph);
/* enable address 1 match mode */
void usart_address_1_match_mode_enable(uint32_t usart_periph);
/* disable address 1 match mode */
void usart_address_1_match_mode_disable(uint32_t usart_periph);
/* configure address 0 of the USART */
void usart_address_0_config(uint32_t usart_periph, uint8_t addr);
/* configure address 1 of the USART */
void usart_address_1_config(uint32_t usart_periph, uint8_t addr);
/* configure address 0 detection mode */
void usart_address_0_detection_mode_config(uint32_t usart_periph, uint32_t addmod);
/* configure address 1 detection mode */
void usart_address_1_detection_mode_config(uint32_t usart_periph, uint32_t addmod);
/* enable mute mode */
void usart_mute_mode_enable(uint32_t usart_periph);
/* disable mute mode */
void usart_mute_mode_disable(uint32_t usart_periph);
/* configure wakeup method in mute mode */
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
/* LIN mode communication */
/* enable LIN mode */
void usart_lin_mode_enable(uint32_t usart_periph);
/* disable LIN mode */
void usart_lin_mode_disable(uint32_t usart_periph);
/* LIN break detection length */
void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
/* half-duplex communication */
/* enable half-duplex mode */
void usart_halfduplex_enable(uint32_t usart_periph);
/* disable half-duplex mode */
void usart_halfduplex_disable(uint32_t usart_periph);
/* synchronous communication */
/* enable clock */
void usart_clock_enable(uint32_t usart_periph);
/* disable clock */
void usart_clock_disable(uint32_t usart_periph);
/* configure USART synchronous mode parameters */
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
/* smartcard communication */
/* configure guard time value in smartcard mode */
void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
/* enable smartcard mode */
void usart_smartcard_mode_enable(uint32_t usart_periph);
/* disable smartcard mode */
void usart_smartcard_mode_disable(uint32_t usart_periph);
/* enable NACK in smartcard mode */
void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
/* disable NACK in smartcard mode */
void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
/* enable early NACK in smartcard mode */
void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph);
/* disable early NACK in smartcard mode */
void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph);
/* configure smartcard auto-retry number */
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum);
/* configure block length */
void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
/* IrDA communication */
/* enable IrDA mode */
void usart_irda_mode_enable(uint32_t usart_periph);
/* disable IrDA mode */
void usart_irda_mode_disable(uint32_t usart_periph);
/* configure the peripheral clock prescaler in USART IrDA low-power or SmartCard mode */
void usart_prescaler_config(uint32_t usart_periph, uint32_t psc);
/* configure IrDA low-power */
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
/* hardware flow communication */
/* configure hardware flow control RTS */
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
/* configure hardware flow control CTS */
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
/* coherence control */
/* configure hardware flow control coherence mode */
void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm);
/* enable RS485 driver */
void usart_rs485_driver_enable(uint32_t usart_periph);
/* disable RS485 driver */
void usart_rs485_driver_disable(uint32_t usart_periph);
/* configure driver enable assertion time */
void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime);
/* configure driver enable de-assertion time */
void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime);
/* configure driver enable polarity mode */
void usart_depolarity_config(uint32_t usart_periph, uint32_t dep);
/* USART DMA */
/* configure USART DMA reception */
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
/* configure USART DMA transmission */
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
/* disable DMA on reception error */
void usart_reception_error_dma_disable(uint32_t usart_periph);
/* enable DMA on reception error */
void usart_reception_error_dma_enable(uint32_t usart_periph);
/* enable USART to wakeup the mcu from deep-sleep mode */
void usart_wakeup_enable(uint32_t usart_periph);
/* disable USART to wakeup the mcu from deep-sleep mode */
void usart_wakeup_disable(uint32_t usart_periph);
/* configure the USART wakeup mode from deep-sleep mode */
void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum);
/* USART FIFO */
/* enable FIFO */
void usart_fifo_enable(uint32_t usart_periph);
/* disable FIFO */
void usart_fifo_disable(uint32_t usart_periph);
/* configure transmit FIFO threshold */
void usart_transmit_fifo_threshold_config(uint32_t usart_periph, uint32_t txthreshold);
/* configure receive FIFO threshold */
void usart_receive_fifo_threshold_config(uint32_t usart_periph, uint32_t rxthreshold);
/* read receive FIFO counter number */
uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph);
/* flag & interrupt functions */
/* get flag in STAT/FCS register */
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
/* clear USART status */
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
/* enable USART interrupt */
void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt);
/* disable USART interrupt */
void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt);
/* get USART interrupt and flag status */
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
/* clear USART interrupt flag */
void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
#endif /* GD32H75E_USART_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_vref.h
+103
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/*!
\file gd32h75e_vref.h
\brief definitions for the VREF
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_VREF_H
#define GD32H75E_VREF_H
#include "gd32h75e.h"
/* VREF definitions */
#define VREF VREF_BASE /*!< VREF base address */
/* registers definitions */
#define VREF_CS REG32(VREF + 0x00000000U) /*!< VREF Control and status register */
#define VREF_CALIB REG32(VREF + 0x00000004U) /*!< VREF Calibration register */
/* bits definitions */
/* VREF_CS */
#define VREF_CS_VREFEN BIT(0) /*!< VREF enable */
#define VREF_CS_HIPM BIT(1) /*!< High impedance mode */
#define VREF_CS_VREFRDY BIT(3) /*!< VREF ready */
#define VREF_CS_VREFS BITS(4,5) /*!< VREF voltage reference select */
/* VREF_CALIB */
#define VREF_CALIB_VREFCAL BITS(0,5) /*!< VREF calibration */
/* constants definitions */
/* VREF bit devinitions */
#define VREF_EN VREF_CS_VREFEN /*!< VREF enable */
#define VREF_HIGH_IMPEDANCE_MODE VREF_CS_HIPM /*!< High impedance mode */
#define VREF_RDY VREF_CS_VREFRDY /*!< VREF ready */
/* VREF voltage reference select */
#define CS_VREFS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U))
#define VREF_VOLTAGE_SEL_2_5V CS_VREFS(0) /*!< VREF voltage reference select 2.5 V */
#define VREF_VOLTAGE_SEL_2_048V CS_VREFS(1) /*!< VREF voltage reference select 2.048 V */
#define VREF_VOLTAGE_SEL_1_8V CS_VREFS(2) /*!< VREF voltage reference select 1.8 V */
#define VREF_VOLTAGE_SEL_1_5V CS_VREFS(3) /*!< VREF voltage reference select 1.5 V */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check vref_voltage */
#define NOT_VREF_VOLTAGE(vref_voltage) (((vref_voltage) != VREF_VOLTAGE_SEL_2_5V) && ((vref_voltage) != VREF_VOLTAGE_SEL_2_048V) && \
((vref_voltage) != VREF_VOLTAGE_SEL_1_8V) && ((vref_voltage) != VREF_VOLTAGE_SEL_1_5V))
/* check external decode signals delay */
#define VREF_CALIB_VALUE_HIGH ((uint32_t)0x0000003FU)
#define NOT_VREF_CALIB_VALUE(value) (VREF_CALIB_VALUE_HIGH < (value))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* deinitialize the VREF */
void vref_deinit(void);
/* enable VREF */
void vref_enable(void);
/* disable VREF */
void vref_disable(void);
/* enable VREF high impendance mode */
void vref_high_impedance_mode_enable(void);
/* disable VREF high impendance mode */
void vref_high_impedance_mode_disable(void);
/* get the status of VREF */
FlagStatus vref_status_get(void);
/* select the VREF voltage reference */
void vref_voltage_select(uint32_t vref_voltage);
/* set the calibration value of VREF */
void vref_calib_value_set(uint8_t value);
/* get the calibration value of VREF */
uint8_t vref_calib_value_get(void);
#endif /* GD32H75E_VREF_H */
828ECO/libraries/GD32H75E_standard_peripheral/Include/gd32h75e_wwdgt.h
+97
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@@ -0,0 +1,97 @@
/*!
\file gd32h75e_wwdgt.h
\brief definitions for the WWDGT
\version 2025-08-07, V1.2.0, firmware for GD32H75E
*/
/*
Copyright (c) 2025, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32H75E_WWDGT_H
#define GD32H75E_WWDGT_H
#include "gd32h75e.h"
/* WWDGT definitions */
#define WWDGT WWDGT_BASE
/* registers definitions */
#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */
#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */
#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */
/* bits definitions */
/* WWDGT_CTL */
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
/* WWDGT_CFG */
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */
/* WWDGT_STAT */
#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */
/* constants definitions */
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */
#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK3/4096)/1 */
#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK3/4096)/2 */
#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK3/4096)/4 */
#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK3/4096)/8 */
/* parameter check definitions */
#ifdef FW_DEBUG_ERR_REPORT
/* check WWDGT counter value */
#define NOT_WWDGT_COUNTER_VALUE(value) (((value) > 0x7FU))
/* check WWDGT window value */
#define NOT_WWDGT_WINDOW_VALUE(value) (((value) > 0x7FU))
/* check WWDGT counter prescaler value */
#define NOT_WWDGT_PSC_DIV(prescaler) (((prescaler) != WWDGT_CFG_PSC_DIV1) && ((prescaler) != WWDGT_CFG_PSC_DIV2) && \
((prescaler) != WWDGT_CFG_PSC_DIV4) && ((prescaler) != WWDGT_CFG_PSC_DIV8))
#endif /* FW_DEBUG_ERR_REPORT */
/* function declarations */
/* reset the WWDGT configuration */
void wwdgt_deinit(void);
/* start the WWDGT counter */
void wwdgt_enable(void);
/* configure the WWDGT counter value */
void wwdgt_counter_update(uint16_t counter_value);
/* configure counter value, window value, and prescaler divider value */
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
/* enable early wakeup interrupt of WWDGT */
void wwdgt_interrupt_enable(void);
/* check early wakeup interrupt state of WWDGT */
FlagStatus wwdgt_flag_get(void);
/* clear early wakeup interrupt state of WWDGT */
void wwdgt_flag_clear(void);
#endif /* GD32H75E_WWDGT_H */