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440 lines
12 KiB
440 lines
12 KiB
/*
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* Copyright (c) 2006-2025, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2025-11-07 RealThread the first version
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*/
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#include "drv_usb_hw.h"
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#include "drv_usb_core.h"
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#if defined(BSP_USING_USB)
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/* local function prototypes ('static') */
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static void usb_core_reset(usb_core_regs *usb_regs);
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/*!
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\brief configures USB parameters
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\param[in] udev: pointer to USB core instance
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\param[in] usb_periph: USBHSx(x=0,1)
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\param[in] usb_speed: USB speed type (full-speed or high-speed)
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\param[out] none
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\retval none
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*/
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void usb_para_init(usb_core_driver *udev, uint32_t usb_periph, uint32_t usb_speed)
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{
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usb_core_basic *usb_basic = &udev->bp;
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/* configure USB default transfer mode as FIFO mode */
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usb_basic->transfer_mode = (uint8_t)USB_USE_FIFO;
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/* USB default speed is full-speed */
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usb_basic->core_speed = (uint8_t)USB_SPEED_FULL;
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/* USB basic register address setting */
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switch (usb_periph)
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{
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case USBHS0:
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usb_basic->base_reg = (uint32_t)USBHS0_REG_BASE;
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break;
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case USBHS1:
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usb_basic->base_reg = (uint32_t)USBHS1_REG_BASE;
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break;
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default:
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break;
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}
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/* set the host channel numbers */
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usb_basic->num_pipe = USBHS_MAX_CHANNEL_COUNT;
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/* set the device endpoint numbers */
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usb_basic->num_ep = USBHS_MAX_EP_COUNT;
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if (USB_SPEED_HIGH == usb_speed)
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{
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#ifdef USB_EXTERNAL_ULPI_PHY_ENABLED
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usb_basic->phy_itf = USB_ULPI_PHY_EXTERNAL;
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#endif /* USB_EXTERNAL_ULPI_PHY_ENABLED */
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#ifdef USB_EMBEDDED_HS_PHY_ENABLED
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usb_basic->phy_itf = USB_EMBEDDED_PHY_HS;
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#endif /* USB_EMBEDDED_HS_PHY_ENABLED */
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}
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else if (USB_SPEED_FULL == usb_speed)
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{
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#ifdef USB_EMBEDDED_FS_PHY_ENABLED
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usb_basic->phy_itf = USB_EMBEDDED_PHY_FS;
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#endif /* USB_EMBEDDED_FS_PHY_ENABLED */
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}
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else
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{
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/* no operation */
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}
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#ifdef USB_INTERNAL_DMA_ENABLED
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usb_basic->transfer_mode = USB_USE_DMA;
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#endif /* USB_INTERNAL_DMA_ENABLED */
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usb_basic->sof_enable = (uint8_t)USB_SOF_OUTPUT;
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usb_basic->low_power = (uint8_t)USB_LOW_POWER;
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#if (1U == LPM_ENABLED)
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usb_basic->lpm_enable = 1U;
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#endif /* LPM_ENABLED */
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}
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/*!
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\brief configure USB core basic
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\param[in] usb_basic: pointer to USB capabilities
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\param[in] usb_regs: pointer to USB core registers
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\param[out] none
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\retval operation status
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*/
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usb_status usb_basic_init(usb_core_basic *usb_basic, usb_core_regs *usb_regs)
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{
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/* assign main registers address */
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*usb_regs = (usb_core_regs){
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.gr = (usb_gr *)(usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_CORE),
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.hr = (usb_hr *)(usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_HOST),
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.dr = (usb_dr *)(usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_DEV),
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.HPCS = (uint32_t *)(usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_PORT),
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.PWRCLKCTL = (uint32_t *)(usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_PWRCLKCTL)
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};
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/* assign device endpoint registers address */
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for (uint8_t i = 0U; i < usb_basic->num_ep; i++)
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{
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usb_regs->er_in[i] = (usb_erin *)(usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_EP_IN + (i * (uint32_t)USB_REG_OFFSET_EP));
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usb_regs->er_out[i] = (usb_erout *)(usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_EP_OUT + (i * (uint32_t)USB_REG_OFFSET_EP));
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}
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/* assign host pipe registers address */
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for (uint8_t i = 0U; i < usb_basic->num_pipe; i++)
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{
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usb_regs->pr[i] = (usb_pr *)(usb_basic->base_reg + (uint32_t)USB_REG_OFFSET_CH_INOUT + (i * (uint32_t)USB_REG_OFFSET_CH));
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usb_regs->DFIFO[i] = (uint32_t *)(usb_basic->base_reg + (uint32_t)USB_DATA_FIFO_OFFSET + (i * (uint32_t)USB_DATA_FIFO_SIZE));
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}
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return USB_OK;
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}
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/*!
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\brief initializes the USB controller registers and
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prepares the core device mode or host mode operation
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\param[in] usb_basic: pointer to USB capabilities
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\param[in] usb_regs: pointer to USB core registers
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\param[out] none
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\retval operation status
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*/
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usb_status usb_core_init(usb_core_basic usb_basic, usb_core_regs *usb_regs)
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{
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if (USB_ULPI_PHY_EXTERNAL == usb_basic.phy_itf)
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{
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usb_regs->gr->GCCFG &= ~GCCFG_PWRON;
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usb_regs->gr->GUSBCS &= ~(GUSBCS_EMBPHY_HS | GUSBCS_EMBPHY_FS);
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if (usb_basic.sof_enable)
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{
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usb_regs->gr->GCCFG |= GCCFG_SOFOEN;
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}
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/* initialize the ULPI interface */
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usb_regs->gr->GUSBCS &= ~GUSBCS_ULPIEOI;
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#ifdef USBHS_EXTERNAL_VBUS_ENABLED
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/* use external VBUS driver */
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usb_regs->gr->GUSBCS |= GUSBCS_ULPIEVD;
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#else
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/* use internal VBUS driver */
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usb_regs->gr->GUSBCS &= ~GUSBCS_ULPIEVD;
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#endif /* USBHS_EXTERNAL_VBUS_ENABLED */
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/* soft reset the core */
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usb_core_reset(usb_regs);
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}
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else if (USB_EMBEDDED_PHY_HS == usb_basic.phy_itf)
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{
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usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY_HS;
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/* soft reset the core */
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usb_core_reset(usb_regs);
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usb_regs->gr->GCCFG = 0U;
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#ifdef VBUS_SENSING_ENABLED
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/* active the transceiver and enable VBUS sensing */
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usb_regs->gr->GCCFG |= GCCFG_VDEN | GCCFG_PWRON;
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#else
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#ifdef USE_HOST_MODE
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usb_regs->gr->GOTGCS |= GOTGCS_AVOV | GOTGCS_AVOE;
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#endif /* USE_HOST_MODE */
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#ifdef USE_DEVICE_MODE
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usb_regs->gr->GOTGCS |= GOTGCS_BVOV | GOTGCS_BVOE;
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#endif /* USE_DEVICE_MODE */
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/* active the transceiver */
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usb_regs->gr->GCCFG |= GCCFG_PWRON;
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#endif /* VBUS_SENSING_ENABLED */
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if (usb_basic.sof_enable)
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{
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usb_regs->gr->GCCFG |= GCCFG_SOFOEN;
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}
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usb_mdelay(20U);
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}
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else if (USB_EMBEDDED_PHY_FS == usb_basic.phy_itf)
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{
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usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY_FS;
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/* soft reset the core */
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usb_core_reset(usb_regs);
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#ifdef VBUS_SENSING_ENABLED
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/* active the transceiver and enable VBUS sensing */
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usb_regs->gr->GCCFG |= GCCFG_VDEN | GCCFG_PWRON;
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#else
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#ifdef USE_HOST_MODE
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usb_regs->gr->GOTGCS |= GOTGCS_AVOV | GOTGCS_AVOE;
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#endif /* USE_HOST_MODE */
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#ifdef USE_DEVICE_MODE
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usb_regs->gr->GOTGCS |= GOTGCS_BVOV | GOTGCS_BVOE;
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#endif /* USE_DEVICE_MODE */
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/* active the transceiver */
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usb_regs->gr->GCCFG |= GCCFG_PWRON;
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#endif /* VBUS_SENSING_ENABLED */
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/* enable SOF output */
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if (usb_basic.sof_enable)
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{
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usb_regs->gr->GCCFG |= GCCFG_SOFOEN;
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}
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usb_mdelay(20U);
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}
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else
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{
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/* no operation */
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}
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if ((uint8_t)USB_USE_DMA == usb_basic.transfer_mode)
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{
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usb_regs->gr->GAHBCS &= ~GAHBCS_BURST;
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usb_regs->gr->GAHBCS |= DMA_INCR8 | GAHBCS_DMAEN;
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}
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#ifdef USE_OTG_MODE
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/* enable USB OTG features */
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usb_regs->gr->GUSBCS |= GUSBCS_HNPCEN | GUSBCS_SRPCEN;
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/* enable the USB wakeup and suspend interrupts */
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usb_regs->gr->GINTF = 0xBFFFFFFFU;
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usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE |
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GINTEN_OTGIE | GINTEN_SESIE | GINTEN_IDPSCIE;
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#endif /* USE_OTG_MODE */
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return USB_OK;
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}
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/*!
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\brief write a packet into the TX FIFO associated with the endpoint
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\param[in] usb_regs: pointer to USB core registers
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\param[in] src_buf: pointer to source buffer
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\param[in] fifo_num: FIFO number which is in (0..5)
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\param[in] byte_count: packet byte count
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\param[out] none
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\retval operation status
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*/
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usb_status usb_txfifo_write(usb_core_regs *usb_regs,
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uint8_t *src_buf,
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uint8_t fifo_num,
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uint16_t byte_count)
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{
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uint32_t word_count = (byte_count + 3U) / 4U;
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__IO uint32_t *fifo = usb_regs->DFIFO[fifo_num];
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while (word_count-- > 0U)
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{
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*fifo = *((__IO uint32_t *)src_buf);
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src_buf += 4U;
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}
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return USB_OK;
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}
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/*!
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\brief read a packet from the Rx FIFO associated with the endpoint
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\param[in] usb_regs: pointer to USB core registers
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\param[in] dest_buf: pointer to destination buffer
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\param[in] byte_count: packet byte count
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\param[out] none
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\retval void type pointer
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*/
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void *usb_rxfifo_read(usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count)
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{
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__IO uint32_t word_count = (byte_count + 3U) / 4U;
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__IO uint32_t *fifo = usb_regs->DFIFO[0];
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while (word_count-- > 0U)
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{
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*(__IO uint32_t *)dest_buf = *fifo;
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dest_buf += 4U;
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}
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return ((void *)dest_buf);
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}
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/*!
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\brief flush a TX FIFO or all TX FIFOs
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\param[in] usb_regs: pointer to USB core registers
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\param[in] fifo_num: FIFO number which is in (0..5)
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\param[out] none
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\retval operation status
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*/
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usb_status usb_txfifo_flush(usb_core_regs *usb_regs, uint8_t fifo_num)
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{
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usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6) | GRSTCTL_TXFF;
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/* wait for TX FIFO flush bit is set */
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while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF)
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{
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/* no operation */
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}
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/* wait for 3 PHY clocks*/
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usb_udelay(3U);
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return USB_OK;
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}
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/*!
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\brief flush the entire RX FIFO
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\param[in] usb_regs: pointer to USB core registers
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\param[out] none
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\retval operation status
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*/
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usb_status usb_rxfifo_flush(usb_core_regs *usb_regs)
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{
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usb_regs->gr->GRSTCTL = GRSTCTL_RXFF;
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/* wait for RX FIFO flush bit is set */
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while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF)
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{
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/* no operation */
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}
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/* wait for 3 PHY clocks */
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usb_udelay(3U);
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return USB_OK;
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}
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/*!
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\brief set endpoint or channel TX FIFO size
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\param[in] usb_regs: pointer to USB core registers
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\param[in] fifo: TX FIFO number
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\param[in] size: assigned TX FIFO size
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\param[out] none
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\retval none
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*/
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void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size)
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{
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uint32_t tx_offset = usb_regs->gr->GRFLEN;
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if (0U == fifo)
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{
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usb_regs->gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)size << 16) | tx_offset;
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}
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else
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{
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tx_offset += (usb_regs->gr->DIEP0TFLEN_HNPTFLEN) >> 16;
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for (uint8_t i = 0U; i < (fifo - 1U); i++)
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{
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tx_offset += (usb_regs->gr->DIEPTFLEN[i] >> 16);
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}
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usb_regs->gr->DIEPTFLEN[fifo - 1U] = ((uint32_t)size << 16) | tx_offset;
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}
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}
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/*!
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\brief set USB current mode
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\param[in] usb_regs: pointer to USB core registers
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\param[in] mode: USB current mode
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\param[out] none
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\retval none
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*/
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void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode)
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{
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usb_regs->gr->GUSBCS &= ~(GUSBCS_FDM | GUSBCS_FHM);
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if (DEVICE_MODE == mode)
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{
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usb_regs->gr->GUSBCS |= GUSBCS_FDM;
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}
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else if (HOST_MODE == mode)
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{
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usb_regs->gr->GUSBCS |= GUSBCS_FHM;
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}
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else
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{
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/* OTG mode and other mode can not be here! */
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}
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}
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/*!
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\brief configure USB core to soft reset
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\param[in] usb_regs: pointer to USB core registers
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\param[out] none
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\retval none
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*/
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static void usb_core_reset(usb_core_regs *usb_regs)
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{
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/* enable core soft reset */
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usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST;
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/* wait for the core to be soft reset */
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while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST)
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{
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/* no operation */
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}
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/* wait for additional 3 PHY clocks */
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usb_udelay(3U);
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}
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/*!
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\brief active USB core clock
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\param[in] udev: pointer to USB device
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\param[out] none
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\retval none
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*/
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void usb_clock_active(usb_core_driver *udev)
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{
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if (udev->bp.low_power)
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{
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if (udev->regs.dr->DSTAT & DSTAT_SPST)
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{
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/* un-gate USB Core clock */
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*udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK);
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}
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}
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}
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#endif /* BSP_USING_USB */
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