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272 lines
18 KiB
272 lines
18 KiB
/*!
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\file gd32h75e_cmp.h
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\brief definitions for the CMP
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\version 2025-08-07, V1.2.0, firmware for GD32H75E
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H75E_CMP_H
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#define GD32H75E_CMP_H
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#include "gd32h75e.h"
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/* CMP definitions */
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#define CMP CMP_BASE /*!< CMP base address */
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/* registers definitions */
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#define CMP_STAT REG32((CMP) + 0x00000000U) /*!< CMP status register */
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#define CMP_IFC REG32((CMP) + 0x00000004U) /*!< CMP interrupt flag clear register */
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#define CMP_SR REG32((CMP) + 0x00000008U) /*!< CMP alternate select register */
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#define CMP0_CS REG32((CMP) + 0x0000000CU) /*!< CMP0 control and status register */
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#define CMP1_CS REG32((CMP) + 0x00000010U) /*!< CMP1 control and status register */
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/* bits definitions */
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/* CMP_STAT */
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#define CMP_STAT_CMP0O BIT(0) /*!< CMP0 output */
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#define CMP_STAT_CMP1O BIT(1) /*!< CMP1 output */
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#define CMP_STAT_CMP0IF BIT(16) /*!< CMP0 interrupt flag */
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#define CMP_STAT_CMP1IF BIT(17) /*!< CMP1 interrupt flag */
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/* CMP_IFC */
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#define CMP_IFC_CMP0IC BIT(16) /*!< CMP0 interrupt flag clear */
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#define CMP_IFC_CMP1IC BIT(17) /*!< CMP1 interrupt flag clear */
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/* CMP_SR */
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#define CMP_SR_AFSE_PA6 BIT(0) /*!< PA6 alternate function select for CMPx_OUT */
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#define CMP_SR_AFSE_PA8 BIT(1) /*!< PA8 alternate function select for CMPx_OUT */
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#define CMP_SR_AFSE_PB12 BIT(2) /*!< PB12 alternate function select for CMPx_OUT */
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#define CMP_SR_AFSE_PE6 BIT(3) /*!< PE6 alternate function select for CMPx_OUT */
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#define CMP_SR_AFSE_PE15 BIT(4) /*!< PE15 alternate function select for CMPx_OUT */
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#define CMP_SR_AFSE_PG2 BIT(5) /*!< PG2 alternate function select for CMPx_OUT */
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#define CMP_SR_AFSE_PG3 BIT(6) /*!< PG3 alternate function select for CMPx_OUT */
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#define CMP_SR_AFSE_PG4 BIT(7) /*!< PG4 alternate function select for CMPx_OUT */
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#define CMP_SR_AFSE_PK0 BIT(8) /*!< PK0 alternate function select for CMPx_OUT */
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#define CMP_SR_AFSE_PK1 BIT(9) /*!< PK1 alternate function select for CMPx_OUT */
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#define CMP_SR_AFSE_PK2 BIT(10) /*!< PK2 alternate function select for CMPx_OUT */
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/* CMPx_CS */
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#define CMP_CS_CMPXEN BIT(0) /*!< CMPx enable */
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#define CMP_CS_CMPXBEN BIT(1) /*!< CMPx scaler bridge enable bit */
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#define CMP_CS_CMPXSEN BIT(2) /*!< CMPx voltage scaler enable bit */
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#define CMP_CS_CMPXPL BIT(3) /*!< CMPx output polarity */
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#define CMP_CS_WNDEN BIT(4) /*!< CMP Window mode enable */
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#define CMP_CS_CMPXINTEN BIT(6) /*!< CMPx interrupt enable */
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#define CMP_CS_CMPXHST BITS(8,9) /*!< CMPx hysteresis */
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#define CMP_CS_CMPXM BITS(12,13) /*!< CMPx mode */
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#define CMP_CS_CMPXMISEL BITS(16,18) /*!< CMP_IM input selection */
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#define CMP_CS_CMPXPSEL BIT(20) /*!< CMP_IP input selection */
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#define CMP_CS_CMPXBLK BITS(24,27) /*!< CMPx output blanking source */
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#define CMP_CS_CMPXLK BIT(31) /*!< CMPx lock */
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/* constants definitions */
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/* CMP units */
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typedef enum{
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CMP0, /*!< comparator 0 */
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CMP1 /*!< comparator 1 */
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}cmp_enum;
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/* CMP operating mode */
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#define CS_CMPXM(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U))
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#define CMP_MODE_HIGHSPEED CS_CMPXM(0) /*!< CMP mode high speed */
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#define CMP_MODE_MIDDLESPEED CS_CMPXM(1) /*!< CMP mode middle speed */
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#define CMP_MODE_VERYLOWSPEED CS_CMPXM(3) /*!< CMP mode very low speed */
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/* CMP hysteresis */
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#define CS_CMPXHST(regval) (BITS(8,9) & ((uint32_t)(regval) << 8U))
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#define CMP_HYSTERESIS_NO CS_CMPXHST(0) /*!< CMP output no hysteresis */
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#define CMP_HYSTERESIS_LOW CS_CMPXHST(1) /*!< CMP output low hysteresis */
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#define CMP_HYSTERESIS_MIDDLE CS_CMPXHST(2) /*!< CMP output middle hysteresis */
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#define CMP_HYSTERESIS_HIGH CS_CMPXHST(3) /*!< CMP output high hysteresis */
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/* CMP inverting input */
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#define CS_CMPXMSEL(regval) (BITS(16,18) & ((uint32_t)(regval) << 16U))
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#define CMP_INVERTING_INPUT_1_4VREFINT CS_CMPXMSEL(0) /*!< CMP inverting input 1/4 Vrefint */
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#define CMP_INVERTING_INPUT_1_2VREFINT CS_CMPXMSEL(1) /*!< CMP inverting input 1/2 Vrefint */
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#define CMP_INVERTING_INPUT_3_4VREFINT CS_CMPXMSEL(2) /*!< CMP inverting input 3/4 Vrefint */
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#define CMP_INVERTING_INPUT_VREFINT CS_CMPXMSEL(3) /*!< CMP inverting input Vrefint */
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#define CMP_INVERTING_INPUT_DAC0_OUT0 CS_CMPXMSEL(4) /*!< CMP inverting input DAC0_OUT0 */
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#define CMP_INVERTING_INPUT_DAC0_OUT1 CS_CMPXMSEL(5) /*!< CMP inverting input DAC0_OUT1 */
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#define CMP_INVERTING_INPUT_PB1_PE10 CS_CMPXMSEL(6) /*!< CMP inverting input PB1 for CMP0 or PE10 for CMP1 */
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#define CMP_INVERTING_INPUT_PC4_PE7 CS_CMPXMSEL(7) /*!< CMP inverting input PC4 for CMP0 or PE7 for CMP1 */
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/* CMP noninverting input*/
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#define CS_CMPXPSEL(regval) (BIT(20) & ((uint32_t)(regval) << 20U))
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#define CMP_NONINVERTING_INPUT_PB0_PE9 CS_CMPXPSEL(0) /*!< CMP noninverting input PB0 for CMP0 or PE9 for CMP1 */
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#define CMP_NONINVERTING_INPUT_PB2_PE11 CS_CMPXPSEL(1) /*!< CMP noninverting input PB2 for CMP0 or PE11 for CMP1 */
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/* CMP output polarity*/
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#define CS_CMPXPL(regval) (BIT(3) & ((uint32_t)(regval) << 3U))
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#define CMP_OUTPUT_POLARITY_NONINVERTED CS_CMPXPL(0) /*!< CMP output not inverted */
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#define CMP_OUTPUT_POLARITY_INVERTED CS_CMPXPL(1) /*!< CMP output inverted */
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/* CMP blanking suorce */
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#define CS_CMPXBLK(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U))
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#define CMP_BLANKING_NONE CS_CMPXBLK(0) /*!< CMP no blanking source */
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#define CMP_BLANKING_TIMER0_OC0 CS_CMPXBLK(1) /*!< CMP TIMER0_CH0 output compare signal selected as blanking source */
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#define CMP_BLANKING_TIMER1_OC2 CS_CMPXBLK(2) /*!< CMP TIMER1_CH2 output compare signal selected as blanking source */
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#define CMP_BLANKING_TIMER2_OC2 CS_CMPXBLK(3) /*!< CMP TIMER2_CH2 output compare signal selected as blanking source */
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#define CMP_BLANKING_TIMER2_OC3 CS_CMPXBLK(4) /*!< CMP TIMER2_CH3 output compare signal selected as blanking source */
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#define CMP_BLANKING_TIMER7_OC0 CS_CMPXBLK(5) /*!< CMP TIMER7_CH0 output compare signal selected as blanking source */
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#define CMP_BLANKING_TIMER14_OC0 CS_CMPXBLK(6) /*!< CMP TIMER14_CH0 output compare signal selected as blanking source */
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/* comparator output level */
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#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001U) /*!< comparator output high */
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#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000U) /*!< comparator output low */
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/* CMP alternate output ports */
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#define CMP_AFSE_GPIO_PA6 CMP_SR_AFSE_PA6 /*!< CMP alternate GPIO PA6 */
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#define CMP_AFSE_GPIO_PA8 CMP_SR_AFSE_PA8 /*!< CMP alternate GPIO PA8 */
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#define CMP_AFSE_GPIO_PB12 CMP_SR_AFSE_PB12 /*!< CMP alternate GPIO PB12 */
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#define CMP_AFSE_GPIO_PE6 CMP_SR_AFSE_PE6 /*!< CMP alternate GPIO PE6 */
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#define CMP_AFSE_GPIO_PE15 CMP_SR_AFSE_PE15 /*!< CMP alternate GPIO PE15 */
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#define CMP_AFSE_GPIO_PG2 CMP_SR_AFSE_PG2 /*!< CMP alternate GPIO PG2 */
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#define CMP_AFSE_GPIO_PG3 CMP_SR_AFSE_PG3 /*!< CMP alternate GPIO PG3 */
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#define CMP_AFSE_GPIO_PG4 CMP_SR_AFSE_PG4 /*!< CMP alternate GPIO PG4 */
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#define CMP_AFSE_GPIO_PK0 CMP_SR_AFSE_PK0 /*!< CMP alternate GPIO PK0 */
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#define CMP_AFSE_GPIO_PK1 CMP_SR_AFSE_PK1 /*!< CMP alternate GPIO PK1*/
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#define CMP_AFSE_GPIO_PK2 CMP_SR_AFSE_PK2 /*!< CMP alternate GPIO PK2 */
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/* CMP flag definitions */
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#define CMP_FLAG_COMPARE CMP_STAT_CMP0IF /*!< CMP compare flag */
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/* CMP interrupt definitions */
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#define CMP_INT_COMPARE CMP_CS_CMPXINTEN /*!< CMP compare interrupt */
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/* CMP interrupt flag */
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#define CMP_INT_FLAG_COMPARE CMP_STAT_CMP0IF /*!< CMP interrupt flag */
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/* parameter check definitions */
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#ifdef FW_DEBUG_ERR_REPORT
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/* check CMP operating mode */
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#define NOT_CMP_OPERATING_MODE(operating_mode) (((operating_mode) != CMP_MODE_HIGHSPEED) && ((operating_mode) != CMP_MODE_MIDDLESPEED) && \
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((operating_mode) != CMP_MODE_VERYLOWSPEED))
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/* check CMP output hysteresis */
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#define NOT_CMP_OUTPUT_HYSTERESIS(output_hysteresis) (((output_hysteresis) != CMP_HYSTERESIS_NO) && ((output_hysteresis) != CMP_HYSTERESIS_LOW) && \
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((output_hysteresis) != CMP_HYSTERESIS_MIDDLE) && ((output_hysteresis) != CMP_HYSTERESIS_HIGH))
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/* check CMP inverting input */
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#define NOT_CMP_INVERTING_INPUT(inverting_input) (((inverting_input) != CMP_INVERTING_INPUT_1_4VREFINT) && ((inverting_input) != CMP_INVERTING_INPUT_1_2VREFINT) && \
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((inverting_input) != CMP_INVERTING_INPUT_3_4VREFINT) && ((inverting_input) != CMP_INVERTING_INPUT_VREFINT) && \
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((inverting_input) != CMP_INVERTING_INPUT_DAC0_OUT0) && ((inverting_input) != CMP_INVERTING_INPUT_DAC0_OUT1) && \
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((inverting_input) != CMP_INVERTING_INPUT_PB1_PE10) && ((inverting_input) != CMP_INVERTING_INPUT_PC4_PE7))
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/* check CMP noninverting input */
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#define NOT_CMP_NONINVERTING_INPUT(noninverting_input) (((noninverting_input) != CMP_NONINVERTING_INPUT_PB0_PE9) && ((noninverting_input) != CMP_NONINVERTING_INPUT_PB2_PE11))
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/* check CMP output polarity */
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#define NOT_CMP_OUTPUT_POLARITY(output_polarity) (((output_polarity) != CMP_OUTPUT_POLARITY_NONINVERTED) && ((output_polarity) != CMP_OUTPUT_POLARITY_INVERTED))
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/* check CMP output selection */
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#define NOT_CMP_OUTPUT_SELECTION(output_selection) (((output_selection) != CMP_OUTPUT_NONE) && ((output_selection) != CMP_OUTPUT_TIMER0_BKIN) && \
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((output_selection) != CMP_OUTPUT_TIMER0_IC0) && ((output_selection) != CMP_OUTPUT_TIMER0_OCPRECLR) && \
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((output_selection) != CMP_OUTPUT_TIMER1_IC3) && ((output_selection) != CMP_OUTPUT_TIMER1_OCPRECLR) && \
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((output_selection) != CMP_OUTPUT_TIMER2_IC0) && ((output_selection) != CMP_OUTPUT_TIMER2_OCPRECLR))
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#define NOT_CMP_AFSE_GPIO_PIN(cmp_output_sel) (((cmp_output_sel) != CMP_AFSE_GPIO_PA6) && ((cmp_output_sel) != CMP_AFSE_GPIO_PA8) && \
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((cmp_output_sel) != CMP_AFSE_GPIO_PB12) && ((cmp_output_sel) != CMP_AFSE_GPIO_PE6) && \
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((cmp_output_sel) != CMP_AFSE_GPIO_PE15) && ((cmp_output_sel) != CMP_AFSE_GPIO_PG2) && \
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((cmp_output_sel) != CMP_AFSE_GPIO_PG3) && ((cmp_output_sel) != CMP_AFSE_GPIO_PG4) && \
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((cmp_output_sel) != CMP_AFSE_GPIO_PK0) && ((cmp_output_sel) != CMP_AFSE_GPIO_PK1) && \
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((cmp_output_sel) != CMP_AFSE_GPIO_PK2))
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/* check CMP blanking source selection */
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#define NOT_CMP_BLK_SOURCE_SEL(blanking_source) (((blanking_source_selection) != CMP_BLANKING_NONE) && ((blanking_source_selection) != CMP_BLANKING_TIMER0_OC0) && \
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((blanking_source_selection) != CMP_BLANKING_TIMER1_OC2) && ((blanking_source_selection) != CMP_BLANKING_TIMER2_OC2) && \
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((blanking_source_selection) != CMP_BLANKING_TIMER2_OC3) && ((blanking_source_selection) != CMP_BLANKING_TIMER7_OC0) && \
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((blanking_source_selection) != CMP_BLANKING_TIMER14_OC0))
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/* check CMP falg */
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#define NOT_CMP_FLAG(flag) ((flag) != CMP_FLAG_COMPARE)
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/* check CMP interrupt */
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#define NOT_CMP_INTERRUPT(interrupt) ((interrupt) != CMP_INT_COMPARE)
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/* check CMP interrupt flag */
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#define NOT_CMP_INTERRUPT_FLAG(flag) ((flag) != CMP_INT_FLAG_COMPARE)
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#endif
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/* function declarations */
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/* initialization functions */
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/* CMP deinit */
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void cmp_deinit(cmp_enum cmp_periph);
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/* CMP mode init */
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void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis);
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/* CMP noninverting input select */
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void cmp_noninverting_input_select(cmp_enum cmp_periph, uint32_t noninverting_input);
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/* CMP output init */
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void cmp_output_init(cmp_enum cmp_periph, uint32_t output_polarity);
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/* config comparator output port */
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void cmp_output_mux_config(cmp_enum cmp_periph, uint32_t cmp_output_sel);
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/* CMP output blanking function init */
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void cmp_blanking_init(cmp_enum cmp_periph,uint32_t blanking_source_selection);
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/* enable functions */
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/* enable CMP */
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void cmp_enable(cmp_enum cmp_periph);
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/* disable CMP */
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void cmp_disable(cmp_enum cmp_periph);
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/* enable the window mode */
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void cmp_window_enable(void);
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/* disable the window mode */
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void cmp_window_disable(void);
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/* lock the CMP */
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void cmp_lock_enable(cmp_enum cmp_periph);
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/* enable the voltage scaler */
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void cmp_voltage_scaler_enable(cmp_enum cmp_periph);
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/* disable the voltage scaler */
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void cmp_voltage_scaler_disable(cmp_enum cmp_periph);
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/* enable the scaler bridge */
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void cmp_scaler_bridge_enable(cmp_enum cmp_periph);
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/* disable the scaler bridge */
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void cmp_scaler_bridge_disable(cmp_enum cmp_periph);
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/* get state related functions */
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/* get output level */
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uint32_t cmp_output_level_get(cmp_enum cmp_periph);
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/* flag and interrupt functions */
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/* get CMP flag */
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FlagStatus cmp_flag_get(cmp_enum cmp_periph, uint32_t flag);
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/* clear CMP flag */
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void cmp_flag_clear(cmp_enum cmp_periph, uint32_t flag);
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/* enable CMP interrupt */
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void cmp_interrupt_enable(cmp_enum cmp_periph, uint32_t interrupt);
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/* disable CMP interrupt */
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void cmp_interrupt_disable(cmp_enum cmp_periph, uint32_t interrupt);
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/* get CMP interrupt flag */
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FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag);
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/* clear CMP interrupt flag */
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void cmp_interrupt_flag_clear(cmp_enum cmp_periph, uint32_t flag);
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#endif /* GD32H75E_CMP_H */
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