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955 lines
86 KiB
955 lines
86 KiB
/*!
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\file gd32h75e_ospi.h
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\brief definitions for the OSPI
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\version 2025-08-07, V1.2.0, firmware for GD32H75E
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H75E_OSPI_H
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#define GD32H75E_OSPI_H
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#include "gd32h75e.h"
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/* OSPI definitions */
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#define OSPI0 OSPI_BASE
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#define OSPI1 (OSPI_BASE + 0x00005000U)
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/* registers definitions */
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#define OSPI_CTL(ospix) REG32((ospix) + 0x00000000U) /*!< OSPI control register */
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#define OSPI_DCFG0(ospix) REG32((ospix) + 0x00000008U) /*!< OSPI device configuration register */
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#define OSPI_DCFG1(ospix) REG32((ospix) + 0x0000000CU) /*!< OSPI device configuration register */
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#define OSPI_STAT(ospix) REG32((ospix) + 0x00000020U) /*!< OSPI status register */
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#define OSPI_STATC(ospix) REG32((ospix) + 0x00000024U) /*!< OSPI status clear register */
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#define OSPI_DTLEN(ospix) REG32((ospix) + 0x00000040U) /*!< OSPI data length register */
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#define OSPI_ADDR(ospix) REG32((ospix) + 0x00000048U) /*!< OSPI address register */
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#define OSPI_DATA(ospix) REG32((ospix) + 0x00000050U) /*!< OSPI data register */
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#define OSPI_STATMK(ospix) REG32((ospix) + 0x00000080U) /*!< OSPI status mask register */
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#define OSPI_STATMATCH(ospix) REG32((ospix) + 0x00000088U) /*!< OSPI status match register */
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#define OSPI_INTERVAL(ospix) REG32((ospix) + 0x00000090U) /*!< OSPI interval register */
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#define OSPI_TCFG(ospix) REG32((ospix) + 0x00000100U) /*!< OSPI transfer configuration register */
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#define OSPI_TIMCFG(ospix) REG32((ospix) + 0x00000108U) /*!< OSPI timing configuration register */
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#define OSPI_INS(ospix) REG32((ospix) + 0x00000110U) /*!< OSPI instruction register */
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#define OSPI_ALTE(ospix) REG32((ospix) + 0x00000120U) /*!< OSPI alternate bytes register */
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#define OSPI_WPTCFG(ospix) REG32((ospix) + 0x00000140U) /*!< OSPI wrap transfer configuration register */
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#define OSPI_WPTIMCFG(ospix) REG32((ospix) + 0x00000148U) /*!< OSPI wrap timing configuration register */
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#define OSPI_WPINS(ospix) REG32((ospix) + 0x00000150U) /*!< OSPI wrap instruction register */
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#define OSPI_WPALTE(ospix) REG32((ospix) + 0x00000160U) /*!< OSPI wrap alternate bytes register */
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#define OSPI_WTCFG(ospix) REG32((ospix) + 0x00000180U) /*!< OSPI write transfer configuration register */
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#define OSPI_WTIMCFG(ospix) REG32((ospix) + 0x00000188U) /*!< OSPI write timing configuration register */
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#define OSPI_WINS(ospix) REG32((ospix) + 0x00000190U) /*!< OSPI write instruction register */
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#define OSPI_WALTE(ospix) REG32((ospix) + 0x000001A0U) /*!< OSPI write alternate bytes register */
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/* bits definitions */
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/* OSPI_CTL */
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#define OSPI_CTL_OSPIEN BIT(0) /*!< enable the quadspi */
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#define OSPI_CTL_DMAEN BIT(2) /*!< dma enable */
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#define OSPI_CTL_FTL BITS(8,12) /*!< fifo threshold level */
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#define OSPI_CTL_TERRIE BIT(16) /*!< transfer error interrupt enable */
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#define OSPI_CTL_TCIE BIT(17) /*!< transfer complete interrupt enable */
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#define OSPI_CTL_FTIE BIT(18) /*!< fifo threshold interrupt enable */
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#define OSPI_CTL_SMIE BIT(19) /*!< status match interrupt enable */
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#define OSPI_CTL_SPS BIT(22) /*!< status polling mode stop */
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#define OSPI_CTL_SPMOD BIT(23) /*!< status polling match mode */
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#define OSPI_CTL_FMOD BITS(28,29) /*!< functional mode select */
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/* OSPI_DCFG0 */
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#define OSPI_DCFG0_CSHC BITS(8,13) /*!< chip select high cycle */
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#define OSPI_DCFG0_MESZ BITS(16,20) /*!< memory size */
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#define OSPI_DCFG0_DTYSEL BITS(24,26) /*!< select device type */
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/* OSPI_DCFG1 */
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#define OSPI_DCFG1_PSC BITS(0,7) /*!< prescaler set */
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#define OSPI_DCFG1_WPSZ BITS(16,18) /*!< wrap size */
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/* OSPI_STAT */
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#define OSPI_STAT_TERR BIT(0) /*!< transfer error flag */
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#define OSPI_STAT_TC BIT(1) /*!< transfer complete flag */
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#define OSPI_STAT_FT BIT(2) /*!< fifo threshold flag */
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#define OSPI_STAT_SM BIT(3) /*!< status match flag */
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#define OSPI_STAT_BUSY BIT(5) /*!< busy flag */
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#define OSPI_STAT_FL BITS(8,13) /*!< fifo level */
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/* OSPI_STATC */
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#define OSPI_STATC_TERRC BIT(0) /*!< clear transfer error flag */
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#define OSPI_STATC_TCC BIT(1) /*!< clear transfer complete flag */
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#define OSPI_STATC_SMC BIT(3) /*!< clear status match flag */
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/* OSPI_DTLEN */
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#define OSPI_DTLEN_DTLEN BITS(0,31) /*!< data length */
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/* OSPI_ADDR */
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#define OSPI_ADDR_ADDR BITS(0,31) /*!< address to be send to the external flash memory */
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/* OSPI_DATA */
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#define OSPI_DATA_DATA BITS(0,31) /*!< data to be transferred through the flash memory */
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/* OSPI_STATMK */
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#define OSPI_STATMK_MASK BITS(0,31) /*!< status mask */
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/* OSPI_STATMATCH */
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#define OSPI_STATMATCH_MATCH BITS(0,31) /*!< status match */
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/* OSPI_INTERVAL */
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#define OSPI_INTERVAL_INTERVAL BITS(0,15) /*!< interval cycle */
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/* OSPI_TCFG */
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#define OSPI_TCFG_IMOD BITS(0,2) /*!< instruction mode */
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#define OSPI_TCFG_INSSZ BITS(4,5) /*!< instruction size */
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#define OSPI_TCFG_ADDRMOD BITS(8,10) /*!< address mode */
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#define OSPI_TCFG_ADDRDTR BIT(11) /*!< address double transfer rate */
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#define OSPI_TCFG_ADDRSZ BITS(12,13) /*!< address size */
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#define OSPI_TCFG_ALTEMOD BITS(16,18) /*!< alternate bytes mode */
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#define OSPI_TCFG_ABDTR BIT(19) /*!< alternate bytes double transfer rate */
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#define OSPI_TCFG_ALTESZ BITS(20,21) /*!< alternate bytes size */
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#define OSPI_TCFG_DATAMOD BITS(24,26) /*!< data mode */
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#define OSPI_TCFG_DADTR BIT(27) /*!< data double transfer rate */
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/* OSPI_TIMCFG */
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#define OSPI_TIMCFG_DUMYC BITS(0,4) /*!< number of dummy cycles */
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#define OSPI_TIMCFG_DEHQC BIT(27) /*!< delay hold quarter cycle */
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#define OSPI_TIMCFG_SSAMPLE BIT(30) /*!< sample shift */
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/* OSPI_INS */
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#define OSPI_INS_INSTRUCTION BITS(0,31) /*!< command information to be send to the flash memory */
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/* OSPI_ALTE */
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#define OSPI_ALTE_ALTE BITS(0,31) /*!< alternate bytes to be send to the flash memory */
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/* OSPI_WPTCFG */
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#define OSPI_WPTCFG_IMOD BITS(0,2) /*!< instruction mode */
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#define OSPI_WPTCFG_INSSZ BITS(4,5) /*!< instruction size */
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#define OSPI_WPTCFG_ADDRMOD BITS(8,10) /*!< address mode */
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#define OSPI_WPTCFG_ADDRDTR BIT(11) /*!< address double transfer rate */
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#define OSPI_WPTCFG_ADDRSZ BITS(12,13) /*!< address size */
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#define OSPI_WPTCFG_ALTEMOD BITS(16,18) /*!< alternate bytes mode */
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#define OSPI_WPTCFG_ABDTR BIT(19) /*!< alternate bytes double transfer rate */
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#define OSPI_WPTCFG_ALTESZ BITS(20,21) /*!< alternate bytes size */
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#define OSPI_WPTCFG_DATAMOD BITS(24,26) /*!< data mode */
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#define OSPI_WPTCFG_DADTR BIT(27) /*!< data double transfer rate */
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/* OSPI_WPTIMCFG */
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#define OSPI_WPTIMCFG_DUMYC BITS(0,4) /*!< number of dummy cycles */
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#define OSPI_WPTIMCFG_DEHQC BIT(28) /*!< delay hold quarter cycle */
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#define OSPI_WPTIMCFG_SSAMPLE BIT(30) /*!< sample shift */
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/* OSPI_WPINS */
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#define OSPI_WPINS_INSTRUCTION BITS(0,31) /*!< command information to be send to the flash memory */
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/* OSPI_WPALTE */
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#define OSPI_WPALTE_ALTE BITS(0,31) /*!< optional data to be send to the flash memory */
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/* OSPI_WTCFG */
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#define OSPI_WTCFG_IMOD BITS(0,2) /*!< instruction mode */
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#define OSPI_WTCFG_INSSZ BITS(4,5) /*!< instruction size */
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#define OSPI_WTCFG_ADDRMOD BITS(8,10) /*!< address mode */
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#define OSPI_WTCFG_ADDRDTR BIT(11) /*!< address double transfer rate */
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#define OSPI_WTCFG_ADDRSZ BITS(12,13) /*!< address size */
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#define OSPI_WTCFG_ALTEMOD BITS(16,18) /*!< alternate bytes mode */
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#define OSPI_WTCFG_ABDTR BIT(19) /*!< alternate bytes double transfer rate */
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#define OSPI_WTCFG_ALTESZ BITS(20,21) /*!< alternate bytes size */
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#define OSPI_WTCFG_DATAMOD BITS(24,26) /*!< data mode */
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#define OSPI_WTCFG_DADTR BIT(27) /*!< data double transfer rate */
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/* OSPI_WTIMCFG */
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#define OSPI_WTIMCFG_DUMYC BITS(0,4) /*!< number of dummy cycles */
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/* OSPI_WINS */
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#define OSPI_WINS_INSTRUCTION BITS(0,31) /*!< command information to be send to the flash memory */
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/* OSPI_WALTE */
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#define OSPI_WALTE_ALTE BITS(0,31) /*!< optional data to be send to the flash memory */
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/* OSPI_HBLCFG */
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#define OSPI_HBLCFG_LMOD BIT(0) /*!< latency mode */
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#define OSPI_HBLCFG_WZLAT BIT(1) /*!< write zero latency */
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#define OSPI_HBLCFG_ACCTM BITS(8,15) /*!< access time */
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#define OSPI_HBLCFG_RWRTM BITS(16,23) /*!< read write recovery time */
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/* constants definitions */
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/* ospi init struct definitions */
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typedef struct {
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uint32_t prescaler; /*! specifies the prescaler factor for generating clock based on the kernel clock.
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this parameter can be a number between 0 and 255 */
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uint32_t fifo_threshold; /*! specifies the threshold number of bytes in the FIFO (used only in indirect mode)
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this parameter can be a value between 1 and 31 */
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uint32_t sample_shift; /*! specifies the sample shift. The data is sampled 1/2 clock cycle delay later to
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take in account external signal delays. (it should be OSPI_SAMPLE_SHIFTING_NONE in DTR mode) */
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uint32_t device_size; /*! specifies the device size. FlashSize+1 is effectively the number of address bits
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required to address the flash memory. The flash capacity can be up to 4GB
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(addressed using 32 bits) in indirect mode, but the addressable space in
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memory-mapped mode is limited to 256MB
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this parameter can be a number between 0 and 31 */
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uint32_t cs_hightime; /*! specifies the chip select high time. chipselecthightime+1 defines the minimum number
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of clock cycles which the chip select must remain high between commands. */
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uint32_t memory_type; /*! it indicates the external device type connected to the OSPI. */
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uint32_t wrap_size; /*! it indicates the wrap-size corresponding the external device configuration. */
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uint32_t delay_hold_cycle; /*! it allows to hold to 1/4 cycle the data. */
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} ospi_parameter_struct;
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/* ospi regular command struct definitions */
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typedef struct {
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uint32_t operation_type; /*! it indicates if the configuration applies to the common regsiters or
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to the registers for the write operation (these registers are only
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used for memory-mapped mode). */
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uint32_t instruction; /*! it contains the instruction to be sent to the device.
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this parameter can be a value between 0 and 0xFFFFFFFF */
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uint32_t ins_mode; /*! it indicates the mode of the instruction */
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uint32_t ins_size; /*! it indicates the size of the instruction */
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uint32_t address; /*! it contains the address to be sent to the device.
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this parameter can be a value between 0 and 0xFFFFFFFF */
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uint32_t addr_mode; /*! it indicates the mode of the address */
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uint32_t addr_size; /*! it indicates the size of the address */
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uint32_t addr_dtr_mode; /*! it enables or not the DTR mode for the address phase */
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uint32_t alter_bytes; /*! it contains the alternate bytes to be sent to the device.
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this parameter can be a value between 0 and 0xFFFFFFFF */
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uint32_t alter_bytes_mode; /*! it indicates the mode of the alternate bytes */
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uint32_t alter_bytes_size; /*! it indicates the size of the alternate bytes */
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uint32_t alter_bytes_dtr_mode; /*! it enables or not the DTR mode for the alternate bytes phase */
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uint32_t data_mode; /*! it indicates the mode of the data */
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uint32_t nbdata; /*! it indicates the number of data transferred with this command.
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this field is only used for indirect mode.
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this parameter can be a value between 1 and 0xFFFFFFFF */
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uint32_t data_dtr_mode; /*! it enables or not the DTR mode for the data phase */
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uint32_t dummy_cycles; /*! it indicates the number of dummy cycles inserted before data phase.
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this parameter can be a value between 0 and 31 */
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} ospi_regular_cmd_struct;
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/* ospi autopolling struct definitions */
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typedef struct {
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uint32_t match; /*! specifies the value to be compared with the masked status register to get a match.
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this parameter can be any value between 0 and 0xFFFFFFFF */
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uint32_t mask; /*! specifies the mask to be applied to the status bytes received.
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this parameter can be any value between 0 and 0xFFFFFFFF */
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uint32_t interval; /*! specifies the number of clock cycles between two read during automatic polling phases.
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this parameter can be any value between 0 and 0xFFFF */
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uint32_t match_mode; /*! specifies the method used for determining a match */
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uint32_t automatic_stop; /*! specifies if automatic polling is stopped after a match */
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} ospi_autopolling_struct;
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/* OSPI configuration */
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/* OSPI automatic stop */
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#define OSPI_AUTOMATIC_STOP_MATCH OSPI_CTL_SPS /*!< status polling mode stop in match */
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/* OSPI match mode */
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#define OSPI_MATCH_MODE_AND 0x00000000U /*!< OSPI status polling match mode and */
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#define OSPI_MATCH_MODE_OR OSPI_CTL_SPMOD /*!< OSPI status polling match mode or */
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/* OSPI functional mode */
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#define OSPI_FMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28U))
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#define OSPI_INDIRECT_WRITE OSPI_FMOD(0) /*!< OSPI indirect write mode */
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#define OSPI_INDIRECT_READ OSPI_FMOD(1) /*!< OSPI indirect read mode */
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#define OSPI_STATUS_POLLING OSPI_FMOD(2) /*!< OSPI status polling mode */
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#define OSPI_MEMORY_MAPPED OSPI_FMOD(3) /*!< OSPI memory mapped mode */
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/* OSPI FIFO threshold level set */
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#define OSPI_FTL(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U))
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#define OSPI_FIFO_THRESHOLD_1 OSPI_FTL(0) /*!< in indirect write mode, there are 1 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 1 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_2 OSPI_FTL(1) /*!< in indirect write mode, there are 2 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 2 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_3 OSPI_FTL(2) /*!< in indirect write mode, there are 3 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 3 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_4 OSPI_FTL(3) /*!< in indirect write mode, there are 4 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 4 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_5 OSPI_FTL(4) /*!< in indirect write mode, there are 5 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 5 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_6 OSPI_FTL(5) /*!< in indirect write mode, there are 6 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 6 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_7 OSPI_FTL(6) /*!< in indirect write mode, there are 7 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 7 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_8 OSPI_FTL(7) /*!< in indirect write mode, there are 8 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 8 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_9 OSPI_FTL(8) /*!< in indirect write mode, there are 9 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 9 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_10 OSPI_FTL(9) /*!< in indirect write mode, there are 10 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 10 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_11 OSPI_FTL(10) /*!< in indirect write mode, there are 11 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 11 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_12 OSPI_FTL(11) /*!< in indirect write mode, there are 12 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 12 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_13 OSPI_FTL(12) /*!< in indirect write mode, there are 13 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 13 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_14 OSPI_FTL(13) /*!< in indirect write mode, there are 14 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 14 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_15 OSPI_FTL(14) /*!< in indirect write mode, there are 15 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 15 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_16 OSPI_FTL(15) /*!< in indirect write mode, there are 16 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 16 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_17 OSPI_FTL(16) /*!< in indirect write mode, there are 17 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 17 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_18 OSPI_FTL(17) /*!< in indirect write mode, there are 18 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 18 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_19 OSPI_FTL(18) /*!< in indirect write mode, there are 19 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 19 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_20 OSPI_FTL(19) /*!< in indirect write mode, there are 20 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 20 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_21 OSPI_FTL(20) /*!< in indirect write mode, there are 21 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 21 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_22 OSPI_FTL(21) /*!< in indirect write mode, there are 22 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 22 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_23 OSPI_FTL(22) /*!< in indirect write mode, there are 23 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 23 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_24 OSPI_FTL(23) /*!< in indirect write mode, there are 24 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 24 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_25 OSPI_FTL(24) /*!< in indirect write mode, there are 25 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 25 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_26 OSPI_FTL(25) /*!< in indirect write mode, there are 26 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 26 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_27 OSPI_FTL(26) /*!< in indirect write mode, there are 27 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 27 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_28 OSPI_FTL(27) /*!< in indirect write mode, there are 28 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 28 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_29 OSPI_FTL(28) /*!< in indirect write mode, there are 29 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 29 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_30 OSPI_FTL(29) /*!< in indirect write mode, there are 30 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 30 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_31 OSPI_FTL(30) /*!< in indirect write mode, there are 31 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 31 or more free bytes available to be read from the FIFO */
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#define OSPI_FIFO_THRESHOLD_32 OSPI_FTL(31) /*!< in indirect write mode, there are 32 or more free bytes available to be written to the FIFO,
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in indirect read mode, there are 32 or more free bytes available to be read from the FIFO */
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/* OSPI chip select high cycle */
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#define OSPI_CSHC(regval) (BITS(8,13) & ((uint32_t)(regval) << 8U))
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#define OSPI_CS_HIGH_TIME_1_CYCLE OSPI_CSHC(0) /*!< OSPI csn stays high for at least 1 cycle */
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#define OSPI_CS_HIGH_TIME_2_CYCLE OSPI_CSHC(1) /*!< OSPI csn stays high for at least 2 cycle */
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#define OSPI_CS_HIGH_TIME_3_CYCLE OSPI_CSHC(2) /*!< OSPI csn stays high for at least 3 cycle */
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#define OSPI_CS_HIGH_TIME_4_CYCLE OSPI_CSHC(3) /*!< OSPI csn stays high for at least 4 cycle */
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#define OSPI_CS_HIGH_TIME_5_CYCLE OSPI_CSHC(4) /*!< OSPI csn stays high for at least 5 cycle */
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#define OSPI_CS_HIGH_TIME_6_CYCLE OSPI_CSHC(5) /*!< OSPI csn stays high for at least 6 cycle */
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#define OSPI_CS_HIGH_TIME_7_CYCLE OSPI_CSHC(6) /*!< OSPI csn stays high for at least 7 cycle */
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#define OSPI_CS_HIGH_TIME_8_CYCLE OSPI_CSHC(7) /*!< OSPI csn stays high for at least 8 cycle */
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#define OSPI_CS_HIGH_TIME_9_CYCLE OSPI_CSHC(8) /*!< OSPI csn stays high for at least 9 cycle */
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#define OSPI_CS_HIGH_TIME_10_CYCLE OSPI_CSHC(9) /*!< OSPI csn stays high for at least 10 cycle */
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#define OSPI_CS_HIGH_TIME_11_CYCLE OSPI_CSHC(10) /*!< OSPI csn stays high for at least 11 cycle */
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#define OSPI_CS_HIGH_TIME_12_CYCLE OSPI_CSHC(11) /*!< OSPI csn stays high for at least 12 cycle */
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#define OSPI_CS_HIGH_TIME_13_CYCLE OSPI_CSHC(12) /*!< OSPI csn stays high for at least 13 cycle */
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#define OSPI_CS_HIGH_TIME_14_CYCLE OSPI_CSHC(13) /*!< OSPI csn stays high for at least 14 cycle */
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#define OSPI_CS_HIGH_TIME_15_CYCLE OSPI_CSHC(14) /*!< OSPI csn stays high for at least 15 cycle */
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#define OSPI_CS_HIGH_TIME_16_CYCLE OSPI_CSHC(15) /*!< OSPI csn stays high for at least 16 cycle */
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#define OSPI_CS_HIGH_TIME_17_CYCLE OSPI_CSHC(16) /*!< OSPI csn stays high for at least 17 cycle */
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#define OSPI_CS_HIGH_TIME_18_CYCLE OSPI_CSHC(17) /*!< OSPI csn stays high for at least 18 cycle */
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#define OSPI_CS_HIGH_TIME_19_CYCLE OSPI_CSHC(18) /*!< OSPI csn stays high for at least 19 cycle */
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#define OSPI_CS_HIGH_TIME_20_CYCLE OSPI_CSHC(19) /*!< OSPI csn stays high for at least 20 cycle */
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#define OSPI_CS_HIGH_TIME_21_CYCLE OSPI_CSHC(20) /*!< OSPI csn stays high for at least 21 cycle */
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#define OSPI_CS_HIGH_TIME_22_CYCLE OSPI_CSHC(21) /*!< OSPI csn stays high for at least 22 cycle */
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#define OSPI_CS_HIGH_TIME_23_CYCLE OSPI_CSHC(22) /*!< OSPI csn stays high for at least 23 cycle */
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#define OSPI_CS_HIGH_TIME_24_CYCLE OSPI_CSHC(23) /*!< OSPI csn stays high for at least 24 cycle */
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#define OSPI_CS_HIGH_TIME_25_CYCLE OSPI_CSHC(24) /*!< OSPI csn stays high for at least 25 cycle */
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#define OSPI_CS_HIGH_TIME_26_CYCLE OSPI_CSHC(25) /*!< OSPI csn stays high for at least 26 cycle */
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#define OSPI_CS_HIGH_TIME_27_CYCLE OSPI_CSHC(26) /*!< OSPI csn stays high for at least 27 cycle */
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#define OSPI_CS_HIGH_TIME_28_CYCLE OSPI_CSHC(27) /*!< OSPI csn stays high for at least 28 cycle */
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#define OSPI_CS_HIGH_TIME_29_CYCLE OSPI_CSHC(28) /*!< OSPI csn stays high for at least 29 cycle */
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#define OSPI_CS_HIGH_TIME_30_CYCLE OSPI_CSHC(29) /*!< OSPI csn stays high for at least 30 cycle */
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#define OSPI_CS_HIGH_TIME_31_CYCLE OSPI_CSHC(30) /*!< OSPI csn stays high for at least 31 cycle */
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#define OSPI_CS_HIGH_TIME_32_CYCLE OSPI_CSHC(31) /*!< OSPI csn stays high for at least 32 cycle */
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#define OSPI_CS_HIGH_TIME_33_CYCLE OSPI_CSHC(32) /*!< OSPI csn stays high for at least 33 cycle */
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#define OSPI_CS_HIGH_TIME_34_CYCLE OSPI_CSHC(33) /*!< OSPI csn stays high for at least 34 cycle */
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#define OSPI_CS_HIGH_TIME_35_CYCLE OSPI_CSHC(34) /*!< OSPI csn stays high for at least 35 cycle */
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#define OSPI_CS_HIGH_TIME_36_CYCLE OSPI_CSHC(35) /*!< OSPI csn stays high for at least 36 cycle */
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#define OSPI_CS_HIGH_TIME_37_CYCLE OSPI_CSHC(36) /*!< OSPI csn stays high for at least 37 cycle */
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#define OSPI_CS_HIGH_TIME_38_CYCLE OSPI_CSHC(37) /*!< OSPI csn stays high for at least 38 cycle */
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#define OSPI_CS_HIGH_TIME_39_CYCLE OSPI_CSHC(38) /*!< OSPI csn stays high for at least 39 cycle */
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#define OSPI_CS_HIGH_TIME_40_CYCLE OSPI_CSHC(39) /*!< OSPI csn stays high for at least 40 cycle */
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#define OSPI_CS_HIGH_TIME_41_CYCLE OSPI_CSHC(40) /*!< OSPI csn stays high for at least 41 cycle */
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#define OSPI_CS_HIGH_TIME_42_CYCLE OSPI_CSHC(41) /*!< OSPI csn stays high for at least 42 cycle */
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#define OSPI_CS_HIGH_TIME_43_CYCLE OSPI_CSHC(42) /*!< OSPI csn stays high for at least 43 cycle */
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#define OSPI_CS_HIGH_TIME_44_CYCLE OSPI_CSHC(43) /*!< OSPI csn stays high for at least 44 cycle */
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#define OSPI_CS_HIGH_TIME_45_CYCLE OSPI_CSHC(44) /*!< OSPI csn stays high for at least 45 cycle */
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#define OSPI_CS_HIGH_TIME_46_CYCLE OSPI_CSHC(45) /*!< OSPI csn stays high for at least 46 cycle */
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#define OSPI_CS_HIGH_TIME_47_CYCLE OSPI_CSHC(46) /*!< OSPI csn stays high for at least 47 cycle */
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#define OSPI_CS_HIGH_TIME_48_CYCLE OSPI_CSHC(47) /*!< OSPI csn stays high for at least 48 cycle */
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#define OSPI_CS_HIGH_TIME_49_CYCLE OSPI_CSHC(48) /*!< OSPI csn stays high for at least 49 cycle */
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#define OSPI_CS_HIGH_TIME_50_CYCLE OSPI_CSHC(49) /*!< OSPI csn stays high for at least 50 cycle */
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#define OSPI_CS_HIGH_TIME_51_CYCLE OSPI_CSHC(50) /*!< OSPI csn stays high for at least 51 cycle */
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#define OSPI_CS_HIGH_TIME_52_CYCLE OSPI_CSHC(51) /*!< OSPI csn stays high for at least 52 cycle */
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#define OSPI_CS_HIGH_TIME_53_CYCLE OSPI_CSHC(52) /*!< OSPI csn stays high for at least 53 cycle */
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#define OSPI_CS_HIGH_TIME_54_CYCLE OSPI_CSHC(53) /*!< OSPI csn stays high for at least 54 cycle */
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#define OSPI_CS_HIGH_TIME_55_CYCLE OSPI_CSHC(54) /*!< OSPI csn stays high for at least 55 cycle */
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#define OSPI_CS_HIGH_TIME_56_CYCLE OSPI_CSHC(55) /*!< OSPI csn stays high for at least 56 cycle */
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#define OSPI_CS_HIGH_TIME_57_CYCLE OSPI_CSHC(56) /*!< OSPI csn stays high for at least 57 cycle */
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#define OSPI_CS_HIGH_TIME_58_CYCLE OSPI_CSHC(57) /*!< OSPI csn stays high for at least 58 cycle */
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#define OSPI_CS_HIGH_TIME_59_CYCLE OSPI_CSHC(58) /*!< OSPI csn stays high for at least 59 cycle */
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#define OSPI_CS_HIGH_TIME_60_CYCLE OSPI_CSHC(59) /*!< OSPI csn stays high for at least 60 cycle */
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#define OSPI_CS_HIGH_TIME_61_CYCLE OSPI_CSHC(60) /*!< OSPI csn stays high for at least 61 cycle */
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#define OSPI_CS_HIGH_TIME_62_CYCLE OSPI_CSHC(61) /*!< OSPI csn stays high for at least 62 cycle */
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#define OSPI_CS_HIGH_TIME_63_CYCLE OSPI_CSHC(62) /*!< OSPI csn stays high for at least 63 cycle */
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#define OSPI_CS_HIGH_TIME_64_CYCLE OSPI_CSHC(63) /*!< OSPI csn stays high for at least 64 cycle */
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/* OSPI flash memory size */
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#define OSPI_MESZ(regval) (BITS(16,20) & ((uint32_t)(regval) << 16U))
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#define OSPI_MESZ_2_BYTES OSPI_MESZ(0) /*!< the size of external memory is 2 bytes */
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#define OSPI_MESZ_4_BYTES OSPI_MESZ(1) /*!< the size of external memory is 4 bytes */
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#define OSPI_MESZ_8_BYTES OSPI_MESZ(2) /*!< the size of external memory is 8 bytes */
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#define OSPI_MESZ_16_BYTES OSPI_MESZ(3) /*!< the size of external memory is 16 bytes */
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#define OSPI_MESZ_32_BYTES OSPI_MESZ(4) /*!< the size of external memory is 32 bytes */
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#define OSPI_MESZ_64_BYTES OSPI_MESZ(5) /*!< the size of external memory is 64 bytes */
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#define OSPI_MESZ_128_BYTES OSPI_MESZ(6) /*!< the size of external memory is 128 bytes */
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#define OSPI_MESZ_256_BYTES OSPI_MESZ(7) /*!< the size of external memory is 256 bytes */
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#define OSPI_MESZ_512_BYTES OSPI_MESZ(8) /*!< the size of external memory is 512 bytes */
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#define OSPI_MESZ_1024_BYTES OSPI_MESZ(9) /*!< the size of external memory is 1024 bytes */
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#define OSPI_MESZ_2_KBS OSPI_MESZ(10) /*!< the size of external memory is 2 KB */
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#define OSPI_MESZ_4_KBS OSPI_MESZ(11) /*!< the size of external memory is 4 KB */
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#define OSPI_MESZ_8_KBS OSPI_MESZ(12) /*!< the size of external memory is 8 KB */
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#define OSPI_MESZ_16_KBS OSPI_MESZ(13) /*!< the size of external memory is 16 KB */
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#define OSPI_MESZ_32_KBS OSPI_MESZ(14) /*!< the size of external memory is 32 KB */
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#define OSPI_MESZ_64_KBS OSPI_MESZ(15) /*!< the size of external memory is 64 KB */
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#define OSPI_MESZ_128_KBS OSPI_MESZ(16) /*!< the size of external memory is 128 KB */
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#define OSPI_MESZ_256_KBS OSPI_MESZ(17) /*!< the size of external memory is 256 KB */
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#define OSPI_MESZ_512_KBS OSPI_MESZ(18) /*!< the size of external memory is 512 KB */
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#define OSPI_MESZ_1024_KBS OSPI_MESZ(19) /*!< the size of external memory is 1024 KBS */
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#define OSPI_MESZ_2_MBS OSPI_MESZ(20) /*!< the size of external memory is 2 MB */
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#define OSPI_MESZ_4_MBS OSPI_MESZ(21) /*!< the size of external memory is 4 MB */
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#define OSPI_MESZ_8_MBS OSPI_MESZ(22) /*!< the size of external memory is 8 MB */
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#define OSPI_MESZ_16_MBS OSPI_MESZ(23) /*!< the size of external memory is 16 MB */
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#define OSPI_MESZ_32_MBS OSPI_MESZ(24) /*!< the size of external memory is 32 MB */
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#define OSPI_MESZ_64_MBS OSPI_MESZ(25) /*!< the size of external memory is 64 MB */
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#define OSPI_MESZ_128_MBS OSPI_MESZ(26) /*!< the size of external memory is 128 MB */
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#define OSPI_MESZ_256_MBS OSPI_MESZ(27) /*!< the size of external memory is 256 MB */
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#define OSPI_MESZ_512_MBS OSPI_MESZ(28) /*!< the size of external memory is 512 MB */
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#define OSPI_MESZ_1024_MBS OSPI_MESZ(29) /*!< the size of external memory is 1024 MB */
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#define OSPI_MESZ_2048_MBS OSPI_MESZ(30) /*!< the size of external memory is 2048 MB */
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#define OSPI_MESZ_4096_MBS OSPI_MESZ(31) /*!< the size of external memory is 4096 MB */
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/* OSPI device type select */
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#define OSPI_DTYSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24U))
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#define OSPI_MICRON_MODE OSPI_DTYSEL(0) /*!< device type select micron mode */
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#define OSPI_MACRONIX_MODE OSPI_DTYSEL(1) /*!< device type select micronix mode */
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#define OSPI_STANDARD_MODE OSPI_DTYSEL(2) /*!< device type select standard mode */
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#define OSPI_MACRONIX_RAM_MODE OSPI_DTYSEL(3) /*!< device type select micronix ram mode */
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#define OSPI_RESERVE_MODE OSPI_DTYSEL(7) /*!< reserve mode, not use */
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/* OSPI prescaler set */
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#define OSPI_PSC(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U))
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/* OSPI wrap size set */
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#define OSPI_WPSZ(regval) (BITS(16,18) & ((uint32_t)(regval) << 16U))
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#define OSPI_DIRECT OSPI_WPSZ(0) /*!< external memory indirect device does not support wrap read */
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#define OSPI_WRAP_16BYTES OSPI_WPSZ(2) /*!< external memory device supports wrap size of 16 bytes */
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#define OSPI_WRAP_32BYTES OSPI_WPSZ(3) /*!< external memory device supports wrap size of 32 bytes */
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#define OSPI_WRAP_64BYTES OSPI_WPSZ(4) /*!< external memory device supports wrap size of 64 bytes */
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#define OSPI_WRAP_128BYTES OSPI_WPSZ(5) /*!< external memory device supports wrap size of 128 bytes */
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/* OSPI transmit configuration */
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/* OSPI operation type */
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#define OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< common configuration (indirect or auto-polling mode) */
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#define OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< read configuration (memory-mapped mode) */
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#define OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< write configuration (memory-mapped mode) */
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#define OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U) /*!< wrap configuration (memory-mapped mode) */
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/* OSPI instruction mode */
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#define OSPI_IMOD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
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#define OSPI_INSTRUCTION_NONE OSPI_IMOD(0) /*!< no instruction mode */
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#define OSPI_INSTRUCTION_1_LINE OSPI_IMOD(1) /*!< instruction mode on a single line */
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#define OSPI_INSTRUCTION_2_LINES OSPI_IMOD(2) /*!< instruction mode on two lines */
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#define OSPI_INSTRUCTION_4_LINES OSPI_IMOD(3) /*!< instruction mode on four lines */
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#define OSPI_INSTRUCTION_8_LINES OSPI_IMOD(4) /*!< instruction mode on eight lines */
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/* OSPI instruction size */
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#define OSPI_INSSZ(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U))
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#define OSPI_INSTRUCTION_8_BITS OSPI_INSSZ(0) /*!< instruction size on 8-bit address */
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#define OSPI_INSTRUCTION_16_BITS OSPI_INSSZ(1) /*!< instruction size on 16-bit address */
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#define OSPI_INSTRUCTION_24_BITS OSPI_INSSZ(2) /*!< instruction size on 24-bit address */
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#define OSPI_INSTRUCTION_32_BITS OSPI_INSSZ(3) /*!< instruction size on 32-bit address */
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/* OSPI address mode */
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#define OSPI_ADDRMOD(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U))
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#define OSPI_ADDRESS_NONE OSPI_ADDRMOD(0) /*!< no address mode */
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#define OSPI_ADDRESS_1_LINE OSPI_ADDRMOD(1) /*!< address mode on a single line */
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#define OSPI_ADDRESS_2_LINES OSPI_ADDRMOD(2) /*!< address mode on two lines */
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#define OSPI_ADDRESS_4_LINES OSPI_ADDRMOD(3) /*!< address mode on four lines */
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#define OSPI_ADDRESS_8_LINES OSPI_ADDRMOD(4) /*!< address mode on eight lines */
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|
/* OSPI address size */
|
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#define OSPI_ADDRSZ(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U))
|
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#define OSPI_ADDRESS_8_BITS OSPI_ADDRSZ(0) /*!< address size on 8-bit address */
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|
#define OSPI_ADDRESS_16_BITS OSPI_ADDRSZ(1) /*!< address size on 16-bit address */
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#define OSPI_ADDRESS_24_BITS OSPI_ADDRSZ(2) /*!< address size on 24-bit address */
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#define OSPI_ADDRESS_32_BITS OSPI_ADDRSZ(3) /*!< address size on 32-bit address */
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/* OSPI address double transfer rate */
|
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#define OSPI_ADDRDTR_MODE_DISABLE 0x00000000U /*!< address double transfer rate mode disable */
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#define OSPI_ADDRDTR_MODE_ENABLE OSPI_TCFG_ADDRDTR /*!< address double transfer rate mode disable */
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/* OSPI alternate bytes mode */
|
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#define OSPI_ALTEMOD(regval) (BITS(16,18) & ((uint32_t)(regval) << 16U))
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#define OSPI_ALTERNATE_BYTES_NONE OSPI_ALTEMOD(0) /*!< no alternate bytes mode */
|
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#define OSPI_ALTERNATE_BYTES_1_LINE OSPI_ALTEMOD(1) /*!< alternate bytes mode on a single line */
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#define OSPI_ALTERNATE_BYTES_2_LINES OSPI_ALTEMOD(2) /*!< alternate bytes mode on two lines */
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#define OSPI_ALTERNATE_BYTES_4_LINES OSPI_ALTEMOD(3) /*!< alternate bytes mode on four lines */
|
|
#define OSPI_ALTERNATE_BYTES_8_LINES OSPI_ALTEMOD(4) /*!< alternate bytes mode on eight lines */
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|
|
|
/* OSPI alternate bytes size */
|
|
#define OSPI_ALTESZ(regval) (BITS(20,21) & ((uint32_t)(regval) << 20U))
|
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#define OSPI_ALTERNATE_BYTES_8_BITS OSPI_ALTESZ(0) /*!< alternate bytes size on 8-bit address */
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#define OSPI_ALTERNATE_BYTES_16_BITS OSPI_ALTESZ(1) /*!< alternate bytes size on 16-bit address */
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|
#define OSPI_ALTERNATE_BYTES_24_BITS OSPI_ALTESZ(2) /*!< alternate bytes size on 24-bit address */
|
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#define OSPI_ALTERNATE_BYTES_32_BITS OSPI_ALTESZ(3) /*!< alternate bytes size on 32-bit address */
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|
|
|
/* OSPI alternate bytes double transfer rate */
|
|
#define OSPI_ABDTR_MODE_DISABLE 0x00000000U /*!< alternate bytes double transfer rate mode disable */
|
|
#define OSPI_ABDTR_MODE_ENABLE OSPI_TCFG_ABDTR /*!< alternate bytes double transfer rate mode enable */
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|
|
/* OSPI data mode */
|
|
#define OSPI_DATAMOD(regval) (BITS(24,26) & ((uint32_t)(regval) << 24U))
|
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#define OSPI_DATA_NONE OSPI_DATAMOD(0) /*!< no data mode */
|
|
#define OSPI_DATA_1_LINE OSPI_DATAMOD(1) /*!< data mode on a single line */
|
|
#define OSPI_DATA_2_LINES OSPI_DATAMOD(2) /*!< data mode on two lines */
|
|
#define OSPI_DATA_4_LINES OSPI_DATAMOD(3) /*!< data mode on four lines */
|
|
#define OSPI_DATA_8_LINES OSPI_DATAMOD(4) /*!< data mode on eight lines */
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|
|
|
/* OSPI data double transfer rate */
|
|
#define OSPI_DADTR_MODE_DISABLE 0x00000000U /*!< data double transfer rate mode disable */
|
|
#define OSPI_DADTR_MODE_ENABLE OSPI_TCFG_DADTR /*!< data double transfer rate mode enable */
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|
|
|
/* OSPI dummy cycles */
|
|
#define OSPI_DUMYC(regval) (BITS(0,4) & ((uint32_t)(regval) << 0U))
|
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#define OSPI_DUMYC_CYCLES_0 OSPI_DUMYC(0) /*!< duration of the dummy instruction phase is 0 cycle */
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#define OSPI_DUMYC_CYCLES_1 OSPI_DUMYC(1) /*!< duration of the dummy instruction phase is 1 cycle */
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#define OSPI_DUMYC_CYCLES_2 OSPI_DUMYC(2) /*!< duration of the dummy instruction phase is 2 cycle */
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#define OSPI_DUMYC_CYCLES_3 OSPI_DUMYC(3) /*!< duration of the dummy instruction phase is 3 cycle */
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#define OSPI_DUMYC_CYCLES_4 OSPI_DUMYC(4) /*!< duration of the dummy instruction phase is 4 cycle */
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#define OSPI_DUMYC_CYCLES_5 OSPI_DUMYC(5) /*!< duration of the dummy instruction phase is 5 cycle */
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#define OSPI_DUMYC_CYCLES_6 OSPI_DUMYC(6) /*!< duration of the dummy instruction phase is 6 cycle */
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#define OSPI_DUMYC_CYCLES_7 OSPI_DUMYC(7) /*!< duration of the dummy instruction phase is 7 cycle */
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#define OSPI_DUMYC_CYCLES_8 OSPI_DUMYC(8) /*!< duration of the dummy instruction phase is 8 cycle */
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#define OSPI_DUMYC_CYCLES_9 OSPI_DUMYC(9) /*!< duration of the dummy instruction phase is 9 cycle */
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#define OSPI_DUMYC_CYCLES_10 OSPI_DUMYC(10) /*!< duration of the dummy instruction phase is 10 cycle */
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#define OSPI_DUMYC_CYCLES_11 OSPI_DUMYC(11) /*!< duration of the dummy instruction phase is 11 cycle */
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#define OSPI_DUMYC_CYCLES_12 OSPI_DUMYC(12) /*!< duration of the dummy instruction phase is 12 cycle */
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#define OSPI_DUMYC_CYCLES_13 OSPI_DUMYC(13) /*!< duration of the dummy instruction phase is 13 cycle */
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#define OSPI_DUMYC_CYCLES_14 OSPI_DUMYC(14) /*!< duration of the dummy instruction phase is 14 cycle */
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#define OSPI_DUMYC_CYCLES_15 OSPI_DUMYC(15) /*!< duration of the dummy instruction phase is 15 cycle */
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#define OSPI_DUMYC_CYCLES_16 OSPI_DUMYC(16) /*!< duration of the dummy instruction phase is 16 cycle */
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#define OSPI_DUMYC_CYCLES_17 OSPI_DUMYC(17) /*!< duration of the dummy instruction phase is 17 cycle */
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#define OSPI_DUMYC_CYCLES_18 OSPI_DUMYC(18) /*!< duration of the dummy instruction phase is 18 cycle */
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#define OSPI_DUMYC_CYCLES_19 OSPI_DUMYC(19) /*!< duration of the dummy instruction phase is 19 cycle */
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#define OSPI_DUMYC_CYCLES_20 OSPI_DUMYC(20) /*!< duration of the dummy instruction phase is 20 cycle */
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#define OSPI_DUMYC_CYCLES_21 OSPI_DUMYC(21) /*!< duration of the dummy instruction phase is 21 cycle */
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#define OSPI_DUMYC_CYCLES_22 OSPI_DUMYC(22) /*!< duration of the dummy instruction phase is 22 cycle */
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#define OSPI_DUMYC_CYCLES_23 OSPI_DUMYC(23) /*!< duration of the dummy instruction phase is 23 cycle */
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#define OSPI_DUMYC_CYCLES_24 OSPI_DUMYC(24) /*!< duration of the dummy instruction phase is 24 cycle */
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#define OSPI_DUMYC_CYCLES_25 OSPI_DUMYC(25) /*!< duration of the dummy instruction phase is 25 cycle */
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#define OSPI_DUMYC_CYCLES_26 OSPI_DUMYC(26) /*!< duration of the dummy instruction phase is 26 cycle */
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#define OSPI_DUMYC_CYCLES_27 OSPI_DUMYC(27) /*!< duration of the dummy instruction phase is 27 cycle */
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#define OSPI_DUMYC_CYCLES_28 OSPI_DUMYC(28) /*!< duration of the dummy instruction phase is 28 cycle */
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#define OSPI_DUMYC_CYCLES_29 OSPI_DUMYC(29) /*!< duration of the dummy instruction phase is 29 cycle */
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#define OSPI_DUMYC_CYCLES_30 OSPI_DUMYC(30) /*!< duration of the dummy instruction phase is 30 cycle */
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#define OSPI_DUMYC_CYCLES_31 OSPI_DUMYC(31) /*!< duration of the dummy instruction phase is 31 cycle */
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/* OSPI delay hold quarter cycle */
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#define OSPI_DELAY_HOLD_NONE 0x00000000U /*!< OSPI no delay hold cycle */
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#define OSPI_DELAY_HOLD_QUARTER_CYCLE OSPI_TIMCFG_DEHQC /*!< OSPI delay hold 1/4 cycle */
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|
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/* OSPI sample shift */
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#define OSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!< OSPI no sample shift */
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#define OSPI_SAMPLE_SHIFTING_HALF_CYCLE OSPI_TIMCFG_SSAMPLE /*!< OSPI have 1/2 cycle sample shift */
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|
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/* OSPI interrupt constants definitions */
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#define OSPI_INT_TERR OSPI_CTL_TERRIE /*!< transfer error interrupt enable */
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#define OSPI_INT_TC OSPI_CTL_TCIE /*!< transfer complete interrupt enable */
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#define OSPI_INT_FT OSPI_CTL_FTIE /*!< fifo threshold interrupt enable */
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#define OSPI_INT_SM OSPI_CTL_SMIE /*!< status match interrupt enable */
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|
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/* OSPI flag definitions */
|
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#define OSPI_FLAG_TERR OSPI_STAT_TERR /*!< transfer error flag */
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#define OSPI_FLAG_TC OSPI_STAT_TC /*!< transfer complete flag */
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#define OSPI_FLAG_FT OSPI_STAT_FT /*!< fifo threshold flag */
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#define OSPI_FLAG_SM OSPI_STAT_SM /*!< status match flag */
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#define OSPI_FLAG_BUSY OSPI_STAT_BUSY /*!< busy flag */
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|
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/* define the OSPI bit position and its register index offset */
|
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#define OSPI_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
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#define OSPI_REG_VAL(ospix, offset) (REG32((ospix) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
|
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#define OSPI_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
|
|
#define OSPI_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
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| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
|
#define OSPI_REG_VAL2(ospix, offset) (REG32((ospix) + ((uint32_t)(offset) >> 22)))
|
|
#define OSPI_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
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|
|
|
/* register offset */
|
|
#define OSPI_CTL_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL register offset */
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#define OSPI_STAT_REG_OFFSET ((uint32_t)0x00000020U) /*!< STAT register offset */
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|
|
|
/* OSPI interrupt flags */
|
|
typedef enum {
|
|
OSPI_INT_FLAG_TERR = OSPI_REGIDX_BIT2(OSPI_CTL_REG_OFFSET, 16U, OSPI_STAT_REG_OFFSET, 0U), /*!< transfer error interrupt flag */
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OSPI_INT_FLAG_TC = OSPI_REGIDX_BIT2(OSPI_CTL_REG_OFFSET, 17U, OSPI_STAT_REG_OFFSET, 1U), /*!< transfer complete interrupt enable */
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OSPI_INT_FLAG_FT = OSPI_REGIDX_BIT2(OSPI_CTL_REG_OFFSET, 18U, OSPI_STAT_REG_OFFSET, 2U), /*!< fifo threshold interrupt flag */
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OSPI_INT_FLAG_SM = OSPI_REGIDX_BIT2(OSPI_CTL_REG_OFFSET, 19U, OSPI_STAT_REG_OFFSET, 3U), /*!< status match interrupt flag */
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|
} ospi_interrupt_flag_enum;
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|
|
|
#ifdef FW_DEBUG_ERR_REPORT
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|
/* check peripherals */
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#define NOT_OSPI_PERIPH(ospi_periph) (((ospi_periph) != OSPI0) && ((ospi_periph) != OSPI1))
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|
/* check OSPI prescaler */
|
|
#define NOT_OSPI_PSC(psc) ((psc) > 255U)
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|
/* check OSPI FIFO threshold */
|
|
#define NOT_OSPI_FIFO_THRESHOLD(fifo_threshold) (((fifo_threshold) != OSPI_FIFO_THRESHOLD_1) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_2) && \
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((fifo_threshold) != OSPI_FIFO_THRESHOLD_3) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_4) && \
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((fifo_threshold) != OSPI_FIFO_THRESHOLD_5) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_6) && \
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((fifo_threshold) != OSPI_FIFO_THRESHOLD_7) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_8) && \
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((fifo_threshold) != OSPI_FIFO_THRESHOLD_9) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_10) && \
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((fifo_threshold) != OSPI_FIFO_THRESHOLD_11) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_12) && \
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((fifo_threshold) != OSPI_FIFO_THRESHOLD_13) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_14) && \
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((fifo_threshold) != OSPI_FIFO_THRESHOLD_15) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_16) && \
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((fifo_threshold) != OSPI_FIFO_THRESHOLD_17) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_18) && \
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|
((fifo_threshold) != OSPI_FIFO_THRESHOLD_19) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_20) && \
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|
((fifo_threshold) != OSPI_FIFO_THRESHOLD_21) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_22) && \
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((fifo_threshold) != OSPI_FIFO_THRESHOLD_23) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_24) && \
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((fifo_threshold) != OSPI_FIFO_THRESHOLD_25) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_26) && \
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|
((fifo_threshold) != OSPI_FIFO_THRESHOLD_27) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_28) && \
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((fifo_threshold) != OSPI_FIFO_THRESHOLD_29) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_30) && \
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|
((fifo_threshold) != OSPI_FIFO_THRESHOLD_31) && ((fifo_threshold) != OSPI_FIFO_THRESHOLD_32))
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|
|
|
/* check OSPI sample shift */
|
|
#define NOT_OSPI_SAMPLE_SHIFTING(sample_shift) (((sample_shift) != OSPI_SAMPLE_SHIFTING_NONE) && ((sample_shift) != OSPI_SAMPLE_SHIFTING_HALF_CYCLE))
|
|
/* check OPSI memory size */
|
|
#define NOT_OSPI_MESZ(device_size) (((device_size) != OSPI_MESZ_2_BYTES) && ((device_size) != OSPI_MESZ_4_BYTES) && \
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((device_size) != OSPI_MESZ_8_BYTES) && ((device_size) != OSPI_MESZ_16_BYTES) && \
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((device_size) != OSPI_MESZ_32_BYTES) && ((device_size) != OSPI_MESZ_64_BYTES) && \
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((device_size) != OSPI_MESZ_128_BYTES) && ((device_size) != OSPI_MESZ_256_BYTES) && \
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((device_size) != OSPI_MESZ_512_BYTES) && ((device_size) != OSPI_MESZ_1024_BYTES) && \
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|
((device_size) != OSPI_MESZ_2_KBS) && ((device_size) != OSPI_MESZ_4_KBS) && \
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|
((device_size) != OSPI_MESZ_8_KBS) && ((device_size) != OSPI_MESZ_16_KBS) && \
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((device_size) != OSPI_MESZ_32_KBS) && ((device_size) != OSPI_MESZ_64_KBS) && \
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|
((device_size) != OSPI_MESZ_128_KBS) && ((device_size) != OSPI_MESZ_256_KBS) && \
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|
((device_size) != OSPI_MESZ_512_KBS) && ((device_size) != OSPI_MESZ_1024_KBS) && \
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((device_size) != OSPI_MESZ_2_MBS) && ((device_size) != OSPI_MESZ_4_MBS) && \
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((device_size) != OSPI_MESZ_8_MBS) && ((device_size) != OSPI_MESZ_16_MBS) && \
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|
((device_size) != OSPI_MESZ_32_MBS) && ((device_size) != OSPI_MESZ_64_MBS) && \
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((device_size) != OSPI_MESZ_128_MBS) && ((device_size) != OSPI_MESZ_256_MBS) && \
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((device_size) != OSPI_MESZ_512_MBS) && ((device_size) != OSPI_MESZ_1024_MBS) && \
|
|
((device_size) != OSPI_MESZ_2048_MBS) && ((device_size) != OSPI_MESZ_4096_MBS))
|
|
/* check OSPI CS high time */
|
|
#define NOT_OSPI_CS_HIGH_TIME(cs_hightime) (((cs_hightime) != OSPI_CS_HIGH_TIME_1_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_2_CYCLE) && \
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((cs_hightime) != OSPI_CS_HIGH_TIME_3_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_4_CYCLE) && \
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((cs_hightime) != OSPI_CS_HIGH_TIME_5_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_6_CYCLE) && \
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|
((cs_hightime) != OSPI_CS_HIGH_TIME_7_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_8_CYCLE) && \
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|
((cs_hightime) != OSPI_CS_HIGH_TIME_9_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_10_CYCLE) && \
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|
((cs_hightime) != OSPI_CS_HIGH_TIME_11_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_12_CYCLE) && \
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|
((cs_hightime) != OSPI_CS_HIGH_TIME_13_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_14_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_15_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_16_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_17_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_18_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_19_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_20_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_21_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_22_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_23_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_24_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_25_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_26_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_27_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_28_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_29_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_30_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_31_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_32_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_33_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_34_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_35_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_36_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_37_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_38_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_39_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_40_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_41_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_42_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_43_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_44_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_45_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_46_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_47_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_48_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_49_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_50_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_51_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_52_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_53_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_54_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_55_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_56_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_57_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_58_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_59_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_60_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_61_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_62_CYCLE) && \
|
|
((cs_hightime) != OSPI_CS_HIGH_TIME_63_CYCLE) && ((cs_hightime) != OSPI_CS_HIGH_TIME_64_CYCLE))
|
|
/* check OSPI memory type */
|
|
#define NOT_OSPI_MEMORY_TYPE(memory_type) (((memory_type) != OSPI_MICRON_MODE) && ((memory_type) != OSPI_MACRONIX_MODE) && \
|
|
((memory_type) != OSPI_STANDARD_MODE) && ((memory_type) != OSPI_MACRONIX_RAM_MODE))
|
|
/* check wrap size */
|
|
#define NOT_OSPI_WRAP_SIZE(wrap_size) (((wrap_size) != OSPI_DIRECT) && ((wrap_size) != OSPI_WRAP_16BYTES) && \
|
|
((wrap_size) != OSPI_WRAP_32BYTES) && ((wrap_size) != OSPI_WRAP_64BYTES) && \
|
|
((wrap_size) != OSPI_WRAP_128BYTES))
|
|
/* check delay hold cycle */
|
|
#define NOT_OSPI_DELAY_HOLD_CYCLE(delay_hold_cycle) (((delay_hold_cycle) != OSPI_DELAY_HOLD_NONE) && ((delay_hold_cycle) != OSPI_DELAY_HOLD_QUARTER_CYCLE))
|
|
/* check OSPI function mode */
|
|
#define NOT_OSPI_MODE(fmod) (((fmod) != OSPI_INDIRECT_WRITE) && ((fmod) != OSPI_INDIRECT_READ) && \
|
|
((fmod) != OSPI_STATUS_POLLING) && ((fmod) != OSPI_MEMORY_MAPPED))
|
|
/* check status polling mode stop */
|
|
#define NOT_OSPI_AUTOMATIC_STOP_MATCH(stop) (((stop) != OSPI_AUTOMATIC_STOP_MATCH))
|
|
/* check OSPI status polling match mode */
|
|
#define NOT_OSPI_MATCH_MODE(mode) (((mode) != OSPI_MATCH_MODE_AND) && ((mode) != OSPI_MATCH_MODE_OR))
|
|
/* check OSPI dumyc cycles */
|
|
#define NOT_OSPI_DUMYC_CYCLES(dumyc) (((dumyc) != OSPI_DUMYC_CYCLES_0) && ((dumyc) != OSPI_DUMYC_CYCLES_1) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_2) && ((dumyc) != OSPI_DUMYC_CYCLES_3) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_4) && ((dumyc) != OSPI_DUMYC_CYCLES_5) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_6) && ((dumyc) != OSPI_DUMYC_CYCLES_7) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_8) && ((dumyc) != OSPI_DUMYC_CYCLES_9) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_10) && ((dumyc) != OSPI_DUMYC_CYCLES_11) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_12) && ((dumyc) != OSPI_DUMYC_CYCLES_13) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_14) && ((dumyc) != OSPI_DUMYC_CYCLES_15) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_16) && ((dumyc) != OSPI_DUMYC_CYCLES_17) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_18) && ((dumyc) != OSPI_DUMYC_CYCLES_19) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_20) && ((dumyc) != OSPI_DUMYC_CYCLES_21) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_22) && ((dumyc) != OSPI_DUMYC_CYCLES_23) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_24) && ((dumyc) != OSPI_DUMYC_CYCLES_25) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_26) && ((dumyc) != OSPI_DUMYC_CYCLES_27) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_28) && ((dumyc) != OSPI_DUMYC_CYCLES_29) && \
|
|
((dumyc) != OSPI_DUMYC_CYCLES_30) && ((dumyc) != OSPI_DUMYC_CYCLES_31))
|
|
/* check OSPI instruction mode */
|
|
#define NOT_OSPI_INSTRUCTION_MODE(imod) (((imod) != OSPI_INSTRUCTION_NONE) && ((imod) != OSPI_INSTRUCTION_1_LINE) && \
|
|
((imod) != OSPI_INSTRUCTION_2_LINES) && ((imod) != OSPI_INSTRUCTION_4_LINES) && \
|
|
((imod) != OSPI_INSTRUCTION_8_LINES))
|
|
/* check OSPI instruction size */
|
|
#define NOT_OSPI_INSTRUCTION_SIZE(inssz) (((inssz) != OSPI_INSTRUCTION_8_BITS) && ((inssz) != OSPI_INSTRUCTION_16_BITS) && \
|
|
((inssz) != OSPI_INSTRUCTION_24_BITS) && ((inssz) != OSPI_INSTRUCTION_32_BITS))
|
|
/* check OSPI address mode */
|
|
#define NOT_OSPI_ADDRESS_MODE(addrmod) (((addrmod) != OSPI_ADDRESS_NONE) && ((addrmod) != OSPI_ADDRESS_1_LINE) && \
|
|
((addrmod) != OSPI_ADDRESS_2_LINES) && ((addrmod) != OSPI_ADDRESS_4_LINES) && \
|
|
((addrmod) != OSPI_ADDRESS_8_LINES))
|
|
/* check OSPI address DTR mode */
|
|
#define NOT_OSPI_ADDRDTR_MODE(addrdtr) (((addrdtr) != OSPI_ADDRDTR_MODE_DISABLE) && ((addrdtr) != OSPI_ADDRDTR_MODE_ENABLE))
|
|
/* check OSPI address size */
|
|
#define NOT_OSPI_ADDRESS_SIZE(addrsz) (((addrsz) != OSPI_ADDRESS_8_BITS) && ((addrsz) != OSPI_ADDRESS_16_BITS) && \
|
|
((addrsz) != OSPI_ADDRESS_24_BITS) && ((addrsz) != OSPI_ADDRESS_32_BITS))
|
|
/* check OSPI alternate bytes mode */
|
|
#define NOT_OSPI_ALTERNATE_BYTES_MODE(atlemod) (((atlemod) != OSPI_ALTERNATE_BYTES_NONE) && ((atlemod) != OSPI_ALTERNATE_BYTES_1_LINE) && \
|
|
((atlemod) != OSPI_ALTERNATE_BYTES_2_LINES) && ((atlemod) != OSPI_ALTERNATE_BYTES_4_LINES) && \
|
|
((atlemod) != OSPI_ALTERNATE_BYTES_8_LINES))
|
|
/* check OSPI alternate bytes DTR mode */
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#define NOT_OSPI_ABDTR_MODE(abdtr) (((abdtr) != OSPI_ABDTR_MODE_DISABLE) && ((abdtr) != OSPI_ABDTR_MODE_ENABLE))
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/* check OSPI alternate bytes size */
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#define NOT_OSPI_ALTERNATE_BYTES_SIZE(altesz) (((altesz) != OSPI_ALTERNATE_BYTES_8_BITS) && ((altesz) != OSPI_ALTERNATE_BYTES_16_BITS) && \
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((altesz) != OSPI_ALTERNATE_BYTES_24_BITS) && ((altesz) != OSPI_ALTERNATE_BYTES_32_BITS))
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#define NOT_OSPI_DATA_MODE(datamod) (((datamod) != OSPI_DATA_NONE) && ((datamod) != OSPI_DATA_1_LINE) && \
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((datamod) != OSPI_DATA_2_LINES) && ((datamod) != OSPI_DATA_4_LINES) && \
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((datamod) != OSPI_DATA_8_LINES))
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/* check OSPI data DTR mode */
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#define NOT_OSPI_DADTR_MODE(dadtr) (((dadtr) != OSPI_DADTR_MODE_DISABLE) && ((dadtr) != OSPI_DADTR_MODE_ENABLE))
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/* check OSPI operation type */
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#define NOT_OSPI_OPTYPE(operation_type) (((operation_type) != OSPI_OPTYPE_COMMON_CFG) && ((operation_type) != OSPI_OPTYPE_READ_CFG) && \
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((operation_type) != OSPI_OPTYPE_WRITE_CFG) && ((operation_type) != OSPI_OPTYPE_WRAP_CFG))
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/* check the number of clock cycles between two read during automatic polling phases */
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#define NOT_INTERVAL_NUM(interval) (((interval) > 0xFFFFU))
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/* check OSPI interrupt */
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#define NOT_OSPI_INTERRUPT(interrupt) (((interrupt) != OSPI_INT_TERR) && ((interrupt) != OSPI_INT_TC) && \
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((interrupt) != OSPI_INT_FT) && ((interrupt) != OSPI_INT_SM))
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/* check OSPI flag */
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#define NOT_OSPI_FLAG(flag) (((flag) != OSPI_FLAG_TERR) && ((flag) != OSPI_FLAG_TC) && \
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((flag) != OSPI_FLAG_SM) && ((flag) != OSPI_FLAG_BUSY))
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#endif /* FW_DEBUG_ERR_REPORT */
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/* function declarations */
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/* deinitialization initialization functions */
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/* reset OSPI */
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void ospi_deinit(uint32_t ospi_periph);
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/* initialize the parameters of OSPI struct with the default values */
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void ospi_struct_init(ospi_parameter_struct *ospi_struct);
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/* initialize OSPI parameter */
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void ospi_init(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct);
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/* enable OSPI */
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void ospi_enable(uint32_t ospi_periph);
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/* disable OSPI */
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void ospi_disable(uint32_t ospi_periph);
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/* device configuration functions */
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/* configure device memory type */
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void ospi_device_memory_type_config(uint32_t ospi_periph, uint32_t dtysel);
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/* configure device memory size */
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void ospi_device_memory_size_config(uint32_t ospi_periph, uint32_t mesz);
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/* functional mode functions */
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/* select functional mode */
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void ospi_functional_mode_config(uint32_t ospi_periph, uint32_t fmod);
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/* configure status polling mode */
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void ospi_status_polling_config(uint32_t ospi_periph, uint32_t stop, uint32_t mode);
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/* configure status mask */
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void ospi_status_mask_config(uint32_t ospi_periph, uint32_t mask);
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/* configure status match */
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void ospi_status_match_config(uint32_t ospi_periph, uint32_t match);
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/* configure interval cycle */
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void ospi_interval_cycle_config(uint32_t ospi_periph, uint16_t interval);
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/* OSPI mode functions */
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/* configure OSPI fifo threshold level */
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void ospi_fifo_level_config(uint32_t ospi_periph, uint32_t ftl);
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/* configure chip select high cycle */
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void ospi_chip_select_high_cycle_config(uint32_t ospi_periph, uint32_t cshc);
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/* configure OSPI prescaler */
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void ospi_prescaler_config(uint32_t ospi_periph, uint32_t psc);
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/* configure send instruction only once mode */
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void ospi_send_instruction_mode_config(uint32_t ospi_periph, uint32_t sioo);
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/* configure dummy cycles number */
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void ospi_dummy_cycles_config(uint32_t ospi_periph, uint32_t dumyc);
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/* configure delay hold 1/4 cycle */
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void ospi_delay_hold_cycle_config(uint32_t ospi_periph, uint32_t dehqc);
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/* configure sample shift */
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void ospi_sample_shift_config(uint32_t ospi_periph, uint32_t ssample);
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/* OSPI tansfer configuration functions */
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/* configure data length */
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void ospi_data_length_config(uint32_t ospi_periph, uint32_t dtlen);
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/* configure OSPI instruction */
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void ospi_instruction_config(uint32_t ospi_periph, uint32_t instruction);
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/* configure OSPI instruction mode */
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void ospi_instruction_mode_config(uint32_t ospi_periph, uint32_t imod);
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/* configure OSPI instruction size */
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void ospi_instruction_size_config(uint32_t ospi_periph, uint32_t inssz);
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/* configure OSPI address */
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void ospi_address_config(uint32_t ospi_periph, uint32_t addr);
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/* configure OSPI address mode */
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void ospi_address_mode_config(uint32_t ospi_periph, uint32_t addrmod);
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/* configure OSPI address dtr */
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void ospi_address_dtr_config(uint32_t ospi_periph, uint32_t addrdtr);
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/* configure OSPI address size */
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void ospi_address_size_config(uint32_t ospi_periph, uint32_t addrsz);
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/* configure alternate byte */
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void ospi_alternate_byte_config(uint32_t ospi_periph, uint32_t alte);
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/* configure OSPI alternate byte mode */
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void ospi_alternate_byte_mode_config(uint32_t ospi_periph, uint32_t atlemod);
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/* configure OSPI alternate byte dtr */
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void ospi_alternate_byte_dtr_config(uint32_t ospi_periph, uint32_t abdtr);
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/* configure OSPI alternate byte size */
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void ospi_alternate_byte_size_config(uint32_t ospi_periph, uint32_t altesz);
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/* configure data mode */
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void ospi_data_mode_config(uint32_t ospi_periph, uint32_t datamod);
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/* configure data size */
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void ospi_data_dtr_config(uint32_t ospi_periph, uint32_t dadtr);
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/* OSPI transmit data */
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void ospi_data_transmit(uint32_t ospi_periph, uint32_t data);
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/* OSPI receive data */
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uint32_t ospi_data_receive(uint32_t ospi_periph);
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/* OSPI DMA functions */
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/* enable OSPI DMA */
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void ospi_dma_enable(uint32_t ospi_periph);
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/* disable OSPI DMA */
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void ospi_dma_disable(uint32_t ospi_periph);
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/* OSPI wrap configuration functions */
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/* configure wrap size */
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void ospi_wrap_size_config(uint32_t ospi_periph, uint32_t wpsz);
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/* configure wrap instruction */
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void ospi_wrap_instruction_config(uint32_t ospi_periph, uint32_t instruction);
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/* configure wrap instruction mode */
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void ospi_wrap_instruction_mode_config(uint32_t ospi_periph, uint32_t imod);
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/* configure wrap instruction size */
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void ospi_wrap_instruction_size_config(uint32_t ospi_periph, uint32_t inssz);
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/* configure wrap address */
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void ospi_wrap_address_config(uint32_t ospi_periph, uint32_t addr);
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/* configure wrap address mode */
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void ospi_wrap_address_mode_config(uint32_t ospi_periph, uint32_t addrmod);
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/* configure wrap address dtr */
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void ospi_wrap_address_dtr_config(uint32_t ospi_periph, uint32_t addrdtr);
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/* configure wrap address size */
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void ospi_wrap_address_size_config(uint32_t ospi_periph, uint32_t addrsz);
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/* configure wrap alternate byte */
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void ospi_wrap_alternate_byte_config(uint32_t ospi_periph, uint32_t alte);
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/* configure wrap alternate bytes mode */
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void ospi_wrap_alternate_byte_mode_config(uint32_t ospi_periph, uint32_t atlemod);
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/* configure wrap alternate bytes dtr */
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void ospi_wrap_alternate_byte_dtr_config(uint32_t ospi_periph, uint32_t abdtr);
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/* configure wrap alternate bytes mode */
|
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void ospi_wrap_alternate_byte_size_config(uint32_t ospi_periph, uint32_t altesz);
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/* configure wrap data mode */
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void ospi_wrap_data_mode_config(uint32_t ospi_periph, uint32_t datamod);
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/* configure wrap data mode */
|
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void ospi_wrap_data_dtr_config(uint32_t ospi_periph, uint32_t dadtr);
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/* configure wrap dummy cycles number */
|
|
void ospi_wrap_dummy_cycles_config(uint32_t ospi_periph, uint32_t dumyc);
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/* delay hold 1/4 cycle in wrap */
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void ospi_wrap_delay_hold_cycle_config(uint32_t ospi_periph, uint32_t dehqc);
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/* configure sample shift in wrap */
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void ospi_wrap_sample_shift_config(uint32_t ospi_periph, uint32_t ssample);
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/* OSPI write configure functions */
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|
/* configure write instruction */
|
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void ospi_write_instruction_config(uint32_t ospi_periph, uint32_t instruction);
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/* configure write instruction mode */
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void ospi_write_instruction_mode_config(uint32_t ospi_periph, uint32_t imod);
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/* configure write instruction size */
|
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void ospi_write_instruction_size_config(uint32_t ospi_periph, uint32_t inssz);
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/* configure write address */
|
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void ospi_write_address_config(uint32_t ospi_periph, uint32_t addr);
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/* configure write address mode */
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void ospi_write_address_mode_config(uint32_t ospi_periph, uint32_t addrmod);
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/* configure write address dtr */
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void ospi_write_address_dtr_config(uint32_t ospi_periph, uint32_t addrdtr);
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/* configure write address size */
|
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void ospi_write_address_size_config(uint32_t ospi_periph, uint32_t addrsz);
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|
/* configure write alternate bytes mode */
|
|
void ospi_write_alternate_byte_config(uint32_t ospi_periph, uint32_t alte);
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/* configure write alternate byte mode */
|
|
void ospi_write_alternate_byte_mode_config(uint32_t ospi_periph, uint32_t atlemod);
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/* configure write alternate byte dtr */
|
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void ospi_write_alternate_byte_dtr_config(uint32_t ospi_periph, uint32_t abdtr);
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/* configure write alternate byte size */
|
|
void ospi_write_alternate_byte_size_config(uint32_t ospi_periph, uint32_t altesz);
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/* configure write data mode */
|
|
void ospi_write_data_mode_config(uint32_t ospi_periph, uint32_t datamod);
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|
/* configure write data dtr */
|
|
void ospi_write_data_dtr_config(uint32_t ospi_periph, uint32_t dadtr);
|
|
/* configure write dummy cycles number */
|
|
void ospi_write_dummy_cycles_config(uint32_t ospi_periph, uint32_t dumyc);
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|
|
|
/* configure OSPI regular command parameter */
|
|
void ospi_command_config(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct, ospi_regular_cmd_struct *cmd_struct);
|
|
/* transmit data */
|
|
void ospi_transmit(uint32_t ospi_periph, uint8_t *pdata);
|
|
/* receive data */
|
|
void ospi_receive(uint32_t ospi_periph, uint8_t *pdata);
|
|
/* configure the OSPI automatic polling mode */
|
|
void ospi_autopolling_mode(uint32_t ospi_periph, ospi_parameter_struct *ospi_struct, ospi_autopolling_struct *autopl_cfg_struct);
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|
|
|
/* flag & interrupt functions */
|
|
/* enable OSPI interrupt */
|
|
void ospi_interrupt_enable(uint32_t ospi_periph, uint32_t interrupt);
|
|
/* disable OSPI interrupt */
|
|
void ospi_interrupt_disable(uint32_t ospi_periph, uint32_t interrupt);
|
|
/* get OSPI fifo level */
|
|
uint32_t ospi_fifo_level_get(uint32_t ospi_periph);
|
|
/* get OSPI flag status */
|
|
FlagStatus ospi_flag_get(uint32_t ospi_periph, uint32_t flag);
|
|
/* clear OSPI flag status */
|
|
void ospi_flag_clear(uint32_t ospi_periph, uint32_t flag);
|
|
/* get OSPI interrupt status */
|
|
FlagStatus ospi_interrupt_flag_get(uint32_t ospi_periph, ospi_interrupt_flag_enum int_flag);
|
|
/* clear OSPI interrupt flag status */
|
|
void ospi_interrupt_flag_clear(uint32_t ospi_periph, ospi_interrupt_flag_enum int_flag);
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|
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#endif /* GD32H75E_OSPI_H */
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