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292 lines
21 KiB
292 lines
21 KiB
/*!
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\file gd32h75e_efuse.h
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\brief definitions for the EFUSE
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\version 2025-08-07, V1.2.0, firmware for GD32H75E
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H75E_EFUSE_H
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#define GD32H75E_EFUSE_H
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#include "gd32h75e.h"
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/* EFUSE definitions */
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#define EFUSE EFUSE_BASE /*!< EFUSE base address */
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/* registers definitions */
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#define EFUSE_CTL REG32(EFUSE + 0x00000000U) /*!< EFUSE control register */
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#define EFUSE_ADDR REG32(EFUSE + 0x00000004U) /*!< EFUSE address register */
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#define EFUSE_STAT REG32(EFUSE + 0x0000000CU) /*!< EFUSE status register */
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#define EFUSE_STATC REG32(EFUSE + 0x00000010U) /*!< EFUSE status clear register */
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#define EFUSE_USER_CTL REG32(EFUSE + 0x00000014U) /*!< EFUSE user control register */
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#define EFUSE_MCU_RSV REG32(EFUSE + 0x00000018U) /*!< EFUSE MCU reserved register */
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#define EFUSE_DP0 REG32(EFUSE + 0x0000001CU) /*!< EFUSE debug password register 0 */
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#define EFUSE_DP1 REG32(EFUSE + 0x00000020U) /*!< EFUSE debug password register 1 */
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#define EFUSE_AES_KEY0 REG32(EFUSE + 0x00000024U) /*!< EFUSE firmware AES key register 0 */
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#define EFUSE_AES_KEY1 REG32(EFUSE + 0x00000028U) /*!< EFUSE firmware AES key register 1 */
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#define EFUSE_AES_KEY2 REG32(EFUSE + 0x0000002CU) /*!< EFUSE firmware AES key register 2 */
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#define EFUSE_AES_KEY3 REG32(EFUSE + 0x00000030U) /*!< EFUSE firmware AES key register3 */
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#define EFUSE_USER_DATA0 REG32(EFUSE + 0x00000034U) /*!< EFUSE user data register 0 */
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#define EFUSE_USER_DATA1 REG32(EFUSE + 0x00000038U) /*!< EFUSE user data register 1 */
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#define EFUSE_USER_DATA2 REG32(EFUSE + 0x0000003CU) /*!< EFUSE user data register 2 */
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#define EFUSE_USER_DATA3 REG32(EFUSE + 0x00000040U) /*!< EFUSE user data register 3 */
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/* bits definitions */
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/* EFUSE_CTL */
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#define EFUSE_CTL_EFSTR BIT(0) /*!< start EFUSE operation */
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#define EFUSE_CTL_EFRW BIT(1) /*!< selection of EFUSE operation */
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#define EFUSE_CTL_MPVEN BIT(15) /*!< enable bit for program-voltage monitoring function */
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#define EFUSE_CTL_IAERRIE BIT(16) /*!< enable bit for illegal access error interrupt */
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#define EFUSE_CTL_PGIE BIT(17) /*!< enable bit for program complete interrupt */
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#define EFUSE_CTL_RDIE BIT(18) /*!< enable bit for read complete interrupt */
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#define EFUSE_CTL_PVIE BIT(19) /*!< enable bit for program voltage setting error interrupt */
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#define EFUSE_CTL_AES_KEY_CRC BITS(24,31) /*!< 8-bits CRC calculation result value of AES key bits */
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/* EFUSE_ADDR */
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#define EFUSE_ADDR_EFADDR BITS(0,9) /*!< read or write EFUSE data start address */
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#define EFUSE_ADDR_EFSIZE BITS(10,14) /*!< read or write EFUSE data size */
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/* EFUSE_STAT */
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#define EFUSE_STAT_IAERRIF BIT(0) /*!< illegal access error flag */
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#define EFUSE_STAT_PGIF BIT(1) /*!< program complete flag */
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#define EFUSE_STAT_RDIF BIT(2) /*!< read complete flag */
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#define EFUSE_STAT_PVIF BIT(3) /*!< program voltage setting error flag */
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#define EFUSE_STAT_LDO_RDY BIT(4) /*!< EFUSE LDO ready signal */
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/* EFUSE_STATC */
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#define EFUSE_STATC_IAERRIC BIT(0) /*!< clear bit for illegal access error interrupt */
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#define EFUSE_STATC_PGIC BIT(1) /*!< clear bit for program complete interrupt flag */
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#define EFUSE_STATC_RDIC BIT(2) /*!< clear bit for read complete interrupt flag */
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#define EFUSE_STATC_PVIC BIT(3) /*!< clear bit for program voltage setting error interrupt flag */
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/* EFUSE_USER_CTL */
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#define EFUSE_USER_CTL_DPLK BIT(0) /*!< EFUSE_DP register lock bit */
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#define EFUSE_USER_CTL_SCRLK BIT(1) /*!< secure-access area start/end address lock bit */
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#define EFUSE_USER_CTL_UCLK BIT(2) /*!< low 16 bits of EFUSE_USER_CTL register lock bit */
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#define EFUSE_USER_CTL_AESEN BIT(3) /*!< lock EFUSE_AES_KEY register and enable AES decrypt function */
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#define EFUSE_USER_CTL_UDLK BIT(4) /*!< EFUSE_USER_DATA register lock bit */
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#define EFUSE_USER_CTL_NDBG BITS(8,9) /*!< debug mode setting bit */
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#define EFUSE_USER_CTL_JTAGNSW BIT(10) /*!< debugger select bit */
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#define EFUSE_USER_CTL_SPC_L BIT(11) /*!< low security protection */
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#define EFUSE_USER_CTL_SPC_H BIT(12) /*!< high security protection */
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#define EFUSE_USER_CTL_SCR BIT(13) /*!< secure access mode enable bit */
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#define EFUSE_USER_CTL_ESPI_START_MODE BITS(14,15) /*!< external SPI start mode */
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#define EFUSE_USER_CTL_SCR_AREA_START BITS(16,23) /*!< secure-access area start address */
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#define EFUSE_USER_CTL_SCR_AREA_END BITS(24,31) /*!< secure-access area end address */
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/* EFUSE_MCU_RSV */
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#define EFUSE_MCU_RSV_DISLFI BIT(6) /*!< disable bit for licensed firmware install (LFI) */
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#define EFUSE_MCU_RSV_VFIMG BIT(7) /*!< enable bit for verify firmware image */
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#define EFUSE_MCU_RSV_MCURSVLK BIT(8) /*!< lock bit for low 16 bits of EFUSE_MCU_RSV register */
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#define EFUSE_MCU_RSV_DCRPLK BIT(9) /*!< lock bit for DCRP area start/end address */
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#define EFUSE_MCU_RSV_MCU_RSV BITS(10,15) /*!< MCU reserved value */
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#define EFUSE_MCU_RSV_DCRP_AREA_START BITS(16,23) /*!< DCRP area start address */
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#define EFUSE_MCU_RSV_DCRP_AREA_END BITS(24,31) /*!< DCRP area end address */
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/* EFUSE_DP */
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#define EFUSE_DP_DP BITS(0,31) /*!< EFUSE Debug password value */
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/* EFUSE_AES_KEY */
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#define EFUSE_AES_KEY_AESKEY BITS(0,31) /*!< EFUSE AES key value */
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/* EFUSE_USER_DATA */
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#define EFUSE_USER_DATA_USERDATA BITS(0,31) /*!< EFUSE USER_DATA value */
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/* constants definitions */
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/* define the EFUSE bit position and its register index offset */
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#define EFUSE_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
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#define EFUSE_REG_VAL(offset) (REG32(EFUSE + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
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#define EFUSE_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
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#define EFUSE_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
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| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
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#define EFUSE_REG_VAL2(offset) (REG32(EFUSE + ((uint32_t)(offset) >> 22)))
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#define EFUSE_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
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/* register offset */
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#define EFUSE_CTL_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */
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#define EFUSE_STAT_REG_OFFSET ((uint32_t)0x0000000CU) /*!< STAT register offset */
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#define EFUSE_STATC_REG_OFFSET ((uint32_t)0x00000010U) /*!< STATC register offset */
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/* EFUSE interrupt flags */
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typedef enum {
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EFUSE_INT_FLAG_ILLEGAL_ACCESS_ERR = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 16U, EFUSE_STAT_REG_OFFSET, 0U), /*!< illegal access error interrupt flag */
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EFUSE_INT_FLAG_PROGRAM_COMPLETE = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 17U, EFUSE_STAT_REG_OFFSET, 1U), /*!< programming operation completion interrupt flag */
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EFUSE_INT_FLAG_READ_COMPLETE = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 18U, EFUSE_STAT_REG_OFFSET, 2U), /*!< read operation completion interrupt flag */
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EFUSE_INT_FLAG_PROGRAM_VOLTAGE_ERR = EFUSE_REGIDX_BIT2(EFUSE_CTL_REG_OFFSET, 19U, EFUSE_STAT_REG_OFFSET, 3U), /*!< program voltage setting error flag */
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} efuse_interrupt_flag_enum;
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/* EFUSE flag */
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#define EFUSE_FLAG_LDO_READY EFUSE_STAT_LDO_RDY /*!< EFUSE LDO ready signal flag */
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#define EFUSE_FLAG_ILLEGAL_ACCESS_ERR EFUSE_STAT_IAERRIF /*!< illegal access error flag */
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#define EFUSE_FLAG_PROGRAM_COMPLETE EFUSE_STAT_PGIF /*!< programming operation completion flag */
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#define EFUSE_FLAG_READ_COMPLETE EFUSE_STAT_RDIF /*!< read operation completion flag */
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#define EFUSE_FLAG_PROGRAM_VOLTAGE_ERR EFUSE_STAT_PVIF /*!< program voltage setting error flag */
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/* EFUSE flag clear */
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#define EFUSE_FLAG_ILLEGAL_ACCESS_ERR_CLR EFUSE_STATC_IAERRIC /*!< clear illegal access error flag */
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#define EFUSE_FLAG_PROGRAM_COMPLETE_CLR EFUSE_STATC_PGIC /*!< clear programming operation completion flag */
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#define EFUSE_FLAG_READ_COMPLETE_CLR EFUSE_STATC_RDIC /*!< clear read operation completion flag */
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#define EFUSE_FLAG_PROGRAM_VOLTAGE_ERR_CLR EFUSE_STATC_PVIC /*!< clear program voltage setting error interrupt flag */
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/* EFUSE interrupt enable */
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#define EFUSE_INT_ILLEGAL_ACCESS_ERR EFUSE_CTL_IAERRIE /*!< illegal access error interrupt enable */
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#define EFUSE_INT_PROGRAM_COMPLETE EFUSE_CTL_PGIE /*!< programming operation completion interrupt enable */
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#define EFUSE_INT_READ_COMPLETE EFUSE_CTL_RDIE /*!< read operation completion interrupt enable */
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#define EFUSE_INT_PROGRAM_VOLTAGE_ERR EFUSE_CTL_PVIE /*!< program voltage setting error interrupt enable */
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/* EFUSE interrupt flag clear */
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#define EFUSE_INT_FLAG_ILLEGAL_ACCESS_ERR_CLR EFUSE_STATC_IAERRIC /*!< clear illegal access error interrupt flag */
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#define EFUSE_INT_FLAG_PROGRAM_COMPLETE_CLR EFUSE_STATC_PGIC /*!< clear programming operation completion interrupt flag */
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#define EFUSE_INT_FLAG_READ_COMPLETE_CLR EFUSE_STATC_RDIC /*!< clear read operation completion interrupt flag */
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#define EFUSE_INT_FLAG_PROGRAM_VOLTAGE_ERR_CLR EFUSE_STATC_PVIC /*!< clear program voltage setting error interrupt flag */
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/* EFUSE system parameter size enum, in byte unit */
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typedef enum {
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USER_CTL_MCU_RESERVED_SIZE = 4U, /*!< user control parameter size,MCU reserved parameter size */
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DP_SIZE = 8U, /*!< debug password parameter size */
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AES_KEY_SIZE = 16U, /*!< AES key parameter size */
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USER_DATA_SIZE = 16U, /*!< user data parameter size */
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} efuse_system_para_size_enum;
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/* EFUSE system parameter index */
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typedef enum {
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USER_CTL_IDX = 0U, /*!< index of user control parameter */
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MCU_RESERVED_IDX = 1U, /*!< index of MCU reserved parameter */
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DP_IDX = 2U, /*!< index of debug password parameter */
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AES_KEY_IDX = 3U, /*!< index of AES key parameter */
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USER_DATA_IDX = 4U, /*!< index of user data parameter */
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} efuse_system_para_index_enum;
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/* EFUSE state */
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typedef enum {
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EFUSE_READY = 0U, /*!< operation has been completed */
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EFUSE_BUSY, /*!< operation is in progress */
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EFUSE_IAERR, /*!< illegal access error */
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EFUSE_PVERR, /*!< program voltage setting error */
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EFUSE_TOERR, /*!< timeout error */
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} efuse_state_enum;
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/* EFADDR of EFUSE system parameters */
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#define USER_CTL_EFADDR ((uint32_t)0x00000000U) /*!< user control parameter start address */
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#define MCU_RESERVED_EFADDR ((uint32_t)0x00000020U) /*!< MCU reserved parameter start address */
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#define DP_EFADDR ((uint32_t)0x00000040U) /*!< debug password parameter start address */
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#define AES_KEY_EFADDR ((uint32_t)0x00000080U) /*!< AES key parameter start address */
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#define USER_DATA_EFADDR ((uint32_t)0x00000100U) /*!< user data parameter start address */
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#define MAX_EFADDR ((uint32_t)0x0000017FU) /*!< max efuse address */
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#define EFUSE_PARA_CNT ((uint32_t)0x00000005U) /*!< the count of system parameters in EFUSE */
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/* EFUSE parameters' register address */
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#define EFUSE_USER_CTL_REG_ADDR (EFUSE + 0x00000014U) /*!< user control register address */
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#define EFUSE_MCU_RSV_REG_ADDR (EFUSE + 0x00000018U) /*!< MCU reserved register address */
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#define EFUSE_DP_REG_ADDR (EFUSE + 0x0000001CU) /*!< debug password register address */
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#define EFUSE_AES_KEY_REG_ADDR (EFUSE + 0x00000024U) /*!< AES key register address */
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#define EFUSE_USER_DATA_REG_ADDR (EFUSE + 0x00000034U) /*!< user data register address */
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/* parameter check definitions */
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#ifdef FW_DEBUG_ERR_REPORT
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/* check efuse addresss to be read */
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#define NOT_EFUSE_ADDR(addr) (((addr) != USER_CTL_EFADDR) && ((addr) != MCU_RESERVED_EFADDR) && \
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((addr) != DP_EFADDR) && ((addr) != USER_DATA_EFADDR))
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/* check efuse size to be read*/
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#define NOT_EFUSE_SIZE(size) (((size) != USER_CTL_MCU_RESERVED_SIZE) && ((size) != DP_SIZE) && ((size) != USER_DATA_SIZE))
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/* check efuse size to be programmed*/
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#define NOT_EFUSE_VALID_SIZE(size) (((size) == 0U) || ((size) > 16U))
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/* check efuse addresss to be programmed */
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#define NOT_EFUSE_VALID_ADDR(addr) ((((addr) % 8U) != 0U) || ((addr) > MAX_EFADDR))
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/* check efuse addresss configuration */
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#define NOT_EFUSE_VALID_ADDR_CONFIG5(ef_addr, size) (((ef_addr) >= USER_DATA_EFADDR) && (((ef_addr) + (size) * 8U - 1U) > MAX_EFADDR))
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/* check efuse addresss configuration */
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#define NOT_EFUSE_VALID_ADDR_CONFIG4(ef_addr, size) (((ef_addr) >= AES_KEY_EFADDR) && ((ef_addr) < USER_DATA_EFADDR) && (((ef_addr) + (size) * 8U - 1U) > USER_DATA_EFADDR))
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/* check efuse addresss configuration */
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#define NOT_EFUSE_VALID_ADDR_CONFIG3(ef_addr, size) (((ef_addr) >= DP_EFADDR) && ((ef_addr) < AES_KEY_EFADDR) && (((ef_addr) + ((size) * 8U - 1U)) > AES_KEY_EFADDR))
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/* check efuse addresss configuration */
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#define NOT_EFUSE_VALID_ADDR_CONFIG2(ef_addr, size) (((ef_addr) >= MCU_RESERVED_EFADDR) && ((ef_addr) < DP_EFADDR) && (((ef_addr) + (size) * 8U - 1U) > DP_EFADDR))
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/* check efuse addresss configuration */
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#define NOT_EFUSE_VALID_ADDR_CONFIG1(ef_addr, size) (((ef_addr) < MCU_RESERVED_EFADDR) && (((ef_addr) + (size) * 8U - 1U) > MCU_RESERVED_EFADDR))
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/* check efuse addresss configuration */
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#define NOT_EFUSE_VALID_ADDR_CONFIG0(ef_addr, size) (((ef_addr) >= AES_KEY_EFADDR) && ((ef_addr) < USER_DATA_EFADDR) && ((size) != AES_KEY_SIZE))
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/* check efuse flag */
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#define NOT_EFUSE_FLAG(flag) (((flag) != EFUSE_FLAG_ILLEGAL_ACCESS_ERR) && ((flag) != EFUSE_FLAG_PROGRAM_COMPLETE) && \
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((flag) != EFUSE_FLAG_READ_COMPLETE) && ((flag) != EFUSE_FLAG_PROGRAM_VOLTAGE_ERR))
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/* check efuse flag clear */
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#define NOT_EFUSE_FLAG_CLR(flag_clear) (((flag_clear) != EFUSE_FLAG_ILLEGAL_ACCESS_ERR_CLR) && ((flag_clear) != EFUSE_FLAG_PROGRAM_COMPLETE_CLR) && \
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((flag_clear) != EFUSE_FLAG_READ_COMPLETE_CLR) && ((flag_clear) != EFUSE_FLAG_PROGRAM_VOLTAGE_ERR_CLR))
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/* check efuse interrupt */
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#define NOT_EFUSE_INT(int_en) (((int_en) != EFUSE_INT_ILLEGAL_ACCESS_ERR) && ((int_en) != EFUSE_INT_PROGRAM_COMPLETE) && \
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((int_en) != EFUSE_INT_READ_COMPLETE) && ((int_en) != EFUSE_INT_PROGRAM_VOLTAGE_ERR))
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/* check efuse interrupt flag clear */
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#define NOT_EFUSE_INT_FLAG_CLR(int_flag_clear) (((int_flag_clear) != EFUSE_INT_FLAG_ILLEGAL_ACCESS_ERR_CLR) && ((int_flag_clear) != EFUSE_INT_FLAG_PROGRAM_COMPLETE_CLR) && \
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((int_flag_clear) != EFUSE_INT_FLAG_READ_COMPLETE_CLR) && ((int_flag_clear) != EFUSE_INT_FLAG_PROGRAM_VOLTAGE_ERR_CLR))
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#endif /* FW_DEBUG_ERR_REPORT */
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/* function declarations */
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/* EFUSE operation functions */
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/* read system parameters from EFUSE macro to registers */
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ErrStatus efuse_read(uint32_t ef_addr, uint32_t size, uint32_t buf[]);
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/* program register values to EFUSE macro system parameters */
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ErrStatus efuse_write(uint32_t ef_addr, uint32_t size, uint8_t *buf);
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/* program all user control parameters */
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ErrStatus efuse_user_control_write(uint8_t *buf);
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/* program all MCU reserved parameters */
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ErrStatus efuse_mcu_reserved_write(uint8_t *buf);
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/* program all debug password parameters */
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ErrStatus efuse_dp_write(uint8_t *buf);
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/* program all AES key parameters */
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ErrStatus efuse_aes_key_write(uint8_t *buf);
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/* program all user data parameters */
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ErrStatus efuse_user_data_write(uint8_t *buf);
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/* FMC universal functions */
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/* get 8-bits CRC calculation result value of AES key */
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uint8_t efuse_aes_key_crc_get(void);
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/* enable monitor program voltage function */
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void efuse_monitor_program_voltage_enable(void);
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/* disable monitor program voltage function */
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void efuse_monitor_program_voltage_disable(void);
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/* get monitor program voltage function */
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FlagStatus efuse_monitor_program_voltage_get(void);
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/* get ldo ready signal */
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FlagStatus efuse_ldo_ready_get(void);
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/* flag and interrupt functions */
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/* check EFUSE flag is set or not */
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FlagStatus efuse_flag_get(uint32_t flag);
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/* clear EFUSE pending flag */
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void efuse_flag_clear(uint32_t flag);
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/* enable EFUSE interrupt */
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void efuse_interrupt_enable(uint32_t interrupt);
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/* disable EFUSE interrupt */
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void efuse_interrupt_disable(uint32_t interrupt);
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/* check EFUSE interrupt flag is set or not */
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FlagStatus efuse_interrupt_flag_get(efuse_interrupt_flag_enum int_flag);
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/* clear EFUSE pending interrupt flag */
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void efuse_interrupt_flag_clear(uint32_t int_flag);
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#endif /* GD32H75E_EFUSE_H */
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