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325 lines
21 KiB
325 lines
21 KiB
/*!
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\file gd32h75e_pmu.h
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\brief definitions for the PMU
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\version 2025-08-07, V1.2.0, firmware for GD32H75E
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H75E_PMU_H
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#define GD32H75E_PMU_H
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#include "gd32h75e.h"
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/* PMU definitions */
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#define PMU PMU_BASE /*!< PMU base address */
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/* registers definitions */
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#define PMU_CTL0 REG32((PMU) + 0x00000000U) /*!< PMU control register 0 */
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#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */
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#define PMU_CTL1 REG32((PMU) + 0x00000008U) /*!< PMU control register 1 */
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#define PMU_CTL2 REG32((PMU) + 0x00000010U) /*!< PMU control register 2 */
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#define PMU_CTL3 REG32((PMU) + 0x00000014U) /*!< PMU control register 3 */
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#define PMU_PAR REG32((PMU) + 0x00000018U) /*!< PMU parameter register */
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/* bits definitions */
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/* PMU_CTL0 */
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#define PMU_CTL0_STBMOD BIT(1) /*!< standby mode */
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#define PMU_CTL0_WURST BIT(2) /*!< wakeup flag reset */
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#define PMU_CTL0_STBRST BIT(3) /*!< standby flag reset */
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#define PMU_CTL0_LVDEN BIT(4) /*!< low voltage detector enable */
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#define PMU_CTL0_LVDT BITS(5,7) /*!< low voltage detector threshold */
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#define PMU_CTL0_BKPWEN BIT(8) /*!< backup domain write enable */
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#define PMU_CTL0_SLDOVS BITS(14,15) /*!< deep sleep mode mode LDO output voltage select */
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#define PMU_CTL0_VAVDEN BIT(16) /*!< VDDA analog voltage detector enable */
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#define PMU_CTL0_VAVDVC BITS(17,18) /*!< VDDA analog voltage detector level configure bits */
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#define PMU_CTL0_VOVDEN BIT(19) /*!< peripheral voltage on V0.9V detector enable bit */
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/* PMU_CS */
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#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
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#define PMU_CS_STBF BIT(1) /*!< standby flag */
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#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
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#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin0(PA0) enable */
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#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin1(PA2) enable */
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#define PMU_CS_WUPEN3 BIT(11) /*!< wakeup pin3(PC13) enable */
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#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin5(PC1) enable */
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#define PMU_CS_VAVDF BIT(16) /*!< VDDA analog voltage detector voltage output on VDDA flag */
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#define PMU_CS_VOVDF BIT(20) /*!< peripheral voltage on V0.9V detector flag bit */
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/* PMU_CTL1 */
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#define PMU_CTL1_BKPVSEN BIT(0) /*!< backup voltage stabilizer enable */
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#define PMU_CTL1_VBTMEN BIT(4) /*!< VBAT and temperature monitoring enable */
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#define PMU_CTL1_BKPVSRF BIT(16) /*!< backup regulator ready */
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#define PMU_CTL1_VBATLF BIT(20) /*!< VBAT level monitoring versus low threshold */
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#define PMU_CTL1_VBATHF BIT(21) /*!< VBAT level monitoring versus high threshold */
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#define PMU_CTL1_TEMPLF BIT(22) /*!< temperature level monitoring versus low threshold */
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#define PMU_CTL1_TEMPHF BIT(23) /*!< temperature level monitoring versus high threshold */
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/* PMU_CTL2 */
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#define PMU_CTL2_BYPASS BIT(0) /*!< power management unit bypass control bit */
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#define PMU_CTL2_LDOEN BIT(1) /*!< Low drop-out voltage stabilizer enable bit */
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#define PMU_CTL2_DVSEN BIT(2) /*!< step-down voltage stabilizer enable bit */
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#define PMU_CTL2_VCRSEL BIT(8) /*!< VBAT battery charging resistor selection */
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#define PMU_CTL2_VCEN BIT(9) /*!< VBAT battery charging enable */
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#define PMU_CTL2_DVSRF BIT(16) /*!< step-down voltage stabilizer ready flag bit */
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#define PMU_CTL2_VUSB33DEN BIT(24) /*!< VDD33USB voltage level detector enable bit */
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#define PMU_CTL2_USBSEN BIT(25) /*!< USB voltage stabilizer enable */
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#define PMU_CTL2_USB33RF BIT(26) /*!< USB supply ready flag */
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/* PMU_CTL3 */
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#define PMU_CTL3_LDOVS BITS(12,14) /*!< voltage scaling selection according to performance */
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#define PMU_CTL3_VOVRF BIT(16) /*!< V0.9V voltage ready bit */
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/* PMU_PAR */
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#define PMU_PAR_CNT BITS(0,11) /*!< exit deep-sleep mode wait time count configure bits */
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#define PMU_PAR_TSW_IRCCNT BITS(16,20) /*!< when enter deep-sleep, switch to IRC wait clock */
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/* constants definitions */
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/* PMU low voltage detector threshold definitions */
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#define CTL0_LVDT(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U))
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#define PMU_LVDT_0 CTL0_LVDT(0) /*!< voltage threshold is 1.90V */
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#define PMU_LVDT_1 CTL0_LVDT(1) /*!< voltage threshold is 2.05V */
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#define PMU_LVDT_2 CTL0_LVDT(2) /*!< voltage threshold is 2.20V */
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#define PMU_LVDT_3 CTL0_LVDT(3) /*!< voltage threshold is 2.35V */
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#define PMU_LVDT_4 CTL0_LVDT(4) /*!< voltage threshold is 2.50V */
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#define PMU_LVDT_5 CTL0_LVDT(5) /*!< voltage threshold is 2.65V */
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#define PMU_LVDT_6 CTL0_LVDT(6) /*!< voltage threshold is 2.80V */
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#define PMU_LVDT_7 CTL0_LVDT(7) /*!< input analog voltage on PB7 (compared with 0.8V) */
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/* PMU deep-sleep mode voltage scaling selection */
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#define CTL0_SLDOVS(regval) (BITS(14,15) & ((uint32_t)(regval) << 14U))
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#define PMU_SLDOVS_0 CTL0_SLDOVS(0) /*!< SLDOVS scale 0.6V */
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#define PMU_SLDOVS_1 CTL0_SLDOVS(1) /*!< SLDOVS scale 0.7V */
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#define PMU_SLDOVS_2 CTL0_SLDOVS(2) /*!< SLDOVS scale 0.8V (default) */
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#define PMU_SLDOVS_3 CTL0_SLDOVS(3) /*!< SLDOVS scale 0.9V */
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/* PMU analog voltage detector threshold definitions */
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#define CTL0_VAVDVC(regval) (BITS(17,18) & ((uint32_t)(regval) << 17U))
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#define PMU_VAVDVC_0 CTL0_VAVDVC(0) /*!< voltage threshold is 1.7V */
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#define PMU_VAVDVC_1 CTL0_VAVDVC(1) /*!< voltage threshold is 2.1V */
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#define PMU_VAVDVC_2 CTL0_VAVDVC(2) /*!< voltage threshold is 2.5V */
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#define PMU_VAVDVC_3 CTL0_VAVDVC(3) /*!< voltage threshold is 2.8V */
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/* PMU VBAT battery charging resistor selection */
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#define CTL2_VCRSEL(regval) (BIT(9) & ((uint32_t)(regval) << 9U))
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#define PMU_VCRSEL_5K CTL2_VCRSEL(0) /*!< 5 kOhms resistor is selected for charing VBAT battery */
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#define PMU_VCRSEL_1P5K CTL2_VCRSEL(1) /*!< 1.5 kOhms resistor is selected for charing VBAT battery */
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/* PMU LDO output voltage select definitions */
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#define CTL3_LDOVS(regval) (BITS(12,14) & ((uint32_t)(regval) << 12U))
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#define PMU_LDOVS_0 CTL3_LDOVS(0) /*!< LDO output voltage 0.8V mode */
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#define PMU_LDOVS_1 CTL3_LDOVS(1) /*!< LDO output voltage 0.85V mode */
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#define PMU_LDOVS_2 CTL3_LDOVS(2) /*!< LDO output voltage 0.9V mode */
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#define PMU_LDOVS_3 CTL3_LDOVS(3) /*!< LDO output voltage 0.95V mode */
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#define PMU_LDOVS_4 CTL3_LDOVS(4) /*!< LDO output voltage 0.975V mode */
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#define PMU_LDOVS_5 CTL3_LDOVS(5) /*!< LDO output voltage 1V mode */
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/* PMU flag definitions */
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#define PMU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
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#define PMU_REG_VAL(periph) (REG32(PMU + ((uint32_t)(periph) >> 6U)))
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#define PMU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
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#define PMU_CTL0_OFFSET (0x00000000U) /*!< PMU control register 0 offset */
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#define PMU_CS_OFFSET (0x00000004U) /*!< PMU control and status register offset */
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#define PMU_CTL1_OFFSET (0x00000008U) /*!< PMU control register 1 offset */
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#define PMU_CTL2_OFFSET (0x00000010U) /*!< PMU control register 2 offset */
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#define PMU_CTL3_OFFSET (0x00000014U) /*!< PMU control register 3 offset */
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#define PMU_PAR_OFFSET (0x00000018U) /*!< PMU parameter register offset */
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#define PMU_FLAG_WAKEUP PMU_REGIDX_BIT(PMU_CS_OFFSET, 0) /*!< wakeup flag */
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#define PMU_FLAG_STANDBY PMU_REGIDX_BIT(PMU_CS_OFFSET, 1) /*!< standby flag */
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#define PMU_FLAG_LVDF PMU_REGIDX_BIT(PMU_CS_OFFSET, 2) /*!< low voltage detector status flag */
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#define PMU_FLAG_VAVDF PMU_REGIDX_BIT(PMU_CS_OFFSET, 16) /*!< VDDA analog voltage detector voltage output on VDDA flag */
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#define PMU_FLAG_VOVDF PMU_REGIDX_BIT(PMU_CS_OFFSET, 20) /*!< peripheral voltage on VDDA detector flag */
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#define PMU_FLAG_BKPVSRF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 16) /*!< backup voltage stabilizer ready flag */
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#define PMU_FLAG_VBATLF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 20) /*!< VBAT level monitoring versus low threshold */
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#define PMU_FLAG_VBATHF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 21) /*!< VBAT level monitoring versus high threshold */
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#define PMU_FLAG_TEMPLF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 22) /*!< temperature level monitoring versus low threshold */
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#define PMU_FLAG_TEMPHF PMU_REGIDX_BIT(PMU_CTL1_OFFSET, 23) /*!< temperature level monitoring versus high threshold */
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#define PMU_FLAG_DVSRF PMU_REGIDX_BIT(PMU_CTL2_OFFSET, 16) /*!< step-down voltage stabilizer ready flag bit */
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#define PMU_FLAG_USB33RF PMU_REGIDX_BIT(PMU_CTL2_OFFSET, 26) /*!< USB supply ready flag bit */
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#define PMU_FLAG_PWRRF PMU_REGIDX_BIT(PMU_CTL3_OFFSET, 16) /*!< Power Ready flag bit */
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/* PMU wakeup pin definitions */
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#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< wakeup pin 0 */
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#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< wakeup pin 1 */
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#define PMU_WAKEUP_PIN3 PMU_CS_WUPEN3 /*!< wakeup pin 3 */
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#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< wakeup pin 5 */
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/* PMU SMPS LDO supply mode definitions */
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#define PMU_LDO_SUPPLY PMU_CTL2_LDOEN /*!< V0.9V domains are suppplied from the LDO */
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#define PMU_DIRECT_SMPS_SUPPLY PMU_CTL2_DVSEN /*!< V0.9V domains are suppplied from the SMPS only */
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#define PMU_BYPASS PMU_CTL2_BYPASS /*!< The SMPS disabled and the LDO Bypass. The V0.9V domains are supplied from an external source */
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/* PMU command constants definitions */
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#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
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#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
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/* parameter check definitions */
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#ifdef FW_DEBUG_ERR_REPORT
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/* check PMU low voltage detector threshold */
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#define NOT_PMU_LVD(lvdt_n) (((lvdt_n) != PMU_LVDT_0) && ((lvdt_n) != PMU_LVDT_1) && \
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((lvdt_n) != PMU_LVDT_2) && ((lvdt_n) != PMU_LVDT_3) && \
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((lvdt_n) != PMU_LVDT_4) && ((lvdt_n) != PMU_LVDT_5) && \
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((lvdt_n) != PMU_LVDT_6) && ((lvdt_n) != PMU_LVDT_7))
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/* check PMU analog voltage detector threshold */
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#define NOT_PMU_VAVD(vavdt_n) (((vavdt_n) != PMU_VAVDVC_0) && ((vavdt_n) != PMU_VAVDVC_1) && \
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((vavdt_n) != PMU_VAVDVC_2) && ((vavdt_n) != PMU_VAVDVC_3))
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/* check PMU V0.9V core voltage level */
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#define NOT_PMU_LDO(ldo_n) (((ldo_n) != PMU_LDOVS_0) && ((ldo_n) != PMU_LDOVS_1) && \
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((ldo_n) != PMU_LDOVS_2) && ((ldo_n) != PMU_LDOVS_3) && \
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((ldo_n) != PMU_LDOVS_4) && ((ldo_n) != PMU_LDOVS_5))
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/* check PMU Deep-sleep mode V0.9V core voltage select */
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#define NOT_PMU_SLDO(sldo_n) (((sldo_n) != PMU_SLDOVS_0) && ((sldo_n) != PMU_SLDOVS_1) && \
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((sldo_n) != PMU_SLDOVS_2) && ((sldo_n) != PMU_SLDOVS_3))
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/* check PMU VBAT battery charging resistor selection */
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#define NOT_PMU_VBAT(resistor) (((resistor) != PMU_VCRSEL_5K) && ((resistor) != PMU_VCRSEL_1P5K))
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/* check PMU power supply */
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#define NOT_PMU_SMPS_LDO_SUPPLY(smpsmode) (((smpsmode) != PMU_LDO_SUPPLY) && ((smpsmode) != PMU_DIRECT_SMPS_SUPPLY) && \
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((smpsmode) != PMU_BYPASS))
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/* check PMU sleep mode */
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#define NOT_PMU_SLEEPMODE(sleepmodecmd) (((sleepmodecmd) != WFI_CMD) && ((sleepmodecmd) != WFE_CMD))
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/* check PMU deepsleep mode */
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#define NOT_PMU_DEEPSLEEPMODE(deepsleepmodecmd) (((deepsleepmodecmd) != WFI_CMD) && ((deepsleepmodecmd) != WFE_CMD))
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/* check PMU wakeup pin */
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#define NOT_PMU_WAKEUP_PIN(wakeup_pin) (((wakeup_pin) != PMU_WAKEUP_PIN0) && ((wakeup_pin) != PMU_WAKEUP_PIN1) && \
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((wakeup_pin) != PMU_WAKEUP_PIN3) && ((wakeup_pin) != PMU_WAKEUP_PIN5))
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/* check PMU IRC counter before enter Deep-sleep mode */
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#define NOT_PMU_ENTER_DEEPSLEEP_WAIT_TIME(wait_time) (((wait_time) > 0x1F) || ((wait_time) < 0x0))
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/* check PMU IRC counter before exit Deep-sleep mode */
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#define NOT_PMU_EXIT_DEEPSLEEP_WAIT_TIME(wait_time) (((wait_time) > 0xFFF) || ((wait_time) < 0x0))
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/* check PMU flag state */
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#define NOT_PMU_FLAG(flag) (((flag) != PMU_FLAG_WAKEUP) && ((flag) != PMU_FLAG_STANDBY) && \
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((flag) != PMU_FLAG_LVDF) && ((flag) != PMU_FLAG_VAVDF) && \
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((flag) != PMU_FLAG_VOVDF) && ((flag) != PMU_FLAG_VBATLF) && \
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((flag) != PMU_FLAG_VBATHF) && ((flag) != PMU_FLAG_TEMPLF) && \
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((flag) != PMU_FLAG_TEMPHF) && ((flag) != PMU_FLAG_DVSRF) && \
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((flag) != PMU_FLAG_USB33RF) && ((flag) != PMU_FLAG_PWRRF))
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/* check PMU reset flag state */
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#define NOT_PMU_FLAG_RESET(flag_reset) (((flag_reset) != PMU_FLAG_WAKEUP) && ((flag_reset) != PMU_FLAG_STANDBY))
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#endif /* FW_DEBUG_ERR_REPORT */
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/* function declarations */
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/* reset PMU registers */
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void pmu_deinit(void);
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/* select low voltage detector threshold */
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void pmu_lvd_select(uint32_t lvdt_n);
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/* enable PMU lvd */
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void pmu_lvd_enable(void);
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/* disable PMU lvd */
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void pmu_lvd_disable(void);
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/* select analog voltage detector threshold */
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void pmu_vavd_select(uint32_t vavdt_n);
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/* enable PMU analog voltage detector */
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void pmu_vavd_enable(void);
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/* disable PMU analog voltage detector */
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void pmu_vavd_disable(void);
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/* enable PMU core voltage detector */
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void pmu_vovd_enable(void);
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/* disable PMU V0.9V core voltage detector */
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void pmu_vovd_disable(void);
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/* control the V0.9V core voltage level */
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void pmu_ldo_output_select(uint32_t ldo_n);
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/* Deep-sleep mode V0.9V core voltage select */
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void pmu_sldo_output_select(uint32_t sldo_n);
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/* PMU VBAT battery charging resistor selection */
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void pmu_vbat_charging_select(uint32_t resistor);
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/* enable VBAT battery charging */
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void pmu_vbat_charging_enable(void);
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/* disable VBAT battery charging */
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void pmu_vbat_charging_disable(void);
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/* enable VBAT and temperature monitoring */
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void pmu_vbat_temp_moniter_enable(void);
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/* disable VBAT and temperature monitoring */
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void pmu_vbat_temp_moniter_disable(void);
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/* USB regulator */
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/* enable USB regulator */
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void pmu_usb_regulator_enable(void);
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/* disable USB regulator */
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void pmu_usb_regulator_disable(void);
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/* enable VDD33USB voltage level detector */
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void pmu_usb_voltage_detector_enable(void);
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/* disable VDD33USB voltage level detector */
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void pmu_usb_voltage_detector_disable(void);
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/* power supply configurations */
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void pmu_smps_ldo_supply_config(uint32_t smpsmode);
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/* set PMU mode */
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/* enter sleep mode */
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void pmu_to_sleepmode(uint8_t sleepmodecmd);
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/* enter deepsleep mode */
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void pmu_to_deepsleepmode(uint8_t deepsleepmodecmd);
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/* enter standby mode */
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void pmu_to_standbymode(void);
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/* enable PMU wakeup pin */
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void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
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/* disable PMU wakeup pin */
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void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
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/* backup related functions */
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/* enable backup domain write */
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void pmu_backup_write_enable(void);
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/* disable backup domain write */
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void pmu_backup_write_disable(void);
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/* enable backup voltage stabilizer */
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void pmu_backup_voltage_stabilizer_enable(void);
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/* disable backup voltage stabilizer */
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void pmu_backup_voltage_stabilizer_disable(void);
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/* configure IRC counter before enter Deep-sleep mode */
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void pmu_enter_deepsleep_wait_time_config(int32_t wait_time);
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/* configure IRC counter before exit Deep-sleep mode */
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void pmu_exit_deepsleep_wait_time_config(int32_t wait_time);
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/* flag functions */
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/* get flag state */
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FlagStatus pmu_flag_get(uint32_t flag);
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/* clear flag bit */
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void pmu_flag_clear(uint32_t flag_reset);
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#endif /* GD32H75E_PMU_H */
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